]>
git.proxmox.com Git - qemu.git/blob - target-sparc/op_helper.c
2 #include "host-utils.h"
4 #if !defined(CONFIG_USER_ONLY)
5 #include "softmmu_exec.h"
6 #endif /* !defined(CONFIG_USER_ONLY) */
10 //#define DEBUG_UNALIGNED
11 //#define DEBUG_UNASSIGNED
16 #define DPRINTF_MMU(fmt, args...) \
17 do { printf("MMU: " fmt , ##args); } while (0)
19 #define DPRINTF_MMU(fmt, args...) do {} while (0)
23 #define DPRINTF_MXCC(fmt, args...) \
24 do { printf("MXCC: " fmt , ##args); } while (0)
26 #define DPRINTF_MXCC(fmt, args...) do {} while (0)
30 #define DPRINTF_ASI(fmt, args...) \
31 do { printf("ASI: " fmt , ##args); } while (0)
33 #define DPRINTF_ASI(fmt, args...) do {} while (0)
38 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
40 #define AM_CHECK(env1) (1)
44 static inline void address_mask(CPUState
*env1
, target_ulong
*addr
)
48 *addr
&= 0xffffffffULL
;
52 void raise_exception(int tt
)
54 env
->exception_index
= tt
;
58 static inline void set_cwp(int new_cwp
)
60 cpu_set_cwp(env
, new_cwp
);
63 void helper_check_align(target_ulong addr
, uint32_t align
)
66 #ifdef DEBUG_UNALIGNED
67 printf("Unaligned access to 0x" TARGET_FMT_lx
" from 0x" TARGET_FMT_lx
70 raise_exception(TT_UNALIGNED
);
74 #define F_HELPER(name, p) void helper_f##name##p(void)
76 #define F_BINOP(name) \
77 float32 helper_f ## name ## s (float32 src1, float32 src2) \
79 return float32_ ## name (src1, src2, &env->fp_status); \
83 DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \
87 QT0 = float128_ ## name (QT0, QT1, &env->fp_status); \
96 void helper_fsmuld(float32 src1
, float32 src2
)
98 DT0
= float64_mul(float32_to_float64(src1
, &env
->fp_status
),
99 float32_to_float64(src2
, &env
->fp_status
),
103 void helper_fdmulq(void)
105 QT0
= float128_mul(float64_to_float128(DT0
, &env
->fp_status
),
106 float64_to_float128(DT1
, &env
->fp_status
),
110 float32
helper_fnegs(float32 src
)
112 return float32_chs(src
);
115 #ifdef TARGET_SPARC64
118 DT0
= float64_chs(DT1
);
123 QT0
= float128_chs(QT1
);
127 /* Integer to float conversion. */
128 float32
helper_fitos(int32_t src
)
130 return int32_to_float32(src
, &env
->fp_status
);
133 void helper_fitod(int32_t src
)
135 DT0
= int32_to_float64(src
, &env
->fp_status
);
138 void helper_fitoq(int32_t src
)
140 QT0
= int32_to_float128(src
, &env
->fp_status
);
143 #ifdef TARGET_SPARC64
144 float32
helper_fxtos(void)
146 return int64_to_float32(*((int64_t *)&DT1
), &env
->fp_status
);
151 DT0
= int64_to_float64(*((int64_t *)&DT1
), &env
->fp_status
);
156 QT0
= int64_to_float128(*((int64_t *)&DT1
), &env
->fp_status
);
161 /* floating point conversion */
162 float32
helper_fdtos(void)
164 return float64_to_float32(DT1
, &env
->fp_status
);
167 void helper_fstod(float32 src
)
169 DT0
= float32_to_float64(src
, &env
->fp_status
);
172 float32
helper_fqtos(void)
174 return float128_to_float32(QT1
, &env
->fp_status
);
177 void helper_fstoq(float32 src
)
179 QT0
= float32_to_float128(src
, &env
->fp_status
);
182 void helper_fqtod(void)
184 DT0
= float128_to_float64(QT1
, &env
->fp_status
);
187 void helper_fdtoq(void)
189 QT0
= float64_to_float128(DT1
, &env
->fp_status
);
192 /* Float to integer conversion. */
193 int32_t helper_fstoi(float32 src
)
195 return float32_to_int32_round_to_zero(src
, &env
->fp_status
);
198 int32_t helper_fdtoi(void)
200 return float64_to_int32_round_to_zero(DT1
, &env
->fp_status
);
203 int32_t helper_fqtoi(void)
205 return float128_to_int32_round_to_zero(QT1
, &env
->fp_status
);
208 #ifdef TARGET_SPARC64
209 void helper_fstox(float32 src
)
211 *((int64_t *)&DT0
) = float32_to_int64_round_to_zero(src
, &env
->fp_status
);
214 void helper_fdtox(void)
216 *((int64_t *)&DT0
) = float64_to_int64_round_to_zero(DT1
, &env
->fp_status
);
219 void helper_fqtox(void)
221 *((int64_t *)&DT0
) = float128_to_int64_round_to_zero(QT1
, &env
->fp_status
);
224 void helper_faligndata(void)
228 tmp
= (*((uint64_t *)&DT0
)) << ((env
->gsr
& 7) * 8);
229 /* on many architectures a shift of 64 does nothing */
230 if ((env
->gsr
& 7) != 0) {
231 tmp
|= (*((uint64_t *)&DT1
)) >> (64 - (env
->gsr
& 7) * 8);
233 *((uint64_t *)&DT0
) = tmp
;
236 #ifdef WORDS_BIGENDIAN
237 #define VIS_B64(n) b[7 - (n)]
238 #define VIS_W64(n) w[3 - (n)]
239 #define VIS_SW64(n) sw[3 - (n)]
240 #define VIS_L64(n) l[1 - (n)]
241 #define VIS_B32(n) b[3 - (n)]
242 #define VIS_W32(n) w[1 - (n)]
244 #define VIS_B64(n) b[n]
245 #define VIS_W64(n) w[n]
246 #define VIS_SW64(n) sw[n]
247 #define VIS_L64(n) l[n]
248 #define VIS_B32(n) b[n]
249 #define VIS_W32(n) w[n]
267 void helper_fpmerge(void)
274 // Reverse calculation order to handle overlap
275 d
.VIS_B64(7) = s
.VIS_B64(3);
276 d
.VIS_B64(6) = d
.VIS_B64(3);
277 d
.VIS_B64(5) = s
.VIS_B64(2);
278 d
.VIS_B64(4) = d
.VIS_B64(2);
279 d
.VIS_B64(3) = s
.VIS_B64(1);
280 d
.VIS_B64(2) = d
.VIS_B64(1);
281 d
.VIS_B64(1) = s
.VIS_B64(0);
282 //d.VIS_B64(0) = d.VIS_B64(0);
287 void helper_fmul8x16(void)
296 tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r); \
297 if ((tmp & 0xff) > 0x7f) \
299 d.VIS_W64(r) = tmp >> 8;
310 void helper_fmul8x16al(void)
319 tmp = (int32_t)d.VIS_SW64(1) * (int32_t)s.VIS_B64(r); \
320 if ((tmp & 0xff) > 0x7f) \
322 d.VIS_W64(r) = tmp >> 8;
333 void helper_fmul8x16au(void)
342 tmp = (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r); \
343 if ((tmp & 0xff) > 0x7f) \
345 d.VIS_W64(r) = tmp >> 8;
356 void helper_fmul8sux16(void)
365 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
366 if ((tmp & 0xff) > 0x7f) \
368 d.VIS_W64(r) = tmp >> 8;
379 void helper_fmul8ulx16(void)
388 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
389 if ((tmp & 0xff) > 0x7f) \
391 d.VIS_W64(r) = tmp >> 8;
402 void helper_fmuld8sux16(void)
411 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
412 if ((tmp & 0xff) > 0x7f) \
416 // Reverse calculation order to handle overlap
424 void helper_fmuld8ulx16(void)
433 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
434 if ((tmp & 0xff) > 0x7f) \
438 // Reverse calculation order to handle overlap
446 void helper_fexpand(void)
451 s
.l
= (uint32_t)(*(uint64_t *)&DT0
& 0xffffffff);
453 d
.VIS_L64(0) = s
.VIS_W32(0) << 4;
454 d
.VIS_L64(1) = s
.VIS_W32(1) << 4;
455 d
.VIS_L64(2) = s
.VIS_W32(2) << 4;
456 d
.VIS_L64(3) = s
.VIS_W32(3) << 4;
461 #define VIS_HELPER(name, F) \
462 void name##16(void) \
469 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0)); \
470 d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1)); \
471 d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2)); \
472 d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3)); \
477 uint32_t name##16s(uint32_t src1, uint32_t src2) \
484 d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0)); \
485 d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1)); \
490 void name##32(void) \
497 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0)); \
498 d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1)); \
503 uint32_t name##32s(uint32_t src1, uint32_t src2) \
515 #define FADD(a, b) ((a) + (b))
516 #define FSUB(a, b) ((a) - (b))
517 VIS_HELPER(helper_fpadd
, FADD
)
518 VIS_HELPER(helper_fpsub
, FSUB
)
520 #define VIS_CMPHELPER(name, F) \
521 void name##16(void) \
528 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0))? 1: 0; \
529 d.VIS_W64(0) |= F(d.VIS_W64(1), s.VIS_W64(1))? 2: 0; \
530 d.VIS_W64(0) |= F(d.VIS_W64(2), s.VIS_W64(2))? 4: 0; \
531 d.VIS_W64(0) |= F(d.VIS_W64(3), s.VIS_W64(3))? 8: 0; \
536 void name##32(void) \
543 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0))? 1: 0; \
544 d.VIS_L64(0) |= F(d.VIS_L64(1), s.VIS_L64(1))? 2: 0; \
549 #define FCMPGT(a, b) ((a) > (b))
550 #define FCMPEQ(a, b) ((a) == (b))
551 #define FCMPLE(a, b) ((a) <= (b))
552 #define FCMPNE(a, b) ((a) != (b))
554 VIS_CMPHELPER(helper_fcmpgt
, FCMPGT
)
555 VIS_CMPHELPER(helper_fcmpeq
, FCMPEQ
)
556 VIS_CMPHELPER(helper_fcmple
, FCMPLE
)
557 VIS_CMPHELPER(helper_fcmpne
, FCMPNE
)
560 void helper_check_ieee_exceptions(void)
564 status
= get_float_exception_flags(&env
->fp_status
);
566 /* Copy IEEE 754 flags into FSR */
567 if (status
& float_flag_invalid
)
569 if (status
& float_flag_overflow
)
571 if (status
& float_flag_underflow
)
573 if (status
& float_flag_divbyzero
)
575 if (status
& float_flag_inexact
)
578 if ((env
->fsr
& FSR_CEXC_MASK
) & ((env
->fsr
& FSR_TEM_MASK
) >> 23)) {
579 /* Unmasked exception, generate a trap */
580 env
->fsr
|= FSR_FTT_IEEE_EXCP
;
581 raise_exception(TT_FP_EXCP
);
583 /* Accumulate exceptions */
584 env
->fsr
|= (env
->fsr
& FSR_CEXC_MASK
) << 5;
589 void helper_clear_float_exceptions(void)
591 set_float_exception_flags(0, &env
->fp_status
);
594 float32
helper_fabss(float32 src
)
596 return float32_abs(src
);
599 #ifdef TARGET_SPARC64
600 void helper_fabsd(void)
602 DT0
= float64_abs(DT1
);
605 void helper_fabsq(void)
607 QT0
= float128_abs(QT1
);
611 float32
helper_fsqrts(float32 src
)
613 return float32_sqrt(src
, &env
->fp_status
);
616 void helper_fsqrtd(void)
618 DT0
= float64_sqrt(DT1
, &env
->fp_status
);
621 void helper_fsqrtq(void)
623 QT0
= float128_sqrt(QT1
, &env
->fp_status
);
626 #define GEN_FCMP(name, size, reg1, reg2, FS, TRAP) \
627 void glue(helper_, name) (void) \
629 target_ulong new_fsr; \
631 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
632 switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
633 case float_relation_unordered: \
634 new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \
635 if ((env->fsr & FSR_NVM) || TRAP) { \
636 env->fsr |= new_fsr; \
637 env->fsr |= FSR_NVC; \
638 env->fsr |= FSR_FTT_IEEE_EXCP; \
639 raise_exception(TT_FP_EXCP); \
641 env->fsr |= FSR_NVA; \
644 case float_relation_less: \
645 new_fsr = FSR_FCC0 << FS; \
647 case float_relation_greater: \
648 new_fsr = FSR_FCC1 << FS; \
654 env->fsr |= new_fsr; \
656 #define GEN_FCMPS(name, size, FS, TRAP) \
657 void glue(helper_, name)(float32 src1, float32 src2) \
659 target_ulong new_fsr; \
661 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
662 switch (glue(size, _compare) (src1, src2, &env->fp_status)) { \
663 case float_relation_unordered: \
664 new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \
665 if ((env->fsr & FSR_NVM) || TRAP) { \
666 env->fsr |= new_fsr; \
667 env->fsr |= FSR_NVC; \
668 env->fsr |= FSR_FTT_IEEE_EXCP; \
669 raise_exception(TT_FP_EXCP); \
671 env->fsr |= FSR_NVA; \
674 case float_relation_less: \
675 new_fsr = FSR_FCC0 << FS; \
677 case float_relation_greater: \
678 new_fsr = FSR_FCC1 << FS; \
684 env->fsr |= new_fsr; \
687 GEN_FCMPS(fcmps
, float32
, 0, 0);
688 GEN_FCMP(fcmpd
, float64
, DT0
, DT1
, 0, 0);
690 GEN_FCMPS(fcmpes
, float32
, 0, 1);
691 GEN_FCMP(fcmped
, float64
, DT0
, DT1
, 0, 1);
693 GEN_FCMP(fcmpq
, float128
, QT0
, QT1
, 0, 0);
694 GEN_FCMP(fcmpeq
, float128
, QT0
, QT1
, 0, 1);
696 #ifdef TARGET_SPARC64
697 GEN_FCMPS(fcmps_fcc1
, float32
, 22, 0);
698 GEN_FCMP(fcmpd_fcc1
, float64
, DT0
, DT1
, 22, 0);
699 GEN_FCMP(fcmpq_fcc1
, float128
, QT0
, QT1
, 22, 0);
701 GEN_FCMPS(fcmps_fcc2
, float32
, 24, 0);
702 GEN_FCMP(fcmpd_fcc2
, float64
, DT0
, DT1
, 24, 0);
703 GEN_FCMP(fcmpq_fcc2
, float128
, QT0
, QT1
, 24, 0);
705 GEN_FCMPS(fcmps_fcc3
, float32
, 26, 0);
706 GEN_FCMP(fcmpd_fcc3
, float64
, DT0
, DT1
, 26, 0);
707 GEN_FCMP(fcmpq_fcc3
, float128
, QT0
, QT1
, 26, 0);
709 GEN_FCMPS(fcmpes_fcc1
, float32
, 22, 1);
710 GEN_FCMP(fcmped_fcc1
, float64
, DT0
, DT1
, 22, 1);
711 GEN_FCMP(fcmpeq_fcc1
, float128
, QT0
, QT1
, 22, 1);
713 GEN_FCMPS(fcmpes_fcc2
, float32
, 24, 1);
714 GEN_FCMP(fcmped_fcc2
, float64
, DT0
, DT1
, 24, 1);
715 GEN_FCMP(fcmpeq_fcc2
, float128
, QT0
, QT1
, 24, 1);
717 GEN_FCMPS(fcmpes_fcc3
, float32
, 26, 1);
718 GEN_FCMP(fcmped_fcc3
, float64
, DT0
, DT1
, 26, 1);
719 GEN_FCMP(fcmpeq_fcc3
, float128
, QT0
, QT1
, 26, 1);
723 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
725 static void dump_mxcc(CPUState
*env
)
727 printf("mxccdata: %016llx %016llx %016llx %016llx\n",
728 env
->mxccdata
[0], env
->mxccdata
[1],
729 env
->mxccdata
[2], env
->mxccdata
[3]);
730 printf("mxccregs: %016llx %016llx %016llx %016llx\n"
731 " %016llx %016llx %016llx %016llx\n",
732 env
->mxccregs
[0], env
->mxccregs
[1],
733 env
->mxccregs
[2], env
->mxccregs
[3],
734 env
->mxccregs
[4], env
->mxccregs
[5],
735 env
->mxccregs
[6], env
->mxccregs
[7]);
739 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
740 && defined(DEBUG_ASI)
741 static void dump_asi(const char *txt
, target_ulong addr
, int asi
, int size
,
747 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %02" PRIx64
"\n", txt
,
748 addr
, asi
, r1
& 0xff);
751 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %04" PRIx64
"\n", txt
,
752 addr
, asi
, r1
& 0xffff);
755 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %08" PRIx64
"\n", txt
,
756 addr
, asi
, r1
& 0xffffffff);
759 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %016" PRIx64
"\n", txt
,
766 #ifndef TARGET_SPARC64
767 #ifndef CONFIG_USER_ONLY
768 uint64_t helper_ld_asi(target_ulong addr
, int asi
, int size
, int sign
)
771 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
772 uint32_t last_addr
= addr
;
775 helper_check_align(addr
, size
- 1);
777 case 2: /* SuperSparc MXCC registers */
779 case 0x01c00a00: /* MXCC control register */
781 ret
= env
->mxccregs
[3];
783 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
786 case 0x01c00a04: /* MXCC control register */
788 ret
= env
->mxccregs
[3];
790 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
793 case 0x01c00c00: /* Module reset register */
795 ret
= env
->mxccregs
[5];
796 // should we do something here?
798 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
801 case 0x01c00f00: /* MBus port address register */
803 ret
= env
->mxccregs
[7];
805 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
809 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr
,
813 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
814 "addr = %08x -> ret = %" PRIx64
","
815 "addr = %08x\n", asi
, size
, sign
, last_addr
, ret
, addr
);
820 case 3: /* MMU probe */
824 mmulev
= (addr
>> 8) & 15;
828 ret
= mmu_probe(env
, addr
, mmulev
);
829 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64
"\n",
833 case 4: /* read MMU regs */
835 int reg
= (addr
>> 8) & 0x1f;
837 ret
= env
->mmuregs
[reg
];
838 if (reg
== 3) /* Fault status cleared on read */
840 else if (reg
== 0x13) /* Fault status read */
841 ret
= env
->mmuregs
[3];
842 else if (reg
== 0x14) /* Fault address read */
843 ret
= env
->mmuregs
[4];
844 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64
"\n", reg
, ret
);
847 case 5: // Turbosparc ITLB Diagnostic
848 case 6: // Turbosparc DTLB Diagnostic
849 case 7: // Turbosparc IOTLB Diagnostic
851 case 9: /* Supervisor code access */
854 ret
= ldub_code(addr
);
857 ret
= lduw_code(addr
);
861 ret
= ldl_code(addr
);
864 ret
= ldq_code(addr
);
868 case 0xa: /* User data access */
871 ret
= ldub_user(addr
);
874 ret
= lduw_user(addr
);
878 ret
= ldl_user(addr
);
881 ret
= ldq_user(addr
);
885 case 0xb: /* Supervisor data access */
888 ret
= ldub_kernel(addr
);
891 ret
= lduw_kernel(addr
);
895 ret
= ldl_kernel(addr
);
898 ret
= ldq_kernel(addr
);
902 case 0xc: /* I-cache tag */
903 case 0xd: /* I-cache data */
904 case 0xe: /* D-cache tag */
905 case 0xf: /* D-cache data */
907 case 0x20: /* MMU passthrough */
910 ret
= ldub_phys(addr
);
913 ret
= lduw_phys(addr
);
917 ret
= ldl_phys(addr
);
920 ret
= ldq_phys(addr
);
924 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
927 ret
= ldub_phys((target_phys_addr_t
)addr
928 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
931 ret
= lduw_phys((target_phys_addr_t
)addr
932 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
936 ret
= ldl_phys((target_phys_addr_t
)addr
937 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
940 ret
= ldq_phys((target_phys_addr_t
)addr
941 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
945 case 0x30: // Turbosparc secondary cache diagnostic
946 case 0x31: // Turbosparc RAM snoop
947 case 0x32: // Turbosparc page table descriptor diagnostic
948 case 0x39: /* data cache diagnostic register */
951 case 8: /* User code access, XXX */
953 do_unassigned_access(addr
, 0, 0, asi
);
973 dump_asi("read ", last_addr
, asi
, size
, ret
);
978 void helper_st_asi(target_ulong addr
, uint64_t val
, int asi
, int size
)
980 helper_check_align(addr
, size
- 1);
982 case 2: /* SuperSparc MXCC registers */
984 case 0x01c00000: /* MXCC stream data register 0 */
986 env
->mxccdata
[0] = val
;
988 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
991 case 0x01c00008: /* MXCC stream data register 1 */
993 env
->mxccdata
[1] = val
;
995 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
998 case 0x01c00010: /* MXCC stream data register 2 */
1000 env
->mxccdata
[2] = val
;
1002 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1005 case 0x01c00018: /* MXCC stream data register 3 */
1007 env
->mxccdata
[3] = val
;
1009 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1012 case 0x01c00100: /* MXCC stream source */
1014 env
->mxccregs
[0] = val
;
1016 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1018 env
->mxccdata
[0] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
1020 env
->mxccdata
[1] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
1022 env
->mxccdata
[2] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
1024 env
->mxccdata
[3] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
1027 case 0x01c00200: /* MXCC stream destination */
1029 env
->mxccregs
[1] = val
;
1031 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1033 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 0,
1035 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 8,
1037 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 16,
1039 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 24,
1042 case 0x01c00a00: /* MXCC control register */
1044 env
->mxccregs
[3] = val
;
1046 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1049 case 0x01c00a04: /* MXCC control register */
1051 env
->mxccregs
[3] = (env
->mxccregs
[3] & 0xffffffff00000000ULL
)
1054 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1057 case 0x01c00e00: /* MXCC error register */
1058 // writing a 1 bit clears the error
1060 env
->mxccregs
[6] &= ~val
;
1062 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1065 case 0x01c00f00: /* MBus port address register */
1067 env
->mxccregs
[7] = val
;
1069 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1073 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr
,
1077 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64
"\n",
1078 asi
, size
, addr
, val
);
1083 case 3: /* MMU flush */
1087 mmulev
= (addr
>> 8) & 15;
1088 DPRINTF_MMU("mmu flush level %d\n", mmulev
);
1090 case 0: // flush page
1091 tlb_flush_page(env
, addr
& 0xfffff000);
1093 case 1: // flush segment (256k)
1094 case 2: // flush region (16M)
1095 case 3: // flush context (4G)
1096 case 4: // flush entire
1107 case 4: /* write MMU regs */
1109 int reg
= (addr
>> 8) & 0x1f;
1112 oldreg
= env
->mmuregs
[reg
];
1114 case 0: // Control Register
1115 env
->mmuregs
[reg
] = (env
->mmuregs
[reg
] & 0xff000000) |
1117 // Mappings generated during no-fault mode or MMU
1118 // disabled mode are invalid in normal mode
1119 if ((oldreg
& (MMU_E
| MMU_NF
| env
->def
->mmu_bm
)) !=
1120 (env
->mmuregs
[reg
] & (MMU_E
| MMU_NF
| env
->def
->mmu_bm
)))
1123 case 1: // Context Table Pointer Register
1124 env
->mmuregs
[reg
] = val
& env
->def
->mmu_ctpr_mask
;
1126 case 2: // Context Register
1127 env
->mmuregs
[reg
] = val
& env
->def
->mmu_cxr_mask
;
1128 if (oldreg
!= env
->mmuregs
[reg
]) {
1129 /* we flush when the MMU context changes because
1130 QEMU has no MMU context support */
1134 case 3: // Synchronous Fault Status Register with Clear
1135 case 4: // Synchronous Fault Address Register
1137 case 0x10: // TLB Replacement Control Register
1138 env
->mmuregs
[reg
] = val
& env
->def
->mmu_trcr_mask
;
1140 case 0x13: // Synchronous Fault Status Register with Read and Clear
1141 env
->mmuregs
[3] = val
& env
->def
->mmu_sfsr_mask
;
1143 case 0x14: // Synchronous Fault Address Register
1144 env
->mmuregs
[4] = val
;
1147 env
->mmuregs
[reg
] = val
;
1150 if (oldreg
!= env
->mmuregs
[reg
]) {
1151 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
1152 reg
, oldreg
, env
->mmuregs
[reg
]);
1159 case 5: // Turbosparc ITLB Diagnostic
1160 case 6: // Turbosparc DTLB Diagnostic
1161 case 7: // Turbosparc IOTLB Diagnostic
1163 case 0xa: /* User data access */
1166 stb_user(addr
, val
);
1169 stw_user(addr
, val
);
1173 stl_user(addr
, val
);
1176 stq_user(addr
, val
);
1180 case 0xb: /* Supervisor data access */
1183 stb_kernel(addr
, val
);
1186 stw_kernel(addr
, val
);
1190 stl_kernel(addr
, val
);
1193 stq_kernel(addr
, val
);
1197 case 0xc: /* I-cache tag */
1198 case 0xd: /* I-cache data */
1199 case 0xe: /* D-cache tag */
1200 case 0xf: /* D-cache data */
1201 case 0x10: /* I/D-cache flush page */
1202 case 0x11: /* I/D-cache flush segment */
1203 case 0x12: /* I/D-cache flush region */
1204 case 0x13: /* I/D-cache flush context */
1205 case 0x14: /* I/D-cache flush user */
1207 case 0x17: /* Block copy, sta access */
1213 uint32_t src
= val
& ~3, dst
= addr
& ~3, temp
;
1215 for (i
= 0; i
< 32; i
+= 4, src
+= 4, dst
+= 4) {
1216 temp
= ldl_kernel(src
);
1217 stl_kernel(dst
, temp
);
1221 case 0x1f: /* Block fill, stda access */
1224 // fill 32 bytes with val
1226 uint32_t dst
= addr
& 7;
1228 for (i
= 0; i
< 32; i
+= 8, dst
+= 8)
1229 stq_kernel(dst
, val
);
1232 case 0x20: /* MMU passthrough */
1236 stb_phys(addr
, val
);
1239 stw_phys(addr
, val
);
1243 stl_phys(addr
, val
);
1246 stq_phys(addr
, val
);
1251 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1255 stb_phys((target_phys_addr_t
)addr
1256 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
1259 stw_phys((target_phys_addr_t
)addr
1260 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
1264 stl_phys((target_phys_addr_t
)addr
1265 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
1268 stq_phys((target_phys_addr_t
)addr
1269 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
1274 case 0x30: // store buffer tags or Turbosparc secondary cache diagnostic
1275 case 0x31: // store buffer data, Ross RT620 I-cache flush or
1276 // Turbosparc snoop RAM
1277 case 0x32: // store buffer control or Turbosparc page table
1278 // descriptor diagnostic
1279 case 0x36: /* I-cache flash clear */
1280 case 0x37: /* D-cache flash clear */
1281 case 0x38: /* breakpoint diagnostics */
1282 case 0x4c: /* breakpoint action */
1284 case 8: /* User code access, XXX */
1285 case 9: /* Supervisor code access, XXX */
1287 do_unassigned_access(addr
, 1, 0, asi
);
1291 dump_asi("write", addr
, asi
, size
, val
);
1295 #endif /* CONFIG_USER_ONLY */
1296 #else /* TARGET_SPARC64 */
1298 #ifdef CONFIG_USER_ONLY
1299 uint64_t helper_ld_asi(target_ulong addr
, int asi
, int size
, int sign
)
1302 #if defined(DEBUG_ASI)
1303 target_ulong last_addr
= addr
;
1307 raise_exception(TT_PRIV_ACT
);
1309 helper_check_align(addr
, size
- 1);
1310 address_mask(env
, &addr
);
1313 case 0x82: // Primary no-fault
1314 case 0x8a: // Primary no-fault LE
1315 if (page_check_range(addr
, size
, PAGE_READ
) == -1) {
1317 dump_asi("read ", last_addr
, asi
, size
, ret
);
1322 case 0x80: // Primary
1323 case 0x88: // Primary LE
1327 ret
= ldub_raw(addr
);
1330 ret
= lduw_raw(addr
);
1333 ret
= ldl_raw(addr
);
1337 ret
= ldq_raw(addr
);
1342 case 0x83: // Secondary no-fault
1343 case 0x8b: // Secondary no-fault LE
1344 if (page_check_range(addr
, size
, PAGE_READ
) == -1) {
1346 dump_asi("read ", last_addr
, asi
, size
, ret
);
1351 case 0x81: // Secondary
1352 case 0x89: // Secondary LE
1359 /* Convert from little endian */
1361 case 0x88: // Primary LE
1362 case 0x89: // Secondary LE
1363 case 0x8a: // Primary no-fault LE
1364 case 0x8b: // Secondary no-fault LE
1382 /* Convert to signed number */
1389 ret
= (int16_t) ret
;
1392 ret
= (int32_t) ret
;
1399 dump_asi("read ", last_addr
, asi
, size
, ret
);
1404 void helper_st_asi(target_ulong addr
, target_ulong val
, int asi
, int size
)
1407 dump_asi("write", addr
, asi
, size
, val
);
1410 raise_exception(TT_PRIV_ACT
);
1412 helper_check_align(addr
, size
- 1);
1413 address_mask(env
, &addr
);
1415 /* Convert to little endian */
1417 case 0x88: // Primary LE
1418 case 0x89: // Secondary LE
1421 addr
= bswap16(addr
);
1424 addr
= bswap32(addr
);
1427 addr
= bswap64(addr
);
1437 case 0x80: // Primary
1438 case 0x88: // Primary LE
1457 case 0x81: // Secondary
1458 case 0x89: // Secondary LE
1462 case 0x82: // Primary no-fault, RO
1463 case 0x83: // Secondary no-fault, RO
1464 case 0x8a: // Primary no-fault LE, RO
1465 case 0x8b: // Secondary no-fault LE, RO
1467 do_unassigned_access(addr
, 1, 0, 1);
1472 #else /* CONFIG_USER_ONLY */
1474 uint64_t helper_ld_asi(target_ulong addr
, int asi
, int size
, int sign
)
1477 #if defined(DEBUG_ASI)
1478 target_ulong last_addr
= addr
;
1481 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
1482 || ((env
->def
->features
& CPU_FEATURE_HYPV
)
1483 && asi
>= 0x30 && asi
< 0x80
1484 && !(env
->hpstate
& HS_PRIV
)))
1485 raise_exception(TT_PRIV_ACT
);
1487 helper_check_align(addr
, size
- 1);
1489 case 0x82: // Primary no-fault
1490 case 0x8a: // Primary no-fault LE
1491 if (cpu_get_phys_page_debug(env
, addr
) == -1ULL) {
1493 dump_asi("read ", last_addr
, asi
, size
, ret
);
1498 case 0x10: // As if user primary
1499 case 0x18: // As if user primary LE
1500 case 0x80: // Primary
1501 case 0x88: // Primary LE
1502 case 0xe2: // UA2007 Primary block init
1503 case 0xe3: // UA2007 Secondary block init
1504 if ((asi
& 0x80) && (env
->pstate
& PS_PRIV
)) {
1505 if ((env
->def
->features
& CPU_FEATURE_HYPV
)
1506 && env
->hpstate
& HS_PRIV
) {
1509 ret
= ldub_hypv(addr
);
1512 ret
= lduw_hypv(addr
);
1515 ret
= ldl_hypv(addr
);
1519 ret
= ldq_hypv(addr
);
1525 ret
= ldub_kernel(addr
);
1528 ret
= lduw_kernel(addr
);
1531 ret
= ldl_kernel(addr
);
1535 ret
= ldq_kernel(addr
);
1542 ret
= ldub_user(addr
);
1545 ret
= lduw_user(addr
);
1548 ret
= ldl_user(addr
);
1552 ret
= ldq_user(addr
);
1557 case 0x14: // Bypass
1558 case 0x15: // Bypass, non-cacheable
1559 case 0x1c: // Bypass LE
1560 case 0x1d: // Bypass, non-cacheable LE
1564 ret
= ldub_phys(addr
);
1567 ret
= lduw_phys(addr
);
1570 ret
= ldl_phys(addr
);
1574 ret
= ldq_phys(addr
);
1579 case 0x24: // Nucleus quad LDD 128 bit atomic
1580 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
1581 // Only ldda allowed
1582 raise_exception(TT_ILL_INSN
);
1584 case 0x83: // Secondary no-fault
1585 case 0x8b: // Secondary no-fault LE
1586 if (cpu_get_phys_page_debug(env
, addr
) == -1ULL) {
1588 dump_asi("read ", last_addr
, asi
, size
, ret
);
1593 case 0x04: // Nucleus
1594 case 0x0c: // Nucleus Little Endian (LE)
1595 case 0x11: // As if user secondary
1596 case 0x19: // As if user secondary LE
1597 case 0x4a: // UPA config
1598 case 0x81: // Secondary
1599 case 0x89: // Secondary LE
1605 case 0x50: // I-MMU regs
1607 int reg
= (addr
>> 3) & 0xf;
1609 ret
= env
->immuregs
[reg
];
1612 case 0x51: // I-MMU 8k TSB pointer
1613 case 0x52: // I-MMU 64k TSB pointer
1616 case 0x55: // I-MMU data access
1618 int reg
= (addr
>> 3) & 0x3f;
1620 ret
= env
->itlb_tte
[reg
];
1623 case 0x56: // I-MMU tag read
1625 int reg
= (addr
>> 3) & 0x3f;
1627 ret
= env
->itlb_tag
[reg
];
1630 case 0x58: // D-MMU regs
1632 int reg
= (addr
>> 3) & 0xf;
1634 ret
= env
->dmmuregs
[reg
];
1637 case 0x5d: // D-MMU data access
1639 int reg
= (addr
>> 3) & 0x3f;
1641 ret
= env
->dtlb_tte
[reg
];
1644 case 0x5e: // D-MMU tag read
1646 int reg
= (addr
>> 3) & 0x3f;
1648 ret
= env
->dtlb_tag
[reg
];
1651 case 0x46: // D-cache data
1652 case 0x47: // D-cache tag access
1653 case 0x4b: // E-cache error enable
1654 case 0x4c: // E-cache asynchronous fault status
1655 case 0x4d: // E-cache asynchronous fault address
1656 case 0x4e: // E-cache tag data
1657 case 0x66: // I-cache instruction access
1658 case 0x67: // I-cache tag access
1659 case 0x6e: // I-cache predecode
1660 case 0x6f: // I-cache LRU etc.
1661 case 0x76: // E-cache tag
1662 case 0x7e: // E-cache tag
1664 case 0x59: // D-MMU 8k TSB pointer
1665 case 0x5a: // D-MMU 64k TSB pointer
1666 case 0x5b: // D-MMU data pointer
1667 case 0x48: // Interrupt dispatch, RO
1668 case 0x49: // Interrupt data receive
1669 case 0x7f: // Incoming interrupt vector, RO
1672 case 0x54: // I-MMU data in, WO
1673 case 0x57: // I-MMU demap, WO
1674 case 0x5c: // D-MMU data in, WO
1675 case 0x5f: // D-MMU demap, WO
1676 case 0x77: // Interrupt vector, WO
1678 do_unassigned_access(addr
, 0, 0, 1);
1683 /* Convert from little endian */
1685 case 0x0c: // Nucleus Little Endian (LE)
1686 case 0x18: // As if user primary LE
1687 case 0x19: // As if user secondary LE
1688 case 0x1c: // Bypass LE
1689 case 0x1d: // Bypass, non-cacheable LE
1690 case 0x88: // Primary LE
1691 case 0x89: // Secondary LE
1692 case 0x8a: // Primary no-fault LE
1693 case 0x8b: // Secondary no-fault LE
1711 /* Convert to signed number */
1718 ret
= (int16_t) ret
;
1721 ret
= (int32_t) ret
;
1728 dump_asi("read ", last_addr
, asi
, size
, ret
);
1733 void helper_st_asi(target_ulong addr
, target_ulong val
, int asi
, int size
)
1736 dump_asi("write", addr
, asi
, size
, val
);
1738 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
1739 || ((env
->def
->features
& CPU_FEATURE_HYPV
)
1740 && asi
>= 0x30 && asi
< 0x80
1741 && !(env
->hpstate
& HS_PRIV
)))
1742 raise_exception(TT_PRIV_ACT
);
1744 helper_check_align(addr
, size
- 1);
1745 /* Convert to little endian */
1747 case 0x0c: // Nucleus Little Endian (LE)
1748 case 0x18: // As if user primary LE
1749 case 0x19: // As if user secondary LE
1750 case 0x1c: // Bypass LE
1751 case 0x1d: // Bypass, non-cacheable LE
1752 case 0x88: // Primary LE
1753 case 0x89: // Secondary LE
1756 addr
= bswap16(addr
);
1759 addr
= bswap32(addr
);
1762 addr
= bswap64(addr
);
1772 case 0x10: // As if user primary
1773 case 0x18: // As if user primary LE
1774 case 0x80: // Primary
1775 case 0x88: // Primary LE
1776 case 0xe2: // UA2007 Primary block init
1777 case 0xe3: // UA2007 Secondary block init
1778 if ((asi
& 0x80) && (env
->pstate
& PS_PRIV
)) {
1779 if ((env
->def
->features
& CPU_FEATURE_HYPV
)
1780 && env
->hpstate
& HS_PRIV
) {
1783 stb_hypv(addr
, val
);
1786 stw_hypv(addr
, val
);
1789 stl_hypv(addr
, val
);
1793 stq_hypv(addr
, val
);
1799 stb_kernel(addr
, val
);
1802 stw_kernel(addr
, val
);
1805 stl_kernel(addr
, val
);
1809 stq_kernel(addr
, val
);
1816 stb_user(addr
, val
);
1819 stw_user(addr
, val
);
1822 stl_user(addr
, val
);
1826 stq_user(addr
, val
);
1831 case 0x14: // Bypass
1832 case 0x15: // Bypass, non-cacheable
1833 case 0x1c: // Bypass LE
1834 case 0x1d: // Bypass, non-cacheable LE
1838 stb_phys(addr
, val
);
1841 stw_phys(addr
, val
);
1844 stl_phys(addr
, val
);
1848 stq_phys(addr
, val
);
1853 case 0x24: // Nucleus quad LDD 128 bit atomic
1854 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
1855 // Only ldda allowed
1856 raise_exception(TT_ILL_INSN
);
1858 case 0x04: // Nucleus
1859 case 0x0c: // Nucleus Little Endian (LE)
1860 case 0x11: // As if user secondary
1861 case 0x19: // As if user secondary LE
1862 case 0x4a: // UPA config
1863 case 0x81: // Secondary
1864 case 0x89: // Secondary LE
1872 env
->lsu
= val
& (DMMU_E
| IMMU_E
);
1873 // Mappings generated during D/I MMU disabled mode are
1874 // invalid in normal mode
1875 if (oldreg
!= env
->lsu
) {
1876 DPRINTF_MMU("LSU change: 0x%" PRIx64
" -> 0x%" PRIx64
"\n",
1885 case 0x50: // I-MMU regs
1887 int reg
= (addr
>> 3) & 0xf;
1890 oldreg
= env
->immuregs
[reg
];
1895 case 1: // Not in I-MMU
1902 val
= 0; // Clear SFSR
1904 case 5: // TSB access
1905 case 6: // Tag access
1909 env
->immuregs
[reg
] = val
;
1910 if (oldreg
!= env
->immuregs
[reg
]) {
1911 DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64
" -> 0x%08"
1912 PRIx64
"\n", reg
, oldreg
, env
->immuregs
[reg
]);
1919 case 0x54: // I-MMU data in
1923 // Try finding an invalid entry
1924 for (i
= 0; i
< 64; i
++) {
1925 if ((env
->itlb_tte
[i
] & 0x8000000000000000ULL
) == 0) {
1926 env
->itlb_tag
[i
] = env
->immuregs
[6];
1927 env
->itlb_tte
[i
] = val
;
1931 // Try finding an unlocked entry
1932 for (i
= 0; i
< 64; i
++) {
1933 if ((env
->itlb_tte
[i
] & 0x40) == 0) {
1934 env
->itlb_tag
[i
] = env
->immuregs
[6];
1935 env
->itlb_tte
[i
] = val
;
1942 case 0x55: // I-MMU data access
1946 unsigned int i
= (addr
>> 3) & 0x3f;
1948 env
->itlb_tag
[i
] = env
->immuregs
[6];
1949 env
->itlb_tte
[i
] = val
;
1952 case 0x57: // I-MMU demap
1956 for (i
= 0; i
< 64; i
++) {
1957 if ((env
->itlb_tte
[i
] & 0x8000000000000000ULL
) != 0) {
1958 target_ulong mask
= 0xffffffffffffe000ULL
;
1960 mask
<<= 3 * ((env
->itlb_tte
[i
] >> 61) & 3);
1961 if ((val
& mask
) == (env
->itlb_tag
[i
] & mask
)) {
1962 env
->itlb_tag
[i
] = 0;
1963 env
->itlb_tte
[i
] = 0;
1970 case 0x58: // D-MMU regs
1972 int reg
= (addr
>> 3) & 0xf;
1975 oldreg
= env
->dmmuregs
[reg
];
1981 if ((val
& 1) == 0) {
1982 val
= 0; // Clear SFSR, Fault address
1983 env
->dmmuregs
[4] = 0;
1985 env
->dmmuregs
[reg
] = val
;
1987 case 1: // Primary context
1988 case 2: // Secondary context
1989 case 5: // TSB access
1990 case 6: // Tag access
1991 case 7: // Virtual Watchpoint
1992 case 8: // Physical Watchpoint
1996 env
->dmmuregs
[reg
] = val
;
1997 if (oldreg
!= env
->dmmuregs
[reg
]) {
1998 DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64
" -> 0x%08"
1999 PRIx64
"\n", reg
, oldreg
, env
->dmmuregs
[reg
]);
2006 case 0x5c: // D-MMU data in
2010 // Try finding an invalid entry
2011 for (i
= 0; i
< 64; i
++) {
2012 if ((env
->dtlb_tte
[i
] & 0x8000000000000000ULL
) == 0) {
2013 env
->dtlb_tag
[i
] = env
->dmmuregs
[6];
2014 env
->dtlb_tte
[i
] = val
;
2018 // Try finding an unlocked entry
2019 for (i
= 0; i
< 64; i
++) {
2020 if ((env
->dtlb_tte
[i
] & 0x40) == 0) {
2021 env
->dtlb_tag
[i
] = env
->dmmuregs
[6];
2022 env
->dtlb_tte
[i
] = val
;
2029 case 0x5d: // D-MMU data access
2031 unsigned int i
= (addr
>> 3) & 0x3f;
2033 env
->dtlb_tag
[i
] = env
->dmmuregs
[6];
2034 env
->dtlb_tte
[i
] = val
;
2037 case 0x5f: // D-MMU demap
2041 for (i
= 0; i
< 64; i
++) {
2042 if ((env
->dtlb_tte
[i
] & 0x8000000000000000ULL
) != 0) {
2043 target_ulong mask
= 0xffffffffffffe000ULL
;
2045 mask
<<= 3 * ((env
->dtlb_tte
[i
] >> 61) & 3);
2046 if ((val
& mask
) == (env
->dtlb_tag
[i
] & mask
)) {
2047 env
->dtlb_tag
[i
] = 0;
2048 env
->dtlb_tte
[i
] = 0;
2055 case 0x49: // Interrupt data receive
2058 case 0x46: // D-cache data
2059 case 0x47: // D-cache tag access
2060 case 0x4b: // E-cache error enable
2061 case 0x4c: // E-cache asynchronous fault status
2062 case 0x4d: // E-cache asynchronous fault address
2063 case 0x4e: // E-cache tag data
2064 case 0x66: // I-cache instruction access
2065 case 0x67: // I-cache tag access
2066 case 0x6e: // I-cache predecode
2067 case 0x6f: // I-cache LRU etc.
2068 case 0x76: // E-cache tag
2069 case 0x7e: // E-cache tag
2071 case 0x51: // I-MMU 8k TSB pointer, RO
2072 case 0x52: // I-MMU 64k TSB pointer, RO
2073 case 0x56: // I-MMU tag read, RO
2074 case 0x59: // D-MMU 8k TSB pointer, RO
2075 case 0x5a: // D-MMU 64k TSB pointer, RO
2076 case 0x5b: // D-MMU data pointer, RO
2077 case 0x5e: // D-MMU tag read, RO
2078 case 0x48: // Interrupt dispatch, RO
2079 case 0x7f: // Incoming interrupt vector, RO
2080 case 0x82: // Primary no-fault, RO
2081 case 0x83: // Secondary no-fault, RO
2082 case 0x8a: // Primary no-fault LE, RO
2083 case 0x8b: // Secondary no-fault LE, RO
2085 do_unassigned_access(addr
, 1, 0, 1);
2089 #endif /* CONFIG_USER_ONLY */
2091 void helper_ldda_asi(target_ulong addr
, int asi
, int rd
)
2093 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
2094 || ((env
->def
->features
& CPU_FEATURE_HYPV
)
2095 && asi
>= 0x30 && asi
< 0x80
2096 && !(env
->hpstate
& HS_PRIV
)))
2097 raise_exception(TT_PRIV_ACT
);
2100 case 0x24: // Nucleus quad LDD 128 bit atomic
2101 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
2102 helper_check_align(addr
, 0xf);
2104 env
->gregs
[1] = ldq_kernel(addr
+ 8);
2106 bswap64s(&env
->gregs
[1]);
2107 } else if (rd
< 8) {
2108 env
->gregs
[rd
] = ldq_kernel(addr
);
2109 env
->gregs
[rd
+ 1] = ldq_kernel(addr
+ 8);
2111 bswap64s(&env
->gregs
[rd
]);
2112 bswap64s(&env
->gregs
[rd
+ 1]);
2115 env
->regwptr
[rd
] = ldq_kernel(addr
);
2116 env
->regwptr
[rd
+ 1] = ldq_kernel(addr
+ 8);
2118 bswap64s(&env
->regwptr
[rd
]);
2119 bswap64s(&env
->regwptr
[rd
+ 1]);
2124 helper_check_align(addr
, 0x3);
2126 env
->gregs
[1] = helper_ld_asi(addr
+ 4, asi
, 4, 0);
2128 env
->gregs
[rd
] = helper_ld_asi(addr
, asi
, 4, 0);
2129 env
->gregs
[rd
+ 1] = helper_ld_asi(addr
+ 4, asi
, 4, 0);
2131 env
->regwptr
[rd
] = helper_ld_asi(addr
, asi
, 4, 0);
2132 env
->regwptr
[rd
+ 1] = helper_ld_asi(addr
+ 4, asi
, 4, 0);
2138 void helper_ldf_asi(target_ulong addr
, int asi
, int size
, int rd
)
2143 helper_check_align(addr
, 3);
2145 case 0xf0: // Block load primary
2146 case 0xf1: // Block load secondary
2147 case 0xf8: // Block load primary LE
2148 case 0xf9: // Block load secondary LE
2150 raise_exception(TT_ILL_INSN
);
2153 helper_check_align(addr
, 0x3f);
2154 for (i
= 0; i
< 16; i
++) {
2155 *(uint32_t *)&env
->fpr
[rd
++] = helper_ld_asi(addr
, asi
& 0x8f, 4,
2165 val
= helper_ld_asi(addr
, asi
, size
, 0);
2169 *((uint32_t *)&env
->fpr
[rd
]) = val
;
2172 *((int64_t *)&DT0
) = val
;
2180 void helper_stf_asi(target_ulong addr
, int asi
, int size
, int rd
)
2183 target_ulong val
= 0;
2185 helper_check_align(addr
, 3);
2187 case 0xe0: // UA2007 Block commit store primary (cache flush)
2188 case 0xe1: // UA2007 Block commit store secondary (cache flush)
2189 case 0xf0: // Block store primary
2190 case 0xf1: // Block store secondary
2191 case 0xf8: // Block store primary LE
2192 case 0xf9: // Block store secondary LE
2194 raise_exception(TT_ILL_INSN
);
2197 helper_check_align(addr
, 0x3f);
2198 for (i
= 0; i
< 16; i
++) {
2199 val
= *(uint32_t *)&env
->fpr
[rd
++];
2200 helper_st_asi(addr
, val
, asi
& 0x8f, 4);
2212 val
= *((uint32_t *)&env
->fpr
[rd
]);
2215 val
= *((int64_t *)&DT0
);
2221 helper_st_asi(addr
, val
, asi
, size
);
2224 target_ulong
helper_cas_asi(target_ulong addr
, target_ulong val1
,
2225 target_ulong val2
, uint32_t asi
)
2229 val2
&= 0xffffffffUL
;
2230 ret
= helper_ld_asi(addr
, asi
, 4, 0);
2231 ret
&= 0xffffffffUL
;
2233 helper_st_asi(addr
, val1
& 0xffffffffUL
, asi
, 4);
2237 target_ulong
helper_casx_asi(target_ulong addr
, target_ulong val1
,
2238 target_ulong val2
, uint32_t asi
)
2242 ret
= helper_ld_asi(addr
, asi
, 8, 0);
2244 helper_st_asi(addr
, val1
, asi
, 8);
2247 #endif /* TARGET_SPARC64 */
2249 #ifndef TARGET_SPARC64
2250 void helper_rett(void)
2254 if (env
->psret
== 1)
2255 raise_exception(TT_ILL_INSN
);
2258 cwp
= cpu_cwp_inc(env
, env
->cwp
+ 1) ;
2259 if (env
->wim
& (1 << cwp
)) {
2260 raise_exception(TT_WIN_UNF
);
2263 env
->psrs
= env
->psrps
;
2267 target_ulong
helper_udiv(target_ulong a
, target_ulong b
)
2272 x0
= (a
& 0xffffffff) | ((int64_t) (env
->y
) << 32);
2276 raise_exception(TT_DIV_ZERO
);
2280 if (x0
> 0xffffffff) {
2289 target_ulong
helper_sdiv(target_ulong a
, target_ulong b
)
2294 x0
= (a
& 0xffffffff) | ((int64_t) (env
->y
) << 32);
2298 raise_exception(TT_DIV_ZERO
);
2302 if ((int32_t) x0
!= x0
) {
2304 return x0
< 0? 0x80000000: 0x7fffffff;
2311 void helper_stdf(target_ulong addr
, int mem_idx
)
2313 helper_check_align(addr
, 7);
2314 #if !defined(CONFIG_USER_ONLY)
2317 stfq_user(addr
, DT0
);
2320 stfq_kernel(addr
, DT0
);
2322 #ifdef TARGET_SPARC64
2324 stfq_hypv(addr
, DT0
);
2331 address_mask(env
, &addr
);
2332 stfq_raw(addr
, DT0
);
2336 void helper_lddf(target_ulong addr
, int mem_idx
)
2338 helper_check_align(addr
, 7);
2339 #if !defined(CONFIG_USER_ONLY)
2342 DT0
= ldfq_user(addr
);
2345 DT0
= ldfq_kernel(addr
);
2347 #ifdef TARGET_SPARC64
2349 DT0
= ldfq_hypv(addr
);
2356 address_mask(env
, &addr
);
2357 DT0
= ldfq_raw(addr
);
2361 void helper_ldqf(target_ulong addr
, int mem_idx
)
2363 // XXX add 128 bit load
2366 helper_check_align(addr
, 7);
2367 #if !defined(CONFIG_USER_ONLY)
2370 u
.ll
.upper
= ldq_user(addr
);
2371 u
.ll
.lower
= ldq_user(addr
+ 8);
2375 u
.ll
.upper
= ldq_kernel(addr
);
2376 u
.ll
.lower
= ldq_kernel(addr
+ 8);
2379 #ifdef TARGET_SPARC64
2381 u
.ll
.upper
= ldq_hypv(addr
);
2382 u
.ll
.lower
= ldq_hypv(addr
+ 8);
2390 address_mask(env
, &addr
);
2391 u
.ll
.upper
= ldq_raw(addr
);
2392 u
.ll
.lower
= ldq_raw((addr
+ 8) & 0xffffffffULL
);
2397 void helper_stqf(target_ulong addr
, int mem_idx
)
2399 // XXX add 128 bit store
2402 helper_check_align(addr
, 7);
2403 #if !defined(CONFIG_USER_ONLY)
2407 stq_user(addr
, u
.ll
.upper
);
2408 stq_user(addr
+ 8, u
.ll
.lower
);
2412 stq_kernel(addr
, u
.ll
.upper
);
2413 stq_kernel(addr
+ 8, u
.ll
.lower
);
2415 #ifdef TARGET_SPARC64
2418 stq_hypv(addr
, u
.ll
.upper
);
2419 stq_hypv(addr
+ 8, u
.ll
.lower
);
2427 address_mask(env
, &addr
);
2428 stq_raw(addr
, u
.ll
.upper
);
2429 stq_raw((addr
+ 8) & 0xffffffffULL
, u
.ll
.lower
);
2433 static inline void set_fsr(void)
2437 switch (env
->fsr
& FSR_RD_MASK
) {
2438 case FSR_RD_NEAREST
:
2439 rnd_mode
= float_round_nearest_even
;
2443 rnd_mode
= float_round_to_zero
;
2446 rnd_mode
= float_round_up
;
2449 rnd_mode
= float_round_down
;
2452 set_float_rounding_mode(rnd_mode
, &env
->fp_status
);
2455 void helper_ldfsr(uint32_t new_fsr
)
2457 env
->fsr
= (new_fsr
& FSR_LDFSR_MASK
) | (env
->fsr
& FSR_LDFSR_OLDMASK
);
2461 #ifdef TARGET_SPARC64
2462 void helper_ldxfsr(uint64_t new_fsr
)
2464 env
->fsr
= (new_fsr
& FSR_LDXFSR_MASK
) | (env
->fsr
& FSR_LDXFSR_OLDMASK
);
2469 void helper_debug(void)
2471 env
->exception_index
= EXCP_DEBUG
;
2475 #ifndef TARGET_SPARC64
2476 /* XXX: use another pointer for %iN registers to avoid slow wrapping
2478 void helper_save(void)
2482 cwp
= cpu_cwp_dec(env
, env
->cwp
- 1);
2483 if (env
->wim
& (1 << cwp
)) {
2484 raise_exception(TT_WIN_OVF
);
2489 void helper_restore(void)
2493 cwp
= cpu_cwp_inc(env
, env
->cwp
+ 1);
2494 if (env
->wim
& (1 << cwp
)) {
2495 raise_exception(TT_WIN_UNF
);
2500 void helper_wrpsr(target_ulong new_psr
)
2502 if ((new_psr
& PSR_CWP
) >= env
->nwindows
)
2503 raise_exception(TT_ILL_INSN
);
2505 PUT_PSR(env
, new_psr
);
2508 target_ulong
helper_rdpsr(void)
2510 return GET_PSR(env
);
2514 /* XXX: use another pointer for %iN registers to avoid slow wrapping
2516 void helper_save(void)
2520 cwp
= cpu_cwp_dec(env
, env
->cwp
- 1);
2521 if (env
->cansave
== 0) {
2522 raise_exception(TT_SPILL
| (env
->otherwin
!= 0 ?
2523 (TT_WOTHER
| ((env
->wstate
& 0x38) >> 1)):
2524 ((env
->wstate
& 0x7) << 2)));
2526 if (env
->cleanwin
- env
->canrestore
== 0) {
2527 // XXX Clean windows without trap
2528 raise_exception(TT_CLRWIN
);
2537 void helper_restore(void)
2541 cwp
= cpu_cwp_inc(env
, env
->cwp
+ 1);
2542 if (env
->canrestore
== 0) {
2543 raise_exception(TT_FILL
| (env
->otherwin
!= 0 ?
2544 (TT_WOTHER
| ((env
->wstate
& 0x38) >> 1)):
2545 ((env
->wstate
& 0x7) << 2)));
2553 void helper_flushw(void)
2555 if (env
->cansave
!= env
->nwindows
- 2) {
2556 raise_exception(TT_SPILL
| (env
->otherwin
!= 0 ?
2557 (TT_WOTHER
| ((env
->wstate
& 0x38) >> 1)):
2558 ((env
->wstate
& 0x7) << 2)));
2562 void helper_saved(void)
2565 if (env
->otherwin
== 0)
2571 void helper_restored(void)
2574 if (env
->cleanwin
< env
->nwindows
- 1)
2576 if (env
->otherwin
== 0)
2582 target_ulong
helper_rdccr(void)
2584 return GET_CCR(env
);
2587 void helper_wrccr(target_ulong new_ccr
)
2589 PUT_CCR(env
, new_ccr
);
2592 // CWP handling is reversed in V9, but we still use the V8 register
2594 target_ulong
helper_rdcwp(void)
2596 return GET_CWP64(env
);
2599 void helper_wrcwp(target_ulong new_cwp
)
2601 PUT_CWP64(env
, new_cwp
);
2604 // This function uses non-native bit order
2605 #define GET_FIELD(X, FROM, TO) \
2606 ((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1))
2608 // This function uses the order in the manuals, i.e. bit 0 is 2^0
2609 #define GET_FIELD_SP(X, FROM, TO) \
2610 GET_FIELD(X, 63 - (TO), 63 - (FROM))
2612 target_ulong
helper_array8(target_ulong pixel_addr
, target_ulong cubesize
)
2614 return (GET_FIELD_SP(pixel_addr
, 60, 63) << (17 + 2 * cubesize
)) |
2615 (GET_FIELD_SP(pixel_addr
, 39, 39 + cubesize
- 1) << (17 + cubesize
)) |
2616 (GET_FIELD_SP(pixel_addr
, 17 + cubesize
- 1, 17) << 17) |
2617 (GET_FIELD_SP(pixel_addr
, 56, 59) << 13) |
2618 (GET_FIELD_SP(pixel_addr
, 35, 38) << 9) |
2619 (GET_FIELD_SP(pixel_addr
, 13, 16) << 5) |
2620 (((pixel_addr
>> 55) & 1) << 4) |
2621 (GET_FIELD_SP(pixel_addr
, 33, 34) << 2) |
2622 GET_FIELD_SP(pixel_addr
, 11, 12);
2625 target_ulong
helper_alignaddr(target_ulong addr
, target_ulong offset
)
2629 tmp
= addr
+ offset
;
2631 env
->gsr
|= tmp
& 7ULL;
2635 target_ulong
helper_popc(target_ulong val
)
2637 return ctpop64(val
);
2640 static inline uint64_t *get_gregset(uint64_t pstate
)
2655 static inline void change_pstate(uint64_t new_pstate
)
2657 uint64_t pstate_regs
, new_pstate_regs
;
2658 uint64_t *src
, *dst
;
2660 pstate_regs
= env
->pstate
& 0xc01;
2661 new_pstate_regs
= new_pstate
& 0xc01;
2662 if (new_pstate_regs
!= pstate_regs
) {
2663 // Switch global register bank
2664 src
= get_gregset(new_pstate_regs
);
2665 dst
= get_gregset(pstate_regs
);
2666 memcpy32(dst
, env
->gregs
);
2667 memcpy32(env
->gregs
, src
);
2669 env
->pstate
= new_pstate
;
2672 void helper_wrpstate(target_ulong new_state
)
2674 if (!(env
->def
->features
& CPU_FEATURE_GL
))
2675 change_pstate(new_state
& 0xf3f);
2678 void helper_done(void)
2680 env
->pc
= env
->tsptr
->tpc
;
2681 env
->npc
= env
->tsptr
->tnpc
+ 4;
2682 PUT_CCR(env
, env
->tsptr
->tstate
>> 32);
2683 env
->asi
= (env
->tsptr
->tstate
>> 24) & 0xff;
2684 change_pstate((env
->tsptr
->tstate
>> 8) & 0xf3f);
2685 PUT_CWP64(env
, env
->tsptr
->tstate
& 0xff);
2687 env
->tsptr
= &env
->ts
[env
->tl
& MAXTL_MASK
];
2690 void helper_retry(void)
2692 env
->pc
= env
->tsptr
->tpc
;
2693 env
->npc
= env
->tsptr
->tnpc
;
2694 PUT_CCR(env
, env
->tsptr
->tstate
>> 32);
2695 env
->asi
= (env
->tsptr
->tstate
>> 24) & 0xff;
2696 change_pstate((env
->tsptr
->tstate
>> 8) & 0xf3f);
2697 PUT_CWP64(env
, env
->tsptr
->tstate
& 0xff);
2699 env
->tsptr
= &env
->ts
[env
->tl
& MAXTL_MASK
];
2702 void helper_set_softint(uint64_t value
)
2704 env
->softint
|= (uint32_t)value
;
2707 void helper_clear_softint(uint64_t value
)
2709 env
->softint
&= (uint32_t)~value
;
2712 void helper_write_softint(uint64_t value
)
2714 env
->softint
= (uint32_t)value
;
2718 void helper_flush(target_ulong addr
)
2721 tb_invalidate_page_range(addr
, addr
+ 8);
2724 #ifdef TARGET_SPARC64
2726 static const char * const excp_names
[0x80] = {
2727 [TT_TFAULT
] = "Instruction Access Fault",
2728 [TT_TMISS
] = "Instruction Access MMU Miss",
2729 [TT_CODE_ACCESS
] = "Instruction Access Error",
2730 [TT_ILL_INSN
] = "Illegal Instruction",
2731 [TT_PRIV_INSN
] = "Privileged Instruction",
2732 [TT_NFPU_INSN
] = "FPU Disabled",
2733 [TT_FP_EXCP
] = "FPU Exception",
2734 [TT_TOVF
] = "Tag Overflow",
2735 [TT_CLRWIN
] = "Clean Windows",
2736 [TT_DIV_ZERO
] = "Division By Zero",
2737 [TT_DFAULT
] = "Data Access Fault",
2738 [TT_DMISS
] = "Data Access MMU Miss",
2739 [TT_DATA_ACCESS
] = "Data Access Error",
2740 [TT_DPROT
] = "Data Protection Error",
2741 [TT_UNALIGNED
] = "Unaligned Memory Access",
2742 [TT_PRIV_ACT
] = "Privileged Action",
2743 [TT_EXTINT
| 0x1] = "External Interrupt 1",
2744 [TT_EXTINT
| 0x2] = "External Interrupt 2",
2745 [TT_EXTINT
| 0x3] = "External Interrupt 3",
2746 [TT_EXTINT
| 0x4] = "External Interrupt 4",
2747 [TT_EXTINT
| 0x5] = "External Interrupt 5",
2748 [TT_EXTINT
| 0x6] = "External Interrupt 6",
2749 [TT_EXTINT
| 0x7] = "External Interrupt 7",
2750 [TT_EXTINT
| 0x8] = "External Interrupt 8",
2751 [TT_EXTINT
| 0x9] = "External Interrupt 9",
2752 [TT_EXTINT
| 0xa] = "External Interrupt 10",
2753 [TT_EXTINT
| 0xb] = "External Interrupt 11",
2754 [TT_EXTINT
| 0xc] = "External Interrupt 12",
2755 [TT_EXTINT
| 0xd] = "External Interrupt 13",
2756 [TT_EXTINT
| 0xe] = "External Interrupt 14",
2757 [TT_EXTINT
| 0xf] = "External Interrupt 15",
2761 void do_interrupt(CPUState
*env
)
2763 int intno
= env
->exception_index
;
2766 if (loglevel
& CPU_LOG_INT
) {
2770 if (intno
< 0 || intno
>= 0x180)
2772 else if (intno
>= 0x100)
2773 name
= "Trap Instruction";
2774 else if (intno
>= 0xc0)
2775 name
= "Window Fill";
2776 else if (intno
>= 0x80)
2777 name
= "Window Spill";
2779 name
= excp_names
[intno
];
2784 fprintf(logfile
, "%6d: %s (v=%04x) pc=%016" PRIx64
" npc=%016" PRIx64
2785 " SP=%016" PRIx64
"\n",
2788 env
->npc
, env
->regwptr
[6]);
2789 cpu_dump_state(env
, logfile
, fprintf
, 0);
2795 fprintf(logfile
, " code=");
2796 ptr
= (uint8_t *)env
->pc
;
2797 for(i
= 0; i
< 16; i
++) {
2798 fprintf(logfile
, " %02x", ldub(ptr
+ i
));
2800 fprintf(logfile
, "\n");
2806 #if !defined(CONFIG_USER_ONLY)
2807 if (env
->tl
>= env
->maxtl
) {
2808 cpu_abort(env
, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
2809 " Error state", env
->exception_index
, env
->tl
, env
->maxtl
);
2813 if (env
->tl
< env
->maxtl
- 1) {
2816 env
->pstate
|= PS_RED
;
2817 if (env
->tl
< env
->maxtl
)
2820 env
->tsptr
= &env
->ts
[env
->tl
& MAXTL_MASK
];
2821 env
->tsptr
->tstate
= ((uint64_t)GET_CCR(env
) << 32) |
2822 ((env
->asi
& 0xff) << 24) | ((env
->pstate
& 0xf3f) << 8) |
2824 env
->tsptr
->tpc
= env
->pc
;
2825 env
->tsptr
->tnpc
= env
->npc
;
2826 env
->tsptr
->tt
= intno
;
2827 if (!(env
->def
->features
& CPU_FEATURE_GL
)) {
2830 change_pstate(PS_PEF
| PS_PRIV
| PS_IG
);
2837 change_pstate(PS_PEF
| PS_PRIV
| PS_MG
);
2840 change_pstate(PS_PEF
| PS_PRIV
| PS_AG
);
2844 if (intno
== TT_CLRWIN
)
2845 cpu_set_cwp(env
, cpu_cwp_dec(env
, env
->cwp
- 1));
2846 else if ((intno
& 0x1c0) == TT_SPILL
)
2847 cpu_set_cwp(env
, cpu_cwp_dec(env
, env
->cwp
- env
->cansave
- 2));
2848 else if ((intno
& 0x1c0) == TT_FILL
)
2849 cpu_set_cwp(env
, cpu_cwp_inc(env
, env
->cwp
+ 1));
2850 env
->tbr
&= ~0x7fffULL
;
2851 env
->tbr
|= ((env
->tl
> 1) ? 1 << 14 : 0) | (intno
<< 5);
2853 env
->npc
= env
->pc
+ 4;
2854 env
->exception_index
= 0;
2858 static const char * const excp_names
[0x80] = {
2859 [TT_TFAULT
] = "Instruction Access Fault",
2860 [TT_ILL_INSN
] = "Illegal Instruction",
2861 [TT_PRIV_INSN
] = "Privileged Instruction",
2862 [TT_NFPU_INSN
] = "FPU Disabled",
2863 [TT_WIN_OVF
] = "Window Overflow",
2864 [TT_WIN_UNF
] = "Window Underflow",
2865 [TT_UNALIGNED
] = "Unaligned Memory Access",
2866 [TT_FP_EXCP
] = "FPU Exception",
2867 [TT_DFAULT
] = "Data Access Fault",
2868 [TT_TOVF
] = "Tag Overflow",
2869 [TT_EXTINT
| 0x1] = "External Interrupt 1",
2870 [TT_EXTINT
| 0x2] = "External Interrupt 2",
2871 [TT_EXTINT
| 0x3] = "External Interrupt 3",
2872 [TT_EXTINT
| 0x4] = "External Interrupt 4",
2873 [TT_EXTINT
| 0x5] = "External Interrupt 5",
2874 [TT_EXTINT
| 0x6] = "External Interrupt 6",
2875 [TT_EXTINT
| 0x7] = "External Interrupt 7",
2876 [TT_EXTINT
| 0x8] = "External Interrupt 8",
2877 [TT_EXTINT
| 0x9] = "External Interrupt 9",
2878 [TT_EXTINT
| 0xa] = "External Interrupt 10",
2879 [TT_EXTINT
| 0xb] = "External Interrupt 11",
2880 [TT_EXTINT
| 0xc] = "External Interrupt 12",
2881 [TT_EXTINT
| 0xd] = "External Interrupt 13",
2882 [TT_EXTINT
| 0xe] = "External Interrupt 14",
2883 [TT_EXTINT
| 0xf] = "External Interrupt 15",
2884 [TT_TOVF
] = "Tag Overflow",
2885 [TT_CODE_ACCESS
] = "Instruction Access Error",
2886 [TT_DATA_ACCESS
] = "Data Access Error",
2887 [TT_DIV_ZERO
] = "Division By Zero",
2888 [TT_NCP_INSN
] = "Coprocessor Disabled",
2892 void do_interrupt(CPUState
*env
)
2894 int cwp
, intno
= env
->exception_index
;
2897 if (loglevel
& CPU_LOG_INT
) {
2901 if (intno
< 0 || intno
>= 0x100)
2903 else if (intno
>= 0x80)
2904 name
= "Trap Instruction";
2906 name
= excp_names
[intno
];
2911 fprintf(logfile
, "%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
2914 env
->npc
, env
->regwptr
[6]);
2915 cpu_dump_state(env
, logfile
, fprintf
, 0);
2921 fprintf(logfile
, " code=");
2922 ptr
= (uint8_t *)env
->pc
;
2923 for(i
= 0; i
< 16; i
++) {
2924 fprintf(logfile
, " %02x", ldub(ptr
+ i
));
2926 fprintf(logfile
, "\n");
2932 #if !defined(CONFIG_USER_ONLY)
2933 if (env
->psret
== 0) {
2934 cpu_abort(env
, "Trap 0x%02x while interrupts disabled, Error state",
2935 env
->exception_index
);
2940 cwp
= cpu_cwp_dec(env
, env
->cwp
- 1);
2941 cpu_set_cwp(env
, cwp
);
2942 env
->regwptr
[9] = env
->pc
;
2943 env
->regwptr
[10] = env
->npc
;
2944 env
->psrps
= env
->psrs
;
2946 env
->tbr
= (env
->tbr
& TBR_BASE_MASK
) | (intno
<< 4);
2948 env
->npc
= env
->pc
+ 4;
2949 env
->exception_index
= 0;
2953 #if !defined(CONFIG_USER_ONLY)
2955 static void do_unaligned_access(target_ulong addr
, int is_write
, int is_user
,
2958 #define MMUSUFFIX _mmu
2959 #define ALIGNED_ONLY
2962 #include "softmmu_template.h"
2965 #include "softmmu_template.h"
2968 #include "softmmu_template.h"
2971 #include "softmmu_template.h"
2973 /* XXX: make it generic ? */
2974 static void cpu_restore_state2(void *retaddr
)
2976 TranslationBlock
*tb
;
2980 /* now we have a real cpu fault */
2981 pc
= (unsigned long)retaddr
;
2982 tb
= tb_find_pc(pc
);
2984 /* the PC is inside the translated code. It means that we have
2985 a virtual CPU fault */
2986 cpu_restore_state(tb
, env
, pc
, (void *)(long)env
->cond
);
2991 static void do_unaligned_access(target_ulong addr
, int is_write
, int is_user
,
2994 #ifdef DEBUG_UNALIGNED
2995 printf("Unaligned access to 0x" TARGET_FMT_lx
" from 0x" TARGET_FMT_lx
2996 "\n", addr
, env
->pc
);
2998 cpu_restore_state2(retaddr
);
2999 raise_exception(TT_UNALIGNED
);
3002 /* try to fill the TLB and return an exception if error. If retaddr is
3003 NULL, it means that the function was called in C code (i.e. not
3004 from generated code or from helper.c) */
3005 /* XXX: fix it to restore all registers */
3006 void tlb_fill(target_ulong addr
, int is_write
, int mmu_idx
, void *retaddr
)
3009 CPUState
*saved_env
;
3011 /* XXX: hack to restore env in all cases, even if not called from
3014 env
= cpu_single_env
;
3016 ret
= cpu_sparc_handle_mmu_fault(env
, addr
, is_write
, mmu_idx
, 1);
3018 cpu_restore_state2(retaddr
);
3026 #ifndef TARGET_SPARC64
3027 void do_unassigned_access(target_phys_addr_t addr
, int is_write
, int is_exec
,
3030 CPUState
*saved_env
;
3032 /* XXX: hack to restore env in all cases, even if not called from
3035 env
= cpu_single_env
;
3036 #ifdef DEBUG_UNASSIGNED
3038 printf("Unassigned mem %s access to " TARGET_FMT_plx
3039 " asi 0x%02x from " TARGET_FMT_lx
"\n",
3040 is_exec
? "exec" : is_write
? "write" : "read", addr
, is_asi
,
3043 printf("Unassigned mem %s access to " TARGET_FMT_plx
" from "
3045 is_exec
? "exec" : is_write
? "write" : "read", addr
, env
->pc
);
3047 if (env
->mmuregs
[3]) /* Fault status register */
3048 env
->mmuregs
[3] = 1; /* overflow (not read before another fault) */
3050 env
->mmuregs
[3] |= 1 << 16;
3052 env
->mmuregs
[3] |= 1 << 5;
3054 env
->mmuregs
[3] |= 1 << 6;
3056 env
->mmuregs
[3] |= 1 << 7;
3057 env
->mmuregs
[3] |= (5 << 2) | 2;
3058 env
->mmuregs
[4] = addr
; /* Fault address register */
3059 if ((env
->mmuregs
[0] & MMU_E
) && !(env
->mmuregs
[0] & MMU_NF
)) {
3061 raise_exception(TT_CODE_ACCESS
);
3063 raise_exception(TT_DATA_ACCESS
);
3068 void do_unassigned_access(target_phys_addr_t addr
, int is_write
, int is_exec
,
3071 #ifdef DEBUG_UNASSIGNED
3072 CPUState
*saved_env
;
3074 /* XXX: hack to restore env in all cases, even if not called from
3077 env
= cpu_single_env
;
3078 printf("Unassigned mem access to " TARGET_FMT_plx
" from " TARGET_FMT_lx
3079 "\n", addr
, env
->pc
);
3083 raise_exception(TT_CODE_ACCESS
);
3085 raise_exception(TT_DATA_ACCESS
);