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1 /*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5 Copyright (C) 2003 Fabrice Bellard
6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
16
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22 /*
23 TODO-list:
24
25 NPC/PC static optimisations (use JUMP_TB when possible)
26 FPU-Instructions
27 Privileged instructions
28 Coprocessor-Instructions
29 Optimize synthetic instructions
30 Optional alignment and privileged instruction check
31 */
32
33 #include <stdarg.h>
34 #include <stdlib.h>
35 #include <stdio.h>
36 #include <string.h>
37 #include <inttypes.h>
38
39 #include "cpu.h"
40 #include "exec-all.h"
41 #include "disas.h"
42
43 #define DEBUG_DISAS
44
45 #define DYNAMIC_PC 1 /* dynamic pc value */
46 #define JUMP_PC 2 /* dynamic pc value which takes only two values
47 according to jump_pc[T2] */
48
49 typedef struct DisasContext {
50 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
51 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
52 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
53 int is_br;
54 int mem_idx;
55 struct TranslationBlock *tb;
56 } DisasContext;
57
58 static uint16_t *gen_opc_ptr;
59 static uint32_t *gen_opparam_ptr;
60 extern FILE *logfile;
61 extern int loglevel;
62
63 enum {
64 #define DEF(s,n,copy_size) INDEX_op_ ## s,
65 #include "opc.h"
66 #undef DEF
67 NB_OPS
68 };
69
70 #include "gen-op.h"
71
72 #define GET_FIELD(X, FROM, TO) \
73 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
74
75 #define IS_IMM (insn & (1<<13))
76
77 static void disas_sparc_insn(DisasContext * dc);
78
79 static GenOpFunc *gen_op_movl_TN_reg[2][32] = {
80 {
81 gen_op_movl_g0_T0,
82 gen_op_movl_g1_T0,
83 gen_op_movl_g2_T0,
84 gen_op_movl_g3_T0,
85 gen_op_movl_g4_T0,
86 gen_op_movl_g5_T0,
87 gen_op_movl_g6_T0,
88 gen_op_movl_g7_T0,
89 gen_op_movl_o0_T0,
90 gen_op_movl_o1_T0,
91 gen_op_movl_o2_T0,
92 gen_op_movl_o3_T0,
93 gen_op_movl_o4_T0,
94 gen_op_movl_o5_T0,
95 gen_op_movl_o6_T0,
96 gen_op_movl_o7_T0,
97 gen_op_movl_l0_T0,
98 gen_op_movl_l1_T0,
99 gen_op_movl_l2_T0,
100 gen_op_movl_l3_T0,
101 gen_op_movl_l4_T0,
102 gen_op_movl_l5_T0,
103 gen_op_movl_l6_T0,
104 gen_op_movl_l7_T0,
105 gen_op_movl_i0_T0,
106 gen_op_movl_i1_T0,
107 gen_op_movl_i2_T0,
108 gen_op_movl_i3_T0,
109 gen_op_movl_i4_T0,
110 gen_op_movl_i5_T0,
111 gen_op_movl_i6_T0,
112 gen_op_movl_i7_T0,
113 },
114 {
115 gen_op_movl_g0_T1,
116 gen_op_movl_g1_T1,
117 gen_op_movl_g2_T1,
118 gen_op_movl_g3_T1,
119 gen_op_movl_g4_T1,
120 gen_op_movl_g5_T1,
121 gen_op_movl_g6_T1,
122 gen_op_movl_g7_T1,
123 gen_op_movl_o0_T1,
124 gen_op_movl_o1_T1,
125 gen_op_movl_o2_T1,
126 gen_op_movl_o3_T1,
127 gen_op_movl_o4_T1,
128 gen_op_movl_o5_T1,
129 gen_op_movl_o6_T1,
130 gen_op_movl_o7_T1,
131 gen_op_movl_l0_T1,
132 gen_op_movl_l1_T1,
133 gen_op_movl_l2_T1,
134 gen_op_movl_l3_T1,
135 gen_op_movl_l4_T1,
136 gen_op_movl_l5_T1,
137 gen_op_movl_l6_T1,
138 gen_op_movl_l7_T1,
139 gen_op_movl_i0_T1,
140 gen_op_movl_i1_T1,
141 gen_op_movl_i2_T1,
142 gen_op_movl_i3_T1,
143 gen_op_movl_i4_T1,
144 gen_op_movl_i5_T1,
145 gen_op_movl_i6_T1,
146 gen_op_movl_i7_T1,
147 }
148 };
149
150 static GenOpFunc *gen_op_movl_reg_TN[3][32] = {
151 {
152 gen_op_movl_T0_g0,
153 gen_op_movl_T0_g1,
154 gen_op_movl_T0_g2,
155 gen_op_movl_T0_g3,
156 gen_op_movl_T0_g4,
157 gen_op_movl_T0_g5,
158 gen_op_movl_T0_g6,
159 gen_op_movl_T0_g7,
160 gen_op_movl_T0_o0,
161 gen_op_movl_T0_o1,
162 gen_op_movl_T0_o2,
163 gen_op_movl_T0_o3,
164 gen_op_movl_T0_o4,
165 gen_op_movl_T0_o5,
166 gen_op_movl_T0_o6,
167 gen_op_movl_T0_o7,
168 gen_op_movl_T0_l0,
169 gen_op_movl_T0_l1,
170 gen_op_movl_T0_l2,
171 gen_op_movl_T0_l3,
172 gen_op_movl_T0_l4,
173 gen_op_movl_T0_l5,
174 gen_op_movl_T0_l6,
175 gen_op_movl_T0_l7,
176 gen_op_movl_T0_i0,
177 gen_op_movl_T0_i1,
178 gen_op_movl_T0_i2,
179 gen_op_movl_T0_i3,
180 gen_op_movl_T0_i4,
181 gen_op_movl_T0_i5,
182 gen_op_movl_T0_i6,
183 gen_op_movl_T0_i7,
184 },
185 {
186 gen_op_movl_T1_g0,
187 gen_op_movl_T1_g1,
188 gen_op_movl_T1_g2,
189 gen_op_movl_T1_g3,
190 gen_op_movl_T1_g4,
191 gen_op_movl_T1_g5,
192 gen_op_movl_T1_g6,
193 gen_op_movl_T1_g7,
194 gen_op_movl_T1_o0,
195 gen_op_movl_T1_o1,
196 gen_op_movl_T1_o2,
197 gen_op_movl_T1_o3,
198 gen_op_movl_T1_o4,
199 gen_op_movl_T1_o5,
200 gen_op_movl_T1_o6,
201 gen_op_movl_T1_o7,
202 gen_op_movl_T1_l0,
203 gen_op_movl_T1_l1,
204 gen_op_movl_T1_l2,
205 gen_op_movl_T1_l3,
206 gen_op_movl_T1_l4,
207 gen_op_movl_T1_l5,
208 gen_op_movl_T1_l6,
209 gen_op_movl_T1_l7,
210 gen_op_movl_T1_i0,
211 gen_op_movl_T1_i1,
212 gen_op_movl_T1_i2,
213 gen_op_movl_T1_i3,
214 gen_op_movl_T1_i4,
215 gen_op_movl_T1_i5,
216 gen_op_movl_T1_i6,
217 gen_op_movl_T1_i7,
218 },
219 {
220 gen_op_movl_T2_g0,
221 gen_op_movl_T2_g1,
222 gen_op_movl_T2_g2,
223 gen_op_movl_T2_g3,
224 gen_op_movl_T2_g4,
225 gen_op_movl_T2_g5,
226 gen_op_movl_T2_g6,
227 gen_op_movl_T2_g7,
228 gen_op_movl_T2_o0,
229 gen_op_movl_T2_o1,
230 gen_op_movl_T2_o2,
231 gen_op_movl_T2_o3,
232 gen_op_movl_T2_o4,
233 gen_op_movl_T2_o5,
234 gen_op_movl_T2_o6,
235 gen_op_movl_T2_o7,
236 gen_op_movl_T2_l0,
237 gen_op_movl_T2_l1,
238 gen_op_movl_T2_l2,
239 gen_op_movl_T2_l3,
240 gen_op_movl_T2_l4,
241 gen_op_movl_T2_l5,
242 gen_op_movl_T2_l6,
243 gen_op_movl_T2_l7,
244 gen_op_movl_T2_i0,
245 gen_op_movl_T2_i1,
246 gen_op_movl_T2_i2,
247 gen_op_movl_T2_i3,
248 gen_op_movl_T2_i4,
249 gen_op_movl_T2_i5,
250 gen_op_movl_T2_i6,
251 gen_op_movl_T2_i7,
252 }
253 };
254
255 static GenOpFunc1 *gen_op_movl_TN_im[3] = {
256 gen_op_movl_T0_im,
257 gen_op_movl_T1_im,
258 gen_op_movl_T2_im
259 };
260
261 #define GEN32(func, NAME) \
262 static GenOpFunc *NAME ## _table [32] = { \
263 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
264 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
265 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
266 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
267 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
268 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
269 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
270 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
271 }; \
272 static inline void func(int n) \
273 { \
274 NAME ## _table[n](); \
275 }
276
277 /* floating point registers moves */
278 GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fprf);
279 GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fprf);
280 GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fprf);
281 GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fprf);
282 GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fprf);
283 GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fprf);
284
285 GEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fprf);
286 GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf);
287 GEN32(gen_op_load_fpr_DT2, gen_op_load_fpr_DT2_fprf);
288 GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf);
289 GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
290 GEN32(gen_op_store_DT2_fpr, gen_op_store_DT2_fpr_fprf);
291
292 #if defined(CONFIG_USER_ONLY)
293 #define gen_op_ldst(name) gen_op_##name##_raw()
294 #define OP_LD_TABLE(width) \
295 static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
296 { \
297 }
298 #define supervisor(dc) 0
299 #else
300 #define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
301 #define OP_LD_TABLE(width) \
302 static GenOpFunc *gen_op_##width[] = { \
303 &gen_op_##width##_user, \
304 &gen_op_##width##_kernel, \
305 }; \
306 \
307 static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
308 { \
309 int asi; \
310 \
311 asi = GET_FIELD(insn, 19, 26); \
312 switch (asi) { \
313 case 10: /* User data access */ \
314 gen_op_##width##_user(); \
315 break; \
316 case 11: /* Supervisor data access */ \
317 gen_op_##width##_kernel(); \
318 break; \
319 case 0x20 ... 0x2f: /* MMU passthrough */ \
320 if (is_ld) \
321 gen_op_ld_asi(asi, size, sign); \
322 else \
323 gen_op_st_asi(asi, size, sign); \
324 break; \
325 default: \
326 if (is_ld) \
327 gen_op_ld_asi(asi, size, sign); \
328 else \
329 gen_op_st_asi(asi, size, sign); \
330 break; \
331 } \
332 }
333
334 #define supervisor(dc) (dc->mem_idx == 1)
335 #endif
336
337 OP_LD_TABLE(ld);
338 OP_LD_TABLE(st);
339 OP_LD_TABLE(ldub);
340 OP_LD_TABLE(lduh);
341 OP_LD_TABLE(ldsb);
342 OP_LD_TABLE(ldsh);
343 OP_LD_TABLE(stb);
344 OP_LD_TABLE(sth);
345 OP_LD_TABLE(std);
346 OP_LD_TABLE(ldstub);
347 OP_LD_TABLE(swap);
348 OP_LD_TABLE(ldd);
349 OP_LD_TABLE(stf);
350 OP_LD_TABLE(stdf);
351 OP_LD_TABLE(ldf);
352 OP_LD_TABLE(lddf);
353
354 static inline void gen_movl_imm_TN(int reg, int imm)
355 {
356 gen_op_movl_TN_im[reg] (imm);
357 }
358
359 static inline void gen_movl_imm_T1(int val)
360 {
361 gen_movl_imm_TN(1, val);
362 }
363
364 static inline void gen_movl_imm_T0(int val)
365 {
366 gen_movl_imm_TN(0, val);
367 }
368
369 static inline void gen_movl_reg_TN(int reg, int t)
370 {
371 if (reg)
372 gen_op_movl_reg_TN[t][reg] ();
373 else
374 gen_movl_imm_TN(t, 0);
375 }
376
377 static inline void gen_movl_reg_T0(int reg)
378 {
379 gen_movl_reg_TN(reg, 0);
380 }
381
382 static inline void gen_movl_reg_T1(int reg)
383 {
384 gen_movl_reg_TN(reg, 1);
385 }
386
387 static inline void gen_movl_reg_T2(int reg)
388 {
389 gen_movl_reg_TN(reg, 2);
390 }
391
392 static inline void gen_movl_TN_reg(int reg, int t)
393 {
394 if (reg)
395 gen_op_movl_TN_reg[t][reg] ();
396 }
397
398 static inline void gen_movl_T0_reg(int reg)
399 {
400 gen_movl_TN_reg(reg, 0);
401 }
402
403 static inline void gen_movl_T1_reg(int reg)
404 {
405 gen_movl_TN_reg(reg, 1);
406 }
407
408 /* call this function before using T2 as it may have been set for a jump */
409 static inline void flush_T2(DisasContext * dc)
410 {
411 if (dc->npc == JUMP_PC) {
412 gen_op_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
413 dc->npc = DYNAMIC_PC;
414 }
415 }
416
417 static inline void save_npc(DisasContext * dc)
418 {
419 if (dc->npc == JUMP_PC) {
420 gen_op_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
421 dc->npc = DYNAMIC_PC;
422 } else if (dc->npc != DYNAMIC_PC) {
423 gen_op_movl_npc_im(dc->npc);
424 }
425 }
426
427 static inline void save_state(DisasContext * dc)
428 {
429 gen_op_jmp_im((uint32_t)dc->pc);
430 save_npc(dc);
431 }
432
433 static void gen_cond(int cond)
434 {
435 switch (cond) {
436 case 0x0:
437 gen_op_movl_T2_0();
438 break;
439 case 0x1:
440 gen_op_eval_be();
441 break;
442 case 0x2:
443 gen_op_eval_ble();
444 break;
445 case 0x3:
446 gen_op_eval_bl();
447 break;
448 case 0x4:
449 gen_op_eval_bleu();
450 break;
451 case 0x5:
452 gen_op_eval_bcs();
453 break;
454 case 0x6:
455 gen_op_eval_bneg();
456 break;
457 case 0x7:
458 gen_op_eval_bvs();
459 break;
460 case 0x8:
461 gen_op_movl_T2_1();
462 break;
463 case 0x9:
464 gen_op_eval_bne();
465 break;
466 case 0xa:
467 gen_op_eval_bg();
468 break;
469 case 0xb:
470 gen_op_eval_bge();
471 break;
472 case 0xc:
473 gen_op_eval_bgu();
474 break;
475 case 0xd:
476 gen_op_eval_bcc();
477 break;
478 case 0xe:
479 gen_op_eval_bpos();
480 break;
481 default:
482 case 0xf:
483 gen_op_eval_bvc();
484 break;
485 }
486 }
487
488 static void gen_fcond(int cond)
489 {
490 switch (cond) {
491 case 0x0:
492 gen_op_movl_T2_0();
493 break;
494 case 0x1:
495 gen_op_eval_fbne();
496 break;
497 case 0x2:
498 gen_op_eval_fblg();
499 break;
500 case 0x3:
501 gen_op_eval_fbul();
502 break;
503 case 0x4:
504 gen_op_eval_fbl();
505 break;
506 case 0x5:
507 gen_op_eval_fbug();
508 break;
509 case 0x6:
510 gen_op_eval_fbg();
511 break;
512 case 0x7:
513 gen_op_eval_fbu();
514 break;
515 case 0x8:
516 gen_op_movl_T2_1();
517 break;
518 case 0x9:
519 gen_op_eval_fbe();
520 break;
521 case 0xa:
522 gen_op_eval_fbue();
523 break;
524 case 0xb:
525 gen_op_eval_fbge();
526 break;
527 case 0xc:
528 gen_op_eval_fbuge();
529 break;
530 case 0xd:
531 gen_op_eval_fble();
532 break;
533 case 0xe:
534 gen_op_eval_fbule();
535 break;
536 default:
537 case 0xf:
538 gen_op_eval_fbo();
539 break;
540 }
541 }
542
543 static void do_branch(DisasContext * dc, uint32_t target, uint32_t insn)
544 {
545 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
546 target += (uint32_t) dc->pc;
547 if (cond == 0x0) {
548 /* unconditional not taken */
549 if (a) {
550 dc->pc = dc->npc + 4;
551 dc->npc = dc->pc + 4;
552 } else {
553 dc->pc = dc->npc;
554 dc->npc = dc->pc + 4;
555 }
556 } else if (cond == 0x8) {
557 /* unconditional taken */
558 if (a) {
559 dc->pc = target;
560 dc->npc = dc->pc + 4;
561 } else {
562 dc->pc = dc->npc;
563 dc->npc = target;
564 }
565 } else {
566 flush_T2(dc);
567 gen_cond(cond);
568 if (a) {
569 gen_op_branch_a((long)dc->tb, target, dc->npc);
570 dc->is_br = 1;
571 } else {
572 dc->pc = dc->npc;
573 dc->jump_pc[0] = target;
574 dc->jump_pc[1] = dc->npc + 4;
575 dc->npc = JUMP_PC;
576 }
577 }
578 }
579
580 static void do_fbranch(DisasContext * dc, uint32_t target, uint32_t insn)
581 {
582 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
583 target += (uint32_t) dc->pc;
584 if (cond == 0x0) {
585 /* unconditional not taken */
586 if (a) {
587 dc->pc = dc->npc + 4;
588 dc->npc = dc->pc + 4;
589 } else {
590 dc->pc = dc->npc;
591 dc->npc = dc->pc + 4;
592 }
593 } else if (cond == 0x8) {
594 /* unconditional taken */
595 if (a) {
596 dc->pc = target;
597 dc->npc = dc->pc + 4;
598 } else {
599 dc->pc = dc->npc;
600 dc->npc = target;
601 }
602 } else {
603 flush_T2(dc);
604 gen_fcond(cond);
605 if (a) {
606 gen_op_branch_a((long)dc->tb, target, dc->npc);
607 dc->is_br = 1;
608 } else {
609 dc->pc = dc->npc;
610 dc->jump_pc[0] = target;
611 dc->jump_pc[1] = dc->npc + 4;
612 dc->npc = JUMP_PC;
613 }
614 }
615 }
616
617 static void gen_debug(DisasContext *s, uint32_t pc)
618 {
619 gen_op_jmp_im(pc);
620 gen_op_debug();
621 s->is_br = 1;
622 }
623
624 #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
625
626 static int sign_extend(int x, int len)
627 {
628 len = 32 - len;
629 return (x << len) >> len;
630 }
631
632 static void disas_sparc_insn(DisasContext * dc)
633 {
634 unsigned int insn, opc, rs1, rs2, rd;
635
636 insn = ldl_code((uint8_t *)dc->pc);
637 opc = GET_FIELD(insn, 0, 1);
638
639 rd = GET_FIELD(insn, 2, 6);
640 switch (opc) {
641 case 0: /* branches/sethi */
642 {
643 unsigned int xop = GET_FIELD(insn, 7, 9);
644 int target;
645 target = GET_FIELD(insn, 10, 31);
646 switch (xop) {
647 case 0x0:
648 case 0x1: /* UNIMPL */
649 case 0x5: /*CBN+x */
650 default:
651 goto illegal_insn;
652 case 0x2: /* BN+x */
653 {
654 target <<= 2;
655 target = sign_extend(target, 22);
656 do_branch(dc, target, insn);
657 goto jmp_insn;
658 }
659 case 0x6: /* FBN+x */
660 {
661 #if !defined(CONFIG_USER_ONLY)
662 gen_op_trap_ifnofpu();
663 #endif
664 target <<= 2;
665 target = sign_extend(target, 22);
666 do_fbranch(dc, target, insn);
667 goto jmp_insn;
668 }
669 case 0x4: /* SETHI */
670 #define OPTIM
671 #if defined(OPTIM)
672 if (rd) { // nop
673 #endif
674 gen_movl_imm_T0(target << 10);
675 gen_movl_T0_reg(rd);
676 #if defined(OPTIM)
677 }
678 #endif
679 break;
680 }
681 break;
682 }
683 case 1:
684 /*CALL*/ {
685 unsigned int target = GET_FIELDs(insn, 2, 31) << 2;
686
687 gen_op_movl_T0_im((long) (dc->pc));
688 gen_movl_T0_reg(15);
689 target = dc->pc + target;
690 dc->pc = dc->npc;
691 dc->npc = target;
692 }
693 goto jmp_insn;
694 case 2: /* FPU & Logical Operations */
695 {
696 unsigned int xop = GET_FIELD(insn, 7, 12);
697 if (xop == 0x3a) { /* generate trap */
698 int cond;
699 rs1 = GET_FIELD(insn, 13, 17);
700 gen_movl_reg_T0(rs1);
701 if (IS_IMM) {
702 rs2 = GET_FIELD(insn, 25, 31);
703 #if defined(OPTIM)
704 if (rs2 != 0) {
705 #endif
706 gen_movl_imm_T1(rs2);
707 gen_op_add_T1_T0();
708 #if defined(OPTIM)
709 }
710 #endif
711 } else {
712 rs2 = GET_FIELD(insn, 27, 31);
713 #if defined(OPTIM)
714 if (rs2 != 0) {
715 #endif
716 gen_movl_reg_T1(rs2);
717 gen_op_add_T1_T0();
718 #if defined(OPTIM)
719 }
720 #endif
721 }
722 save_state(dc);
723 cond = GET_FIELD(insn, 3, 6);
724 if (cond == 0x8) {
725 gen_op_trap_T0();
726 dc->is_br = 1;
727 goto jmp_insn;
728 } else {
729 gen_cond(cond);
730 gen_op_trapcc_T0();
731 }
732 } else if (xop == 0x28) {
733 rs1 = GET_FIELD(insn, 13, 17);
734 switch(rs1) {
735 case 0: /* rdy */
736 gen_op_rdy();
737 gen_movl_T0_reg(rd);
738 break;
739 case 15: /* stbar */
740 break; /* no effect? */
741 default:
742 goto illegal_insn;
743 }
744 #if !defined(CONFIG_USER_ONLY)
745 } else if (xop == 0x29) {
746 if (!supervisor(dc))
747 goto priv_insn;
748 gen_op_rdpsr();
749 gen_movl_T0_reg(rd);
750 break;
751 } else if (xop == 0x2a) {
752 if (!supervisor(dc))
753 goto priv_insn;
754 gen_op_rdwim();
755 gen_movl_T0_reg(rd);
756 break;
757 } else if (xop == 0x2b) {
758 if (!supervisor(dc))
759 goto priv_insn;
760 gen_op_rdtbr();
761 gen_movl_T0_reg(rd);
762 break;
763 #endif
764 } else if (xop == 0x34) { /* FPU Operations */
765 #if !defined(CONFIG_USER_ONLY)
766 gen_op_trap_ifnofpu();
767 #endif
768 rs1 = GET_FIELD(insn, 13, 17);
769 rs2 = GET_FIELD(insn, 27, 31);
770 xop = GET_FIELD(insn, 18, 26);
771 switch (xop) {
772 case 0x1: /* fmovs */
773 gen_op_load_fpr_FT0(rs2);
774 gen_op_store_FT0_fpr(rd);
775 break;
776 case 0x5: /* fnegs */
777 gen_op_load_fpr_FT1(rs2);
778 gen_op_fnegs();
779 gen_op_store_FT0_fpr(rd);
780 break;
781 case 0x9: /* fabss */
782 gen_op_load_fpr_FT1(rs2);
783 gen_op_fabss();
784 gen_op_store_FT0_fpr(rd);
785 break;
786 case 0x29: /* fsqrts */
787 gen_op_load_fpr_FT1(rs2);
788 gen_op_fsqrts();
789 gen_op_store_FT0_fpr(rd);
790 break;
791 case 0x2a: /* fsqrtd */
792 gen_op_load_fpr_DT1(rs2);
793 gen_op_fsqrtd();
794 gen_op_store_DT0_fpr(rd);
795 break;
796 case 0x2b: /* fsqrtq */
797 goto nfpu_insn;
798 case 0x41:
799 gen_op_load_fpr_FT0(rs1);
800 gen_op_load_fpr_FT1(rs2);
801 gen_op_fadds();
802 gen_op_store_FT0_fpr(rd);
803 break;
804 case 0x42:
805 gen_op_load_fpr_DT0(rs1);
806 gen_op_load_fpr_DT1(rs2);
807 gen_op_faddd();
808 gen_op_store_DT0_fpr(rd);
809 break;
810 case 0x43: /* faddq */
811 goto nfpu_insn;
812 case 0x45:
813 gen_op_load_fpr_FT0(rs1);
814 gen_op_load_fpr_FT1(rs2);
815 gen_op_fsubs();
816 gen_op_store_FT0_fpr(rd);
817 break;
818 case 0x46:
819 gen_op_load_fpr_DT0(rs1);
820 gen_op_load_fpr_DT1(rs2);
821 gen_op_fsubd();
822 gen_op_store_DT0_fpr(rd);
823 break;
824 case 0x47: /* fsubq */
825 goto nfpu_insn;
826 case 0x49:
827 gen_op_load_fpr_FT0(rs1);
828 gen_op_load_fpr_FT1(rs2);
829 gen_op_fmuls();
830 gen_op_store_FT0_fpr(rd);
831 break;
832 case 0x4a:
833 gen_op_load_fpr_DT0(rs1);
834 gen_op_load_fpr_DT1(rs2);
835 gen_op_fmuld();
836 gen_op_store_DT0_fpr(rd);
837 break;
838 case 0x4b: /* fmulq */
839 goto nfpu_insn;
840 case 0x4d:
841 gen_op_load_fpr_FT0(rs1);
842 gen_op_load_fpr_FT1(rs2);
843 gen_op_fdivs();
844 gen_op_store_FT0_fpr(rd);
845 break;
846 case 0x4e:
847 gen_op_load_fpr_DT0(rs1);
848 gen_op_load_fpr_DT1(rs2);
849 gen_op_fdivd();
850 gen_op_store_DT0_fpr(rd);
851 break;
852 case 0x4f: /* fdivq */
853 goto nfpu_insn;
854 case 0x69:
855 gen_op_load_fpr_FT0(rs1);
856 gen_op_load_fpr_FT1(rs2);
857 gen_op_fsmuld();
858 gen_op_store_DT0_fpr(rd);
859 break;
860 case 0x6e: /* fdmulq */
861 goto nfpu_insn;
862 case 0xc4:
863 gen_op_load_fpr_FT1(rs2);
864 gen_op_fitos();
865 gen_op_store_FT0_fpr(rd);
866 break;
867 case 0xc6:
868 gen_op_load_fpr_DT1(rs2);
869 gen_op_fdtos();
870 gen_op_store_FT0_fpr(rd);
871 break;
872 case 0xc7: /* fqtos */
873 goto nfpu_insn;
874 case 0xc8:
875 gen_op_load_fpr_FT1(rs2);
876 gen_op_fitod();
877 gen_op_store_DT0_fpr(rd);
878 break;
879 case 0xc9:
880 gen_op_load_fpr_FT1(rs2);
881 gen_op_fstod();
882 gen_op_store_DT0_fpr(rd);
883 break;
884 case 0xcb: /* fqtod */
885 goto nfpu_insn;
886 case 0xcc: /* fitoq */
887 goto nfpu_insn;
888 case 0xcd: /* fstoq */
889 goto nfpu_insn;
890 case 0xce: /* fdtoq */
891 goto nfpu_insn;
892 case 0xd1:
893 gen_op_load_fpr_FT1(rs2);
894 gen_op_fstoi();
895 gen_op_store_FT0_fpr(rd);
896 break;
897 case 0xd2:
898 gen_op_load_fpr_DT1(rs2);
899 gen_op_fdtoi();
900 gen_op_store_FT0_fpr(rd);
901 break;
902 case 0xd3: /* fqtoi */
903 goto nfpu_insn;
904 default:
905 goto illegal_insn;
906 }
907 } else if (xop == 0x35) { /* FPU Operations */
908 #if !defined(CONFIG_USER_ONLY)
909 gen_op_trap_ifnofpu();
910 #endif
911 rs1 = GET_FIELD(insn, 13, 17);
912 rs2 = GET_FIELD(insn, 27, 31);
913 xop = GET_FIELD(insn, 18, 26);
914 switch (xop) {
915 case 0x51:
916 gen_op_load_fpr_FT0(rs1);
917 gen_op_load_fpr_FT1(rs2);
918 gen_op_fcmps();
919 break;
920 case 0x52:
921 gen_op_load_fpr_DT0(rs1);
922 gen_op_load_fpr_DT1(rs2);
923 gen_op_fcmpd();
924 break;
925 case 0x53: /* fcmpq */
926 goto nfpu_insn;
927 case 0x55: /* fcmpes */
928 gen_op_load_fpr_FT0(rs1);
929 gen_op_load_fpr_FT1(rs2);
930 gen_op_fcmps(); /* XXX should trap if qNaN or sNaN */
931 break;
932 case 0x56: /* fcmped */
933 gen_op_load_fpr_DT0(rs1);
934 gen_op_load_fpr_DT1(rs2);
935 gen_op_fcmpd(); /* XXX should trap if qNaN or sNaN */
936 break;
937 case 0x57: /* fcmpeq */
938 goto nfpu_insn;
939 default:
940 goto illegal_insn;
941 }
942 #if defined(OPTIM)
943 } else if (xop == 0x2) {
944 // clr/mov shortcut
945
946 rs1 = GET_FIELD(insn, 13, 17);
947 if (rs1 == 0) {
948 // or %g0, x, y -> mov T1, x; mov y, T1
949 if (IS_IMM) { /* immediate */
950 rs2 = GET_FIELDs(insn, 19, 31);
951 gen_movl_imm_T1(rs2);
952 } else { /* register */
953 rs2 = GET_FIELD(insn, 27, 31);
954 gen_movl_reg_T1(rs2);
955 }
956 gen_movl_T1_reg(rd);
957 } else {
958 gen_movl_reg_T0(rs1);
959 if (IS_IMM) { /* immediate */
960 // or x, #0, y -> mov T1, x; mov y, T1
961 rs2 = GET_FIELDs(insn, 19, 31);
962 if (rs2 != 0) {
963 gen_movl_imm_T1(rs2);
964 gen_op_or_T1_T0();
965 }
966 } else { /* register */
967 // or x, %g0, y -> mov T1, x; mov y, T1
968 rs2 = GET_FIELD(insn, 27, 31);
969 if (rs2 != 0) {
970 gen_movl_reg_T1(rs2);
971 gen_op_or_T1_T0();
972 }
973 }
974 gen_movl_T0_reg(rd);
975 }
976 #endif
977 } else if (xop < 0x38) {
978 rs1 = GET_FIELD(insn, 13, 17);
979 gen_movl_reg_T0(rs1);
980 if (IS_IMM) { /* immediate */
981 rs2 = GET_FIELDs(insn, 19, 31);
982 gen_movl_imm_T1(rs2);
983 } else { /* register */
984 rs2 = GET_FIELD(insn, 27, 31);
985 gen_movl_reg_T1(rs2);
986 }
987 if (xop < 0x20) {
988 switch (xop & ~0x10) {
989 case 0x0:
990 if (xop & 0x10)
991 gen_op_add_T1_T0_cc();
992 else
993 gen_op_add_T1_T0();
994 break;
995 case 0x1:
996 gen_op_and_T1_T0();
997 if (xop & 0x10)
998 gen_op_logic_T0_cc();
999 break;
1000 case 0x2:
1001 gen_op_or_T1_T0();
1002 if (xop & 0x10)
1003 gen_op_logic_T0_cc();
1004 break;
1005 case 0x3:
1006 gen_op_xor_T1_T0();
1007 if (xop & 0x10)
1008 gen_op_logic_T0_cc();
1009 break;
1010 case 0x4:
1011 if (xop & 0x10)
1012 gen_op_sub_T1_T0_cc();
1013 else
1014 gen_op_sub_T1_T0();
1015 break;
1016 case 0x5:
1017 gen_op_andn_T1_T0();
1018 if (xop & 0x10)
1019 gen_op_logic_T0_cc();
1020 break;
1021 case 0x6:
1022 gen_op_orn_T1_T0();
1023 if (xop & 0x10)
1024 gen_op_logic_T0_cc();
1025 break;
1026 case 0x7:
1027 gen_op_xnor_T1_T0();
1028 if (xop & 0x10)
1029 gen_op_logic_T0_cc();
1030 break;
1031 case 0x8:
1032 gen_op_addx_T1_T0();
1033 if (xop & 0x10)
1034 gen_op_set_flags();
1035 break;
1036 case 0xa:
1037 gen_op_umul_T1_T0();
1038 if (xop & 0x10)
1039 gen_op_logic_T0_cc();
1040 break;
1041 case 0xb:
1042 gen_op_smul_T1_T0();
1043 if (xop & 0x10)
1044 gen_op_logic_T0_cc();
1045 break;
1046 case 0xc:
1047 gen_op_subx_T1_T0();
1048 if (xop & 0x10)
1049 gen_op_set_flags();
1050 break;
1051 case 0xe:
1052 gen_op_udiv_T1_T0();
1053 if (xop & 0x10)
1054 gen_op_div_cc();
1055 break;
1056 case 0xf:
1057 gen_op_sdiv_T1_T0();
1058 if (xop & 0x10)
1059 gen_op_div_cc();
1060 break;
1061 default:
1062 goto illegal_insn;
1063 }
1064 gen_movl_T0_reg(rd);
1065 } else {
1066 switch (xop) {
1067 case 0x20: /* taddcc */
1068 case 0x21: /* tsubcc */
1069 case 0x22: /* taddcctv */
1070 case 0x23: /* tsubcctv */
1071 goto illegal_insn;
1072 case 0x24: /* mulscc */
1073 gen_op_mulscc_T1_T0();
1074 gen_movl_T0_reg(rd);
1075 break;
1076 case 0x25: /* SLL */
1077 gen_op_sll();
1078 gen_movl_T0_reg(rd);
1079 break;
1080 case 0x26:
1081 gen_op_srl();
1082 gen_movl_T0_reg(rd);
1083 break;
1084 case 0x27:
1085 gen_op_sra();
1086 gen_movl_T0_reg(rd);
1087 break;
1088 case 0x30:
1089 {
1090 gen_op_xor_T1_T0();
1091 switch(rd) {
1092 case 0:
1093 gen_op_wry();
1094 break;
1095 default:
1096 goto illegal_insn;
1097 }
1098 }
1099 break;
1100 #if !defined(CONFIG_USER_ONLY)
1101 case 0x31:
1102 {
1103 if (!supervisor(dc))
1104 goto priv_insn;
1105 gen_op_xor_T1_T0();
1106 gen_op_wrpsr();
1107 }
1108 break;
1109 case 0x32:
1110 {
1111 if (!supervisor(dc))
1112 goto priv_insn;
1113 gen_op_xor_T1_T0();
1114 gen_op_wrwim();
1115 }
1116 break;
1117 case 0x33:
1118 {
1119 if (!supervisor(dc))
1120 goto priv_insn;
1121 gen_op_xor_T1_T0();
1122 gen_op_wrtbr();
1123 }
1124 break;
1125 #endif
1126 default:
1127 goto illegal_insn;
1128 }
1129 }
1130 } else {
1131 rs1 = GET_FIELD(insn, 13, 17);
1132 gen_movl_reg_T0(rs1);
1133 if (IS_IMM) { /* immediate */
1134 rs2 = GET_FIELDs(insn, 19, 31);
1135 #if defined(OPTIM)
1136 if (rs2) {
1137 #endif
1138 gen_movl_imm_T1(rs2);
1139 gen_op_add_T1_T0();
1140 #if defined(OPTIM)
1141 }
1142 #endif
1143 } else { /* register */
1144 rs2 = GET_FIELD(insn, 27, 31);
1145 #if defined(OPTIM)
1146 if (rs2) {
1147 #endif
1148 gen_movl_reg_T1(rs2);
1149 gen_op_add_T1_T0();
1150 #if defined(OPTIM)
1151 }
1152 #endif
1153 }
1154 switch (xop) {
1155 case 0x38: /* jmpl */
1156 {
1157 gen_op_movl_npc_T0();
1158 if (rd != 0) {
1159 gen_op_movl_T0_im((long) (dc->pc));
1160 gen_movl_T0_reg(rd);
1161 }
1162 dc->pc = dc->npc;
1163 dc->npc = DYNAMIC_PC;
1164 }
1165 goto jmp_insn;
1166 #if !defined(CONFIG_USER_ONLY)
1167 case 0x39: /* rett */
1168 {
1169 if (!supervisor(dc))
1170 goto priv_insn;
1171 gen_op_movl_npc_T0();
1172 gen_op_rett();
1173 }
1174 break;
1175 #endif
1176 case 0x3b: /* flush */
1177 gen_op_flush_T0();
1178 break;
1179 case 0x3c: /* save */
1180 save_state(dc);
1181 gen_op_save();
1182 gen_movl_T0_reg(rd);
1183 break;
1184 case 0x3d: /* restore */
1185 save_state(dc);
1186 gen_op_restore();
1187 gen_movl_T0_reg(rd);
1188 break;
1189 default:
1190 goto illegal_insn;
1191 }
1192 }
1193 break;
1194 }
1195 case 3: /* load/store instructions */
1196 {
1197 unsigned int xop = GET_FIELD(insn, 7, 12);
1198 rs1 = GET_FIELD(insn, 13, 17);
1199 gen_movl_reg_T0(rs1);
1200 if (IS_IMM) { /* immediate */
1201 rs2 = GET_FIELDs(insn, 19, 31);
1202 #if defined(OPTIM)
1203 if (rs2 != 0) {
1204 #endif
1205 gen_movl_imm_T1(rs2);
1206 gen_op_add_T1_T0();
1207 #if defined(OPTIM)
1208 }
1209 #endif
1210 } else { /* register */
1211 rs2 = GET_FIELD(insn, 27, 31);
1212 #if defined(OPTIM)
1213 if (rs2 != 0) {
1214 #endif
1215 gen_movl_reg_T1(rs2);
1216 gen_op_add_T1_T0();
1217 #if defined(OPTIM)
1218 }
1219 #endif
1220 }
1221 if (xop < 4 || (xop > 7 && xop < 0x14) || \
1222 (xop > 0x17 && xop < 0x20)) {
1223 switch (xop) {
1224 case 0x0: /* load word */
1225 gen_op_ldst(ld);
1226 break;
1227 case 0x1: /* load unsigned byte */
1228 gen_op_ldst(ldub);
1229 break;
1230 case 0x2: /* load unsigned halfword */
1231 gen_op_ldst(lduh);
1232 break;
1233 case 0x3: /* load double word */
1234 gen_op_ldst(ldd);
1235 gen_movl_T0_reg(rd + 1);
1236 break;
1237 case 0x9: /* load signed byte */
1238 gen_op_ldst(ldsb);
1239 break;
1240 case 0xa: /* load signed halfword */
1241 gen_op_ldst(ldsh);
1242 break;
1243 case 0xd: /* ldstub -- XXX: should be atomically */
1244 gen_op_ldst(ldstub);
1245 break;
1246 case 0x0f: /* swap register with memory. Also atomically */
1247 gen_movl_reg_T1(rd);
1248 gen_op_ldst(swap);
1249 break;
1250 #if !defined(CONFIG_USER_ONLY)
1251 case 0x10: /* load word alternate */
1252 if (!supervisor(dc))
1253 goto priv_insn;
1254 gen_op_lda(insn, 1, 4, 0);
1255 break;
1256 case 0x11: /* load unsigned byte alternate */
1257 if (!supervisor(dc))
1258 goto priv_insn;
1259 gen_op_lduba(insn, 1, 1, 0);
1260 break;
1261 case 0x12: /* load unsigned halfword alternate */
1262 if (!supervisor(dc))
1263 goto priv_insn;
1264 gen_op_lduha(insn, 1, 2, 0);
1265 break;
1266 case 0x13: /* load double word alternate */
1267 if (!supervisor(dc))
1268 goto priv_insn;
1269 gen_op_ldda(insn, 1, 8, 0);
1270 gen_movl_T0_reg(rd + 1);
1271 break;
1272 case 0x19: /* load signed byte alternate */
1273 if (!supervisor(dc))
1274 goto priv_insn;
1275 gen_op_ldsba(insn, 1, 1, 1);
1276 break;
1277 case 0x1a: /* load signed halfword alternate */
1278 if (!supervisor(dc))
1279 goto priv_insn;
1280 gen_op_ldsha(insn, 1, 2 ,1);
1281 break;
1282 case 0x1d: /* ldstuba -- XXX: should be atomically */
1283 if (!supervisor(dc))
1284 goto priv_insn;
1285 gen_op_ldstuba(insn, 1, 1, 0);
1286 break;
1287 case 0x1f: /* swap reg with alt. memory. Also atomically */
1288 if (!supervisor(dc))
1289 goto priv_insn;
1290 gen_movl_reg_T1(rd);
1291 gen_op_swapa(insn, 1, 4, 0);
1292 break;
1293 #endif
1294 default:
1295 goto illegal_insn;
1296 }
1297 gen_movl_T1_reg(rd);
1298 } else if (xop >= 0x20 && xop < 0x24) {
1299 #if !defined(CONFIG_USER_ONLY)
1300 gen_op_trap_ifnofpu();
1301 #endif
1302 switch (xop) {
1303 case 0x20: /* load fpreg */
1304 gen_op_ldst(ldf);
1305 gen_op_store_FT0_fpr(rd);
1306 break;
1307 case 0x21: /* load fsr */
1308 gen_op_ldfsr();
1309 gen_op_store_FT0_fpr(rd);
1310 break;
1311 case 0x23: /* load double fpreg */
1312 gen_op_ldst(lddf);
1313 gen_op_store_DT0_fpr(rd);
1314 break;
1315 default:
1316 goto illegal_insn;
1317 }
1318 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18)) {
1319 gen_movl_reg_T1(rd);
1320 switch (xop) {
1321 case 0x4:
1322 gen_op_ldst(st);
1323 break;
1324 case 0x5:
1325 gen_op_ldst(stb);
1326 break;
1327 case 0x6:
1328 gen_op_ldst(sth);
1329 break;
1330 case 0x7:
1331 flush_T2(dc);
1332 gen_movl_reg_T2(rd + 1);
1333 gen_op_ldst(std);
1334 break;
1335 #if !defined(CONFIG_USER_ONLY)
1336 case 0x14:
1337 if (!supervisor(dc))
1338 goto priv_insn;
1339 gen_op_sta(insn, 0, 4, 0);
1340 break;
1341 case 0x15:
1342 if (!supervisor(dc))
1343 goto priv_insn;
1344 gen_op_stba(insn, 0, 1, 0);
1345 break;
1346 case 0x16:
1347 if (!supervisor(dc))
1348 goto priv_insn;
1349 gen_op_stha(insn, 0, 2, 0);
1350 break;
1351 case 0x17:
1352 if (!supervisor(dc))
1353 goto priv_insn;
1354 flush_T2(dc);
1355 gen_movl_reg_T2(rd + 1);
1356 gen_op_stda(insn, 0, 8, 0);
1357 break;
1358 #endif
1359 default:
1360 goto illegal_insn;
1361 }
1362 } else if (xop > 0x23 && xop < 0x28) {
1363 #if !defined(CONFIG_USER_ONLY)
1364 gen_op_trap_ifnofpu();
1365 #endif
1366 switch (xop) {
1367 case 0x24:
1368 gen_op_load_fpr_FT0(rd);
1369 gen_op_ldst(stf);
1370 break;
1371 case 0x25:
1372 gen_op_load_fpr_FT0(rd);
1373 gen_op_stfsr();
1374 break;
1375 case 0x27:
1376 gen_op_load_fpr_DT0(rd);
1377 gen_op_ldst(stdf);
1378 break;
1379 case 0x26: /* stdfq */
1380 default:
1381 goto illegal_insn;
1382 }
1383 } else if (xop > 0x33 && xop < 0x38) {
1384 /* Co-processor */
1385 goto illegal_insn;
1386 }
1387 else
1388 goto illegal_insn;
1389 }
1390 }
1391 /* default case for non jump instructions */
1392 if (dc->npc == DYNAMIC_PC) {
1393 dc->pc = DYNAMIC_PC;
1394 gen_op_next_insn();
1395 } else if (dc->npc == JUMP_PC) {
1396 /* we can do a static jump */
1397 gen_op_branch2((long)dc->tb, dc->jump_pc[0], dc->jump_pc[1]);
1398 dc->is_br = 1;
1399 } else {
1400 dc->pc = dc->npc;
1401 dc->npc = dc->npc + 4;
1402 }
1403 jmp_insn:
1404 return;
1405 illegal_insn:
1406 save_state(dc);
1407 gen_op_exception(TT_ILL_INSN);
1408 dc->is_br = 1;
1409 return;
1410 #if !defined(CONFIG_USER_ONLY)
1411 priv_insn:
1412 save_state(dc);
1413 gen_op_exception(TT_PRIV_INSN);
1414 dc->is_br = 1;
1415 return;
1416 #endif
1417 nfpu_insn:
1418 save_state(dc);
1419 gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
1420 dc->is_br = 1;
1421 }
1422
1423 static inline int gen_intermediate_code_internal(TranslationBlock * tb,
1424 int spc, CPUSPARCState *env)
1425 {
1426 target_ulong pc_start, last_pc;
1427 uint16_t *gen_opc_end;
1428 DisasContext dc1, *dc = &dc1;
1429 int j, lj = -1;
1430
1431 memset(dc, 0, sizeof(DisasContext));
1432 dc->tb = tb;
1433 pc_start = tb->pc;
1434 dc->pc = pc_start;
1435 last_pc = dc->pc;
1436 dc->npc = (target_ulong) tb->cs_base;
1437 #if defined(CONFIG_USER_ONLY)
1438 dc->mem_idx = 0;
1439 #else
1440 dc->mem_idx = ((env->psrs) != 0);
1441 #endif
1442 gen_opc_ptr = gen_opc_buf;
1443 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
1444 gen_opparam_ptr = gen_opparam_buf;
1445
1446 do {
1447 if (env->nb_breakpoints > 0) {
1448 for(j = 0; j < env->nb_breakpoints; j++) {
1449 if (env->breakpoints[j] == dc->pc) {
1450 if (dc->pc != pc_start)
1451 save_state(dc);
1452 gen_op_debug();
1453 gen_op_movl_T0_0();
1454 gen_op_exit_tb();
1455 dc->is_br = 1;
1456 goto exit_gen_loop;
1457 }
1458 }
1459 }
1460 if (spc) {
1461 if (loglevel > 0)
1462 fprintf(logfile, "Search PC...\n");
1463 j = gen_opc_ptr - gen_opc_buf;
1464 if (lj < j) {
1465 lj++;
1466 while (lj < j)
1467 gen_opc_instr_start[lj++] = 0;
1468 gen_opc_pc[lj] = dc->pc;
1469 gen_opc_npc[lj] = dc->npc;
1470 gen_opc_instr_start[lj] = 1;
1471 }
1472 }
1473 last_pc = dc->pc;
1474 disas_sparc_insn(dc);
1475 if (dc->is_br)
1476 break;
1477 /* if the next PC is different, we abort now */
1478 if (dc->pc != (last_pc + 4))
1479 break;
1480 /* if single step mode, we generate only one instruction and
1481 generate an exception */
1482 if (env->singlestep_enabled) {
1483 gen_op_jmp_im(dc->pc);
1484 gen_op_movl_T0_0();
1485 gen_op_exit_tb();
1486 break;
1487 }
1488 } while ((gen_opc_ptr < gen_opc_end) &&
1489 (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
1490
1491 exit_gen_loop:
1492 if (!dc->is_br) {
1493 if (dc->pc != DYNAMIC_PC &&
1494 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
1495 /* static PC and NPC: we can use direct chaining */
1496 gen_op_branch((long)tb, dc->pc, dc->npc);
1497 } else {
1498 if (dc->pc != DYNAMIC_PC)
1499 gen_op_jmp_im(dc->pc);
1500 save_npc(dc);
1501 gen_op_movl_T0_0();
1502 gen_op_exit_tb();
1503 }
1504 }
1505 *gen_opc_ptr = INDEX_op_end;
1506 if (spc) {
1507 j = gen_opc_ptr - gen_opc_buf;
1508 lj++;
1509 while (lj <= j)
1510 gen_opc_instr_start[lj++] = 0;
1511 tb->size = 0;
1512 #if 0
1513 if (loglevel > 0) {
1514 page_dump(logfile);
1515 }
1516 #endif
1517 } else {
1518 tb->size = last_pc + 4 - pc_start;
1519 }
1520 #ifdef DEBUG_DISAS
1521 if (loglevel & CPU_LOG_TB_IN_ASM) {
1522 fprintf(logfile, "--------------\n");
1523 fprintf(logfile, "IN: %s\n", lookup_symbol((uint8_t *)pc_start));
1524 disas(logfile, (uint8_t *)pc_start, last_pc + 4 - pc_start, 0, 0);
1525 fprintf(logfile, "\n");
1526 if (loglevel & CPU_LOG_TB_OP) {
1527 fprintf(logfile, "OP:\n");
1528 dump_ops(gen_opc_buf, gen_opparam_buf);
1529 fprintf(logfile, "\n");
1530 }
1531 }
1532 #endif
1533 return 0;
1534 }
1535
1536 int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
1537 {
1538 return gen_intermediate_code_internal(tb, 0, env);
1539 }
1540
1541 int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
1542 {
1543 return gen_intermediate_code_internal(tb, 1, env);
1544 }
1545
1546 extern int ram_size;
1547
1548 void cpu_reset(CPUSPARCState *env)
1549 {
1550 memset(env, 0, sizeof(*env));
1551 env->cwp = 0;
1552 env->wim = 1;
1553 env->regwptr = env->regbase + (env->cwp * 16);
1554 #if defined(CONFIG_USER_ONLY)
1555 env->user_mode_only = 1;
1556 #else
1557 env->psrs = 1;
1558 env->pc = 0xffd00000;
1559 env->gregs[1] = ram_size;
1560 env->mmuregs[0] = (0x04 << 24); /* Impl 0, ver 4, MMU disabled */
1561 env->npc = env->pc + 4;
1562 #endif
1563 }
1564
1565 CPUSPARCState *cpu_sparc_init(void)
1566 {
1567 CPUSPARCState *env;
1568
1569 cpu_exec_init();
1570
1571 if (!(env = malloc(sizeof(CPUSPARCState))))
1572 return (NULL);
1573 cpu_single_env = env;
1574 cpu_reset(env);
1575 return (env);
1576 }
1577
1578 #define GET_FLAG(a,b) ((env->psr & a)?b:'-')
1579
1580 void cpu_dump_state(CPUState *env, FILE *f,
1581 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
1582 int flags)
1583 {
1584 int i, x;
1585
1586 cpu_fprintf(f, "pc: 0x%08x npc: 0x%08x\n", (int) env->pc, (int) env->npc);
1587 cpu_fprintf(f, "General Registers:\n");
1588 for (i = 0; i < 4; i++)
1589 cpu_fprintf(f, "%%g%c: 0x%08x\t", i + '0', env->gregs[i]);
1590 cpu_fprintf(f, "\n");
1591 for (; i < 8; i++)
1592 cpu_fprintf(f, "%%g%c: 0x%08x\t", i + '0', env->gregs[i]);
1593 cpu_fprintf(f, "\nCurrent Register Window:\n");
1594 for (x = 0; x < 3; x++) {
1595 for (i = 0; i < 4; i++)
1596 cpu_fprintf(f, "%%%c%d: 0x%08x\t",
1597 (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
1598 env->regwptr[i + x * 8]);
1599 cpu_fprintf(f, "\n");
1600 for (; i < 8; i++)
1601 cpu_fprintf(f, "%%%c%d: 0x%08x\t",
1602 (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
1603 env->regwptr[i + x * 8]);
1604 cpu_fprintf(f, "\n");
1605 }
1606 cpu_fprintf(f, "\nFloating Point Registers:\n");
1607 for (i = 0; i < 32; i++) {
1608 if ((i & 3) == 0)
1609 cpu_fprintf(f, "%%f%02d:", i);
1610 cpu_fprintf(f, " %016lf", env->fpr[i]);
1611 if ((i & 3) == 3)
1612 cpu_fprintf(f, "\n");
1613 }
1614 cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
1615 GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
1616 GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
1617 env->psrs?'S':'-', env->psrps?'P':'-',
1618 env->psret?'E':'-', env->wim);
1619 cpu_fprintf(f, "fsr: 0x%08x\n", env->fsr);
1620 }
1621
1622 #if defined(CONFIG_USER_ONLY)
1623 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
1624 {
1625 return addr;
1626 }
1627
1628 #else
1629 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
1630 {
1631 uint32_t phys_addr;
1632 int prot, access_index;
1633
1634 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2, 0) != 0)
1635 return -1;
1636 return phys_addr;
1637 }
1638 #endif
1639
1640 void helper_flush(target_ulong addr)
1641 {
1642 addr &= ~7;
1643 tb_invalidate_page_range(addr, addr + 8);
1644 }
Qemu copy for testing