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full system SPARC emulation (Blue Swirl)
[qemu.git] / target-sparc / translate.c
1 /*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5 Copyright (C) 2003 Fabrice Bellard
6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
16
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22 /*
23 TODO-list:
24
25 NPC/PC static optimisations (use JUMP_TB when possible)
26 FPU-Instructions
27 Privileged instructions
28 Coprocessor-Instructions
29 Optimize synthetic instructions
30 Optional alignment and privileged instruction check
31 */
32
33 #include <stdarg.h>
34 #include <stdlib.h>
35 #include <stdio.h>
36 #include <string.h>
37 #include <inttypes.h>
38
39 #include "cpu.h"
40 #include "exec-all.h"
41 #include "disas.h"
42
43 #define DEBUG_DISAS
44
45 #define DYNAMIC_PC 1 /* dynamic pc value */
46 #define JUMP_PC 2 /* dynamic pc value which takes only two values
47 according to jump_pc[T2] */
48
49 typedef struct DisasContext {
50 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
51 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
52 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
53 int is_br;
54 int mem_idx;
55 struct TranslationBlock *tb;
56 } DisasContext;
57
58 static uint16_t *gen_opc_ptr;
59 static uint32_t *gen_opparam_ptr;
60 extern FILE *logfile;
61 extern int loglevel;
62
63 enum {
64 #define DEF(s,n,copy_size) INDEX_op_ ## s,
65 #include "opc.h"
66 #undef DEF
67 NB_OPS
68 };
69
70 #include "gen-op.h"
71
72 #define GET_FIELD(X, FROM, TO) \
73 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
74
75 #define IS_IMM (insn & (1<<13))
76
77 static void disas_sparc_insn(DisasContext * dc);
78
79 static GenOpFunc *gen_op_movl_TN_reg[2][32] = {
80 {
81 gen_op_movl_g0_T0,
82 gen_op_movl_g1_T0,
83 gen_op_movl_g2_T0,
84 gen_op_movl_g3_T0,
85 gen_op_movl_g4_T0,
86 gen_op_movl_g5_T0,
87 gen_op_movl_g6_T0,
88 gen_op_movl_g7_T0,
89 gen_op_movl_o0_T0,
90 gen_op_movl_o1_T0,
91 gen_op_movl_o2_T0,
92 gen_op_movl_o3_T0,
93 gen_op_movl_o4_T0,
94 gen_op_movl_o5_T0,
95 gen_op_movl_o6_T0,
96 gen_op_movl_o7_T0,
97 gen_op_movl_l0_T0,
98 gen_op_movl_l1_T0,
99 gen_op_movl_l2_T0,
100 gen_op_movl_l3_T0,
101 gen_op_movl_l4_T0,
102 gen_op_movl_l5_T0,
103 gen_op_movl_l6_T0,
104 gen_op_movl_l7_T0,
105 gen_op_movl_i0_T0,
106 gen_op_movl_i1_T0,
107 gen_op_movl_i2_T0,
108 gen_op_movl_i3_T0,
109 gen_op_movl_i4_T0,
110 gen_op_movl_i5_T0,
111 gen_op_movl_i6_T0,
112 gen_op_movl_i7_T0,
113 },
114 {
115 gen_op_movl_g0_T1,
116 gen_op_movl_g1_T1,
117 gen_op_movl_g2_T1,
118 gen_op_movl_g3_T1,
119 gen_op_movl_g4_T1,
120 gen_op_movl_g5_T1,
121 gen_op_movl_g6_T1,
122 gen_op_movl_g7_T1,
123 gen_op_movl_o0_T1,
124 gen_op_movl_o1_T1,
125 gen_op_movl_o2_T1,
126 gen_op_movl_o3_T1,
127 gen_op_movl_o4_T1,
128 gen_op_movl_o5_T1,
129 gen_op_movl_o6_T1,
130 gen_op_movl_o7_T1,
131 gen_op_movl_l0_T1,
132 gen_op_movl_l1_T1,
133 gen_op_movl_l2_T1,
134 gen_op_movl_l3_T1,
135 gen_op_movl_l4_T1,
136 gen_op_movl_l5_T1,
137 gen_op_movl_l6_T1,
138 gen_op_movl_l7_T1,
139 gen_op_movl_i0_T1,
140 gen_op_movl_i1_T1,
141 gen_op_movl_i2_T1,
142 gen_op_movl_i3_T1,
143 gen_op_movl_i4_T1,
144 gen_op_movl_i5_T1,
145 gen_op_movl_i6_T1,
146 gen_op_movl_i7_T1,
147 }
148 };
149
150 static GenOpFunc *gen_op_movl_reg_TN[3][32] = {
151 {
152 gen_op_movl_T0_g0,
153 gen_op_movl_T0_g1,
154 gen_op_movl_T0_g2,
155 gen_op_movl_T0_g3,
156 gen_op_movl_T0_g4,
157 gen_op_movl_T0_g5,
158 gen_op_movl_T0_g6,
159 gen_op_movl_T0_g7,
160 gen_op_movl_T0_o0,
161 gen_op_movl_T0_o1,
162 gen_op_movl_T0_o2,
163 gen_op_movl_T0_o3,
164 gen_op_movl_T0_o4,
165 gen_op_movl_T0_o5,
166 gen_op_movl_T0_o6,
167 gen_op_movl_T0_o7,
168 gen_op_movl_T0_l0,
169 gen_op_movl_T0_l1,
170 gen_op_movl_T0_l2,
171 gen_op_movl_T0_l3,
172 gen_op_movl_T0_l4,
173 gen_op_movl_T0_l5,
174 gen_op_movl_T0_l6,
175 gen_op_movl_T0_l7,
176 gen_op_movl_T0_i0,
177 gen_op_movl_T0_i1,
178 gen_op_movl_T0_i2,
179 gen_op_movl_T0_i3,
180 gen_op_movl_T0_i4,
181 gen_op_movl_T0_i5,
182 gen_op_movl_T0_i6,
183 gen_op_movl_T0_i7,
184 },
185 {
186 gen_op_movl_T1_g0,
187 gen_op_movl_T1_g1,
188 gen_op_movl_T1_g2,
189 gen_op_movl_T1_g3,
190 gen_op_movl_T1_g4,
191 gen_op_movl_T1_g5,
192 gen_op_movl_T1_g6,
193 gen_op_movl_T1_g7,
194 gen_op_movl_T1_o0,
195 gen_op_movl_T1_o1,
196 gen_op_movl_T1_o2,
197 gen_op_movl_T1_o3,
198 gen_op_movl_T1_o4,
199 gen_op_movl_T1_o5,
200 gen_op_movl_T1_o6,
201 gen_op_movl_T1_o7,
202 gen_op_movl_T1_l0,
203 gen_op_movl_T1_l1,
204 gen_op_movl_T1_l2,
205 gen_op_movl_T1_l3,
206 gen_op_movl_T1_l4,
207 gen_op_movl_T1_l5,
208 gen_op_movl_T1_l6,
209 gen_op_movl_T1_l7,
210 gen_op_movl_T1_i0,
211 gen_op_movl_T1_i1,
212 gen_op_movl_T1_i2,
213 gen_op_movl_T1_i3,
214 gen_op_movl_T1_i4,
215 gen_op_movl_T1_i5,
216 gen_op_movl_T1_i6,
217 gen_op_movl_T1_i7,
218 },
219 {
220 gen_op_movl_T2_g0,
221 gen_op_movl_T2_g1,
222 gen_op_movl_T2_g2,
223 gen_op_movl_T2_g3,
224 gen_op_movl_T2_g4,
225 gen_op_movl_T2_g5,
226 gen_op_movl_T2_g6,
227 gen_op_movl_T2_g7,
228 gen_op_movl_T2_o0,
229 gen_op_movl_T2_o1,
230 gen_op_movl_T2_o2,
231 gen_op_movl_T2_o3,
232 gen_op_movl_T2_o4,
233 gen_op_movl_T2_o5,
234 gen_op_movl_T2_o6,
235 gen_op_movl_T2_o7,
236 gen_op_movl_T2_l0,
237 gen_op_movl_T2_l1,
238 gen_op_movl_T2_l2,
239 gen_op_movl_T2_l3,
240 gen_op_movl_T2_l4,
241 gen_op_movl_T2_l5,
242 gen_op_movl_T2_l6,
243 gen_op_movl_T2_l7,
244 gen_op_movl_T2_i0,
245 gen_op_movl_T2_i1,
246 gen_op_movl_T2_i2,
247 gen_op_movl_T2_i3,
248 gen_op_movl_T2_i4,
249 gen_op_movl_T2_i5,
250 gen_op_movl_T2_i6,
251 gen_op_movl_T2_i7,
252 }
253 };
254
255 static GenOpFunc1 *gen_op_movl_TN_im[3] = {
256 gen_op_movl_T0_im,
257 gen_op_movl_T1_im,
258 gen_op_movl_T2_im
259 };
260
261 #define GEN32(func, NAME) \
262 static GenOpFunc *NAME ## _table [32] = { \
263 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
264 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
265 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
266 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
267 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
268 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
269 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
270 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
271 }; \
272 static inline void func(int n) \
273 { \
274 NAME ## _table[n](); \
275 }
276
277 /* floating point registers moves */
278 GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fprf);
279 GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fprf);
280 GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fprf);
281 GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fprf);
282 GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fprf);
283 GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fprf);
284
285 GEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fprf);
286 GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf);
287 GEN32(gen_op_load_fpr_DT2, gen_op_load_fpr_DT2_fprf);
288 GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf);
289 GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
290 GEN32(gen_op_store_DT2_fpr, gen_op_store_DT2_fpr_fprf);
291
292 #if defined(CONFIG_USER_ONLY)
293 #define gen_op_ldst(name) gen_op_##name##_raw()
294 #define OP_LD_TABLE(width)
295 #define supervisor(dc) 0
296 #else
297 #define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
298 #define OP_LD_TABLE(width) \
299 static GenOpFunc *gen_op_##width[] = { \
300 &gen_op_##width##_user, \
301 &gen_op_##width##_kernel, \
302 }; \
303 \
304 static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
305 { \
306 int asi; \
307 \
308 asi = GET_FIELD(insn, 19, 26); \
309 switch (asi) { \
310 case 10: /* User data access */ \
311 gen_op_##width##_user(); \
312 break; \
313 case 11: /* Supervisor data access */ \
314 gen_op_##width##_kernel(); \
315 break; \
316 case 0x20 ... 0x2f: /* MMU passthrough */ \
317 if (is_ld) \
318 gen_op_ld_asi(asi, size, sign); \
319 else \
320 gen_op_st_asi(asi, size, sign); \
321 break; \
322 default: \
323 if (is_ld) \
324 gen_op_ld_asi(asi, size, sign); \
325 else \
326 gen_op_st_asi(asi, size, sign); \
327 break; \
328 } \
329 }
330
331 #define supervisor(dc) (dc->mem_idx == 1)
332 #endif
333
334 OP_LD_TABLE(ld);
335 OP_LD_TABLE(st);
336 OP_LD_TABLE(ldub);
337 OP_LD_TABLE(lduh);
338 OP_LD_TABLE(ldsb);
339 OP_LD_TABLE(ldsh);
340 OP_LD_TABLE(stb);
341 OP_LD_TABLE(sth);
342 OP_LD_TABLE(std);
343 OP_LD_TABLE(ldstub);
344 OP_LD_TABLE(swap);
345 OP_LD_TABLE(ldd);
346 OP_LD_TABLE(stf);
347 OP_LD_TABLE(stdf);
348 OP_LD_TABLE(ldf);
349 OP_LD_TABLE(lddf);
350
351 static inline void gen_movl_imm_TN(int reg, int imm)
352 {
353 gen_op_movl_TN_im[reg] (imm);
354 }
355
356 static inline void gen_movl_imm_T1(int val)
357 {
358 gen_movl_imm_TN(1, val);
359 }
360
361 static inline void gen_movl_imm_T0(int val)
362 {
363 gen_movl_imm_TN(0, val);
364 }
365
366 static inline void gen_movl_reg_TN(int reg, int t)
367 {
368 if (reg)
369 gen_op_movl_reg_TN[t][reg] ();
370 else
371 gen_movl_imm_TN(t, 0);
372 }
373
374 static inline void gen_movl_reg_T0(int reg)
375 {
376 gen_movl_reg_TN(reg, 0);
377 }
378
379 static inline void gen_movl_reg_T1(int reg)
380 {
381 gen_movl_reg_TN(reg, 1);
382 }
383
384 static inline void gen_movl_reg_T2(int reg)
385 {
386 gen_movl_reg_TN(reg, 2);
387 }
388
389 static inline void gen_movl_TN_reg(int reg, int t)
390 {
391 if (reg)
392 gen_op_movl_TN_reg[t][reg] ();
393 }
394
395 static inline void gen_movl_T0_reg(int reg)
396 {
397 gen_movl_TN_reg(reg, 0);
398 }
399
400 static inline void gen_movl_T1_reg(int reg)
401 {
402 gen_movl_TN_reg(reg, 1);
403 }
404
405 /* call this function before using T2 as it may have been set for a jump */
406 static inline void flush_T2(DisasContext * dc)
407 {
408 if (dc->npc == JUMP_PC) {
409 gen_op_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
410 dc->npc = DYNAMIC_PC;
411 }
412 }
413
414 static inline void save_npc(DisasContext * dc)
415 {
416 if (dc->npc == JUMP_PC) {
417 gen_op_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
418 dc->npc = DYNAMIC_PC;
419 } else if (dc->npc != DYNAMIC_PC) {
420 gen_op_movl_npc_im(dc->npc);
421 }
422 }
423
424 static inline void save_state(DisasContext * dc)
425 {
426 gen_op_jmp_im((uint32_t)dc->pc);
427 save_npc(dc);
428 }
429
430 static void gen_cond(int cond)
431 {
432 switch (cond) {
433 case 0x0:
434 gen_op_movl_T2_0();
435 break;
436 case 0x1:
437 gen_op_eval_be();
438 break;
439 case 0x2:
440 gen_op_eval_ble();
441 break;
442 case 0x3:
443 gen_op_eval_bl();
444 break;
445 case 0x4:
446 gen_op_eval_bleu();
447 break;
448 case 0x5:
449 gen_op_eval_bcs();
450 break;
451 case 0x6:
452 gen_op_eval_bneg();
453 break;
454 case 0x7:
455 gen_op_eval_bvs();
456 break;
457 case 0x8:
458 gen_op_movl_T2_1();
459 break;
460 case 0x9:
461 gen_op_eval_bne();
462 break;
463 case 0xa:
464 gen_op_eval_bg();
465 break;
466 case 0xb:
467 gen_op_eval_bge();
468 break;
469 case 0xc:
470 gen_op_eval_bgu();
471 break;
472 case 0xd:
473 gen_op_eval_bcc();
474 break;
475 case 0xe:
476 gen_op_eval_bpos();
477 break;
478 default:
479 case 0xf:
480 gen_op_eval_bvc();
481 break;
482 }
483 }
484
485 static void gen_fcond(int cond)
486 {
487 switch (cond) {
488 case 0x0:
489 gen_op_movl_T2_0();
490 break;
491 case 0x1:
492 gen_op_eval_fbne();
493 break;
494 case 0x2:
495 gen_op_eval_fblg();
496 break;
497 case 0x3:
498 gen_op_eval_fbul();
499 break;
500 case 0x4:
501 gen_op_eval_fbl();
502 break;
503 case 0x5:
504 gen_op_eval_fbug();
505 break;
506 case 0x6:
507 gen_op_eval_fbg();
508 break;
509 case 0x7:
510 gen_op_eval_fbu();
511 break;
512 case 0x8:
513 gen_op_movl_T2_1();
514 break;
515 case 0x9:
516 gen_op_eval_fbe();
517 break;
518 case 0xa:
519 gen_op_eval_fbue();
520 break;
521 case 0xb:
522 gen_op_eval_fbge();
523 break;
524 case 0xc:
525 gen_op_eval_fbuge();
526 break;
527 case 0xd:
528 gen_op_eval_fble();
529 break;
530 case 0xe:
531 gen_op_eval_fbule();
532 break;
533 default:
534 case 0xf:
535 gen_op_eval_fbo();
536 break;
537 }
538 }
539
540 static void do_branch(DisasContext * dc, uint32_t target, uint32_t insn)
541 {
542 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
543 target += (uint32_t) dc->pc;
544 if (cond == 0x0) {
545 /* unconditional not taken */
546 if (a) {
547 dc->pc = dc->npc + 4;
548 dc->npc = dc->pc + 4;
549 } else {
550 dc->pc = dc->npc;
551 dc->npc = dc->pc + 4;
552 }
553 } else if (cond == 0x8) {
554 /* unconditional taken */
555 if (a) {
556 dc->pc = target;
557 dc->npc = dc->pc + 4;
558 } else {
559 dc->pc = dc->npc;
560 dc->npc = target;
561 }
562 } else {
563 flush_T2(dc);
564 gen_cond(cond);
565 if (a) {
566 gen_op_branch_a((long)dc->tb, target, dc->npc);
567 dc->is_br = 1;
568 } else {
569 dc->pc = dc->npc;
570 dc->jump_pc[0] = target;
571 dc->jump_pc[1] = dc->npc + 4;
572 dc->npc = JUMP_PC;
573 }
574 }
575 }
576
577 static void do_fbranch(DisasContext * dc, uint32_t target, uint32_t insn)
578 {
579 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
580 target += (uint32_t) dc->pc;
581 if (cond == 0x0) {
582 /* unconditional not taken */
583 if (a) {
584 dc->pc = dc->npc + 4;
585 dc->npc = dc->pc + 4;
586 } else {
587 dc->pc = dc->npc;
588 dc->npc = dc->pc + 4;
589 }
590 } else if (cond == 0x8) {
591 /* unconditional taken */
592 if (a) {
593 dc->pc = target;
594 dc->npc = dc->pc + 4;
595 } else {
596 dc->pc = dc->npc;
597 dc->npc = target;
598 }
599 } else {
600 flush_T2(dc);
601 gen_fcond(cond);
602 if (a) {
603 gen_op_branch_a((long)dc->tb, target, dc->npc);
604 dc->is_br = 1;
605 } else {
606 dc->pc = dc->npc;
607 dc->jump_pc[0] = target;
608 dc->jump_pc[1] = dc->npc + 4;
609 dc->npc = JUMP_PC;
610 }
611 }
612 }
613
614 static void gen_debug(DisasContext *s, uint32_t pc)
615 {
616 gen_op_jmp_im(pc);
617 gen_op_debug();
618 s->is_br = 1;
619 }
620
621 #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
622
623 static int sign_extend(int x, int len)
624 {
625 len = 32 - len;
626 return (x << len) >> len;
627 }
628
629 static void disas_sparc_insn(DisasContext * dc)
630 {
631 unsigned int insn, opc, rs1, rs2, rd;
632
633 insn = ldl_code((uint8_t *)dc->pc);
634 opc = GET_FIELD(insn, 0, 1);
635
636 rd = GET_FIELD(insn, 2, 6);
637 switch (opc) {
638 case 0: /* branches/sethi */
639 {
640 unsigned int xop = GET_FIELD(insn, 7, 9);
641 int target;
642 target = GET_FIELD(insn, 10, 31);
643 switch (xop) {
644 case 0x0:
645 case 0x1: /* UNIMPL */
646 default:
647 goto illegal_insn;
648 case 0x2: /* BN+x */
649 {
650 target <<= 2;
651 target = sign_extend(target, 22);
652 do_branch(dc, target, insn);
653 goto jmp_insn;
654 }
655 case 0x6: /* FBN+x */
656 {
657 target <<= 2;
658 target = sign_extend(target, 22);
659 do_fbranch(dc, target, insn);
660 goto jmp_insn;
661 }
662 case 0x4: /* SETHI */
663 gen_movl_imm_T0(target << 10);
664 gen_movl_T0_reg(rd);
665 break;
666 case 0x5: /*CBN+x */
667 break;
668 }
669 break;
670 }
671 case 1:
672 /*CALL*/ {
673 unsigned int target = GET_FIELDs(insn, 2, 31) << 2;
674
675 gen_op_movl_T0_im((long) (dc->pc));
676 gen_movl_T0_reg(15);
677 target = dc->pc + target;
678 dc->pc = dc->npc;
679 dc->npc = target;
680 }
681 goto jmp_insn;
682 case 2: /* FPU & Logical Operations */
683 {
684 unsigned int xop = GET_FIELD(insn, 7, 12);
685 if (xop == 0x3a) { /* generate trap */
686 int cond;
687 rs1 = GET_FIELD(insn, 13, 17);
688 gen_movl_reg_T0(rs1);
689 if (IS_IMM) {
690 rs2 = GET_FIELD(insn, 25, 31);
691 if (rs2 != 0) {
692 gen_movl_imm_T1(rs2);
693 gen_op_add_T1_T0();
694 }
695 } else {
696 rs2 = GET_FIELD(insn, 27, 31);
697 gen_movl_reg_T1(rs2);
698 gen_op_add_T1_T0();
699 }
700 save_state(dc);
701 cond = GET_FIELD(insn, 3, 6);
702 if (cond == 0x8) {
703 gen_op_trap_T0();
704 dc->is_br = 1;
705 goto jmp_insn;
706 } else {
707 gen_op_trapcc_T0();
708 }
709 } else if (xop == 0x28) {
710 rs1 = GET_FIELD(insn, 13, 17);
711 switch(rs1) {
712 case 0: /* rdy */
713 gen_op_rdy();
714 gen_movl_T0_reg(rd);
715 break;
716 case 15: /* stbar */
717 break; /* no effect? */
718 default:
719 goto illegal_insn;
720 }
721 #if !defined(CONFIG_USER_ONLY)
722 } else if (xop == 0x29) {
723 if (!supervisor(dc))
724 goto priv_insn;
725 gen_op_rdpsr();
726 gen_movl_T0_reg(rd);
727 break;
728 } else if (xop == 0x2a) {
729 if (!supervisor(dc))
730 goto priv_insn;
731 gen_op_rdwim();
732 gen_movl_T0_reg(rd);
733 break;
734 } else if (xop == 0x2b) {
735 if (!supervisor(dc))
736 goto priv_insn;
737 gen_op_rdtbr();
738 gen_movl_T0_reg(rd);
739 break;
740 #endif
741 } else if (xop == 0x34 || xop == 0x35) { /* FPU Operations */
742 rs1 = GET_FIELD(insn, 13, 17);
743 rs2 = GET_FIELD(insn, 27, 31);
744 xop = GET_FIELD(insn, 18, 26);
745 switch (xop) {
746 case 0x1: /* fmovs */
747 gen_op_load_fpr_FT0(rs2);
748 gen_op_store_FT0_fpr(rd);
749 break;
750 case 0x5: /* fnegs */
751 gen_op_load_fpr_FT1(rs2);
752 gen_op_fnegs();
753 gen_op_store_FT0_fpr(rd);
754 break;
755 case 0x9: /* fabss */
756 gen_op_load_fpr_FT1(rs2);
757 gen_op_fabss();
758 gen_op_store_FT0_fpr(rd);
759 break;
760 case 0x29: /* fsqrts */
761 gen_op_load_fpr_FT1(rs2);
762 gen_op_fsqrts();
763 gen_op_store_FT0_fpr(rd);
764 break;
765 case 0x2a: /* fsqrtd */
766 gen_op_load_fpr_DT1(rs2);
767 gen_op_fsqrtd();
768 gen_op_store_DT0_fpr(rd);
769 break;
770 case 0x41:
771 gen_op_load_fpr_FT0(rs1);
772 gen_op_load_fpr_FT1(rs2);
773 gen_op_fadds();
774 gen_op_store_FT0_fpr(rd);
775 break;
776 case 0x42:
777 gen_op_load_fpr_DT0(rs1);
778 gen_op_load_fpr_DT1(rs2);
779 gen_op_faddd();
780 gen_op_store_DT0_fpr(rd);
781 break;
782 case 0x45:
783 gen_op_load_fpr_FT0(rs1);
784 gen_op_load_fpr_FT1(rs2);
785 gen_op_fsubs();
786 gen_op_store_FT0_fpr(rd);
787 break;
788 case 0x46:
789 gen_op_load_fpr_DT0(rs1);
790 gen_op_load_fpr_DT1(rs2);
791 gen_op_fsubd();
792 gen_op_store_DT0_fpr(rd);
793 break;
794 case 0x49:
795 gen_op_load_fpr_FT0(rs1);
796 gen_op_load_fpr_FT1(rs2);
797 gen_op_fmuls();
798 gen_op_store_FT0_fpr(rd);
799 break;
800 case 0x4a:
801 gen_op_load_fpr_DT0(rs1);
802 gen_op_load_fpr_DT1(rs2);
803 gen_op_fmuld();
804 gen_op_store_DT0_fpr(rd);
805 break;
806 case 0x4d:
807 gen_op_load_fpr_FT0(rs1);
808 gen_op_load_fpr_FT1(rs2);
809 gen_op_fdivs();
810 gen_op_store_FT0_fpr(rd);
811 break;
812 case 0x4e:
813 gen_op_load_fpr_DT0(rs1);
814 gen_op_load_fpr_DT1(rs2);
815 gen_op_fdivd();
816 gen_op_store_DT0_fpr(rd);
817 break;
818 case 0x51:
819 gen_op_load_fpr_FT0(rs1);
820 gen_op_load_fpr_FT1(rs2);
821 gen_op_fcmps();
822 break;
823 case 0x52:
824 gen_op_load_fpr_DT0(rs1);
825 gen_op_load_fpr_DT1(rs2);
826 gen_op_fcmpd();
827 break;
828 case 0x55: /* fcmpes */
829 gen_op_load_fpr_FT0(rs1);
830 gen_op_load_fpr_FT1(rs2);
831 gen_op_fcmps(); /* XXX */
832 break;
833 case 0x56: /* fcmped */
834 gen_op_load_fpr_DT0(rs1);
835 gen_op_load_fpr_DT1(rs2);
836 gen_op_fcmpd(); /* XXX */
837 break;
838 case 0x69:
839 gen_op_load_fpr_FT0(rs1);
840 gen_op_load_fpr_FT1(rs2);
841 gen_op_fsmuld();
842 gen_op_store_DT0_fpr(rd);
843 break;
844 case 0xc4:
845 gen_op_load_fpr_FT1(rs2);
846 gen_op_fitos();
847 gen_op_store_FT0_fpr(rd);
848 break;
849 case 0xc6:
850 gen_op_load_fpr_DT1(rs2);
851 gen_op_fdtos();
852 gen_op_store_FT0_fpr(rd);
853 break;
854 case 0xc8:
855 gen_op_load_fpr_FT1(rs2);
856 gen_op_fitod();
857 gen_op_store_DT0_fpr(rd);
858 break;
859 case 0xc9:
860 gen_op_load_fpr_FT1(rs2);
861 gen_op_fstod();
862 gen_op_store_DT0_fpr(rd);
863 break;
864 case 0xd1:
865 gen_op_load_fpr_FT1(rs2);
866 gen_op_fstoi();
867 gen_op_store_FT0_fpr(rd);
868 break;
869 case 0xd2:
870 gen_op_load_fpr_DT1(rs2);
871 gen_op_fdtoi();
872 gen_op_store_FT0_fpr(rd);
873 break;
874 default:
875 goto illegal_insn;
876 }
877 } else {
878 rs1 = GET_FIELD(insn, 13, 17);
879 gen_movl_reg_T0(rs1);
880 if (IS_IMM) { /* immediate */
881 rs2 = GET_FIELDs(insn, 19, 31);
882 gen_movl_imm_T1(rs2);
883 } else { /* register */
884 rs2 = GET_FIELD(insn, 27, 31);
885 gen_movl_reg_T1(rs2);
886 }
887 if (xop < 0x20) {
888 switch (xop & ~0x10) {
889 case 0x0:
890 if (xop & 0x10)
891 gen_op_add_T1_T0_cc();
892 else
893 gen_op_add_T1_T0();
894 break;
895 case 0x1:
896 gen_op_and_T1_T0();
897 if (xop & 0x10)
898 gen_op_logic_T0_cc();
899 break;
900 case 0x2:
901 gen_op_or_T1_T0();
902 if (xop & 0x10)
903 gen_op_logic_T0_cc();
904 break;
905 case 0x3:
906 gen_op_xor_T1_T0();
907 if (xop & 0x10)
908 gen_op_logic_T0_cc();
909 break;
910 case 0x4:
911 if (xop & 0x10)
912 gen_op_sub_T1_T0_cc();
913 else
914 gen_op_sub_T1_T0();
915 break;
916 case 0x5:
917 gen_op_andn_T1_T0();
918 if (xop & 0x10)
919 gen_op_logic_T0_cc();
920 break;
921 case 0x6:
922 gen_op_orn_T1_T0();
923 if (xop & 0x10)
924 gen_op_logic_T0_cc();
925 break;
926 case 0x7:
927 gen_op_xnor_T1_T0();
928 if (xop & 0x10)
929 gen_op_logic_T0_cc();
930 break;
931 case 0x8:
932 gen_op_addx_T1_T0();
933 if (xop & 0x10)
934 gen_op_set_flags();
935 break;
936 case 0xa:
937 gen_op_umul_T1_T0();
938 if (xop & 0x10)
939 gen_op_logic_T0_cc();
940 break;
941 case 0xb:
942 gen_op_smul_T1_T0();
943 if (xop & 0x10)
944 gen_op_logic_T0_cc();
945 break;
946 case 0xc:
947 gen_op_subx_T1_T0();
948 if (xop & 0x10)
949 gen_op_set_flags();
950 break;
951 case 0xe:
952 gen_op_udiv_T1_T0();
953 if (xop & 0x10)
954 gen_op_div_cc();
955 break;
956 case 0xf:
957 gen_op_sdiv_T1_T0();
958 if (xop & 0x10)
959 gen_op_div_cc();
960 break;
961 default:
962 goto illegal_insn;
963 }
964 gen_movl_T0_reg(rd);
965 } else {
966 switch (xop) {
967 case 0x24: /* mulscc */
968 gen_op_mulscc_T1_T0();
969 gen_movl_T0_reg(rd);
970 break;
971 case 0x25: /* SLL */
972 gen_op_sll();
973 gen_movl_T0_reg(rd);
974 break;
975 case 0x26:
976 gen_op_srl();
977 gen_movl_T0_reg(rd);
978 break;
979 case 0x27:
980 gen_op_sra();
981 gen_movl_T0_reg(rd);
982 break;
983 case 0x30:
984 {
985 gen_op_xor_T1_T0();
986 switch(rd) {
987 case 0:
988 gen_op_wry();
989 break;
990 default:
991 goto illegal_insn;
992 }
993 }
994 break;
995 #if !defined(CONFIG_USER_ONLY)
996 case 0x31:
997 {
998 if (!supervisor(dc))
999 goto priv_insn;
1000 gen_op_xor_T1_T0();
1001 gen_op_wrpsr();
1002 }
1003 break;
1004 case 0x32:
1005 {
1006 if (!supervisor(dc))
1007 goto priv_insn;
1008 gen_op_xor_T1_T0();
1009 gen_op_wrwim();
1010 }
1011 break;
1012 case 0x33:
1013 {
1014 if (!supervisor(dc))
1015 goto priv_insn;
1016 gen_op_xor_T1_T0();
1017 gen_op_wrtbr();
1018 }
1019 break;
1020 #endif
1021 case 0x38: /* jmpl */
1022 {
1023 gen_op_add_T1_T0();
1024 gen_op_movl_npc_T0();
1025 if (rd != 0) {
1026 gen_op_movl_T0_im((long) (dc->pc));
1027 gen_movl_T0_reg(rd);
1028 }
1029 dc->pc = dc->npc;
1030 dc->npc = DYNAMIC_PC;
1031 }
1032 goto jmp_insn;
1033 #if !defined(CONFIG_USER_ONLY)
1034 case 0x39: /* rett */
1035 {
1036 if (!supervisor(dc))
1037 goto priv_insn;
1038 gen_op_add_T1_T0();
1039 gen_op_movl_npc_T0();
1040 gen_op_rett();
1041 #if 0
1042 dc->pc = dc->npc;
1043 dc->npc = DYNAMIC_PC;
1044 #endif
1045 }
1046 #if 0
1047 goto jmp_insn;
1048 #endif
1049 break;
1050 #endif
1051 case 0x3b: /* flush */
1052 gen_op_add_T1_T0();
1053 gen_op_flush_T0();
1054 break;
1055 case 0x3c: /* save */
1056 save_state(dc);
1057 gen_op_add_T1_T0();
1058 gen_op_save();
1059 gen_movl_T0_reg(rd);
1060 break;
1061 case 0x3d: /* restore */
1062 save_state(dc);
1063 gen_op_add_T1_T0();
1064 gen_op_restore();
1065 gen_movl_T0_reg(rd);
1066 break;
1067 default:
1068 goto illegal_insn;
1069 }
1070 }
1071 }
1072 break;
1073 }
1074 case 3: /* load/store instructions */
1075 {
1076 unsigned int xop = GET_FIELD(insn, 7, 12);
1077 rs1 = GET_FIELD(insn, 13, 17);
1078 gen_movl_reg_T0(rs1);
1079 if (IS_IMM) { /* immediate */
1080 rs2 = GET_FIELDs(insn, 19, 31);
1081 if (rs2 != 0) {
1082 gen_movl_imm_T1(rs2);
1083 gen_op_add_T1_T0();
1084 }
1085 } else { /* register */
1086 rs2 = GET_FIELD(insn, 27, 31);
1087 gen_movl_reg_T1(rs2);
1088 gen_op_add_T1_T0();
1089 }
1090 if (xop < 4 || (xop > 7 && xop < 0x14) || \
1091 (xop > 0x17 && xop < 0x20)) {
1092 switch (xop) {
1093 case 0x0: /* load word */
1094 gen_op_ldst(ld);
1095 break;
1096 case 0x1: /* load unsigned byte */
1097 gen_op_ldst(ldub);
1098 break;
1099 case 0x2: /* load unsigned halfword */
1100 gen_op_ldst(lduh);
1101 break;
1102 case 0x3: /* load double word */
1103 gen_op_ldst(ldd);
1104 gen_movl_T0_reg(rd + 1);
1105 break;
1106 case 0x9: /* load signed byte */
1107 gen_op_ldst(ldsb);
1108 break;
1109 case 0xa: /* load signed halfword */
1110 gen_op_ldst(ldsh);
1111 break;
1112 case 0xd: /* ldstub -- XXX: should be atomically */
1113 gen_op_ldst(ldstub);
1114 break;
1115 case 0x0f: /* swap register with memory. Also atomically */
1116 gen_op_ldst(swap);
1117 break;
1118 case 0x10: /* load word alternate */
1119 if (!supervisor(dc))
1120 goto priv_insn;
1121 gen_op_lda(insn, 1, 4, 0);
1122 break;
1123 case 0x11: /* load unsigned byte alternate */
1124 if (!supervisor(dc))
1125 goto priv_insn;
1126 gen_op_lduba(insn, 1, 1, 0);
1127 break;
1128 case 0x12: /* load unsigned halfword alternate */
1129 if (!supervisor(dc))
1130 goto priv_insn;
1131 gen_op_lduha(insn, 1, 2, 0);
1132 break;
1133 case 0x13: /* load double word alternate */
1134 if (!supervisor(dc))
1135 goto priv_insn;
1136 gen_op_ldda(insn, 1, 8, 0);
1137 gen_movl_T0_reg(rd + 1);
1138 break;
1139 case 0x19: /* load signed byte alternate */
1140 if (!supervisor(dc))
1141 goto priv_insn;
1142 gen_op_ldsba(insn, 1, 1, 1);
1143 break;
1144 case 0x1a: /* load signed halfword alternate */
1145 if (!supervisor(dc))
1146 goto priv_insn;
1147 gen_op_ldsha(insn, 1, 2 ,1);
1148 break;
1149 case 0x1d: /* ldstuba -- XXX: should be atomically */
1150 if (!supervisor(dc))
1151 goto priv_insn;
1152 gen_op_ldstuba(insn, 1, 1, 0);
1153 break;
1154 case 0x1f: /* swap reg with alt. memory. Also atomically */
1155 if (!supervisor(dc))
1156 goto priv_insn;
1157 gen_op_swapa(insn, 1, 4, 0);
1158 break;
1159 }
1160 gen_movl_T1_reg(rd);
1161 } else if (xop >= 0x20 && xop < 0x24) {
1162 switch (xop) {
1163 case 0x20: /* load fpreg */
1164 gen_op_ldst(ldf);
1165 gen_op_store_FT0_fpr(rd);
1166 break;
1167 case 0x21: /* load fsr */
1168 gen_op_ldfsr();
1169 break;
1170 case 0x23: /* load double fpreg */
1171 gen_op_ldst(lddf);
1172 gen_op_store_DT0_fpr(rd);
1173 break;
1174 }
1175 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18)) {
1176 gen_movl_reg_T1(rd);
1177 switch (xop) {
1178 case 0x4:
1179 gen_op_ldst(st);
1180 break;
1181 case 0x5:
1182 gen_op_ldst(stb);
1183 break;
1184 case 0x6:
1185 gen_op_ldst(sth);
1186 break;
1187 case 0x7:
1188 flush_T2(dc);
1189 gen_movl_reg_T2(rd + 1);
1190 gen_op_ldst(std);
1191 break;
1192 case 0x14:
1193 if (!supervisor(dc))
1194 goto priv_insn;
1195 gen_op_sta(insn, 0, 4, 0);
1196 break;
1197 case 0x15:
1198 if (!supervisor(dc))
1199 goto priv_insn;
1200 gen_op_stba(insn, 0, 1, 0);
1201 break;
1202 case 0x16:
1203 if (!supervisor(dc))
1204 goto priv_insn;
1205 gen_op_stha(insn, 0, 2, 0);
1206 break;
1207 case 0x17:
1208 if (!supervisor(dc))
1209 goto priv_insn;
1210 flush_T2(dc);
1211 gen_movl_reg_T2(rd + 1);
1212 gen_op_stda(insn, 0, 8, 0);
1213 break;
1214 }
1215 } else if (xop > 0x23 && xop < 0x28) {
1216 switch (xop) {
1217 case 0x24:
1218 gen_op_load_fpr_FT0(rd);
1219 gen_op_ldst(stf);
1220 break;
1221 case 0x25:
1222 gen_op_stfsr();
1223 break;
1224 case 0x27:
1225 gen_op_load_fpr_DT0(rd);
1226 gen_op_ldst(stdf);
1227 break;
1228 }
1229 } else if (xop > 0x33 && xop < 0x38) {
1230 /* Co-processor */
1231 }
1232 }
1233 }
1234 /* default case for non jump instructions */
1235 if (dc->npc == DYNAMIC_PC) {
1236 dc->pc = DYNAMIC_PC;
1237 gen_op_next_insn();
1238 } else if (dc->npc == JUMP_PC) {
1239 /* we can do a static jump */
1240 gen_op_branch2((long)dc->tb, dc->jump_pc[0], dc->jump_pc[1]);
1241 dc->is_br = 1;
1242 } else {
1243 dc->pc = dc->npc;
1244 dc->npc = dc->npc + 4;
1245 }
1246 jmp_insn:;
1247 return;
1248 illegal_insn:
1249 save_state(dc);
1250 gen_op_exception(TT_ILL_INSN);
1251 dc->is_br = 1;
1252 return;
1253 priv_insn:
1254 save_state(dc);
1255 gen_op_exception(TT_PRIV_INSN);
1256 dc->is_br = 1;
1257 }
1258
1259 static inline int gen_intermediate_code_internal(TranslationBlock * tb,
1260 int spc, CPUSPARCState *env)
1261 {
1262 target_ulong pc_start, last_pc;
1263 uint16_t *gen_opc_end;
1264 DisasContext dc1, *dc = &dc1;
1265 int j, lj = -1;
1266
1267 memset(dc, 0, sizeof(DisasContext));
1268 dc->tb = tb;
1269 pc_start = tb->pc;
1270 dc->pc = pc_start;
1271 dc->npc = (target_ulong) tb->cs_base;
1272 #if defined(CONFIG_USER_ONLY)
1273 dc->mem_idx = 0;
1274 #else
1275 dc->mem_idx = ((env->psrs) != 0);
1276 #endif
1277 gen_opc_ptr = gen_opc_buf;
1278 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
1279 gen_opparam_ptr = gen_opparam_buf;
1280
1281 env->access_type = ACCESS_CODE;
1282
1283 do {
1284 if (env->nb_breakpoints > 0) {
1285 for(j = 0; j < env->nb_breakpoints; j++) {
1286 if (env->breakpoints[j] == dc->pc) {
1287 gen_debug(dc, dc->pc);
1288 break;
1289 }
1290 }
1291 }
1292 if (spc) {
1293 if (loglevel > 0)
1294 fprintf(logfile, "Search PC...\n");
1295 j = gen_opc_ptr - gen_opc_buf;
1296 if (lj < j) {
1297 lj++;
1298 while (lj < j)
1299 gen_opc_instr_start[lj++] = 0;
1300 gen_opc_pc[lj] = dc->pc;
1301 gen_opc_npc[lj] = dc->npc;
1302 gen_opc_instr_start[lj] = 1;
1303 }
1304 }
1305 last_pc = dc->pc;
1306 disas_sparc_insn(dc);
1307 if (dc->is_br)
1308 break;
1309 /* if the next PC is different, we abort now */
1310 if (dc->pc != (last_pc + 4))
1311 break;
1312 } while ((gen_opc_ptr < gen_opc_end) &&
1313 (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
1314 if (!dc->is_br) {
1315 if (dc->pc != DYNAMIC_PC &&
1316 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
1317 /* static PC and NPC: we can use direct chaining */
1318 gen_op_branch((long)tb, dc->pc, dc->npc);
1319 } else {
1320 if (dc->pc != DYNAMIC_PC)
1321 gen_op_jmp_im(dc->pc);
1322 save_npc(dc);
1323 gen_op_movl_T0_0();
1324 gen_op_exit_tb();
1325 }
1326 }
1327 *gen_opc_ptr = INDEX_op_end;
1328 if (spc) {
1329 j = gen_opc_ptr - gen_opc_buf;
1330 lj++;
1331 while (lj <= j)
1332 gen_opc_instr_start[lj++] = 0;
1333 tb->size = 0;
1334 #if 0
1335 if (loglevel > 0) {
1336 page_dump(logfile);
1337 }
1338 #endif
1339 } else {
1340 tb->size = dc->npc - pc_start;
1341 }
1342 #ifdef DEBUG_DISAS
1343 if (loglevel & CPU_LOG_TB_IN_ASM) {
1344 fprintf(logfile, "--------------\n");
1345 fprintf(logfile, "IN: %s\n", lookup_symbol((uint8_t *)pc_start));
1346 disas(logfile, (uint8_t *)pc_start, last_pc + 4 - pc_start, 0, 0);
1347 fprintf(logfile, "\n");
1348 if (loglevel & CPU_LOG_TB_OP) {
1349 fprintf(logfile, "OP:\n");
1350 dump_ops(gen_opc_buf, gen_opparam_buf);
1351 fprintf(logfile, "\n");
1352 }
1353 }
1354 #endif
1355
1356 env->access_type = ACCESS_DATA;
1357 return 0;
1358 }
1359
1360 int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
1361 {
1362 return gen_intermediate_code_internal(tb, 0, env);
1363 }
1364
1365 int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
1366 {
1367 return gen_intermediate_code_internal(tb, 1, env);
1368 }
1369
1370 CPUSPARCState *cpu_sparc_init(void)
1371 {
1372 CPUSPARCState *env;
1373
1374 cpu_exec_init();
1375
1376 if (!(env = malloc(sizeof(CPUSPARCState))))
1377 return (NULL);
1378 memset(env, 0, sizeof(*env));
1379 env->cwp = 0;
1380 env->wim = 1;
1381 env->regwptr = env->regbase + (env->cwp * 16);
1382 env->access_type = ACCESS_DATA;
1383 #if defined(CONFIG_USER_ONLY)
1384 env->user_mode_only = 1;
1385 #else
1386 /* Emulate Prom */
1387 env->psrs = 1;
1388 env->pc = 0x4000;
1389 env->npc = env->pc + 4;
1390 env->mmuregs[0] = (0x10<<24) | MMU_E; /* Impl 1, ver 0, MMU Enabled */
1391 env->mmuregs[1] = 0x3000 >> 4; /* MMU Context table */
1392 #endif
1393 cpu_single_env = env;
1394 return (env);
1395 }
1396
1397 #define GET_FLAG(a,b) ((env->psr & a)?b:'-')
1398
1399 void cpu_sparc_dump_state(CPUSPARCState * env, FILE * f, int flags)
1400 {
1401 int i, x;
1402
1403 fprintf(f, "pc: 0x%08x npc: 0x%08x\n", (int) env->pc, (int) env->npc);
1404 fprintf(f, "General Registers:\n");
1405 for (i = 0; i < 4; i++)
1406 fprintf(f, "%%g%c: 0x%08x\t", i + '0', env->gregs[i]);
1407 fprintf(f, "\n");
1408 for (; i < 8; i++)
1409 fprintf(f, "%%g%c: 0x%08x\t", i + '0', env->gregs[i]);
1410 fprintf(f, "\nCurrent Register Window:\n");
1411 for (x = 0; x < 3; x++) {
1412 for (i = 0; i < 4; i++)
1413 fprintf(f, "%%%c%d: 0x%08x\t",
1414 (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
1415 env->regwptr[i + x * 8]);
1416 fprintf(f, "\n");
1417 for (; i < 8; i++)
1418 fprintf(f, "%%%c%d: 0x%08x\t",
1419 (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
1420 env->regwptr[i + x * 8]);
1421 fprintf(f, "\n");
1422 }
1423 fprintf(f, "\nFloating Point Registers:\n");
1424 for (i = 0; i < 32; i++) {
1425 if ((i & 3) == 0)
1426 fprintf(f, "%%f%02d:", i);
1427 fprintf(f, " %016lf", env->fpr[i]);
1428 if ((i & 3) == 3)
1429 fprintf(f, "\n");
1430 }
1431 fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
1432 GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
1433 GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
1434 env->psrs?'S':'-', env->psrps?'P':'-',
1435 env->psret?'E':'-', env->wim);
1436 fprintf(f, "fsr: 0x%08x\n", env->fsr);
1437 }
1438
1439 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
1440 {
1441 return addr;
1442 }
1443
1444 void helper_flush(target_ulong addr)
1445 {
1446 addr &= ~7;
1447 tb_invalidate_page_range(addr, addr + 8);
1448 }
Qemu copy for testing