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[qemu.git] / target-sparc / translate.c
1 /*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5 Copyright (C) 2003 Fabrice Bellard
6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
16
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22 /*
23 TODO-list:
24
25 NPC/PC static optimisations (use JUMP_TB when possible)
26 FPU-Instructions
27 Privileged instructions
28 Coprocessor-Instructions
29 Optimize synthetic instructions
30 Optional alignment and privileged instruction check
31 */
32
33 #include <stdarg.h>
34 #include <stdlib.h>
35 #include <stdio.h>
36 #include <string.h>
37 #include <inttypes.h>
38
39 #include "cpu.h"
40 #include "exec-all.h"
41 #include "disas.h"
42
43 #define DEBUG_DISAS
44
45 #define DYNAMIC_PC 1 /* dynamic pc value */
46 #define JUMP_PC 2 /* dynamic pc value which takes only two values
47 according to jump_pc[T2] */
48
49 typedef struct DisasContext {
50 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
51 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
52 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
53 int is_br;
54 int mem_idx;
55 struct TranslationBlock *tb;
56 } DisasContext;
57
58 static uint16_t *gen_opc_ptr;
59 static uint32_t *gen_opparam_ptr;
60 extern FILE *logfile;
61 extern int loglevel;
62
63 enum {
64 #define DEF(s,n,copy_size) INDEX_op_ ## s,
65 #include "opc.h"
66 #undef DEF
67 NB_OPS
68 };
69
70 #include "gen-op.h"
71
72 #define GET_FIELD(X, FROM, TO) \
73 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
74
75 #define IS_IMM (insn & (1<<13))
76
77 static void disas_sparc_insn(DisasContext * dc);
78
79 static GenOpFunc *gen_op_movl_TN_reg[2][32] = {
80 {
81 gen_op_movl_g0_T0,
82 gen_op_movl_g1_T0,
83 gen_op_movl_g2_T0,
84 gen_op_movl_g3_T0,
85 gen_op_movl_g4_T0,
86 gen_op_movl_g5_T0,
87 gen_op_movl_g6_T0,
88 gen_op_movl_g7_T0,
89 gen_op_movl_o0_T0,
90 gen_op_movl_o1_T0,
91 gen_op_movl_o2_T0,
92 gen_op_movl_o3_T0,
93 gen_op_movl_o4_T0,
94 gen_op_movl_o5_T0,
95 gen_op_movl_o6_T0,
96 gen_op_movl_o7_T0,
97 gen_op_movl_l0_T0,
98 gen_op_movl_l1_T0,
99 gen_op_movl_l2_T0,
100 gen_op_movl_l3_T0,
101 gen_op_movl_l4_T0,
102 gen_op_movl_l5_T0,
103 gen_op_movl_l6_T0,
104 gen_op_movl_l7_T0,
105 gen_op_movl_i0_T0,
106 gen_op_movl_i1_T0,
107 gen_op_movl_i2_T0,
108 gen_op_movl_i3_T0,
109 gen_op_movl_i4_T0,
110 gen_op_movl_i5_T0,
111 gen_op_movl_i6_T0,
112 gen_op_movl_i7_T0,
113 },
114 {
115 gen_op_movl_g0_T1,
116 gen_op_movl_g1_T1,
117 gen_op_movl_g2_T1,
118 gen_op_movl_g3_T1,
119 gen_op_movl_g4_T1,
120 gen_op_movl_g5_T1,
121 gen_op_movl_g6_T1,
122 gen_op_movl_g7_T1,
123 gen_op_movl_o0_T1,
124 gen_op_movl_o1_T1,
125 gen_op_movl_o2_T1,
126 gen_op_movl_o3_T1,
127 gen_op_movl_o4_T1,
128 gen_op_movl_o5_T1,
129 gen_op_movl_o6_T1,
130 gen_op_movl_o7_T1,
131 gen_op_movl_l0_T1,
132 gen_op_movl_l1_T1,
133 gen_op_movl_l2_T1,
134 gen_op_movl_l3_T1,
135 gen_op_movl_l4_T1,
136 gen_op_movl_l5_T1,
137 gen_op_movl_l6_T1,
138 gen_op_movl_l7_T1,
139 gen_op_movl_i0_T1,
140 gen_op_movl_i1_T1,
141 gen_op_movl_i2_T1,
142 gen_op_movl_i3_T1,
143 gen_op_movl_i4_T1,
144 gen_op_movl_i5_T1,
145 gen_op_movl_i6_T1,
146 gen_op_movl_i7_T1,
147 }
148 };
149
150 static GenOpFunc *gen_op_movl_reg_TN[3][32] = {
151 {
152 gen_op_movl_T0_g0,
153 gen_op_movl_T0_g1,
154 gen_op_movl_T0_g2,
155 gen_op_movl_T0_g3,
156 gen_op_movl_T0_g4,
157 gen_op_movl_T0_g5,
158 gen_op_movl_T0_g6,
159 gen_op_movl_T0_g7,
160 gen_op_movl_T0_o0,
161 gen_op_movl_T0_o1,
162 gen_op_movl_T0_o2,
163 gen_op_movl_T0_o3,
164 gen_op_movl_T0_o4,
165 gen_op_movl_T0_o5,
166 gen_op_movl_T0_o6,
167 gen_op_movl_T0_o7,
168 gen_op_movl_T0_l0,
169 gen_op_movl_T0_l1,
170 gen_op_movl_T0_l2,
171 gen_op_movl_T0_l3,
172 gen_op_movl_T0_l4,
173 gen_op_movl_T0_l5,
174 gen_op_movl_T0_l6,
175 gen_op_movl_T0_l7,
176 gen_op_movl_T0_i0,
177 gen_op_movl_T0_i1,
178 gen_op_movl_T0_i2,
179 gen_op_movl_T0_i3,
180 gen_op_movl_T0_i4,
181 gen_op_movl_T0_i5,
182 gen_op_movl_T0_i6,
183 gen_op_movl_T0_i7,
184 },
185 {
186 gen_op_movl_T1_g0,
187 gen_op_movl_T1_g1,
188 gen_op_movl_T1_g2,
189 gen_op_movl_T1_g3,
190 gen_op_movl_T1_g4,
191 gen_op_movl_T1_g5,
192 gen_op_movl_T1_g6,
193 gen_op_movl_T1_g7,
194 gen_op_movl_T1_o0,
195 gen_op_movl_T1_o1,
196 gen_op_movl_T1_o2,
197 gen_op_movl_T1_o3,
198 gen_op_movl_T1_o4,
199 gen_op_movl_T1_o5,
200 gen_op_movl_T1_o6,
201 gen_op_movl_T1_o7,
202 gen_op_movl_T1_l0,
203 gen_op_movl_T1_l1,
204 gen_op_movl_T1_l2,
205 gen_op_movl_T1_l3,
206 gen_op_movl_T1_l4,
207 gen_op_movl_T1_l5,
208 gen_op_movl_T1_l6,
209 gen_op_movl_T1_l7,
210 gen_op_movl_T1_i0,
211 gen_op_movl_T1_i1,
212 gen_op_movl_T1_i2,
213 gen_op_movl_T1_i3,
214 gen_op_movl_T1_i4,
215 gen_op_movl_T1_i5,
216 gen_op_movl_T1_i6,
217 gen_op_movl_T1_i7,
218 },
219 {
220 gen_op_movl_T2_g0,
221 gen_op_movl_T2_g1,
222 gen_op_movl_T2_g2,
223 gen_op_movl_T2_g3,
224 gen_op_movl_T2_g4,
225 gen_op_movl_T2_g5,
226 gen_op_movl_T2_g6,
227 gen_op_movl_T2_g7,
228 gen_op_movl_T2_o0,
229 gen_op_movl_T2_o1,
230 gen_op_movl_T2_o2,
231 gen_op_movl_T2_o3,
232 gen_op_movl_T2_o4,
233 gen_op_movl_T2_o5,
234 gen_op_movl_T2_o6,
235 gen_op_movl_T2_o7,
236 gen_op_movl_T2_l0,
237 gen_op_movl_T2_l1,
238 gen_op_movl_T2_l2,
239 gen_op_movl_T2_l3,
240 gen_op_movl_T2_l4,
241 gen_op_movl_T2_l5,
242 gen_op_movl_T2_l6,
243 gen_op_movl_T2_l7,
244 gen_op_movl_T2_i0,
245 gen_op_movl_T2_i1,
246 gen_op_movl_T2_i2,
247 gen_op_movl_T2_i3,
248 gen_op_movl_T2_i4,
249 gen_op_movl_T2_i5,
250 gen_op_movl_T2_i6,
251 gen_op_movl_T2_i7,
252 }
253 };
254
255 static GenOpFunc1 *gen_op_movl_TN_im[3] = {
256 gen_op_movl_T0_im,
257 gen_op_movl_T1_im,
258 gen_op_movl_T2_im
259 };
260
261 #define GEN32(func, NAME) \
262 static GenOpFunc *NAME ## _table [32] = { \
263 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
264 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
265 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
266 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
267 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
268 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
269 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
270 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
271 }; \
272 static inline void func(int n) \
273 { \
274 NAME ## _table[n](); \
275 }
276
277 /* floating point registers moves */
278 GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fprf);
279 GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fprf);
280 GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fprf);
281 GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fprf);
282 GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fprf);
283 GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fprf);
284
285 GEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fprf);
286 GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf);
287 GEN32(gen_op_load_fpr_DT2, gen_op_load_fpr_DT2_fprf);
288 GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf);
289 GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
290 GEN32(gen_op_store_DT2_fpr, gen_op_store_DT2_fpr_fprf);
291
292 #if defined(CONFIG_USER_ONLY)
293 #define gen_op_ldst(name) gen_op_##name##_raw()
294 #define OP_LD_TABLE(width)
295 #define supervisor(dc) 0
296 #else
297 #define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
298 #define OP_LD_TABLE(width) \
299 static GenOpFunc *gen_op_##width[] = { \
300 &gen_op_##width##_user, \
301 &gen_op_##width##_kernel, \
302 }; \
303 \
304 static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
305 { \
306 int asi; \
307 \
308 asi = GET_FIELD(insn, 19, 26); \
309 switch (asi) { \
310 case 10: /* User data access */ \
311 gen_op_##width##_user(); \
312 break; \
313 case 11: /* Supervisor data access */ \
314 gen_op_##width##_kernel(); \
315 break; \
316 case 0x20 ... 0x2f: /* MMU passthrough */ \
317 if (is_ld) \
318 gen_op_ld_asi(asi, size, sign); \
319 else \
320 gen_op_st_asi(asi, size, sign); \
321 break; \
322 default: \
323 if (is_ld) \
324 gen_op_ld_asi(asi, size, sign); \
325 else \
326 gen_op_st_asi(asi, size, sign); \
327 break; \
328 } \
329 }
330
331 #define supervisor(dc) (dc->mem_idx == 1)
332 #endif
333
334 OP_LD_TABLE(ld);
335 OP_LD_TABLE(st);
336 OP_LD_TABLE(ldub);
337 OP_LD_TABLE(lduh);
338 OP_LD_TABLE(ldsb);
339 OP_LD_TABLE(ldsh);
340 OP_LD_TABLE(stb);
341 OP_LD_TABLE(sth);
342 OP_LD_TABLE(std);
343 OP_LD_TABLE(ldstub);
344 OP_LD_TABLE(swap);
345 OP_LD_TABLE(ldd);
346 OP_LD_TABLE(stf);
347 OP_LD_TABLE(stdf);
348 OP_LD_TABLE(ldf);
349 OP_LD_TABLE(lddf);
350
351 static inline void gen_movl_imm_TN(int reg, int imm)
352 {
353 gen_op_movl_TN_im[reg] (imm);
354 }
355
356 static inline void gen_movl_imm_T1(int val)
357 {
358 gen_movl_imm_TN(1, val);
359 }
360
361 static inline void gen_movl_imm_T0(int val)
362 {
363 gen_movl_imm_TN(0, val);
364 }
365
366 static inline void gen_movl_reg_TN(int reg, int t)
367 {
368 if (reg)
369 gen_op_movl_reg_TN[t][reg] ();
370 else
371 gen_movl_imm_TN(t, 0);
372 }
373
374 static inline void gen_movl_reg_T0(int reg)
375 {
376 gen_movl_reg_TN(reg, 0);
377 }
378
379 static inline void gen_movl_reg_T1(int reg)
380 {
381 gen_movl_reg_TN(reg, 1);
382 }
383
384 static inline void gen_movl_reg_T2(int reg)
385 {
386 gen_movl_reg_TN(reg, 2);
387 }
388
389 static inline void gen_movl_TN_reg(int reg, int t)
390 {
391 if (reg)
392 gen_op_movl_TN_reg[t][reg] ();
393 }
394
395 static inline void gen_movl_T0_reg(int reg)
396 {
397 gen_movl_TN_reg(reg, 0);
398 }
399
400 static inline void gen_movl_T1_reg(int reg)
401 {
402 gen_movl_TN_reg(reg, 1);
403 }
404
405 /* call this function before using T2 as it may have been set for a jump */
406 static inline void flush_T2(DisasContext * dc)
407 {
408 if (dc->npc == JUMP_PC) {
409 gen_op_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
410 dc->npc = DYNAMIC_PC;
411 }
412 }
413
414 static inline void save_npc(DisasContext * dc)
415 {
416 if (dc->npc == JUMP_PC) {
417 gen_op_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
418 dc->npc = DYNAMIC_PC;
419 } else if (dc->npc != DYNAMIC_PC) {
420 gen_op_movl_npc_im(dc->npc);
421 }
422 }
423
424 static inline void save_state(DisasContext * dc)
425 {
426 gen_op_jmp_im(dc->pc);
427 save_npc(dc);
428 }
429
430 static inline void gen_mov_pc_npc(DisasContext * dc)
431 {
432 if (dc->npc == JUMP_PC) {
433 gen_op_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
434 gen_op_mov_pc_npc();
435 dc->pc = DYNAMIC_PC;
436 } else if (dc->npc == DYNAMIC_PC) {
437 gen_op_mov_pc_npc();
438 dc->pc = DYNAMIC_PC;
439 } else {
440 dc->pc = dc->npc;
441 }
442 }
443
444 static void gen_cond(int cond)
445 {
446 switch (cond) {
447 case 0x1:
448 gen_op_eval_be();
449 break;
450 case 0x2:
451 gen_op_eval_ble();
452 break;
453 case 0x3:
454 gen_op_eval_bl();
455 break;
456 case 0x4:
457 gen_op_eval_bleu();
458 break;
459 case 0x5:
460 gen_op_eval_bcs();
461 break;
462 case 0x6:
463 gen_op_eval_bneg();
464 break;
465 case 0x7:
466 gen_op_eval_bvs();
467 break;
468 case 0x9:
469 gen_op_eval_bne();
470 break;
471 case 0xa:
472 gen_op_eval_bg();
473 break;
474 case 0xb:
475 gen_op_eval_bge();
476 break;
477 case 0xc:
478 gen_op_eval_bgu();
479 break;
480 case 0xd:
481 gen_op_eval_bcc();
482 break;
483 case 0xe:
484 gen_op_eval_bpos();
485 break;
486 default:
487 case 0xf:
488 gen_op_eval_bvc();
489 break;
490 }
491 }
492
493 static void gen_fcond(int cond)
494 {
495 switch (cond) {
496 case 0x1:
497 gen_op_eval_fbne();
498 break;
499 case 0x2:
500 gen_op_eval_fblg();
501 break;
502 case 0x3:
503 gen_op_eval_fbul();
504 break;
505 case 0x4:
506 gen_op_eval_fbl();
507 break;
508 case 0x5:
509 gen_op_eval_fbug();
510 break;
511 case 0x6:
512 gen_op_eval_fbg();
513 break;
514 case 0x7:
515 gen_op_eval_fbu();
516 break;
517 case 0x9:
518 gen_op_eval_fbe();
519 break;
520 case 0xa:
521 gen_op_eval_fbue();
522 break;
523 case 0xb:
524 gen_op_eval_fbge();
525 break;
526 case 0xc:
527 gen_op_eval_fbuge();
528 break;
529 case 0xd:
530 gen_op_eval_fble();
531 break;
532 case 0xe:
533 gen_op_eval_fbule();
534 break;
535 default:
536 case 0xf:
537 gen_op_eval_fbo();
538 break;
539 }
540 }
541
542 /* XXX: potentially incorrect if dynamic npc */
543 static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn)
544 {
545 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
546 target_ulong target = dc->pc + offset;
547
548 if (cond == 0x0) {
549 /* unconditional not taken */
550 if (a) {
551 dc->pc = dc->npc + 4;
552 dc->npc = dc->pc + 4;
553 } else {
554 dc->pc = dc->npc;
555 dc->npc = dc->pc + 4;
556 }
557 } else if (cond == 0x8) {
558 /* unconditional taken */
559 if (a) {
560 dc->pc = target;
561 dc->npc = dc->pc + 4;
562 } else {
563 dc->pc = dc->npc;
564 dc->npc = target;
565 }
566 } else {
567 flush_T2(dc);
568 gen_cond(cond);
569 if (a) {
570 gen_op_branch_a((long)dc->tb, target, dc->npc);
571 dc->is_br = 1;
572 } else {
573 dc->pc = dc->npc;
574 dc->jump_pc[0] = target;
575 dc->jump_pc[1] = dc->npc + 4;
576 dc->npc = JUMP_PC;
577 }
578 }
579 }
580
581 /* XXX: potentially incorrect if dynamic npc */
582 static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn)
583 {
584 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
585 target_ulong target = dc->pc + offset;
586
587 if (cond == 0x0) {
588 /* unconditional not taken */
589 if (a) {
590 dc->pc = dc->npc + 4;
591 dc->npc = dc->pc + 4;
592 } else {
593 dc->pc = dc->npc;
594 dc->npc = dc->pc + 4;
595 }
596 } else if (cond == 0x8) {
597 /* unconditional taken */
598 if (a) {
599 dc->pc = target;
600 dc->npc = dc->pc + 4;
601 } else {
602 dc->pc = dc->npc;
603 dc->npc = target;
604 }
605 } else {
606 flush_T2(dc);
607 gen_fcond(cond);
608 if (a) {
609 gen_op_branch_a((long)dc->tb, target, dc->npc);
610 dc->is_br = 1;
611 } else {
612 dc->pc = dc->npc;
613 dc->jump_pc[0] = target;
614 dc->jump_pc[1] = dc->npc + 4;
615 dc->npc = JUMP_PC;
616 }
617 }
618 }
619
620 #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
621
622 static int sign_extend(int x, int len)
623 {
624 len = 32 - len;
625 return (x << len) >> len;
626 }
627
628 /* before an instruction, dc->pc must be static */
629 static void disas_sparc_insn(DisasContext * dc)
630 {
631 unsigned int insn, opc, rs1, rs2, rd;
632
633 insn = ldl_code(dc->pc);
634 opc = GET_FIELD(insn, 0, 1);
635
636 rd = GET_FIELD(insn, 2, 6);
637 switch (opc) {
638 case 0: /* branches/sethi */
639 {
640 unsigned int xop = GET_FIELD(insn, 7, 9);
641 int32_t target;
642 target = GET_FIELD(insn, 10, 31);
643 switch (xop) {
644 case 0x0: /* UNIMPL */
645 case 0x1: /* V9 BPcc */
646 case 0x3: /* V9 BPr */
647 case 0x5: /* V9 FBPcc */
648 default:
649 goto illegal_insn;
650 case 0x2: /* BN+x */
651 {
652 target <<= 2;
653 target = sign_extend(target, 22);
654 do_branch(dc, target, insn);
655 goto jmp_insn;
656 }
657 case 0x6: /* FBN+x */
658 {
659 #if !defined(CONFIG_USER_ONLY)
660 gen_op_trap_ifnofpu();
661 #endif
662 target <<= 2;
663 target = sign_extend(target, 22);
664 do_fbranch(dc, target, insn);
665 goto jmp_insn;
666 }
667 case 0x4: /* SETHI */
668 #define OPTIM
669 #if defined(OPTIM)
670 if (rd) { // nop
671 #endif
672 gen_movl_imm_T0(target << 10);
673 gen_movl_T0_reg(rd);
674 #if defined(OPTIM)
675 }
676 #endif
677 break;
678 }
679 break;
680 }
681 break;
682 case 1:
683 /*CALL*/ {
684 target_long target = GET_FIELDs(insn, 2, 31) << 2;
685
686 gen_op_movl_T0_im(dc->pc);
687 gen_movl_T0_reg(15);
688 target += dc->pc;
689 gen_mov_pc_npc(dc);
690 dc->npc = target;
691 }
692 goto jmp_insn;
693 case 2: /* FPU & Logical Operations */
694 {
695 unsigned int xop = GET_FIELD(insn, 7, 12);
696 if (xop == 0x3a) { /* generate trap */
697 int cond;
698 rs1 = GET_FIELD(insn, 13, 17);
699 gen_movl_reg_T0(rs1);
700 if (IS_IMM) {
701 rs2 = GET_FIELD(insn, 25, 31);
702 #if defined(OPTIM)
703 if (rs2 != 0) {
704 #endif
705 gen_movl_imm_T1(rs2);
706 gen_op_add_T1_T0();
707 #if defined(OPTIM)
708 }
709 #endif
710 } else {
711 rs2 = GET_FIELD(insn, 27, 31);
712 #if defined(OPTIM)
713 if (rs2 != 0) {
714 #endif
715 gen_movl_reg_T1(rs2);
716 gen_op_add_T1_T0();
717 #if defined(OPTIM)
718 }
719 #endif
720 }
721 save_state(dc);
722 /* V9 icc/xcc */
723 cond = GET_FIELD(insn, 3, 6);
724 if (cond == 0x8) {
725 gen_op_trap_T0();
726 dc->is_br = 1;
727 goto jmp_insn;
728 } else if (cond != 0) {
729 gen_cond(cond);
730 gen_op_trapcc_T0();
731 }
732 } else if (xop == 0x28) {
733 rs1 = GET_FIELD(insn, 13, 17);
734 switch(rs1) {
735 case 0: /* rdy */
736 gen_op_rdy();
737 gen_movl_T0_reg(rd);
738 break;
739 case 15: /* stbar / V9 membar */
740 break; /* no effect? */
741 default:
742 case 0x2: /* V9 rdccr */
743 case 0x3: /* V9 rdasi */
744 case 0x4: /* V9 rdtick */
745 case 0x5: /* V9 rdpc */
746 case 0x6: /* V9 rdfprs */
747 goto illegal_insn;
748 }
749 #if !defined(CONFIG_USER_ONLY)
750 } else if (xop == 0x29) {
751 if (!supervisor(dc))
752 goto priv_insn;
753 gen_op_rdpsr();
754 gen_movl_T0_reg(rd);
755 break;
756 } else if (xop == 0x2a) {
757 if (!supervisor(dc))
758 goto priv_insn;
759 gen_op_rdwim();
760 gen_movl_T0_reg(rd);
761 break;
762 } else if (xop == 0x2b) {
763 if (!supervisor(dc))
764 goto priv_insn;
765 gen_op_rdtbr();
766 gen_movl_T0_reg(rd);
767 break;
768 #endif
769 } else if (xop == 0x34) { /* FPU Operations */
770 #if !defined(CONFIG_USER_ONLY)
771 gen_op_trap_ifnofpu();
772 #endif
773 rs1 = GET_FIELD(insn, 13, 17);
774 rs2 = GET_FIELD(insn, 27, 31);
775 xop = GET_FIELD(insn, 18, 26);
776 switch (xop) {
777 case 0x1: /* fmovs */
778 gen_op_load_fpr_FT0(rs2);
779 gen_op_store_FT0_fpr(rd);
780 break;
781 case 0x5: /* fnegs */
782 gen_op_load_fpr_FT1(rs2);
783 gen_op_fnegs();
784 gen_op_store_FT0_fpr(rd);
785 break;
786 case 0x9: /* fabss */
787 gen_op_load_fpr_FT1(rs2);
788 gen_op_fabss();
789 gen_op_store_FT0_fpr(rd);
790 break;
791 case 0x29: /* fsqrts */
792 gen_op_load_fpr_FT1(rs2);
793 gen_op_fsqrts();
794 gen_op_store_FT0_fpr(rd);
795 break;
796 case 0x2a: /* fsqrtd */
797 gen_op_load_fpr_DT1(rs2);
798 gen_op_fsqrtd();
799 gen_op_store_DT0_fpr(rd);
800 break;
801 case 0x2b: /* fsqrtq */
802 goto nfpu_insn;
803 case 0x41:
804 gen_op_load_fpr_FT0(rs1);
805 gen_op_load_fpr_FT1(rs2);
806 gen_op_fadds();
807 gen_op_store_FT0_fpr(rd);
808 break;
809 case 0x42:
810 gen_op_load_fpr_DT0(rs1);
811 gen_op_load_fpr_DT1(rs2);
812 gen_op_faddd();
813 gen_op_store_DT0_fpr(rd);
814 break;
815 case 0x43: /* faddq */
816 goto nfpu_insn;
817 case 0x45:
818 gen_op_load_fpr_FT0(rs1);
819 gen_op_load_fpr_FT1(rs2);
820 gen_op_fsubs();
821 gen_op_store_FT0_fpr(rd);
822 break;
823 case 0x46:
824 gen_op_load_fpr_DT0(rs1);
825 gen_op_load_fpr_DT1(rs2);
826 gen_op_fsubd();
827 gen_op_store_DT0_fpr(rd);
828 break;
829 case 0x47: /* fsubq */
830 goto nfpu_insn;
831 case 0x49:
832 gen_op_load_fpr_FT0(rs1);
833 gen_op_load_fpr_FT1(rs2);
834 gen_op_fmuls();
835 gen_op_store_FT0_fpr(rd);
836 break;
837 case 0x4a:
838 gen_op_load_fpr_DT0(rs1);
839 gen_op_load_fpr_DT1(rs2);
840 gen_op_fmuld();
841 gen_op_store_DT0_fpr(rd);
842 break;
843 case 0x4b: /* fmulq */
844 goto nfpu_insn;
845 case 0x4d:
846 gen_op_load_fpr_FT0(rs1);
847 gen_op_load_fpr_FT1(rs2);
848 gen_op_fdivs();
849 gen_op_store_FT0_fpr(rd);
850 break;
851 case 0x4e:
852 gen_op_load_fpr_DT0(rs1);
853 gen_op_load_fpr_DT1(rs2);
854 gen_op_fdivd();
855 gen_op_store_DT0_fpr(rd);
856 break;
857 case 0x4f: /* fdivq */
858 goto nfpu_insn;
859 case 0x69:
860 gen_op_load_fpr_FT0(rs1);
861 gen_op_load_fpr_FT1(rs2);
862 gen_op_fsmuld();
863 gen_op_store_DT0_fpr(rd);
864 break;
865 case 0x6e: /* fdmulq */
866 goto nfpu_insn;
867 case 0xc4:
868 gen_op_load_fpr_FT1(rs2);
869 gen_op_fitos();
870 gen_op_store_FT0_fpr(rd);
871 break;
872 case 0xc6:
873 gen_op_load_fpr_DT1(rs2);
874 gen_op_fdtos();
875 gen_op_store_FT0_fpr(rd);
876 break;
877 case 0xc7: /* fqtos */
878 goto nfpu_insn;
879 case 0xc8:
880 gen_op_load_fpr_FT1(rs2);
881 gen_op_fitod();
882 gen_op_store_DT0_fpr(rd);
883 break;
884 case 0xc9:
885 gen_op_load_fpr_FT1(rs2);
886 gen_op_fstod();
887 gen_op_store_DT0_fpr(rd);
888 break;
889 case 0xcb: /* fqtod */
890 goto nfpu_insn;
891 case 0xcc: /* fitoq */
892 goto nfpu_insn;
893 case 0xcd: /* fstoq */
894 goto nfpu_insn;
895 case 0xce: /* fdtoq */
896 goto nfpu_insn;
897 case 0xd1:
898 gen_op_load_fpr_FT1(rs2);
899 gen_op_fstoi();
900 gen_op_store_FT0_fpr(rd);
901 break;
902 case 0xd2:
903 gen_op_load_fpr_DT1(rs2);
904 gen_op_fdtoi();
905 gen_op_store_FT0_fpr(rd);
906 break;
907 case 0xd3: /* fqtoi */
908 goto nfpu_insn;
909 default:
910 case 0x2: /* V9 fmovd */
911 case 0x6: /* V9 fnegd */
912 case 0xa: /* V9 fabsd */
913 case 0x81: /* V9 fstox */
914 case 0x82: /* V9 fdtox */
915 case 0x84: /* V9 fxtos */
916 case 0x88: /* V9 fxtod */
917
918 case 0x3: /* V9 fmovq */
919 case 0x7: /* V9 fnegq */
920 case 0xb: /* V9 fabsq */
921 case 0x83: /* V9 fqtox */
922 case 0x8c: /* V9 fxtoq */
923 goto illegal_insn;
924 }
925 } else if (xop == 0x35) { /* FPU Operations */
926 #if !defined(CONFIG_USER_ONLY)
927 gen_op_trap_ifnofpu();
928 #endif
929 rs1 = GET_FIELD(insn, 13, 17);
930 rs2 = GET_FIELD(insn, 27, 31);
931 xop = GET_FIELD(insn, 18, 26);
932 /* V9 fmovscc: x5, cond = x >> 1 */
933 /* V9 fmovdcc: x6, cond = x >> 1 */
934
935 /* V9 fmovqcc: x7, cond = x >> 1 */
936 switch (xop) {
937 case 0x51:
938 gen_op_load_fpr_FT0(rs1);
939 gen_op_load_fpr_FT1(rs2);
940 gen_op_fcmps();
941 break;
942 case 0x52:
943 gen_op_load_fpr_DT0(rs1);
944 gen_op_load_fpr_DT1(rs2);
945 gen_op_fcmpd();
946 break;
947 case 0x53: /* fcmpq */
948 goto nfpu_insn;
949 case 0x55: /* fcmpes */
950 gen_op_load_fpr_FT0(rs1);
951 gen_op_load_fpr_FT1(rs2);
952 gen_op_fcmps(); /* XXX should trap if qNaN or sNaN */
953 break;
954 case 0x56: /* fcmped */
955 gen_op_load_fpr_DT0(rs1);
956 gen_op_load_fpr_DT1(rs2);
957 gen_op_fcmpd(); /* XXX should trap if qNaN or sNaN */
958 break;
959 case 0x57: /* fcmpeq */
960 goto nfpu_insn;
961 default:
962 goto illegal_insn;
963 }
964 #if defined(OPTIM)
965 } else if (xop == 0x2) {
966 // clr/mov shortcut
967
968 rs1 = GET_FIELD(insn, 13, 17);
969 if (rs1 == 0) {
970 // or %g0, x, y -> mov T1, x; mov y, T1
971 if (IS_IMM) { /* immediate */
972 rs2 = GET_FIELDs(insn, 19, 31);
973 gen_movl_imm_T1(rs2);
974 } else { /* register */
975 rs2 = GET_FIELD(insn, 27, 31);
976 gen_movl_reg_T1(rs2);
977 }
978 gen_movl_T1_reg(rd);
979 } else {
980 gen_movl_reg_T0(rs1);
981 if (IS_IMM) { /* immediate */
982 // or x, #0, y -> mov T1, x; mov y, T1
983 rs2 = GET_FIELDs(insn, 19, 31);
984 if (rs2 != 0) {
985 gen_movl_imm_T1(rs2);
986 gen_op_or_T1_T0();
987 }
988 } else { /* register */
989 // or x, %g0, y -> mov T1, x; mov y, T1
990 rs2 = GET_FIELD(insn, 27, 31);
991 if (rs2 != 0) {
992 gen_movl_reg_T1(rs2);
993 gen_op_or_T1_T0();
994 }
995 }
996 gen_movl_T0_reg(rd);
997 }
998 #endif
999 } else if (xop < 0x38) {
1000 rs1 = GET_FIELD(insn, 13, 17);
1001 gen_movl_reg_T0(rs1);
1002 if (IS_IMM) { /* immediate */
1003 rs2 = GET_FIELDs(insn, 19, 31);
1004 gen_movl_imm_T1(rs2);
1005 } else { /* register */
1006 rs2 = GET_FIELD(insn, 27, 31);
1007 gen_movl_reg_T1(rs2);
1008 }
1009 if (xop < 0x20) {
1010 switch (xop & ~0x10) {
1011 case 0x0:
1012 if (xop & 0x10)
1013 gen_op_add_T1_T0_cc();
1014 else
1015 gen_op_add_T1_T0();
1016 break;
1017 case 0x1:
1018 gen_op_and_T1_T0();
1019 if (xop & 0x10)
1020 gen_op_logic_T0_cc();
1021 break;
1022 case 0x2:
1023 gen_op_or_T1_T0();
1024 if (xop & 0x10)
1025 gen_op_logic_T0_cc();
1026 break;
1027 case 0x3:
1028 gen_op_xor_T1_T0();
1029 if (xop & 0x10)
1030 gen_op_logic_T0_cc();
1031 break;
1032 case 0x4:
1033 if (xop & 0x10)
1034 gen_op_sub_T1_T0_cc();
1035 else
1036 gen_op_sub_T1_T0();
1037 break;
1038 case 0x5:
1039 gen_op_andn_T1_T0();
1040 if (xop & 0x10)
1041 gen_op_logic_T0_cc();
1042 break;
1043 case 0x6:
1044 gen_op_orn_T1_T0();
1045 if (xop & 0x10)
1046 gen_op_logic_T0_cc();
1047 break;
1048 case 0x7:
1049 gen_op_xnor_T1_T0();
1050 if (xop & 0x10)
1051 gen_op_logic_T0_cc();
1052 break;
1053 case 0x8:
1054 if (xop & 0x10)
1055 gen_op_addx_T1_T0_cc();
1056 else
1057 gen_op_addx_T1_T0();
1058 break;
1059 case 0xa:
1060 gen_op_umul_T1_T0();
1061 if (xop & 0x10)
1062 gen_op_logic_T0_cc();
1063 break;
1064 case 0xb:
1065 gen_op_smul_T1_T0();
1066 if (xop & 0x10)
1067 gen_op_logic_T0_cc();
1068 break;
1069 case 0xc:
1070 if (xop & 0x10)
1071 gen_op_subx_T1_T0_cc();
1072 else
1073 gen_op_subx_T1_T0();
1074 break;
1075 case 0xe:
1076 gen_op_udiv_T1_T0();
1077 if (xop & 0x10)
1078 gen_op_div_cc();
1079 break;
1080 case 0xf:
1081 gen_op_sdiv_T1_T0();
1082 if (xop & 0x10)
1083 gen_op_div_cc();
1084 break;
1085 default:
1086 case 0x9: /* V9 mulx */
1087 case 0xd: /* V9 udivx */
1088 goto illegal_insn;
1089 }
1090 gen_movl_T0_reg(rd);
1091 } else {
1092 switch (xop) {
1093 case 0x20: /* taddcc */
1094 case 0x21: /* tsubcc */
1095 case 0x22: /* taddcctv */
1096 case 0x23: /* tsubcctv */
1097 goto illegal_insn;
1098 case 0x24: /* mulscc */
1099 gen_op_mulscc_T1_T0();
1100 gen_movl_T0_reg(rd);
1101 break;
1102 case 0x25: /* sll, V9 sllx */
1103 gen_op_sll();
1104 gen_movl_T0_reg(rd);
1105 break;
1106 case 0x26: /* srl, V9 srlx */
1107 gen_op_srl();
1108 gen_movl_T0_reg(rd);
1109 break;
1110 case 0x27: /* sra, V9 srax */
1111 gen_op_sra();
1112 gen_movl_T0_reg(rd);
1113 break;
1114 case 0x30:
1115 {
1116 gen_op_xor_T1_T0();
1117 switch(rd) {
1118 case 0:
1119 gen_op_wry();
1120 break;
1121 default:
1122 case 0x2: /* V9 wrccr */
1123 case 0x3: /* V9 wrasi */
1124 case 0x6: /* V9 wrfprs */
1125 case 0xf: /* V9 sir */
1126 goto illegal_insn;
1127 }
1128 }
1129 break;
1130 #if !defined(CONFIG_USER_ONLY)
1131 case 0x31: /* wrpsr, V9 saved, restored */
1132 {
1133 if (!supervisor(dc))
1134 goto priv_insn;
1135 gen_op_xor_T1_T0();
1136 gen_op_wrpsr();
1137 }
1138 break;
1139 case 0x32: /* wrwim, V9 wrpr */
1140 {
1141 if (!supervisor(dc))
1142 goto priv_insn;
1143 gen_op_xor_T1_T0();
1144 gen_op_wrwim();
1145 }
1146 break;
1147 case 0x33:
1148 {
1149 if (!supervisor(dc))
1150 goto priv_insn;
1151 gen_op_xor_T1_T0();
1152 gen_op_wrtbr();
1153 }
1154 break;
1155 #endif
1156 default:
1157 case 0x2a: /* V9 rdpr */
1158 case 0x2b: /* V9 flushw */
1159 case 0x2c: /* V9 movcc */
1160 case 0x2d: /* V9 sdivx */
1161 case 0x2e: /* V9 popc */
1162 case 0x2f: /* V9 movr */
1163 goto illegal_insn;
1164 }
1165 }
1166 } else {
1167 rs1 = GET_FIELD(insn, 13, 17);
1168 gen_movl_reg_T0(rs1);
1169 if (IS_IMM) { /* immediate */
1170 rs2 = GET_FIELDs(insn, 19, 31);
1171 #if defined(OPTIM)
1172 if (rs2) {
1173 #endif
1174 gen_movl_imm_T1(rs2);
1175 gen_op_add_T1_T0();
1176 #if defined(OPTIM)
1177 }
1178 #endif
1179 } else { /* register */
1180 rs2 = GET_FIELD(insn, 27, 31);
1181 #if defined(OPTIM)
1182 if (rs2) {
1183 #endif
1184 gen_movl_reg_T1(rs2);
1185 gen_op_add_T1_T0();
1186 #if defined(OPTIM)
1187 }
1188 #endif
1189 }
1190 switch (xop) {
1191 case 0x38: /* jmpl */
1192 {
1193 if (rd != 0) {
1194 gen_op_movl_T1_im(dc->pc);
1195 gen_movl_T1_reg(rd);
1196 }
1197 gen_mov_pc_npc(dc);
1198 gen_op_movl_npc_T0();
1199 dc->npc = DYNAMIC_PC;
1200 }
1201 goto jmp_insn;
1202 #if !defined(CONFIG_USER_ONLY)
1203 case 0x39: /* rett, V9 return */
1204 {
1205 if (!supervisor(dc))
1206 goto priv_insn;
1207 gen_mov_pc_npc(dc);
1208 gen_op_movl_npc_T0();
1209 dc->npc = DYNAMIC_PC;
1210 gen_op_rett();
1211 }
1212 goto jmp_insn;
1213 #endif
1214 case 0x3b: /* flush */
1215 gen_op_flush_T0();
1216 break;
1217 case 0x3c: /* save */
1218 save_state(dc);
1219 gen_op_save();
1220 gen_movl_T0_reg(rd);
1221 break;
1222 case 0x3d: /* restore */
1223 save_state(dc);
1224 gen_op_restore();
1225 gen_movl_T0_reg(rd);
1226 break;
1227 default:
1228 case 0x3e: /* V9 done/retry */
1229 goto illegal_insn;
1230 }
1231 }
1232 break;
1233 }
1234 break;
1235 case 3: /* load/store instructions */
1236 {
1237 unsigned int xop = GET_FIELD(insn, 7, 12);
1238 rs1 = GET_FIELD(insn, 13, 17);
1239 gen_movl_reg_T0(rs1);
1240 if (IS_IMM) { /* immediate */
1241 rs2 = GET_FIELDs(insn, 19, 31);
1242 #if defined(OPTIM)
1243 if (rs2 != 0) {
1244 #endif
1245 gen_movl_imm_T1(rs2);
1246 gen_op_add_T1_T0();
1247 #if defined(OPTIM)
1248 }
1249 #endif
1250 } else { /* register */
1251 rs2 = GET_FIELD(insn, 27, 31);
1252 #if defined(OPTIM)
1253 if (rs2 != 0) {
1254 #endif
1255 gen_movl_reg_T1(rs2);
1256 gen_op_add_T1_T0();
1257 #if defined(OPTIM)
1258 }
1259 #endif
1260 }
1261 if (xop < 4 || (xop > 7 && xop < 0x14) || \
1262 (xop > 0x17 && xop < 0x20)) {
1263 switch (xop) {
1264 case 0x0: /* load word */
1265 gen_op_ldst(ld);
1266 break;
1267 case 0x1: /* load unsigned byte */
1268 gen_op_ldst(ldub);
1269 break;
1270 case 0x2: /* load unsigned halfword */
1271 gen_op_ldst(lduh);
1272 break;
1273 case 0x3: /* load double word */
1274 gen_op_ldst(ldd);
1275 gen_movl_T0_reg(rd + 1);
1276 break;
1277 case 0x9: /* load signed byte */
1278 gen_op_ldst(ldsb);
1279 break;
1280 case 0xa: /* load signed halfword */
1281 gen_op_ldst(ldsh);
1282 break;
1283 case 0xd: /* ldstub -- XXX: should be atomically */
1284 gen_op_ldst(ldstub);
1285 break;
1286 case 0x0f: /* swap register with memory. Also atomically */
1287 gen_movl_reg_T1(rd);
1288 gen_op_ldst(swap);
1289 break;
1290 #if !defined(CONFIG_USER_ONLY)
1291 case 0x10: /* load word alternate */
1292 if (!supervisor(dc))
1293 goto priv_insn;
1294 gen_op_lda(insn, 1, 4, 0);
1295 break;
1296 case 0x11: /* load unsigned byte alternate */
1297 if (!supervisor(dc))
1298 goto priv_insn;
1299 gen_op_lduba(insn, 1, 1, 0);
1300 break;
1301 case 0x12: /* load unsigned halfword alternate */
1302 if (!supervisor(dc))
1303 goto priv_insn;
1304 gen_op_lduha(insn, 1, 2, 0);
1305 break;
1306 case 0x13: /* load double word alternate */
1307 if (!supervisor(dc))
1308 goto priv_insn;
1309 gen_op_ldda(insn, 1, 8, 0);
1310 gen_movl_T0_reg(rd + 1);
1311 break;
1312 case 0x19: /* load signed byte alternate */
1313 if (!supervisor(dc))
1314 goto priv_insn;
1315 gen_op_ldsba(insn, 1, 1, 1);
1316 break;
1317 case 0x1a: /* load signed halfword alternate */
1318 if (!supervisor(dc))
1319 goto priv_insn;
1320 gen_op_ldsha(insn, 1, 2 ,1);
1321 break;
1322 case 0x1d: /* ldstuba -- XXX: should be atomically */
1323 if (!supervisor(dc))
1324 goto priv_insn;
1325 gen_op_ldstuba(insn, 1, 1, 0);
1326 break;
1327 case 0x1f: /* swap reg with alt. memory. Also atomically */
1328 if (!supervisor(dc))
1329 goto priv_insn;
1330 gen_movl_reg_T1(rd);
1331 gen_op_swapa(insn, 1, 4, 0);
1332 break;
1333
1334 /* avoid warnings */
1335 (void) &gen_op_stfa;
1336 (void) &gen_op_stdfa;
1337 (void) &gen_op_ldfa;
1338 (void) &gen_op_lddfa;
1339 #endif
1340 default:
1341 case 0x08: /* V9 ldsw */
1342 case 0x0b: /* V9 ldx */
1343 case 0x18: /* V9 ldswa */
1344 case 0x1b: /* V9 ldxa */
1345 case 0x2d: /* V9 prefetch */
1346 case 0x30: /* V9 ldfa */
1347 case 0x33: /* V9 lddfa */
1348 case 0x3d: /* V9 prefetcha */
1349
1350 case 0x32: /* V9 ldqfa */
1351 goto illegal_insn;
1352 }
1353 gen_movl_T1_reg(rd);
1354 } else if (xop >= 0x20 && xop < 0x24) {
1355 #if !defined(CONFIG_USER_ONLY)
1356 gen_op_trap_ifnofpu();
1357 #endif
1358 switch (xop) {
1359 case 0x20: /* load fpreg */
1360 gen_op_ldst(ldf);
1361 gen_op_store_FT0_fpr(rd);
1362 break;
1363 case 0x21: /* load fsr */
1364 gen_op_ldfsr();
1365 gen_op_store_FT0_fpr(rd);
1366 break;
1367 case 0x22: /* load quad fpreg */
1368 goto nfpu_insn;
1369 case 0x23: /* load double fpreg */
1370 gen_op_ldst(lddf);
1371 gen_op_store_DT0_fpr(rd);
1372 break;
1373 default:
1374 goto illegal_insn;
1375 }
1376 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18)) {
1377 gen_movl_reg_T1(rd);
1378 switch (xop) {
1379 case 0x4:
1380 gen_op_ldst(st);
1381 break;
1382 case 0x5:
1383 gen_op_ldst(stb);
1384 break;
1385 case 0x6:
1386 gen_op_ldst(sth);
1387 break;
1388 case 0x7:
1389 flush_T2(dc);
1390 gen_movl_reg_T2(rd + 1);
1391 gen_op_ldst(std);
1392 break;
1393 #if !defined(CONFIG_USER_ONLY)
1394 case 0x14:
1395 if (!supervisor(dc))
1396 goto priv_insn;
1397 gen_op_sta(insn, 0, 4, 0);
1398 break;
1399 case 0x15:
1400 if (!supervisor(dc))
1401 goto priv_insn;
1402 gen_op_stba(insn, 0, 1, 0);
1403 break;
1404 case 0x16:
1405 if (!supervisor(dc))
1406 goto priv_insn;
1407 gen_op_stha(insn, 0, 2, 0);
1408 break;
1409 case 0x17:
1410 if (!supervisor(dc))
1411 goto priv_insn;
1412 flush_T2(dc);
1413 gen_movl_reg_T2(rd + 1);
1414 gen_op_stda(insn, 0, 8, 0);
1415 break;
1416 #endif
1417 default:
1418 case 0x0e: /* V9 stx */
1419 case 0x1e: /* V9 stxa */
1420 goto illegal_insn;
1421 }
1422 } else if (xop > 0x23 && xop < 0x28) {
1423 #if !defined(CONFIG_USER_ONLY)
1424 gen_op_trap_ifnofpu();
1425 #endif
1426 switch (xop) {
1427 case 0x24:
1428 gen_op_load_fpr_FT0(rd);
1429 gen_op_ldst(stf);
1430 break;
1431 case 0x25: /* stfsr, V9 stxfsr */
1432 gen_op_load_fpr_FT0(rd);
1433 gen_op_stfsr();
1434 break;
1435 case 0x26: /* stdfq */
1436 goto nfpu_insn;
1437 case 0x27:
1438 gen_op_load_fpr_DT0(rd);
1439 gen_op_ldst(stdf);
1440 break;
1441 default:
1442 case 0x34: /* V9 stfa */
1443 case 0x37: /* V9 stdfa */
1444 case 0x3c: /* V9 casa */
1445 case 0x3e: /* V9 casxa */
1446
1447 case 0x36: /* V9 stqfa */
1448 goto illegal_insn;
1449 }
1450 } else if (xop > 0x33 && xop < 0x38) {
1451 /* Co-processor */
1452 goto illegal_insn;
1453 }
1454 else
1455 goto illegal_insn;
1456 }
1457 break;
1458 }
1459 /* default case for non jump instructions */
1460 if (dc->npc == DYNAMIC_PC) {
1461 dc->pc = DYNAMIC_PC;
1462 gen_op_next_insn();
1463 } else if (dc->npc == JUMP_PC) {
1464 /* we can do a static jump */
1465 gen_op_branch2((long)dc->tb, dc->jump_pc[0], dc->jump_pc[1]);
1466 dc->is_br = 1;
1467 } else {
1468 dc->pc = dc->npc;
1469 dc->npc = dc->npc + 4;
1470 }
1471 jmp_insn:
1472 return;
1473 illegal_insn:
1474 save_state(dc);
1475 gen_op_exception(TT_ILL_INSN);
1476 dc->is_br = 1;
1477 return;
1478 #if !defined(CONFIG_USER_ONLY)
1479 priv_insn:
1480 save_state(dc);
1481 gen_op_exception(TT_PRIV_INSN);
1482 dc->is_br = 1;
1483 return;
1484 #endif
1485 nfpu_insn:
1486 save_state(dc);
1487 gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
1488 dc->is_br = 1;
1489 }
1490
1491 static inline int gen_intermediate_code_internal(TranslationBlock * tb,
1492 int spc, CPUSPARCState *env)
1493 {
1494 target_ulong pc_start, last_pc;
1495 uint16_t *gen_opc_end;
1496 DisasContext dc1, *dc = &dc1;
1497 int j, lj = -1;
1498
1499 memset(dc, 0, sizeof(DisasContext));
1500 dc->tb = tb;
1501 pc_start = tb->pc;
1502 dc->pc = pc_start;
1503 last_pc = dc->pc;
1504 dc->npc = (target_ulong) tb->cs_base;
1505 #if defined(CONFIG_USER_ONLY)
1506 dc->mem_idx = 0;
1507 #else
1508 dc->mem_idx = ((env->psrs) != 0);
1509 #endif
1510 gen_opc_ptr = gen_opc_buf;
1511 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
1512 gen_opparam_ptr = gen_opparam_buf;
1513
1514 do {
1515 if (env->nb_breakpoints > 0) {
1516 for(j = 0; j < env->nb_breakpoints; j++) {
1517 if (env->breakpoints[j] == dc->pc) {
1518 if (dc->pc != pc_start)
1519 save_state(dc);
1520 gen_op_debug();
1521 gen_op_movl_T0_0();
1522 gen_op_exit_tb();
1523 dc->is_br = 1;
1524 goto exit_gen_loop;
1525 }
1526 }
1527 }
1528 if (spc) {
1529 if (loglevel > 0)
1530 fprintf(logfile, "Search PC...\n");
1531 j = gen_opc_ptr - gen_opc_buf;
1532 if (lj < j) {
1533 lj++;
1534 while (lj < j)
1535 gen_opc_instr_start[lj++] = 0;
1536 gen_opc_pc[lj] = dc->pc;
1537 gen_opc_npc[lj] = dc->npc;
1538 gen_opc_instr_start[lj] = 1;
1539 }
1540 }
1541 last_pc = dc->pc;
1542 disas_sparc_insn(dc);
1543 if (dc->is_br)
1544 break;
1545 /* if the next PC is different, we abort now */
1546 if (dc->pc != (last_pc + 4))
1547 break;
1548 /* if single step mode, we generate only one instruction and
1549 generate an exception */
1550 if (env->singlestep_enabled) {
1551 gen_op_jmp_im(dc->pc);
1552 gen_op_movl_T0_0();
1553 gen_op_exit_tb();
1554 break;
1555 }
1556 } while ((gen_opc_ptr < gen_opc_end) &&
1557 (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
1558
1559 exit_gen_loop:
1560 if (!dc->is_br) {
1561 if (dc->pc != DYNAMIC_PC &&
1562 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
1563 /* static PC and NPC: we can use direct chaining */
1564 gen_op_branch((long)tb, dc->pc, dc->npc);
1565 } else {
1566 if (dc->pc != DYNAMIC_PC)
1567 gen_op_jmp_im(dc->pc);
1568 save_npc(dc);
1569 gen_op_movl_T0_0();
1570 gen_op_exit_tb();
1571 }
1572 }
1573 *gen_opc_ptr = INDEX_op_end;
1574 if (spc) {
1575 j = gen_opc_ptr - gen_opc_buf;
1576 lj++;
1577 while (lj <= j)
1578 gen_opc_instr_start[lj++] = 0;
1579 tb->size = 0;
1580 #if 0
1581 if (loglevel > 0) {
1582 page_dump(logfile);
1583 }
1584 #endif
1585 } else {
1586 tb->size = last_pc + 4 - pc_start;
1587 }
1588 #ifdef DEBUG_DISAS
1589 if (loglevel & CPU_LOG_TB_IN_ASM) {
1590 fprintf(logfile, "--------------\n");
1591 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
1592 target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
1593 fprintf(logfile, "\n");
1594 if (loglevel & CPU_LOG_TB_OP) {
1595 fprintf(logfile, "OP:\n");
1596 dump_ops(gen_opc_buf, gen_opparam_buf);
1597 fprintf(logfile, "\n");
1598 }
1599 }
1600 #endif
1601 return 0;
1602 }
1603
1604 int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
1605 {
1606 return gen_intermediate_code_internal(tb, 0, env);
1607 }
1608
1609 int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
1610 {
1611 return gen_intermediate_code_internal(tb, 1, env);
1612 }
1613
1614 extern int ram_size;
1615
1616 void cpu_reset(CPUSPARCState *env)
1617 {
1618 memset(env, 0, sizeof(*env));
1619 tlb_flush(env, 1);
1620 env->cwp = 0;
1621 env->wim = 1;
1622 env->regwptr = env->regbase + (env->cwp * 16);
1623 #if defined(CONFIG_USER_ONLY)
1624 env->user_mode_only = 1;
1625 #else
1626 env->psrs = 1;
1627 env->psrps = 1;
1628 env->pc = 0xffd00000;
1629 env->gregs[1] = ram_size;
1630 env->mmuregs[0] = (0x04 << 24); /* Impl 0, ver 4, MMU disabled */
1631 env->npc = env->pc + 4;
1632 #endif
1633 }
1634
1635 CPUSPARCState *cpu_sparc_init(void)
1636 {
1637 CPUSPARCState *env;
1638
1639 cpu_exec_init();
1640
1641 if (!(env = malloc(sizeof(CPUSPARCState))))
1642 return (NULL);
1643 cpu_single_env = env;
1644 cpu_reset(env);
1645 return (env);
1646 }
1647
1648 #define GET_FLAG(a,b) ((env->psr & a)?b:'-')
1649
1650 void cpu_dump_state(CPUState *env, FILE *f,
1651 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
1652 int flags)
1653 {
1654 int i, x;
1655
1656 cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, env->npc);
1657 cpu_fprintf(f, "General Registers:\n");
1658 for (i = 0; i < 4; i++)
1659 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
1660 cpu_fprintf(f, "\n");
1661 for (; i < 8; i++)
1662 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
1663 cpu_fprintf(f, "\nCurrent Register Window:\n");
1664 for (x = 0; x < 3; x++) {
1665 for (i = 0; i < 4; i++)
1666 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
1667 (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
1668 env->regwptr[i + x * 8]);
1669 cpu_fprintf(f, "\n");
1670 for (; i < 8; i++)
1671 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
1672 (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
1673 env->regwptr[i + x * 8]);
1674 cpu_fprintf(f, "\n");
1675 }
1676 cpu_fprintf(f, "\nFloating Point Registers:\n");
1677 for (i = 0; i < 32; i++) {
1678 if ((i & 3) == 0)
1679 cpu_fprintf(f, "%%f%02d:", i);
1680 cpu_fprintf(f, " %016lf", env->fpr[i]);
1681 if ((i & 3) == 3)
1682 cpu_fprintf(f, "\n");
1683 }
1684 cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
1685 GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
1686 GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
1687 env->psrs?'S':'-', env->psrps?'P':'-',
1688 env->psret?'E':'-', env->wim);
1689 cpu_fprintf(f, "fsr: 0x%08x\n", env->fsr);
1690 }
1691
1692 #if defined(CONFIG_USER_ONLY)
1693 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
1694 {
1695 return addr;
1696 }
1697
1698 #else
1699 extern int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
1700 int *access_index, target_ulong address, int rw,
1701 int is_user);
1702
1703 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
1704 {
1705 target_phys_addr_t phys_addr;
1706 int prot, access_index;
1707
1708 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2, 0) != 0)
1709 return -1;
1710 return phys_addr;
1711 }
1712 #endif
1713
1714 void helper_flush(target_ulong addr)
1715 {
1716 addr &= ~7;
1717 tb_invalidate_page_range(addr, addr + 8);
1718 }
Qemu copy for testing