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git.proxmox.com Git - qemu.git/blob - target-sparc/translate.c
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5 Copyright (C) 2003 Fabrice Bellard
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 NPC/PC static optimisations (use JUMP_TB when possible)
27 Privileged instructions
28 Coprocessor-Instructions
29 Optimize synthetic instructions
30 Optional alignment and privileged instruction check
45 #define DYNAMIC_PC 1 /* dynamic pc value */
46 #define JUMP_PC 2 /* dynamic pc value which takes only two values
47 according to jump_pc[T2] */
49 typedef struct DisasContext
{
50 target_ulong pc
; /* current Program Counter: integer or DYNAMIC_PC */
51 target_ulong npc
; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
52 target_ulong jump_pc
[2]; /* used when JUMP_PC pc value is used */
54 struct TranslationBlock
*tb
;
57 static uint16_t *gen_opc_ptr
;
58 static uint32_t *gen_opparam_ptr
;
63 #define DEF(s,n,copy_size) INDEX_op_ ## s,
71 #define GET_FIELD(X, FROM, TO) \
72 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
74 #define IS_IMM (insn & (1<<13))
76 static void disas_sparc_insn(DisasContext
* dc
);
78 static GenOpFunc
*gen_op_movl_TN_reg
[2][32] = {
149 static GenOpFunc
*gen_op_movl_reg_TN
[3][32] = {
254 static GenOpFunc1
*gen_op_movl_TN_im
[3] = {
260 static inline void gen_movl_imm_TN(int reg
, int imm
)
262 gen_op_movl_TN_im
[reg
] (imm
);
265 static inline void gen_movl_imm_T1(int val
)
267 gen_movl_imm_TN(1, val
);
270 static inline void gen_movl_imm_T0(int val
)
272 gen_movl_imm_TN(0, val
);
275 static inline void gen_movl_reg_TN(int reg
, int t
)
278 gen_op_movl_reg_TN
[t
][reg
] ();
280 gen_movl_imm_TN(t
, 0);
283 static inline void gen_movl_reg_T0(int reg
)
285 gen_movl_reg_TN(reg
, 0);
288 static inline void gen_movl_reg_T1(int reg
)
290 gen_movl_reg_TN(reg
, 1);
293 static inline void gen_movl_reg_T2(int reg
)
295 gen_movl_reg_TN(reg
, 2);
298 static inline void gen_movl_TN_reg(int reg
, int t
)
301 gen_op_movl_TN_reg
[t
][reg
] ();
304 static inline void gen_movl_T0_reg(int reg
)
306 gen_movl_TN_reg(reg
, 0);
309 static inline void gen_movl_T1_reg(int reg
)
311 gen_movl_TN_reg(reg
, 1);
314 /* call this function before using T2 as it may have been set for a jump */
315 static inline void flush_T2(DisasContext
* dc
)
317 if (dc
->npc
== JUMP_PC
) {
318 gen_op_generic_branch(dc
->jump_pc
[0], dc
->jump_pc
[1]);
319 dc
->npc
= DYNAMIC_PC
;
323 static inline void save_npc(DisasContext
* dc
)
325 if (dc
->npc
== JUMP_PC
) {
326 gen_op_generic_branch(dc
->jump_pc
[0], dc
->jump_pc
[1]);
327 dc
->npc
= DYNAMIC_PC
;
328 } else if (dc
->npc
!= DYNAMIC_PC
) {
329 gen_op_movl_npc_im(dc
->npc
);
333 static inline void save_state(DisasContext
* dc
)
335 gen_op_jmp_im((uint32_t)dc
->pc
);
339 static void gen_cond(int cond
)
395 static void do_branch(DisasContext
* dc
, uint32_t target
, uint32_t insn
)
397 unsigned int cond
= GET_FIELD(insn
, 3, 6), a
= (insn
& (1 << 29));
398 target
+= (uint32_t) dc
->pc
;
400 /* unconditional not taken */
402 dc
->pc
= dc
->npc
+ 4;
403 dc
->npc
= dc
->pc
+ 4;
406 dc
->npc
= dc
->pc
+ 4;
408 } else if (cond
== 0x8) {
409 /* unconditional taken */
412 dc
->npc
= dc
->pc
+ 4;
421 gen_op_branch_a((long)dc
->tb
, target
, dc
->npc
);
425 dc
->jump_pc
[0] = target
;
426 dc
->jump_pc
[1] = dc
->npc
+ 4;
432 #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
434 static int sign_extend(int x
, int len
)
437 return (x
<< len
) >> len
;
440 static void disas_sparc_insn(DisasContext
* dc
)
442 unsigned int insn
, opc
, rs1
, rs2
, rd
;
444 insn
= ldl_code((uint8_t *)dc
->pc
);
445 opc
= GET_FIELD(insn
, 0, 1);
447 rd
= GET_FIELD(insn
, 2, 6);
449 case 0: /* branches/sethi */
451 unsigned int xop
= GET_FIELD(insn
, 7, 9);
453 target
= GET_FIELD(insn
, 10, 31);
456 case 0x1: /* UNIMPL */
461 target
= sign_extend(target
, 22);
462 do_branch(dc
, target
, insn
);
465 case 0x3: /* FBN+x */
467 case 0x4: /* SETHI */
468 gen_movl_imm_T0(target
<< 10);
478 unsigned int target
= GET_FIELDs(insn
, 2, 31) << 2;
480 gen_op_movl_T0_im((long) (dc
->pc
));
482 target
= dc
->pc
+ target
;
487 case 2: /* FPU & Logical Operations */
489 unsigned int xop
= GET_FIELD(insn
, 7, 12);
490 if (xop
== 0x3a) { /* generate trap */
492 rs1
= GET_FIELD(insn
, 13, 17);
493 gen_movl_reg_T0(rs1
);
495 gen_movl_imm_T1(GET_FIELD(insn
, 25, 31));
497 rs2
= GET_FIELD(insn
, 27, 31);
498 gen_movl_reg_T1(rs2
);
502 cond
= GET_FIELD(insn
, 3, 6);
510 } else if (xop
== 0x28) {
511 rs1
= GET_FIELD(insn
, 13, 17);
520 } else if (xop
== 0x34 || xop
== 0x35) { /* FPU Operations */
523 rs1
= GET_FIELD(insn
, 13, 17);
524 gen_movl_reg_T0(rs1
);
525 if (IS_IMM
) { /* immediate */
526 rs2
= GET_FIELDs(insn
, 19, 31);
527 gen_movl_imm_T1(rs2
);
528 } else { /* register */
529 rs2
= GET_FIELD(insn
, 27, 31);
530 gen_movl_reg_T1(rs2
);
533 switch (xop
& ~0x10) {
536 gen_op_add_T1_T0_cc();
543 gen_op_logic_T0_cc();
548 gen_op_logic_T0_cc();
553 gen_op_logic_T0_cc();
557 gen_op_sub_T1_T0_cc();
564 gen_op_logic_T0_cc();
569 gen_op_logic_T0_cc();
574 gen_op_logic_T0_cc();
584 gen_op_logic_T0_cc();
589 gen_op_logic_T0_cc();
612 case 0x24: /* mulscc */
613 gen_op_mulscc_T1_T0();
640 case 0x38: /* jmpl */
643 gen_op_movl_npc_T0();
645 gen_op_movl_T0_im((long) (dc
->pc
));
649 dc
->npc
= DYNAMIC_PC
;
652 case 0x3b: /* flush */
655 case 0x3c: /* save */
661 case 0x3d: /* restore */
674 case 3: /* load/store instructions */
676 unsigned int xop
= GET_FIELD(insn
, 7, 12);
677 rs1
= GET_FIELD(insn
, 13, 17);
678 gen_movl_reg_T0(rs1
);
679 if (IS_IMM
) { /* immediate */
680 rs2
= GET_FIELDs(insn
, 19, 31);
681 gen_movl_imm_T1(rs2
);
682 } else { /* register */
683 rs2
= GET_FIELD(insn
, 27, 31);
684 gen_movl_reg_T1(rs2
);
687 if (xop
< 4 || xop
> 7) {
689 case 0x0: /* load word */
692 case 0x1: /* load unsigned byte */
695 case 0x2: /* load unsigned halfword */
698 case 0x3: /* load double word */
700 gen_movl_T0_reg(rd
+ 1);
702 case 0x9: /* load signed byte */
705 case 0xa: /* load signed halfword */
708 case 0xd: /* ldstub -- XXX: should be atomically */
711 case 0x0f: /* swap register with memory. Also atomically */
716 } else if (xop
< 8) {
730 gen_movl_reg_T2(rd
+ 1);
737 /* default case for non jump instructions */
738 if (dc
->npc
== DYNAMIC_PC
) {
741 } else if (dc
->npc
== JUMP_PC
) {
742 /* we can do a static jump */
743 gen_op_branch2((long)dc
->tb
, dc
->jump_pc
[0], dc
->jump_pc
[1]);
747 dc
->npc
= dc
->npc
+ 4;
753 gen_op_exception(TT_ILL_INSN
);
757 static inline int gen_intermediate_code_internal(TranslationBlock
* tb
,
760 target_ulong pc_start
, last_pc
;
761 uint16_t *gen_opc_end
;
762 DisasContext dc1
, *dc
= &dc1
;
764 memset(dc
, 0, sizeof(DisasContext
));
766 printf("SearchPC not yet supported\n");
772 dc
->npc
= (target_ulong
) tb
->cs_base
;
774 gen_opc_ptr
= gen_opc_buf
;
775 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
776 gen_opparam_ptr
= gen_opparam_buf
;
780 disas_sparc_insn(dc
);
783 /* if the next PC is different, we abort now */
784 if (dc
->pc
!= (last_pc
+ 4))
786 } while ((gen_opc_ptr
< gen_opc_end
) &&
787 (dc
->pc
- pc_start
) < (TARGET_PAGE_SIZE
- 32));
789 if (dc
->pc
!= DYNAMIC_PC
&&
790 (dc
->npc
!= DYNAMIC_PC
&& dc
->npc
!= JUMP_PC
)) {
791 /* static PC and NPC: we can use direct chaining */
792 gen_op_branch((long)tb
, dc
->pc
, dc
->npc
);
794 if (dc
->pc
!= DYNAMIC_PC
)
795 gen_op_jmp_im(dc
->pc
);
801 *gen_opc_ptr
= INDEX_op_end
;
803 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
804 fprintf(logfile
, "--------------\n");
805 fprintf(logfile
, "IN: %s\n", lookup_symbol((uint8_t *)pc_start
));
806 disas(logfile
, (uint8_t *)pc_start
, last_pc
+ 4 - pc_start
, 0, 0);
807 fprintf(logfile
, "\n");
808 if (loglevel
& CPU_LOG_TB_OP
) {
809 fprintf(logfile
, "OP:\n");
810 dump_ops(gen_opc_buf
, gen_opparam_buf
);
811 fprintf(logfile
, "\n");
819 int gen_intermediate_code(CPUSPARCState
* env
, TranslationBlock
* tb
)
821 return gen_intermediate_code_internal(tb
, 0);
824 int gen_intermediate_code_pc(CPUSPARCState
* env
, TranslationBlock
* tb
)
826 return gen_intermediate_code_internal(tb
, 1);
829 CPUSPARCState
*cpu_sparc_init(void)
835 if (!(env
= malloc(sizeof(CPUSPARCState
))))
837 memset(env
, 0, sizeof(*env
));
840 env
->regwptr
= env
->regbase
+ (env
->cwp
* 16);
841 env
->user_mode_only
= 1;
845 #define GET_FLAG(a,b) ((env->psr & a)?b:'-')
847 void cpu_sparc_dump_state(CPUSPARCState
* env
, FILE * f
, int flags
)
851 fprintf(f
, "pc: 0x%08x npc: 0x%08x\n", (int) env
->pc
, (int) env
->npc
);
852 fprintf(f
, "General Registers:\n");
853 for (i
= 0; i
< 4; i
++)
854 fprintf(f
, "%%g%c: 0x%08x\t", i
+ '0', env
->gregs
[i
]);
857 fprintf(f
, "%%g%c: 0x%08x\t", i
+ '0', env
->gregs
[i
]);
858 fprintf(f
, "\nCurrent Register Window:\n");
859 for (x
= 0; x
< 3; x
++) {
860 for (i
= 0; i
< 4; i
++)
861 fprintf(f
, "%%%c%d: 0x%08x\t",
862 (x
== 0 ? 'o' : (x
== 1 ? 'l' : 'i')), i
,
863 env
->regwptr
[i
+ x
* 8]);
866 fprintf(f
, "%%%c%d: 0x%08x\t",
867 (x
== 0 ? 'o' : x
== 1 ? 'l' : 'i'), i
,
868 env
->regwptr
[i
+ x
* 8]);
871 fprintf(f
, "psr: 0x%08x -> %c%c%c%c wim: 0x%08x\n", env
->psr
| env
->cwp
,
872 GET_FLAG(PSR_ZERO
, 'Z'), GET_FLAG(PSR_OVF
, 'V'),
873 GET_FLAG(PSR_NEG
, 'N'), GET_FLAG(PSR_CARRY
, 'C'),
877 target_ulong
cpu_get_phys_page_debug(CPUState
*env
, target_ulong addr
)