target-unicore32/helper.c

   1 /*
   2  * Copyright (C) 2010-2012 Guan Xuetao
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * Contributions from 2012-04-01 on are considered under GPL version 2,
   9  * or (at your option) any later version.
  10  */
  11
  12 #include "cpu.h"
  13 #include "gdbstub.h"
  14 #include "helper.h"
  15 #include "host-utils.h"
  16
  17 CPUUniCore32State *uc32_cpu_init(const char *cpu_model)
  18 {
  19     UniCore32CPU *cpu;
  20     CPUUniCore32State *env;
  21     static int inited = 1;
  22
  23     if (object_class_by_name(cpu_model) == NULL) {
  24         return NULL;
  25     }
  26     cpu = UNICORE32_CPU(object_new(cpu_model));
  27     env = &cpu->env;
  28
  29     if (inited) {
  30         inited = 0;
  31         uc32_translate_init();
  32     }
  33
  34     qemu_init_vcpu(env);
  35     return env;
  36 }
  37
  38 uint32_t HELPER(clo)(uint32_t x)
  39 {
  40     return clo32(x);
  41 }
  42
  43 uint32_t HELPER(clz)(uint32_t x)
  44 {
  45     return clz32(x);
  46 }
  47
  48 #ifdef CONFIG_USER_ONLY
  49 void switch_mode(CPUUniCore32State *env, int mode)
  50 {
  51     if (mode != ASR_MODE_USER) {
  52         cpu_abort(env, "Tried to switch out of user mode\n");
  53     }
  54 }
  55
  56 void do_interrupt(CPUUniCore32State *env)
  57 {
  58     cpu_abort(env, "NO interrupt in user mode\n");
  59 }
  60
  61 int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address,
  62                               int access_type, int mmu_idx)
  63 {
  64     cpu_abort(env, "NO mmu fault in user mode\n");
  65     return 1;
  66 }
  67 #endif
  68
  69 /* These should probably raise undefined insn exceptions.  */
  70 void HELPER(set_cp)(CPUUniCore32State *env, uint32_t insn, uint32_t val)
  71 {
  72     int op1 = (insn >> 8) & 0xf;
  73     cpu_abort(env, "cp%i insn %08x\n", op1, insn);
  74     return;
  75 }
  76
  77 uint32_t HELPER(get_cp)(CPUUniCore32State *env, uint32_t insn)
  78 {
  79     int op1 = (insn >> 8) & 0xf;
  80     cpu_abort(env, "cp%i insn %08x\n", op1, insn);
  81     return 0;
  82 }
  83
  84 void HELPER(set_cp0)(CPUUniCore32State *env, uint32_t insn, uint32_t val)
  85 {
  86     cpu_abort(env, "cp0 insn %08x\n", insn);
  87 }
  88
  89 uint32_t HELPER(get_cp0)(CPUUniCore32State *env, uint32_t insn)
  90 {
  91     cpu_abort(env, "cp0 insn %08x\n", insn);
  92     return 0;
  93 }
  94
  95 void HELPER(set_r29_banked)(CPUUniCore32State *env, uint32_t mode, uint32_t val)
  96 {
  97     cpu_abort(env, "banked r29 write\n");
  98 }
  99
 100 uint32_t HELPER(get_r29_banked)(CPUUniCore32State *env, uint32_t mode)
 101 {
 102     cpu_abort(env, "banked r29 read\n");
 103     return 0;
 104 }
 105
 106 /* UniCore-F64 support.  We follow the convention used for F64 instrunctions:
 107    Single precition routines have a "s" suffix, double precision a
 108    "d" suffix.  */
 109
 110 /* Convert host exception flags to f64 form.  */
 111 static inline int ucf64_exceptbits_from_host(int host_bits)
 112 {
 113     int target_bits = 0;
 114
 115     if (host_bits & float_flag_invalid) {
 116         target_bits |= UCF64_FPSCR_FLAG_INVALID;
 117     }
 118     if (host_bits & float_flag_divbyzero) {
 119         target_bits |= UCF64_FPSCR_FLAG_DIVZERO;
 120     }
 121     if (host_bits & float_flag_overflow) {
 122         target_bits |= UCF64_FPSCR_FLAG_OVERFLOW;
 123     }
 124     if (host_bits & float_flag_underflow) {
 125         target_bits |= UCF64_FPSCR_FLAG_UNDERFLOW;
 126     }
 127     if (host_bits & float_flag_inexact) {
 128         target_bits |= UCF64_FPSCR_FLAG_INEXACT;
 129     }
 130     return target_bits;
 131 }
 132
 133 uint32_t HELPER(ucf64_get_fpscr)(CPUUniCore32State *env)
 134 {
 135     int i;
 136     uint32_t fpscr;
 137
 138     fpscr = (env->ucf64.xregs[UC32_UCF64_FPSCR] & UCF64_FPSCR_MASK);
 139     i = get_float_exception_flags(&env->ucf64.fp_status);
 140     fpscr |= ucf64_exceptbits_from_host(i);
 141     return fpscr;
 142 }
 143
 144 /* Convert ucf64 exception flags to target form.  */
 145 static inline int ucf64_exceptbits_to_host(int target_bits)
 146 {
 147     int host_bits = 0;
 148
 149     if (target_bits & UCF64_FPSCR_FLAG_INVALID) {
 150         host_bits |= float_flag_invalid;
 151     }
 152     if (target_bits & UCF64_FPSCR_FLAG_DIVZERO) {
 153         host_bits |= float_flag_divbyzero;
 154     }
 155     if (target_bits & UCF64_FPSCR_FLAG_OVERFLOW) {
 156         host_bits |= float_flag_overflow;
 157     }
 158     if (target_bits & UCF64_FPSCR_FLAG_UNDERFLOW) {
 159         host_bits |= float_flag_underflow;
 160     }
 161     if (target_bits & UCF64_FPSCR_FLAG_INEXACT) {
 162         host_bits |= float_flag_inexact;
 163     }
 164     return host_bits;
 165 }
 166
 167 void HELPER(ucf64_set_fpscr)(CPUUniCore32State *env, uint32_t val)
 168 {
 169     int i;
 170     uint32_t changed;
 171
 172     changed = env->ucf64.xregs[UC32_UCF64_FPSCR];
 173     env->ucf64.xregs[UC32_UCF64_FPSCR] = (val & UCF64_FPSCR_MASK);
 174
 175     changed ^= val;
 176     if (changed & (UCF64_FPSCR_RND_MASK)) {
 177         i = UCF64_FPSCR_RND(val);
 178         switch (i) {
 179         case 0:
 180             i = float_round_nearest_even;
 181             break;
 182         case 1:
 183             i = float_round_to_zero;
 184             break;
 185         case 2:
 186             i = float_round_up;
 187             break;
 188         case 3:
 189             i = float_round_down;
 190             break;
 191         default: /* 100 and 101 not implement */
 192             cpu_abort(env, "Unsupported UniCore-F64 round mode");
 193         }
 194         set_float_rounding_mode(i, &env->ucf64.fp_status);
 195     }
 196
 197     i = ucf64_exceptbits_to_host(UCF64_FPSCR_TRAPEN(val));
 198     set_float_exception_flags(i, &env->ucf64.fp_status);
 199 }
 200
 201 float32 HELPER(ucf64_adds)(float32 a, float32 b, CPUUniCore32State *env)
 202 {
 203     return float32_add(a, b, &env->ucf64.fp_status);
 204 }
 205
 206 float64 HELPER(ucf64_addd)(float64 a, float64 b, CPUUniCore32State *env)
 207 {
 208     return float64_add(a, b, &env->ucf64.fp_status);
 209 }
 210
 211 float32 HELPER(ucf64_subs)(float32 a, float32 b, CPUUniCore32State *env)
 212 {
 213     return float32_sub(a, b, &env->ucf64.fp_status);
 214 }
 215
 216 float64 HELPER(ucf64_subd)(float64 a, float64 b, CPUUniCore32State *env)
 217 {
 218     return float64_sub(a, b, &env->ucf64.fp_status);
 219 }
 220
 221 float32 HELPER(ucf64_muls)(float32 a, float32 b, CPUUniCore32State *env)
 222 {
 223     return float32_mul(a, b, &env->ucf64.fp_status);
 224 }
 225
 226 float64 HELPER(ucf64_muld)(float64 a, float64 b, CPUUniCore32State *env)
 227 {
 228     return float64_mul(a, b, &env->ucf64.fp_status);
 229 }
 230
 231 float32 HELPER(ucf64_divs)(float32 a, float32 b, CPUUniCore32State *env)
 232 {
 233     return float32_div(a, b, &env->ucf64.fp_status);
 234 }
 235
 236 float64 HELPER(ucf64_divd)(float64 a, float64 b, CPUUniCore32State *env)
 237 {
 238     return float64_div(a, b, &env->ucf64.fp_status);
 239 }
 240
 241 float32 HELPER(ucf64_negs)(float32 a)
 242 {
 243     return float32_chs(a);
 244 }
 245
 246 float64 HELPER(ucf64_negd)(float64 a)
 247 {
 248     return float64_chs(a);
 249 }
 250
 251 float32 HELPER(ucf64_abss)(float32 a)
 252 {
 253     return float32_abs(a);
 254 }
 255
 256 float64 HELPER(ucf64_absd)(float64 a)
 257 {
 258     return float64_abs(a);
 259 }
 260
 261 /* XXX: check quiet/signaling case */
 262 void HELPER(ucf64_cmps)(float32 a, float32 b, uint32_t c, CPUUniCore32State *env)
 263 {
 264     int flag;
 265     flag = float32_compare_quiet(a, b, &env->ucf64.fp_status);
 266     env->CF = 0;
 267     switch (c & 0x7) {
 268     case 0: /* F */
 269         break;
 270     case 1: /* UN */
 271         if (flag == 2) {
 272             env->CF = 1;
 273         }
 274         break;
 275     case 2: /* EQ */
 276         if (flag == 0) {
 277             env->CF = 1;
 278         }
 279         break;
 280     case 3: /* UEQ */
 281         if ((flag == 0) || (flag == 2)) {
 282             env->CF = 1;
 283         }
 284         break;
 285     case 4: /* OLT */
 286         if (flag == -1) {
 287             env->CF = 1;
 288         }
 289         break;
 290     case 5: /* ULT */
 291         if ((flag == -1) || (flag == 2)) {
 292             env->CF = 1;
 293         }
 294         break;
 295     case 6: /* OLE */
 296         if ((flag == -1) || (flag == 0)) {
 297             env->CF = 1;
 298         }
 299         break;
 300     case 7: /* ULE */
 301         if (flag != 1) {
 302             env->CF = 1;
 303         }
 304         break;
 305     }
 306     env->ucf64.xregs[UC32_UCF64_FPSCR] = (env->CF << 29)
 307                     | (env->ucf64.xregs[UC32_UCF64_FPSCR] & 0x0fffffff);
 308 }
 309
 310 void HELPER(ucf64_cmpd)(float64 a, float64 b, uint32_t c, CPUUniCore32State *env)
 311 {
 312     int flag;
 313     flag = float64_compare_quiet(a, b, &env->ucf64.fp_status);
 314     env->CF = 0;
 315     switch (c & 0x7) {
 316     case 0: /* F */
 317         break;
 318     case 1: /* UN */
 319         if (flag == 2) {
 320             env->CF = 1;
 321         }
 322         break;
 323     case 2: /* EQ */
 324         if (flag == 0) {
 325             env->CF = 1;
 326         }
 327         break;
 328     case 3: /* UEQ */
 329         if ((flag == 0) || (flag == 2)) {
 330             env->CF = 1;
 331         }
 332         break;
 333     case 4: /* OLT */
 334         if (flag == -1) {
 335             env->CF = 1;
 336         }
 337         break;
 338     case 5: /* ULT */
 339         if ((flag == -1) || (flag == 2)) {
 340             env->CF = 1;
 341         }
 342         break;
 343     case 6: /* OLE */
 344         if ((flag == -1) || (flag == 0)) {
 345             env->CF = 1;
 346         }
 347         break;
 348     case 7: /* ULE */
 349         if (flag != 1) {
 350             env->CF = 1;
 351         }
 352         break;
 353     }
 354     env->ucf64.xregs[UC32_UCF64_FPSCR] = (env->CF << 29)
 355                     | (env->ucf64.xregs[UC32_UCF64_FPSCR] & 0x0fffffff);
 356 }
 357
 358 /* Helper routines to perform bitwise copies between float and int.  */
 359 static inline float32 ucf64_itos(uint32_t i)
 360 {
 361     union {
 362         uint32_t i;
 363         float32 s;
 364     } v;
 365
 366     v.i = i;
 367     return v.s;
 368 }
 369
 370 static inline uint32_t ucf64_stoi(float32 s)
 371 {
 372     union {
 373         uint32_t i;
 374         float32 s;
 375     } v;
 376
 377     v.s = s;
 378     return v.i;
 379 }
 380
 381 static inline float64 ucf64_itod(uint64_t i)
 382 {
 383     union {
 384         uint64_t i;
 385         float64 d;
 386     } v;
 387
 388     v.i = i;
 389     return v.d;
 390 }
 391
 392 static inline uint64_t ucf64_dtoi(float64 d)
 393 {
 394     union {
 395         uint64_t i;
 396         float64 d;
 397     } v;
 398
 399     v.d = d;
 400     return v.i;
 401 }
 402
 403 /* Integer to float conversion.  */
 404 float32 HELPER(ucf64_si2sf)(float32 x, CPUUniCore32State *env)
 405 {
 406     return int32_to_float32(ucf64_stoi(x), &env->ucf64.fp_status);
 407 }
 408
 409 float64 HELPER(ucf64_si2df)(float32 x, CPUUniCore32State *env)
 410 {
 411     return int32_to_float64(ucf64_stoi(x), &env->ucf64.fp_status);
 412 }
 413
 414 /* Float to integer conversion.  */
 415 float32 HELPER(ucf64_sf2si)(float32 x, CPUUniCore32State *env)
 416 {
 417     return ucf64_itos(float32_to_int32(x, &env->ucf64.fp_status));
 418 }
 419
 420 float32 HELPER(ucf64_df2si)(float64 x, CPUUniCore32State *env)
 421 {
 422     return ucf64_itos(float64_to_int32(x, &env->ucf64.fp_status));
 423 }
 424
 425 /* floating point conversion */
 426 float64 HELPER(ucf64_sf2df)(float32 x, CPUUniCore32State *env)
 427 {
 428     return float32_to_float64(x, &env->ucf64.fp_status);
 429 }
 430
 431 float32 HELPER(ucf64_df2sf)(float64 x, CPUUniCore32State *env)
 432 {
 433     return float64_to_float32(x, &env->ucf64.fp_status);
 434 }