target-xtensa/cpu.h

   1 /*
   2  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *     * Redistributions of source code must retain the above copyright
   8  *       notice, this list of conditions and the following disclaimer.
   9  *     * Redistributions in binary form must reproduce the above copyright
  10  *       notice, this list of conditions and the following disclaimer in the
  11  *       documentation and/or other materials provided with the distribution.
  12  *     * Neither the name of the Open Source and Linux Lab nor the
  13  *       names of its contributors may be used to endorse or promote products
  14  *       derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  25  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #ifndef CPU_XTENSA_H
  29 #define CPU_XTENSA_H
  30
  31 #define TARGET_LONG_BITS 32
  32 #define ELF_MACHINE EM_XTENSA
  33
  34 #define CPUState struct CPUXtensaState
  35
  36 #include "config.h"
  37 #include "qemu-common.h"
  38 #include "cpu-defs.h"
  39
  40 #define TARGET_HAS_ICE 1
  41
  42 #define NB_MMU_MODES 4
  43
  44 #define TARGET_PHYS_ADDR_SPACE_BITS 32
  45 #define TARGET_VIRT_ADDR_SPACE_BITS 32
  46 #define TARGET_PAGE_BITS 12
  47
  48 enum {
  49     /* Additional instructions */
  50     XTENSA_OPTION_CODE_DENSITY,
  51     XTENSA_OPTION_LOOP,
  52     XTENSA_OPTION_EXTENDED_L32R,
  53     XTENSA_OPTION_16_BIT_IMUL,
  54     XTENSA_OPTION_32_BIT_IMUL,
  55     XTENSA_OPTION_32_BIT_IMUL_HIGH,
  56     XTENSA_OPTION_32_BIT_IDIV,
  57     XTENSA_OPTION_MAC16,
  58     XTENSA_OPTION_MISC_OP_NSA,
  59     XTENSA_OPTION_MISC_OP_MINMAX,
  60     XTENSA_OPTION_MISC_OP_SEXT,
  61     XTENSA_OPTION_MISC_OP_CLAMPS,
  62     XTENSA_OPTION_COPROCESSOR,
  63     XTENSA_OPTION_BOOLEAN,
  64     XTENSA_OPTION_FP_COPROCESSOR,
  65     XTENSA_OPTION_MP_SYNCHRO,
  66     XTENSA_OPTION_CONDITIONAL_STORE,
  67
  68     /* Interrupts and exceptions */
  69     XTENSA_OPTION_EXCEPTION,
  70     XTENSA_OPTION_RELOCATABLE_VECTOR,
  71     XTENSA_OPTION_UNALIGNED_EXCEPTION,
  72     XTENSA_OPTION_INTERRUPT,
  73     XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
  74     XTENSA_OPTION_TIMER_INTERRUPT,
  75
  76     /* Local memory */
  77     XTENSA_OPTION_ICACHE,
  78     XTENSA_OPTION_ICACHE_TEST,
  79     XTENSA_OPTION_ICACHE_INDEX_LOCK,
  80     XTENSA_OPTION_DCACHE,
  81     XTENSA_OPTION_DCACHE_TEST,
  82     XTENSA_OPTION_DCACHE_INDEX_LOCK,
  83     XTENSA_OPTION_IRAM,
  84     XTENSA_OPTION_IROM,
  85     XTENSA_OPTION_DRAM,
  86     XTENSA_OPTION_DROM,
  87     XTENSA_OPTION_XLMI,
  88     XTENSA_OPTION_HW_ALIGNMENT,
  89     XTENSA_OPTION_MEMORY_ECC_PARITY,
  90
  91     /* Memory protection and translation */
  92     XTENSA_OPTION_REGION_PROTECTION,
  93     XTENSA_OPTION_REGION_TRANSLATION,
  94     XTENSA_OPTION_MMU,
  95
  96     /* Other */
  97     XTENSA_OPTION_WINDOWED_REGISTER,
  98     XTENSA_OPTION_PROCESSOR_INTERFACE,
  99     XTENSA_OPTION_MISC_SR,
 100     XTENSA_OPTION_THREAD_POINTER,
 101     XTENSA_OPTION_PROCESSOR_ID,
 102     XTENSA_OPTION_DEBUG,
 103     XTENSA_OPTION_TRACE_PORT,
 104 };
 105
 106 enum {
 107     THREADPTR = 231,
 108     FCR = 232,
 109     FSR = 233,
 110 };
 111
 112 enum {
 113     LBEG = 0,
 114     LEND = 1,
 115     LCOUNT = 2,
 116     SAR = 3,
 117     BR = 4,
 118     LITBASE = 5,
 119     SCOMPARE1 = 12,
 120     ACCLO = 16,
 121     ACCHI = 17,
 122     MR = 32,
 123     WINDOW_BASE = 72,
 124     WINDOW_START = 73,
 125     PTEVADDR = 83,
 126     RASID = 90,
 127     ITLBCFG = 91,
 128     DTLBCFG = 92,
 129     IBREAKENABLE = 96,
 130     IBREAKA = 128,
 131     EPC1 = 177,
 132     DEPC = 192,
 133     EPS2 = 194,
 134     EXCSAVE1 = 209,
 135     CPENABLE = 224,
 136     INTSET = 226,
 137     INTCLEAR = 227,
 138     INTENABLE = 228,
 139     PS = 230,
 140     VECBASE = 231,
 141     EXCCAUSE = 232,
 142     DEBUGCAUSE = 233,
 143     CCOUNT = 234,
 144     PRID = 235,
 145     ICOUNT = 236,
 146     ICOUNTLEVEL = 237,
 147     EXCVADDR = 238,
 148     CCOMPARE = 240,
 149 };
 150
 151 #define PS_INTLEVEL 0xf
 152 #define PS_INTLEVEL_SHIFT 0
 153
 154 #define PS_EXCM 0x10
 155 #define PS_UM 0x20
 156
 157 #define PS_RING 0xc0
 158 #define PS_RING_SHIFT 6
 159
 160 #define PS_OWB 0xf00
 161 #define PS_OWB_SHIFT 8
 162
 163 #define PS_CALLINC 0x30000
 164 #define PS_CALLINC_SHIFT 16
 165 #define PS_CALLINC_LEN 2
 166
 167 #define PS_WOE 0x40000
 168
 169 #define DEBUGCAUSE_IC 0x1
 170 #define DEBUGCAUSE_IB 0x2
 171 #define DEBUGCAUSE_DB 0x4
 172 #define DEBUGCAUSE_BI 0x8
 173 #define DEBUGCAUSE_BN 0x10
 174 #define DEBUGCAUSE_DI 0x20
 175 #define DEBUGCAUSE_DBNUM 0xf00
 176 #define DEBUGCAUSE_DBNUM_SHIFT 8
 177
 178 #define MAX_NAREG 64
 179 #define MAX_NINTERRUPT 32
 180 #define MAX_NLEVEL 6
 181 #define MAX_NNMI 1
 182 #define MAX_NCCOMPARE 3
 183 #define MAX_TLB_WAY_SIZE 8
 184
 185 #define REGION_PAGE_MASK 0xe0000000
 186
 187 enum {
 188     /* Static vectors */
 189     EXC_RESET,
 190     EXC_MEMORY_ERROR,
 191
 192     /* Dynamic vectors */
 193     EXC_WINDOW_OVERFLOW4,
 194     EXC_WINDOW_UNDERFLOW4,
 195     EXC_WINDOW_OVERFLOW8,
 196     EXC_WINDOW_UNDERFLOW8,
 197     EXC_WINDOW_OVERFLOW12,
 198     EXC_WINDOW_UNDERFLOW12,
 199     EXC_IRQ,
 200     EXC_KERNEL,
 201     EXC_USER,
 202     EXC_DOUBLE,
 203     EXC_DEBUG,
 204     EXC_MAX
 205 };
 206
 207 enum {
 208     ILLEGAL_INSTRUCTION_CAUSE = 0,
 209     SYSCALL_CAUSE,
 210     INSTRUCTION_FETCH_ERROR_CAUSE,
 211     LOAD_STORE_ERROR_CAUSE,
 212     LEVEL1_INTERRUPT_CAUSE,
 213     ALLOCA_CAUSE,
 214     INTEGER_DIVIDE_BY_ZERO_CAUSE,
 215     PRIVILEGED_CAUSE = 8,
 216     LOAD_STORE_ALIGNMENT_CAUSE,
 217
 218     INSTR_PIF_DATA_ERROR_CAUSE = 12,
 219     LOAD_STORE_PIF_DATA_ERROR_CAUSE,
 220     INSTR_PIF_ADDR_ERROR_CAUSE,
 221     LOAD_STORE_PIF_ADDR_ERROR_CAUSE,
 222
 223     INST_TLB_MISS_CAUSE,
 224     INST_TLB_MULTI_HIT_CAUSE,
 225     INST_FETCH_PRIVILEGE_CAUSE,
 226     INST_FETCH_PROHIBITED_CAUSE = 20,
 227     LOAD_STORE_TLB_MISS_CAUSE = 24,
 228     LOAD_STORE_TLB_MULTI_HIT_CAUSE,
 229     LOAD_STORE_PRIVILEGE_CAUSE,
 230     LOAD_PROHIBITED_CAUSE = 28,
 231     STORE_PROHIBITED_CAUSE,
 232
 233     COPROCESSOR0_DISABLED = 32,
 234 };
 235
 236 typedef enum {
 237     INTTYPE_LEVEL,
 238     INTTYPE_EDGE,
 239     INTTYPE_NMI,
 240     INTTYPE_SOFTWARE,
 241     INTTYPE_TIMER,
 242     INTTYPE_DEBUG,
 243     INTTYPE_WRITE_ERR,
 244     INTTYPE_MAX
 245 } interrupt_type;
 246
 247 typedef struct xtensa_tlb_entry {
 248     uint32_t vaddr;
 249     uint32_t paddr;
 250     uint8_t asid;
 251     uint8_t attr;
 252     bool variable;
 253 } xtensa_tlb_entry;
 254
 255 typedef struct xtensa_tlb {
 256     unsigned nways;
 257     const unsigned way_size[10];
 258     bool varway56;
 259     unsigned nrefillentries;
 260 } xtensa_tlb;
 261
 262 typedef struct XtensaGdbReg {
 263     int targno;
 264     int type;
 265     int group;
 266 } XtensaGdbReg;
 267
 268 typedef struct XtensaGdbRegmap {
 269     int num_regs;
 270     int num_core_regs;
 271     /* PC + a + ar + sr + ur */
 272     XtensaGdbReg reg[1 + 16 + 64 + 256 + 256];
 273 } XtensaGdbRegmap;
 274
 275 typedef struct XtensaConfig {
 276     const char *name;
 277     uint64_t options;
 278     XtensaGdbRegmap gdb_regmap;
 279     unsigned nareg;
 280     int excm_level;
 281     int ndepc;
 282     uint32_t vecbase;
 283     uint32_t exception_vector[EXC_MAX];
 284     unsigned ninterrupt;
 285     unsigned nlevel;
 286     uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1];
 287     uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1];
 288     uint32_t inttype_mask[INTTYPE_MAX];
 289     struct {
 290         uint32_t level;
 291         interrupt_type inttype;
 292     } interrupt[MAX_NINTERRUPT];
 293     unsigned nccompare;
 294     uint32_t timerint[MAX_NCCOMPARE];
 295     unsigned nextint;
 296     unsigned extint[MAX_NINTERRUPT];
 297
 298     unsigned debug_level;
 299     unsigned nibreak;
 300     unsigned ndbreak;
 301
 302     uint32_t clock_freq_khz;
 303
 304     xtensa_tlb itlb;
 305     xtensa_tlb dtlb;
 306 } XtensaConfig;
 307
 308 typedef struct XtensaConfigList {
 309     const XtensaConfig *config;
 310     struct XtensaConfigList *next;
 311 } XtensaConfigList;
 312
 313 typedef struct CPUXtensaState {
 314     const XtensaConfig *config;
 315     uint32_t regs[16];
 316     uint32_t pc;
 317     uint32_t sregs[256];
 318     uint32_t uregs[256];
 319     uint32_t phys_regs[MAX_NAREG];
 320
 321     xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE];
 322     xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE];
 323     unsigned autorefill_idx;
 324
 325     int pending_irq_level; /* level of last raised IRQ */
 326     void **irq_inputs;
 327     QEMUTimer *ccompare_timer;
 328     uint32_t wake_ccount;
 329     int64_t halt_clock;
 330
 331     int exception_taken;
 332
 333     CPU_COMMON
 334 } CPUXtensaState;
 335
 336 #define cpu_init cpu_xtensa_init
 337 #define cpu_exec cpu_xtensa_exec
 338 #define cpu_gen_code cpu_xtensa_gen_code
 339 #define cpu_signal_handler cpu_xtensa_signal_handler
 340 #define cpu_list xtensa_cpu_list
 341
 342 CPUXtensaState *cpu_xtensa_init(const char *cpu_model);
 343 void xtensa_translate_init(void);
 344 int cpu_xtensa_exec(CPUXtensaState *s);
 345 void xtensa_register_core(XtensaConfigList *node);
 346 void do_interrupt(CPUXtensaState *s);
 347 void check_interrupts(CPUXtensaState *s);
 348 void xtensa_irq_init(CPUState *env);
 349 void *xtensa_get_extint(CPUState *env, unsigned extint);
 350 void xtensa_advance_ccount(CPUState *env, uint32_t d);
 351 void xtensa_timer_irq(CPUState *env, uint32_t id, uint32_t active);
 352 void xtensa_rearm_ccompare_timer(CPUState *env);
 353 int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc);
 354 void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 355 void xtensa_sync_window_from_phys(CPUState *env);
 356 void xtensa_sync_phys_from_window(CPUState *env);
 357 uint32_t xtensa_tlb_get_addr_mask(const CPUState *env, bool dtlb, uint32_t way);
 358 void split_tlb_entry_spec_way(const CPUState *env, uint32_t v, bool dtlb,
 359         uint32_t *vpn, uint32_t wi, uint32_t *ei);
 360 int xtensa_tlb_lookup(const CPUState *env, uint32_t addr, bool dtlb,
 361         uint32_t *pwi, uint32_t *pei, uint8_t *pring);
 362 void xtensa_tlb_set_entry(CPUState *env, bool dtlb,
 363         unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
 364 int xtensa_get_physical_addr(CPUState *env,
 365         uint32_t vaddr, int is_write, int mmu_idx,
 366         uint32_t *paddr, uint32_t *page_size, unsigned *access);
 367 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env);
 368
 369
 370 #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
 371
 372 static inline bool xtensa_option_bits_enabled(const XtensaConfig *config,
 373         uint64_t opt)
 374 {
 375     return (config->options & opt) != 0;
 376 }
 377
 378 static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt)
 379 {
 380     return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt));
 381 }
 382
 383 static inline int xtensa_get_cintlevel(const CPUState *env)
 384 {
 385     int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT;
 386     if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) {
 387         level = env->config->excm_level;
 388     }
 389     return level;
 390 }
 391
 392 static inline int xtensa_get_ring(const CPUState *env)
 393 {
 394     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 395         return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
 396     } else {
 397         return 0;
 398     }
 399 }
 400
 401 static inline int xtensa_get_cring(const CPUState *env)
 402 {
 403     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) &&
 404             (env->sregs[PS] & PS_EXCM) == 0) {
 405         return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
 406     } else {
 407         return 0;
 408     }
 409 }
 410
 411 static inline xtensa_tlb_entry *xtensa_tlb_get_entry(CPUState *env,
 412         bool dtlb, unsigned wi, unsigned ei)
 413 {
 414     return dtlb ?
 415         env->dtlb[wi] + ei :
 416         env->itlb[wi] + ei;
 417 }
 418
 419 /* MMU modes definitions */
 420 #define MMU_MODE0_SUFFIX _ring0
 421 #define MMU_MODE1_SUFFIX _ring1
 422 #define MMU_MODE2_SUFFIX _ring2
 423 #define MMU_MODE3_SUFFIX _ring3
 424
 425 static inline int cpu_mmu_index(CPUState *env)
 426 {
 427     return xtensa_get_cring(env);
 428 }
 429
 430 #define XTENSA_TBFLAG_RING_MASK 0x3
 431 #define XTENSA_TBFLAG_EXCM 0x4
 432 #define XTENSA_TBFLAG_LITBASE 0x8
 433 #define XTENSA_TBFLAG_DEBUG 0x10
 434 #define XTENSA_TBFLAG_ICOUNT 0x20
 435
 436 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
 437         target_ulong *cs_base, int *flags)
 438 {
 439     *pc = env->pc;
 440     *cs_base = 0;
 441     *flags = 0;
 442     *flags |= xtensa_get_ring(env);
 443     if (env->sregs[PS] & PS_EXCM) {
 444         *flags |= XTENSA_TBFLAG_EXCM;
 445     }
 446     if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
 447             (env->sregs[LITBASE] & 1)) {
 448         *flags |= XTENSA_TBFLAG_LITBASE;
 449     }
 450     if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) {
 451         if (xtensa_get_cintlevel(env) < env->config->debug_level) {
 452             *flags |= XTENSA_TBFLAG_DEBUG;
 453         }
 454         if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
 455             *flags |= XTENSA_TBFLAG_ICOUNT;
 456         }
 457     }
 458 }
 459
 460 #include "cpu-all.h"
 461 #include "exec-all.h"
 462
 463 static inline int cpu_has_work(CPUState *env)
 464 {
 465     return env->pending_irq_level;
 466 }
 467
 468 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
 469 {
 470     env->pc = tb->pc;
 471 }
 472
 473 #endif