target-xtensa/cpu.h

   1 /*
   2  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *     * Redistributions of source code must retain the above copyright
   8  *       notice, this list of conditions and the following disclaimer.
   9  *     * Redistributions in binary form must reproduce the above copyright
  10  *       notice, this list of conditions and the following disclaimer in the
  11  *       documentation and/or other materials provided with the distribution.
  12  *     * Neither the name of the Open Source and Linux Lab nor the
  13  *       names of its contributors may be used to endorse or promote products
  14  *       derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  25  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #ifndef CPU_XTENSA_H
  29 #define CPU_XTENSA_H
  30
  31 #define TARGET_LONG_BITS 32
  32 #define ELF_MACHINE EM_XTENSA
  33
  34 #define CPUState struct CPUXtensaState
  35
  36 #include "config.h"
  37 #include "qemu-common.h"
  38 #include "cpu-defs.h"
  39
  40 #define TARGET_HAS_ICE 1
  41
  42 #define NB_MMU_MODES 4
  43
  44 #define TARGET_PHYS_ADDR_SPACE_BITS 32
  45 #define TARGET_VIRT_ADDR_SPACE_BITS 32
  46 #define TARGET_PAGE_BITS 12
  47
  48 enum {
  49     /* Additional instructions */
  50     XTENSA_OPTION_CODE_DENSITY,
  51     XTENSA_OPTION_LOOP,
  52     XTENSA_OPTION_EXTENDED_L32R,
  53     XTENSA_OPTION_16_BIT_IMUL,
  54     XTENSA_OPTION_32_BIT_IMUL,
  55     XTENSA_OPTION_32_BIT_IDIV,
  56     XTENSA_OPTION_MAC16,
  57     XTENSA_OPTION_MISC_OP,
  58     XTENSA_OPTION_COPROCESSOR,
  59     XTENSA_OPTION_BOOLEAN,
  60     XTENSA_OPTION_FP_COPROCESSOR,
  61     XTENSA_OPTION_MP_SYNCHRO,
  62     XTENSA_OPTION_CONDITIONAL_STORE,
  63
  64     /* Interrupts and exceptions */
  65     XTENSA_OPTION_EXCEPTION,
  66     XTENSA_OPTION_RELOCATABLE_VECTOR,
  67     XTENSA_OPTION_UNALIGNED_EXCEPTION,
  68     XTENSA_OPTION_INTERRUPT,
  69     XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
  70     XTENSA_OPTION_TIMER_INTERRUPT,
  71
  72     /* Local memory */
  73     XTENSA_OPTION_ICACHE,
  74     XTENSA_OPTION_ICACHE_TEST,
  75     XTENSA_OPTION_ICACHE_INDEX_LOCK,
  76     XTENSA_OPTION_DCACHE,
  77     XTENSA_OPTION_DCACHE_TEST,
  78     XTENSA_OPTION_DCACHE_INDEX_LOCK,
  79     XTENSA_OPTION_IRAM,
  80     XTENSA_OPTION_IROM,
  81     XTENSA_OPTION_DRAM,
  82     XTENSA_OPTION_DROM,
  83     XTENSA_OPTION_XLMI,
  84     XTENSA_OPTION_HW_ALIGNMENT,
  85     XTENSA_OPTION_MEMORY_ECC_PARITY,
  86
  87     /* Memory protection and translation */
  88     XTENSA_OPTION_REGION_PROTECTION,
  89     XTENSA_OPTION_REGION_TRANSLATION,
  90     XTENSA_OPTION_MMU,
  91
  92     /* Other */
  93     XTENSA_OPTION_WINDOWED_REGISTER,
  94     XTENSA_OPTION_PROCESSOR_INTERFACE,
  95     XTENSA_OPTION_MISC_SR,
  96     XTENSA_OPTION_THREAD_POINTER,
  97     XTENSA_OPTION_PROCESSOR_ID,
  98     XTENSA_OPTION_DEBUG,
  99     XTENSA_OPTION_TRACE_PORT,
 100 };
 101
 102 enum {
 103     THREADPTR = 231,
 104     FCR = 232,
 105     FSR = 233,
 106 };
 107
 108 enum {
 109     SAR = 3,
 110     SCOMPARE1 = 12,
 111     WINDOW_BASE = 72,
 112     WINDOW_START = 73,
 113     EPC1 = 177,
 114     DEPC = 192,
 115     EXCSAVE1 = 209,
 116     PS = 230,
 117     EXCCAUSE = 232,
 118     EXCVADDR = 238,
 119 };
 120
 121 #define PS_INTLEVEL 0xf
 122 #define PS_INTLEVEL_SHIFT 0
 123
 124 #define PS_EXCM 0x10
 125 #define PS_UM 0x20
 126
 127 #define PS_RING 0xc0
 128 #define PS_RING_SHIFT 6
 129
 130 #define PS_OWB 0xf00
 131 #define PS_OWB_SHIFT 8
 132
 133 #define PS_CALLINC 0x30000
 134 #define PS_CALLINC_SHIFT 16
 135 #define PS_CALLINC_LEN 2
 136
 137 #define PS_WOE 0x40000
 138
 139 #define MAX_NAREG 64
 140
 141 enum {
 142     /* Static vectors */
 143     EXC_RESET,
 144     EXC_MEMORY_ERROR,
 145
 146     /* Dynamic vectors */
 147     EXC_WINDOW_OVERFLOW4,
 148     EXC_WINDOW_UNDERFLOW4,
 149     EXC_WINDOW_OVERFLOW8,
 150     EXC_WINDOW_UNDERFLOW8,
 151     EXC_WINDOW_OVERFLOW12,
 152     EXC_WINDOW_UNDERFLOW12,
 153     EXC_IRQ,
 154     EXC_KERNEL,
 155     EXC_USER,
 156     EXC_DOUBLE,
 157     EXC_MAX
 158 };
 159
 160 enum {
 161     ILLEGAL_INSTRUCTION_CAUSE = 0,
 162     SYSCALL_CAUSE,
 163     INSTRUCTION_FETCH_ERROR_CAUSE,
 164     LOAD_STORE_ERROR_CAUSE,
 165     LEVEL1_INTERRUPT_CAUSE,
 166     ALLOCA_CAUSE,
 167     INTEGER_DIVIDE_BY_ZERO_CAUSE,
 168     PRIVILEGED_CAUSE = 8,
 169     LOAD_STORE_ALIGNMENT_CAUSE,
 170
 171     INSTR_PIF_DATA_ERROR_CAUSE = 12,
 172     LOAD_STORE_PIF_DATA_ERROR_CAUSE,
 173     INSTR_PIF_ADDR_ERROR_CAUSE,
 174     LOAD_STORE_PIF_ADDR_ERROR_CAUSE,
 175
 176     INST_TLB_MISS_CAUSE,
 177     INST_TLB_MULTI_HIT_CAUSE,
 178     INST_FETCH_PRIVILEGE_CAUSE,
 179     INST_FETCH_PROHIBITED_CAUSE = 20,
 180     LOAD_STORE_TLB_MISS_CAUSE = 24,
 181     LOAD_STORE_TLB_MULTI_HIT_CAUSE,
 182     LOAD_STORE_PRIVILEGE_CAUSE,
 183     LOAD_PROHIBITED_CAUSE = 28,
 184     STORE_PROHIBITED_CAUSE,
 185
 186     COPROCESSOR0_DISABLED = 32,
 187 };
 188
 189 typedef struct XtensaConfig {
 190     const char *name;
 191     uint64_t options;
 192     unsigned nareg;
 193     int excm_level;
 194     int ndepc;
 195     uint32_t exception_vector[EXC_MAX];
 196 } XtensaConfig;
 197
 198 typedef struct CPUXtensaState {
 199     const XtensaConfig *config;
 200     uint32_t regs[16];
 201     uint32_t pc;
 202     uint32_t sregs[256];
 203     uint32_t uregs[256];
 204     uint32_t phys_regs[MAX_NAREG];
 205
 206     int exception_taken;
 207
 208     CPU_COMMON
 209 } CPUXtensaState;
 210
 211 #define cpu_init cpu_xtensa_init
 212 #define cpu_exec cpu_xtensa_exec
 213 #define cpu_gen_code cpu_xtensa_gen_code
 214 #define cpu_signal_handler cpu_xtensa_signal_handler
 215 #define cpu_list xtensa_cpu_list
 216
 217 CPUXtensaState *cpu_xtensa_init(const char *cpu_model);
 218 void xtensa_translate_init(void);
 219 int cpu_xtensa_exec(CPUXtensaState *s);
 220 void do_interrupt(CPUXtensaState *s);
 221 int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc);
 222 void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 223 void xtensa_sync_window_from_phys(CPUState *env);
 224 void xtensa_sync_phys_from_window(CPUState *env);
 225
 226 #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
 227
 228 static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt)
 229 {
 230     return (config->options & XTENSA_OPTION_BIT(opt)) != 0;
 231 }
 232
 233 static inline int xtensa_get_cintlevel(const CPUState *env)
 234 {
 235     int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT;
 236     if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) {
 237         level = env->config->excm_level;
 238     }
 239     return level;
 240 }
 241
 242 static inline int xtensa_get_ring(const CPUState *env)
 243 {
 244     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 245         return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
 246     } else {
 247         return 0;
 248     }
 249 }
 250
 251 static inline int xtensa_get_cring(const CPUState *env)
 252 {
 253     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) &&
 254             (env->sregs[PS] & PS_EXCM) == 0) {
 255         return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
 256     } else {
 257         return 0;
 258     }
 259 }
 260
 261 /* MMU modes definitions */
 262 #define MMU_MODE0_SUFFIX _ring0
 263 #define MMU_MODE1_SUFFIX _ring1
 264 #define MMU_MODE2_SUFFIX _ring2
 265 #define MMU_MODE3_SUFFIX _ring3
 266
 267 static inline int cpu_mmu_index(CPUState *env)
 268 {
 269     return xtensa_get_cring(env);
 270 }
 271
 272 #define XTENSA_TBFLAG_RING_MASK 0x3
 273 #define XTENSA_TBFLAG_EXCM 0x4
 274
 275 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
 276         target_ulong *cs_base, int *flags)
 277 {
 278     *pc = env->pc;
 279     *cs_base = 0;
 280     *flags = 0;
 281     *flags |= xtensa_get_ring(env);
 282     if (env->sregs[PS] & PS_EXCM) {
 283         *flags |= XTENSA_TBFLAG_EXCM;
 284     }
 285 }
 286
 287 #include "cpu-all.h"
 288 #include "exec-all.h"
 289
 290 static inline int cpu_has_work(CPUState *env)
 291 {
 292     return 1;
 293 }
 294
 295 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
 296 {
 297     env->pc = tb->pc;
 298 }
 299
 300 #endif