2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of the Open Source and Linux Lab nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 #define TARGET_LONG_BITS 32
32 #define ELF_MACHINE EM_XTENSA
34 #define CPUState struct CPUXtensaState
37 #include "qemu-common.h"
40 #define TARGET_HAS_ICE 1
42 #define NB_MMU_MODES 4
44 #define TARGET_PHYS_ADDR_SPACE_BITS 32
45 #define TARGET_VIRT_ADDR_SPACE_BITS 32
46 #define TARGET_PAGE_BITS 12
49 /* Additional instructions */
50 XTENSA_OPTION_CODE_DENSITY
,
52 XTENSA_OPTION_EXTENDED_L32R
,
53 XTENSA_OPTION_16_BIT_IMUL
,
54 XTENSA_OPTION_32_BIT_IMUL
,
55 XTENSA_OPTION_32_BIT_IDIV
,
57 XTENSA_OPTION_MISC_OP
,
58 XTENSA_OPTION_COPROCESSOR
,
59 XTENSA_OPTION_BOOLEAN
,
60 XTENSA_OPTION_FP_COPROCESSOR
,
61 XTENSA_OPTION_MP_SYNCHRO
,
62 XTENSA_OPTION_CONDITIONAL_STORE
,
64 /* Interrupts and exceptions */
65 XTENSA_OPTION_EXCEPTION
,
66 XTENSA_OPTION_RELOCATABLE_VECTOR
,
67 XTENSA_OPTION_UNALIGNED_EXCEPTION
,
68 XTENSA_OPTION_INTERRUPT
,
69 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
70 XTENSA_OPTION_TIMER_INTERRUPT
,
74 XTENSA_OPTION_ICACHE_TEST
,
75 XTENSA_OPTION_ICACHE_INDEX_LOCK
,
77 XTENSA_OPTION_DCACHE_TEST
,
78 XTENSA_OPTION_DCACHE_INDEX_LOCK
,
84 XTENSA_OPTION_HW_ALIGNMENT
,
85 XTENSA_OPTION_MEMORY_ECC_PARITY
,
87 /* Memory protection and translation */
88 XTENSA_OPTION_REGION_PROTECTION
,
89 XTENSA_OPTION_REGION_TRANSLATION
,
93 XTENSA_OPTION_WINDOWED_REGISTER
,
94 XTENSA_OPTION_PROCESSOR_INTERFACE
,
95 XTENSA_OPTION_MISC_SR
,
96 XTENSA_OPTION_THREAD_POINTER
,
97 XTENSA_OPTION_PROCESSOR_ID
,
99 XTENSA_OPTION_TRACE_PORT
,
125 #define PS_INTLEVEL 0xf
126 #define PS_INTLEVEL_SHIFT 0
132 #define PS_RING_SHIFT 6
135 #define PS_OWB_SHIFT 8
137 #define PS_CALLINC 0x30000
138 #define PS_CALLINC_SHIFT 16
139 #define PS_CALLINC_LEN 2
141 #define PS_WOE 0x40000
150 /* Dynamic vectors */
151 EXC_WINDOW_OVERFLOW4
,
152 EXC_WINDOW_UNDERFLOW4
,
153 EXC_WINDOW_OVERFLOW8
,
154 EXC_WINDOW_UNDERFLOW8
,
155 EXC_WINDOW_OVERFLOW12
,
156 EXC_WINDOW_UNDERFLOW12
,
165 ILLEGAL_INSTRUCTION_CAUSE
= 0,
167 INSTRUCTION_FETCH_ERROR_CAUSE
,
168 LOAD_STORE_ERROR_CAUSE
,
169 LEVEL1_INTERRUPT_CAUSE
,
171 INTEGER_DIVIDE_BY_ZERO_CAUSE
,
172 PRIVILEGED_CAUSE
= 8,
173 LOAD_STORE_ALIGNMENT_CAUSE
,
175 INSTR_PIF_DATA_ERROR_CAUSE
= 12,
176 LOAD_STORE_PIF_DATA_ERROR_CAUSE
,
177 INSTR_PIF_ADDR_ERROR_CAUSE
,
178 LOAD_STORE_PIF_ADDR_ERROR_CAUSE
,
181 INST_TLB_MULTI_HIT_CAUSE
,
182 INST_FETCH_PRIVILEGE_CAUSE
,
183 INST_FETCH_PROHIBITED_CAUSE
= 20,
184 LOAD_STORE_TLB_MISS_CAUSE
= 24,
185 LOAD_STORE_TLB_MULTI_HIT_CAUSE
,
186 LOAD_STORE_PRIVILEGE_CAUSE
,
187 LOAD_PROHIBITED_CAUSE
= 28,
188 STORE_PROHIBITED_CAUSE
,
190 COPROCESSOR0_DISABLED
= 32,
193 typedef struct XtensaConfig
{
199 uint32_t exception_vector
[EXC_MAX
];
202 typedef struct CPUXtensaState
{
203 const XtensaConfig
*config
;
208 uint32_t phys_regs
[MAX_NAREG
];
215 #define cpu_init cpu_xtensa_init
216 #define cpu_exec cpu_xtensa_exec
217 #define cpu_gen_code cpu_xtensa_gen_code
218 #define cpu_signal_handler cpu_xtensa_signal_handler
219 #define cpu_list xtensa_cpu_list
221 CPUXtensaState
*cpu_xtensa_init(const char *cpu_model
);
222 void xtensa_translate_init(void);
223 int cpu_xtensa_exec(CPUXtensaState
*s
);
224 void do_interrupt(CPUXtensaState
*s
);
225 int cpu_xtensa_signal_handler(int host_signum
, void *pinfo
, void *puc
);
226 void xtensa_cpu_list(FILE *f
, fprintf_function cpu_fprintf
);
227 void xtensa_sync_window_from_phys(CPUState
*env
);
228 void xtensa_sync_phys_from_window(CPUState
*env
);
230 #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
232 static inline bool xtensa_option_enabled(const XtensaConfig
*config
, int opt
)
234 return (config
->options
& XTENSA_OPTION_BIT(opt
)) != 0;
237 static inline int xtensa_get_cintlevel(const CPUState
*env
)
239 int level
= (env
->sregs
[PS
] & PS_INTLEVEL
) >> PS_INTLEVEL_SHIFT
;
240 if ((env
->sregs
[PS
] & PS_EXCM
) && env
->config
->excm_level
> level
) {
241 level
= env
->config
->excm_level
;
246 static inline int xtensa_get_ring(const CPUState
*env
)
248 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_MMU
)) {
249 return (env
->sregs
[PS
] & PS_RING
) >> PS_RING_SHIFT
;
255 static inline int xtensa_get_cring(const CPUState
*env
)
257 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_MMU
) &&
258 (env
->sregs
[PS
] & PS_EXCM
) == 0) {
259 return (env
->sregs
[PS
] & PS_RING
) >> PS_RING_SHIFT
;
265 /* MMU modes definitions */
266 #define MMU_MODE0_SUFFIX _ring0
267 #define MMU_MODE1_SUFFIX _ring1
268 #define MMU_MODE2_SUFFIX _ring2
269 #define MMU_MODE3_SUFFIX _ring3
271 static inline int cpu_mmu_index(CPUState
*env
)
273 return xtensa_get_cring(env
);
276 #define XTENSA_TBFLAG_RING_MASK 0x3
277 #define XTENSA_TBFLAG_EXCM 0x4
278 #define XTENSA_TBFLAG_LITBASE 0x8
280 static inline void cpu_get_tb_cpu_state(CPUState
*env
, target_ulong
*pc
,
281 target_ulong
*cs_base
, int *flags
)
286 *flags
|= xtensa_get_ring(env
);
287 if (env
->sregs
[PS
] & PS_EXCM
) {
288 *flags
|= XTENSA_TBFLAG_EXCM
;
290 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_EXTENDED_L32R
) &&
291 (env
->sregs
[LITBASE
] & 1)) {
292 *flags
|= XTENSA_TBFLAG_LITBASE
;
297 #include "exec-all.h"
299 static inline int cpu_has_work(CPUState
*env
)
304 static inline void cpu_pc_from_tb(CPUState
*env
, TranslationBlock
*tb
)