2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of the Open Source and Linux Lab nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 #define TARGET_LONG_BITS 32
32 #define ELF_MACHINE EM_XTENSA
34 #define CPUState struct CPUXtensaState
37 #include "qemu-common.h"
40 #define TARGET_HAS_ICE 1
42 #define NB_MMU_MODES 4
44 #define TARGET_PHYS_ADDR_SPACE_BITS 32
45 #define TARGET_VIRT_ADDR_SPACE_BITS 32
46 #define TARGET_PAGE_BITS 12
49 /* Additional instructions */
50 XTENSA_OPTION_CODE_DENSITY
,
52 XTENSA_OPTION_EXTENDED_L32R
,
53 XTENSA_OPTION_16_BIT_IMUL
,
54 XTENSA_OPTION_32_BIT_IMUL
,
55 XTENSA_OPTION_32_BIT_IDIV
,
57 XTENSA_OPTION_MISC_OP
,
58 XTENSA_OPTION_COPROCESSOR
,
59 XTENSA_OPTION_BOOLEAN
,
60 XTENSA_OPTION_FP_COPROCESSOR
,
61 XTENSA_OPTION_MP_SYNCHRO
,
62 XTENSA_OPTION_CONDITIONAL_STORE
,
64 /* Interrupts and exceptions */
65 XTENSA_OPTION_EXCEPTION
,
66 XTENSA_OPTION_RELOCATABLE_VECTOR
,
67 XTENSA_OPTION_UNALIGNED_EXCEPTION
,
68 XTENSA_OPTION_INTERRUPT
,
69 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
70 XTENSA_OPTION_TIMER_INTERRUPT
,
74 XTENSA_OPTION_ICACHE_TEST
,
75 XTENSA_OPTION_ICACHE_INDEX_LOCK
,
77 XTENSA_OPTION_DCACHE_TEST
,
78 XTENSA_OPTION_DCACHE_INDEX_LOCK
,
84 XTENSA_OPTION_HW_ALIGNMENT
,
85 XTENSA_OPTION_MEMORY_ECC_PARITY
,
87 /* Memory protection and translation */
88 XTENSA_OPTION_REGION_PROTECTION
,
89 XTENSA_OPTION_REGION_TRANSLATION
,
93 XTENSA_OPTION_WINDOWED_REGISTER
,
94 XTENSA_OPTION_PROCESSOR_INTERFACE
,
95 XTENSA_OPTION_MISC_SR
,
96 XTENSA_OPTION_THREAD_POINTER
,
97 XTENSA_OPTION_PROCESSOR_ID
,
99 XTENSA_OPTION_TRACE_PORT
,
134 #define PS_INTLEVEL 0xf
135 #define PS_INTLEVEL_SHIFT 0
141 #define PS_RING_SHIFT 6
144 #define PS_OWB_SHIFT 8
146 #define PS_CALLINC 0x30000
147 #define PS_CALLINC_SHIFT 16
148 #define PS_CALLINC_LEN 2
150 #define PS_WOE 0x40000
153 #define MAX_NINTERRUPT 32
156 #define MAX_NCCOMPARE 3
163 /* Dynamic vectors */
164 EXC_WINDOW_OVERFLOW4
,
165 EXC_WINDOW_UNDERFLOW4
,
166 EXC_WINDOW_OVERFLOW8
,
167 EXC_WINDOW_UNDERFLOW8
,
168 EXC_WINDOW_OVERFLOW12
,
169 EXC_WINDOW_UNDERFLOW12
,
178 ILLEGAL_INSTRUCTION_CAUSE
= 0,
180 INSTRUCTION_FETCH_ERROR_CAUSE
,
181 LOAD_STORE_ERROR_CAUSE
,
182 LEVEL1_INTERRUPT_CAUSE
,
184 INTEGER_DIVIDE_BY_ZERO_CAUSE
,
185 PRIVILEGED_CAUSE
= 8,
186 LOAD_STORE_ALIGNMENT_CAUSE
,
188 INSTR_PIF_DATA_ERROR_CAUSE
= 12,
189 LOAD_STORE_PIF_DATA_ERROR_CAUSE
,
190 INSTR_PIF_ADDR_ERROR_CAUSE
,
191 LOAD_STORE_PIF_ADDR_ERROR_CAUSE
,
194 INST_TLB_MULTI_HIT_CAUSE
,
195 INST_FETCH_PRIVILEGE_CAUSE
,
196 INST_FETCH_PROHIBITED_CAUSE
= 20,
197 LOAD_STORE_TLB_MISS_CAUSE
= 24,
198 LOAD_STORE_TLB_MULTI_HIT_CAUSE
,
199 LOAD_STORE_PRIVILEGE_CAUSE
,
200 LOAD_PROHIBITED_CAUSE
= 28,
201 STORE_PROHIBITED_CAUSE
,
203 COPROCESSOR0_DISABLED
= 32,
217 typedef struct XtensaConfig
{
224 uint32_t exception_vector
[EXC_MAX
];
227 uint32_t interrupt_vector
[MAX_NLEVEL
+ MAX_NNMI
+ 1];
228 uint32_t level_mask
[MAX_NLEVEL
+ MAX_NNMI
+ 1];
229 uint32_t inttype_mask
[INTTYPE_MAX
];
232 interrupt_type inttype
;
233 } interrupt
[MAX_NINTERRUPT
];
235 uint32_t timerint
[MAX_NCCOMPARE
];
236 uint32_t clock_freq_khz
;
239 typedef struct CPUXtensaState
{
240 const XtensaConfig
*config
;
245 uint32_t phys_regs
[MAX_NAREG
];
247 int pending_irq_level
; /* level of last raised IRQ */
249 QEMUTimer
*ccompare_timer
;
250 uint32_t wake_ccount
;
258 #define cpu_init cpu_xtensa_init
259 #define cpu_exec cpu_xtensa_exec
260 #define cpu_gen_code cpu_xtensa_gen_code
261 #define cpu_signal_handler cpu_xtensa_signal_handler
262 #define cpu_list xtensa_cpu_list
264 CPUXtensaState
*cpu_xtensa_init(const char *cpu_model
);
265 void xtensa_translate_init(void);
266 int cpu_xtensa_exec(CPUXtensaState
*s
);
267 void do_interrupt(CPUXtensaState
*s
);
268 void check_interrupts(CPUXtensaState
*s
);
269 void xtensa_irq_init(CPUState
*env
);
270 void xtensa_advance_ccount(CPUState
*env
, uint32_t d
);
271 void xtensa_timer_irq(CPUState
*env
, uint32_t id
, uint32_t active
);
272 int cpu_xtensa_signal_handler(int host_signum
, void *pinfo
, void *puc
);
273 void xtensa_cpu_list(FILE *f
, fprintf_function cpu_fprintf
);
274 void xtensa_sync_window_from_phys(CPUState
*env
);
275 void xtensa_sync_phys_from_window(CPUState
*env
);
277 #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
279 static inline bool xtensa_option_enabled(const XtensaConfig
*config
, int opt
)
281 return (config
->options
& XTENSA_OPTION_BIT(opt
)) != 0;
284 static inline int xtensa_get_cintlevel(const CPUState
*env
)
286 int level
= (env
->sregs
[PS
] & PS_INTLEVEL
) >> PS_INTLEVEL_SHIFT
;
287 if ((env
->sregs
[PS
] & PS_EXCM
) && env
->config
->excm_level
> level
) {
288 level
= env
->config
->excm_level
;
293 static inline int xtensa_get_ring(const CPUState
*env
)
295 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_MMU
)) {
296 return (env
->sregs
[PS
] & PS_RING
) >> PS_RING_SHIFT
;
302 static inline int xtensa_get_cring(const CPUState
*env
)
304 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_MMU
) &&
305 (env
->sregs
[PS
] & PS_EXCM
) == 0) {
306 return (env
->sregs
[PS
] & PS_RING
) >> PS_RING_SHIFT
;
312 /* MMU modes definitions */
313 #define MMU_MODE0_SUFFIX _ring0
314 #define MMU_MODE1_SUFFIX _ring1
315 #define MMU_MODE2_SUFFIX _ring2
316 #define MMU_MODE3_SUFFIX _ring3
318 static inline int cpu_mmu_index(CPUState
*env
)
320 return xtensa_get_cring(env
);
323 #define XTENSA_TBFLAG_RING_MASK 0x3
324 #define XTENSA_TBFLAG_EXCM 0x4
325 #define XTENSA_TBFLAG_LITBASE 0x8
327 static inline void cpu_get_tb_cpu_state(CPUState
*env
, target_ulong
*pc
,
328 target_ulong
*cs_base
, int *flags
)
333 *flags
|= xtensa_get_ring(env
);
334 if (env
->sregs
[PS
] & PS_EXCM
) {
335 *flags
|= XTENSA_TBFLAG_EXCM
;
337 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_EXTENDED_L32R
) &&
338 (env
->sregs
[LITBASE
] & 1)) {
339 *flags
|= XTENSA_TBFLAG_LITBASE
;
344 #include "exec-all.h"
346 static inline int cpu_has_work(CPUState
*env
)
348 return env
->pending_irq_level
;
351 static inline void cpu_pc_from_tb(CPUState
*env
, TranslationBlock
*tb
)