target-xtensa/cpu.h

   1 /*
   2  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *     * Redistributions of source code must retain the above copyright
   8  *       notice, this list of conditions and the following disclaimer.
   9  *     * Redistributions in binary form must reproduce the above copyright
  10  *       notice, this list of conditions and the following disclaimer in the
  11  *       documentation and/or other materials provided with the distribution.
  12  *     * Neither the name of the Open Source and Linux Lab nor the
  13  *       names of its contributors may be used to endorse or promote products
  14  *       derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  25  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #ifndef CPU_XTENSA_H
  29 #define CPU_XTENSA_H
  30
  31 #define TARGET_LONG_BITS 32
  32 #define ELF_MACHINE EM_XTENSA
  33
  34 #define CPUState struct CPUXtensaState
  35
  36 #include "config.h"
  37 #include "qemu-common.h"
  38 #include "cpu-defs.h"
  39
  40 #define TARGET_HAS_ICE 1
  41
  42 #define NB_MMU_MODES 4
  43
  44 #define TARGET_PHYS_ADDR_SPACE_BITS 32
  45 #define TARGET_VIRT_ADDR_SPACE_BITS 32
  46 #define TARGET_PAGE_BITS 12
  47
  48 enum {
  49     /* Additional instructions */
  50     XTENSA_OPTION_CODE_DENSITY,
  51     XTENSA_OPTION_LOOP,
  52     XTENSA_OPTION_EXTENDED_L32R,
  53     XTENSA_OPTION_16_BIT_IMUL,
  54     XTENSA_OPTION_32_BIT_IMUL,
  55     XTENSA_OPTION_32_BIT_IDIV,
  56     XTENSA_OPTION_MAC16,
  57     XTENSA_OPTION_MISC_OP,
  58     XTENSA_OPTION_COPROCESSOR,
  59     XTENSA_OPTION_BOOLEAN,
  60     XTENSA_OPTION_FP_COPROCESSOR,
  61     XTENSA_OPTION_MP_SYNCHRO,
  62     XTENSA_OPTION_CONDITIONAL_STORE,
  63
  64     /* Interrupts and exceptions */
  65     XTENSA_OPTION_EXCEPTION,
  66     XTENSA_OPTION_RELOCATABLE_VECTOR,
  67     XTENSA_OPTION_UNALIGNED_EXCEPTION,
  68     XTENSA_OPTION_INTERRUPT,
  69     XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
  70     XTENSA_OPTION_TIMER_INTERRUPT,
  71
  72     /* Local memory */
  73     XTENSA_OPTION_ICACHE,
  74     XTENSA_OPTION_ICACHE_TEST,
  75     XTENSA_OPTION_ICACHE_INDEX_LOCK,
  76     XTENSA_OPTION_DCACHE,
  77     XTENSA_OPTION_DCACHE_TEST,
  78     XTENSA_OPTION_DCACHE_INDEX_LOCK,
  79     XTENSA_OPTION_IRAM,
  80     XTENSA_OPTION_IROM,
  81     XTENSA_OPTION_DRAM,
  82     XTENSA_OPTION_DROM,
  83     XTENSA_OPTION_XLMI,
  84     XTENSA_OPTION_HW_ALIGNMENT,
  85     XTENSA_OPTION_MEMORY_ECC_PARITY,
  86
  87     /* Memory protection and translation */
  88     XTENSA_OPTION_REGION_PROTECTION,
  89     XTENSA_OPTION_REGION_TRANSLATION,
  90     XTENSA_OPTION_MMU,
  91
  92     /* Other */
  93     XTENSA_OPTION_WINDOWED_REGISTER,
  94     XTENSA_OPTION_PROCESSOR_INTERFACE,
  95     XTENSA_OPTION_MISC_SR,
  96     XTENSA_OPTION_THREAD_POINTER,
  97     XTENSA_OPTION_PROCESSOR_ID,
  98     XTENSA_OPTION_DEBUG,
  99     XTENSA_OPTION_TRACE_PORT,
 100 };
 101
 102 enum {
 103     THREADPTR = 231,
 104     FCR = 232,
 105     FSR = 233,
 106 };
 107
 108 enum {
 109     LBEG = 0,
 110     LEND = 1,
 111     LCOUNT = 2,
 112     SAR = 3,
 113     LITBASE = 5,
 114     SCOMPARE1 = 12,
 115     WINDOW_BASE = 72,
 116     WINDOW_START = 73,
 117     EPC1 = 177,
 118     DEPC = 192,
 119     EPS2 = 194,
 120     EXCSAVE1 = 209,
 121     INTSET = 226,
 122     INTCLEAR = 227,
 123     INTENABLE = 228,
 124     PS = 230,
 125     EXCCAUSE = 232,
 126     CCOUNT = 234,
 127     EXCVADDR = 238,
 128     CCOMPARE = 240,
 129 };
 130
 131 #define PS_INTLEVEL 0xf
 132 #define PS_INTLEVEL_SHIFT 0
 133
 134 #define PS_EXCM 0x10
 135 #define PS_UM 0x20
 136
 137 #define PS_RING 0xc0
 138 #define PS_RING_SHIFT 6
 139
 140 #define PS_OWB 0xf00
 141 #define PS_OWB_SHIFT 8
 142
 143 #define PS_CALLINC 0x30000
 144 #define PS_CALLINC_SHIFT 16
 145 #define PS_CALLINC_LEN 2
 146
 147 #define PS_WOE 0x40000
 148
 149 #define MAX_NAREG 64
 150 #define MAX_NINTERRUPT 32
 151 #define MAX_NLEVEL 6
 152 #define MAX_NNMI 1
 153 #define MAX_NCCOMPARE 3
 154
 155 enum {
 156     /* Static vectors */
 157     EXC_RESET,
 158     EXC_MEMORY_ERROR,
 159
 160     /* Dynamic vectors */
 161     EXC_WINDOW_OVERFLOW4,
 162     EXC_WINDOW_UNDERFLOW4,
 163     EXC_WINDOW_OVERFLOW8,
 164     EXC_WINDOW_UNDERFLOW8,
 165     EXC_WINDOW_OVERFLOW12,
 166     EXC_WINDOW_UNDERFLOW12,
 167     EXC_IRQ,
 168     EXC_KERNEL,
 169     EXC_USER,
 170     EXC_DOUBLE,
 171     EXC_MAX
 172 };
 173
 174 enum {
 175     ILLEGAL_INSTRUCTION_CAUSE = 0,
 176     SYSCALL_CAUSE,
 177     INSTRUCTION_FETCH_ERROR_CAUSE,
 178     LOAD_STORE_ERROR_CAUSE,
 179     LEVEL1_INTERRUPT_CAUSE,
 180     ALLOCA_CAUSE,
 181     INTEGER_DIVIDE_BY_ZERO_CAUSE,
 182     PRIVILEGED_CAUSE = 8,
 183     LOAD_STORE_ALIGNMENT_CAUSE,
 184
 185     INSTR_PIF_DATA_ERROR_CAUSE = 12,
 186     LOAD_STORE_PIF_DATA_ERROR_CAUSE,
 187     INSTR_PIF_ADDR_ERROR_CAUSE,
 188     LOAD_STORE_PIF_ADDR_ERROR_CAUSE,
 189
 190     INST_TLB_MISS_CAUSE,
 191     INST_TLB_MULTI_HIT_CAUSE,
 192     INST_FETCH_PRIVILEGE_CAUSE,
 193     INST_FETCH_PROHIBITED_CAUSE = 20,
 194     LOAD_STORE_TLB_MISS_CAUSE = 24,
 195     LOAD_STORE_TLB_MULTI_HIT_CAUSE,
 196     LOAD_STORE_PRIVILEGE_CAUSE,
 197     LOAD_PROHIBITED_CAUSE = 28,
 198     STORE_PROHIBITED_CAUSE,
 199
 200     COPROCESSOR0_DISABLED = 32,
 201 };
 202
 203 typedef enum {
 204     INTTYPE_LEVEL,
 205     INTTYPE_EDGE,
 206     INTTYPE_NMI,
 207     INTTYPE_SOFTWARE,
 208     INTTYPE_TIMER,
 209     INTTYPE_DEBUG,
 210     INTTYPE_WRITE_ERR,
 211     INTTYPE_MAX
 212 } interrupt_type;
 213
 214 typedef struct XtensaConfig {
 215     const char *name;
 216     uint64_t options;
 217     unsigned nareg;
 218     int excm_level;
 219     int ndepc;
 220     uint32_t exception_vector[EXC_MAX];
 221     unsigned ninterrupt;
 222     unsigned nlevel;
 223     uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1];
 224     uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1];
 225     uint32_t inttype_mask[INTTYPE_MAX];
 226     struct {
 227         uint32_t level;
 228         interrupt_type inttype;
 229     } interrupt[MAX_NINTERRUPT];
 230     unsigned nccompare;
 231     uint32_t timerint[MAX_NCCOMPARE];
 232     uint32_t clock_freq_khz;
 233 } XtensaConfig;
 234
 235 typedef struct CPUXtensaState {
 236     const XtensaConfig *config;
 237     uint32_t regs[16];
 238     uint32_t pc;
 239     uint32_t sregs[256];
 240     uint32_t uregs[256];
 241     uint32_t phys_regs[MAX_NAREG];
 242
 243     int pending_irq_level; /* level of last raised IRQ */
 244     void **irq_inputs;
 245     QEMUTimer *ccompare_timer;
 246     uint32_t wake_ccount;
 247     int64_t halt_clock;
 248
 249     int exception_taken;
 250
 251     CPU_COMMON
 252 } CPUXtensaState;
 253
 254 #define cpu_init cpu_xtensa_init
 255 #define cpu_exec cpu_xtensa_exec
 256 #define cpu_gen_code cpu_xtensa_gen_code
 257 #define cpu_signal_handler cpu_xtensa_signal_handler
 258 #define cpu_list xtensa_cpu_list
 259
 260 CPUXtensaState *cpu_xtensa_init(const char *cpu_model);
 261 void xtensa_translate_init(void);
 262 int cpu_xtensa_exec(CPUXtensaState *s);
 263 void do_interrupt(CPUXtensaState *s);
 264 void check_interrupts(CPUXtensaState *s);
 265 void xtensa_irq_init(CPUState *env);
 266 void xtensa_advance_ccount(CPUState *env, uint32_t d);
 267 void xtensa_timer_irq(CPUState *env, uint32_t id, uint32_t active);
 268 int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc);
 269 void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 270 void xtensa_sync_window_from_phys(CPUState *env);
 271 void xtensa_sync_phys_from_window(CPUState *env);
 272
 273 #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
 274
 275 static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt)
 276 {
 277     return (config->options & XTENSA_OPTION_BIT(opt)) != 0;
 278 }
 279
 280 static inline int xtensa_get_cintlevel(const CPUState *env)
 281 {
 282     int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT;
 283     if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) {
 284         level = env->config->excm_level;
 285     }
 286     return level;
 287 }
 288
 289 static inline int xtensa_get_ring(const CPUState *env)
 290 {
 291     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 292         return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
 293     } else {
 294         return 0;
 295     }
 296 }
 297
 298 static inline int xtensa_get_cring(const CPUState *env)
 299 {
 300     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) &&
 301             (env->sregs[PS] & PS_EXCM) == 0) {
 302         return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
 303     } else {
 304         return 0;
 305     }
 306 }
 307
 308 /* MMU modes definitions */
 309 #define MMU_MODE0_SUFFIX _ring0
 310 #define MMU_MODE1_SUFFIX _ring1
 311 #define MMU_MODE2_SUFFIX _ring2
 312 #define MMU_MODE3_SUFFIX _ring3
 313
 314 static inline int cpu_mmu_index(CPUState *env)
 315 {
 316     return xtensa_get_cring(env);
 317 }
 318
 319 #define XTENSA_TBFLAG_RING_MASK 0x3
 320 #define XTENSA_TBFLAG_EXCM 0x4
 321 #define XTENSA_TBFLAG_LITBASE 0x8
 322
 323 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
 324         target_ulong *cs_base, int *flags)
 325 {
 326     *pc = env->pc;
 327     *cs_base = 0;
 328     *flags = 0;
 329     *flags |= xtensa_get_ring(env);
 330     if (env->sregs[PS] & PS_EXCM) {
 331         *flags |= XTENSA_TBFLAG_EXCM;
 332     }
 333     if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
 334             (env->sregs[LITBASE] & 1)) {
 335         *flags |= XTENSA_TBFLAG_LITBASE;
 336     }
 337 }
 338
 339 #include "cpu-all.h"
 340 #include "exec-all.h"
 341
 342 static inline int cpu_has_work(CPUState *env)
 343 {
 344     return env->pending_irq_level;
 345 }
 346
 347 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
 348 {
 349     env->pc = tb->pc;
 350 }
 351
 352 #endif