target-xtensa/helper.c

   1 /*
   2  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *     * Redistributions of source code must retain the above copyright
   8  *       notice, this list of conditions and the following disclaimer.
   9  *     * Redistributions in binary form must reproduce the above copyright
  10  *       notice, this list of conditions and the following disclaimer in the
  11  *       documentation and/or other materials provided with the distribution.
  12  *     * Neither the name of the Open Source and Linux Lab nor the
  13  *       names of its contributors may be used to endorse or promote products
  14  *       derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  25  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #include "cpu.h"
  29 #include "exec/exec-all.h"
  30 #include "exec/gdbstub.h"
  31 #include "qemu/host-utils.h"
  32 #if !defined(CONFIG_USER_ONLY)
  33 #include "hw/loader.h"
  34 #endif
  35
  36 static struct XtensaConfigList *xtensa_cores;
  37
  38 void xtensa_register_core(XtensaConfigList *node)
  39 {
  40     node->next = xtensa_cores;
  41     xtensa_cores = node;
  42 }
  43
  44 static uint32_t check_hw_breakpoints(CPUXtensaState *env)
  45 {
  46     unsigned i;
  47
  48     for (i = 0; i < env->config->ndbreak; ++i) {
  49         if (env->cpu_watchpoint[i] &&
  50                 env->cpu_watchpoint[i]->flags & BP_WATCHPOINT_HIT) {
  51             return DEBUGCAUSE_DB | (i << DEBUGCAUSE_DBNUM_SHIFT);
  52         }
  53     }
  54     return 0;
  55 }
  56
  57 void xtensa_breakpoint_handler(CPUXtensaState *env)
  58 {
  59     if (env->watchpoint_hit) {
  60         if (env->watchpoint_hit->flags & BP_CPU) {
  61             uint32_t cause;
  62
  63             env->watchpoint_hit = NULL;
  64             cause = check_hw_breakpoints(env);
  65             if (cause) {
  66                 debug_exception_env(env, cause);
  67             }
  68             cpu_resume_from_signal(env, NULL);
  69         }
  70     }
  71 }
  72
  73 XtensaCPU *cpu_xtensa_init(const char *cpu_model)
  74 {
  75     XtensaCPU *cpu;
  76     CPUXtensaState *env;
  77     const XtensaConfig *config = NULL;
  78     XtensaConfigList *core = xtensa_cores;
  79
  80     for (; core; core = core->next)
  81         if (strcmp(core->config->name, cpu_model) == 0) {
  82             config = core->config;
  83             break;
  84         }
  85
  86     if (config == NULL) {
  87         return NULL;
  88     }
  89
  90     cpu = XTENSA_CPU(object_new(TYPE_XTENSA_CPU));
  91     env = &cpu->env;
  92     env->config = config;
  93
  94     xtensa_irq_init(env);
  95
  96     object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
  97
  98     return cpu;
  99 }
 100
 101
 102 void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf)
 103 {
 104     XtensaConfigList *core = xtensa_cores;
 105     cpu_fprintf(f, "Available CPUs:\n");
 106     for (; core; core = core->next) {
 107         cpu_fprintf(f, "  %s\n", core->config->name);
 108     }
 109 }
 110
 111 hwaddr cpu_get_phys_page_debug(CPUXtensaState *env, target_ulong addr)
 112 {
 113     uint32_t paddr;
 114     uint32_t page_size;
 115     unsigned access;
 116
 117     if (xtensa_get_physical_addr(env, false, addr, 0, 0,
 118                 &paddr, &page_size, &access) == 0) {
 119         return paddr;
 120     }
 121     if (xtensa_get_physical_addr(env, false, addr, 2, 0,
 122                 &paddr, &page_size, &access) == 0) {
 123         return paddr;
 124     }
 125     return ~0;
 126 }
 127
 128 static uint32_t relocated_vector(CPUXtensaState *env, uint32_t vector)
 129 {
 130     if (xtensa_option_enabled(env->config,
 131                 XTENSA_OPTION_RELOCATABLE_VECTOR)) {
 132         return vector - env->config->vecbase + env->sregs[VECBASE];
 133     } else {
 134         return vector;
 135     }
 136 }
 137
 138 /*!
 139  * Handle penging IRQ.
 140  * For the high priority interrupt jump to the corresponding interrupt vector.
 141  * For the level-1 interrupt convert it to either user, kernel or double
 142  * exception with the 'level-1 interrupt' exception cause.
 143  */
 144 static void handle_interrupt(CPUXtensaState *env)
 145 {
 146     int level = env->pending_irq_level;
 147
 148     if (level > xtensa_get_cintlevel(env) &&
 149             level <= env->config->nlevel &&
 150             (env->config->level_mask[level] &
 151              env->sregs[INTSET] &
 152              env->sregs[INTENABLE])) {
 153         if (level > 1) {
 154             env->sregs[EPC1 + level - 1] = env->pc;
 155             env->sregs[EPS2 + level - 2] = env->sregs[PS];
 156             env->sregs[PS] =
 157                 (env->sregs[PS] & ~PS_INTLEVEL) | level | PS_EXCM;
 158             env->pc = relocated_vector(env,
 159                     env->config->interrupt_vector[level]);
 160         } else {
 161             env->sregs[EXCCAUSE] = LEVEL1_INTERRUPT_CAUSE;
 162
 163             if (env->sregs[PS] & PS_EXCM) {
 164                 if (env->config->ndepc) {
 165                     env->sregs[DEPC] = env->pc;
 166                 } else {
 167                     env->sregs[EPC1] = env->pc;
 168                 }
 169                 env->exception_index = EXC_DOUBLE;
 170             } else {
 171                 env->sregs[EPC1] = env->pc;
 172                 env->exception_index =
 173                     (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL;
 174             }
 175             env->sregs[PS] |= PS_EXCM;
 176         }
 177         env->exception_taken = 1;
 178     }
 179 }
 180
 181 void do_interrupt(CPUXtensaState *env)
 182 {
 183     if (env->exception_index == EXC_IRQ) {
 184         qemu_log_mask(CPU_LOG_INT,
 185                 "%s(EXC_IRQ) level = %d, cintlevel = %d, "
 186                 "pc = %08x, a0 = %08x, ps = %08x, "
 187                 "intset = %08x, intenable = %08x, "
 188                 "ccount = %08x\n",
 189                 __func__, env->pending_irq_level, xtensa_get_cintlevel(env),
 190                 env->pc, env->regs[0], env->sregs[PS],
 191                 env->sregs[INTSET], env->sregs[INTENABLE],
 192                 env->sregs[CCOUNT]);
 193         handle_interrupt(env);
 194     }
 195
 196     switch (env->exception_index) {
 197     case EXC_WINDOW_OVERFLOW4:
 198     case EXC_WINDOW_UNDERFLOW4:
 199     case EXC_WINDOW_OVERFLOW8:
 200     case EXC_WINDOW_UNDERFLOW8:
 201     case EXC_WINDOW_OVERFLOW12:
 202     case EXC_WINDOW_UNDERFLOW12:
 203     case EXC_KERNEL:
 204     case EXC_USER:
 205     case EXC_DOUBLE:
 206     case EXC_DEBUG:
 207         qemu_log_mask(CPU_LOG_INT, "%s(%d) "
 208                 "pc = %08x, a0 = %08x, ps = %08x, ccount = %08x\n",
 209                 __func__, env->exception_index,
 210                 env->pc, env->regs[0], env->sregs[PS], env->sregs[CCOUNT]);
 211         if (env->config->exception_vector[env->exception_index]) {
 212             env->pc = relocated_vector(env,
 213                     env->config->exception_vector[env->exception_index]);
 214             env->exception_taken = 1;
 215         } else {
 216             qemu_log("%s(pc = %08x) bad exception_index: %d\n",
 217                     __func__, env->pc, env->exception_index);
 218         }
 219         break;
 220
 221     case EXC_IRQ:
 222         break;
 223
 224     default:
 225         qemu_log("%s(pc = %08x) unknown exception_index: %d\n",
 226                 __func__, env->pc, env->exception_index);
 227         break;
 228     }
 229     check_interrupts(env);
 230 }
 231
 232 static void reset_tlb_mmu_all_ways(CPUXtensaState *env,
 233         const xtensa_tlb *tlb, xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
 234 {
 235     unsigned wi, ei;
 236
 237     for (wi = 0; wi < tlb->nways; ++wi) {
 238         for (ei = 0; ei < tlb->way_size[wi]; ++ei) {
 239             entry[wi][ei].asid = 0;
 240             entry[wi][ei].variable = true;
 241         }
 242     }
 243 }
 244
 245 static void reset_tlb_mmu_ways56(CPUXtensaState *env,
 246         const xtensa_tlb *tlb, xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
 247 {
 248     if (!tlb->varway56) {
 249         static const xtensa_tlb_entry way5[] = {
 250             {
 251                 .vaddr = 0xd0000000,
 252                 .paddr = 0,
 253                 .asid = 1,
 254                 .attr = 7,
 255                 .variable = false,
 256             }, {
 257                 .vaddr = 0xd8000000,
 258                 .paddr = 0,
 259                 .asid = 1,
 260                 .attr = 3,
 261                 .variable = false,
 262             }
 263         };
 264         static const xtensa_tlb_entry way6[] = {
 265             {
 266                 .vaddr = 0xe0000000,
 267                 .paddr = 0xf0000000,
 268                 .asid = 1,
 269                 .attr = 7,
 270                 .variable = false,
 271             }, {
 272                 .vaddr = 0xf0000000,
 273                 .paddr = 0xf0000000,
 274                 .asid = 1,
 275                 .attr = 3,
 276                 .variable = false,
 277             }
 278         };
 279         memcpy(entry[5], way5, sizeof(way5));
 280         memcpy(entry[6], way6, sizeof(way6));
 281     } else {
 282         uint32_t ei;
 283         for (ei = 0; ei < 8; ++ei) {
 284             entry[6][ei].vaddr = ei << 29;
 285             entry[6][ei].paddr = ei << 29;
 286             entry[6][ei].asid = 1;
 287             entry[6][ei].attr = 3;
 288         }
 289     }
 290 }
 291
 292 static void reset_tlb_region_way0(CPUXtensaState *env,
 293         xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
 294 {
 295     unsigned ei;
 296
 297     for (ei = 0; ei < 8; ++ei) {
 298         entry[0][ei].vaddr = ei << 29;
 299         entry[0][ei].paddr = ei << 29;
 300         entry[0][ei].asid = 1;
 301         entry[0][ei].attr = 2;
 302         entry[0][ei].variable = true;
 303     }
 304 }
 305
 306 void reset_mmu(CPUXtensaState *env)
 307 {
 308     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 309         env->sregs[RASID] = 0x04030201;
 310         env->sregs[ITLBCFG] = 0;
 311         env->sregs[DTLBCFG] = 0;
 312         env->autorefill_idx = 0;
 313         reset_tlb_mmu_all_ways(env, &env->config->itlb, env->itlb);
 314         reset_tlb_mmu_all_ways(env, &env->config->dtlb, env->dtlb);
 315         reset_tlb_mmu_ways56(env, &env->config->itlb, env->itlb);
 316         reset_tlb_mmu_ways56(env, &env->config->dtlb, env->dtlb);
 317     } else {
 318         reset_tlb_region_way0(env, env->itlb);
 319         reset_tlb_region_way0(env, env->dtlb);
 320     }
 321 }
 322
 323 static unsigned get_ring(const CPUXtensaState *env, uint8_t asid)
 324 {
 325     unsigned i;
 326     for (i = 0; i < 4; ++i) {
 327         if (((env->sregs[RASID] >> i * 8) & 0xff) == asid) {
 328             return i;
 329         }
 330     }
 331     return 0xff;
 332 }
 333
 334 /*!
 335  * Lookup xtensa TLB for the given virtual address.
 336  * See ISA, 4.6.2.2
 337  *
 338  * \param pwi: [out] way index
 339  * \param pei: [out] entry index
 340  * \param pring: [out] access ring
 341  * \return 0 if ok, exception cause code otherwise
 342  */
 343 int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
 344         uint32_t *pwi, uint32_t *pei, uint8_t *pring)
 345 {
 346     const xtensa_tlb *tlb = dtlb ?
 347         &env->config->dtlb : &env->config->itlb;
 348     const xtensa_tlb_entry (*entry)[MAX_TLB_WAY_SIZE] = dtlb ?
 349         env->dtlb : env->itlb;
 350
 351     int nhits = 0;
 352     unsigned wi;
 353
 354     for (wi = 0; wi < tlb->nways; ++wi) {
 355         uint32_t vpn;
 356         uint32_t ei;
 357         split_tlb_entry_spec_way(env, addr, dtlb, &vpn, wi, &ei);
 358         if (entry[wi][ei].vaddr == vpn && entry[wi][ei].asid) {
 359             unsigned ring = get_ring(env, entry[wi][ei].asid);
 360             if (ring < 4) {
 361                 if (++nhits > 1) {
 362                     return dtlb ?
 363                         LOAD_STORE_TLB_MULTI_HIT_CAUSE :
 364                         INST_TLB_MULTI_HIT_CAUSE;
 365                 }
 366                 *pwi = wi;
 367                 *pei = ei;
 368                 *pring = ring;
 369             }
 370         }
 371     }
 372     return nhits ? 0 :
 373         (dtlb ? LOAD_STORE_TLB_MISS_CAUSE : INST_TLB_MISS_CAUSE);
 374 }
 375
 376 /*!
 377  * Convert MMU ATTR to PAGE_{READ,WRITE,EXEC} mask.
 378  * See ISA, 4.6.5.10
 379  */
 380 static unsigned mmu_attr_to_access(uint32_t attr)
 381 {
 382     unsigned access = 0;
 383
 384     if (attr < 12) {
 385         access |= PAGE_READ;
 386         if (attr & 0x1) {
 387             access |= PAGE_EXEC;
 388         }
 389         if (attr & 0x2) {
 390             access |= PAGE_WRITE;
 391         }
 392
 393         switch (attr & 0xc) {
 394         case 0:
 395             access |= PAGE_CACHE_BYPASS;
 396             break;
 397
 398         case 4:
 399             access |= PAGE_CACHE_WB;
 400             break;
 401
 402         case 8:
 403             access |= PAGE_CACHE_WT;
 404             break;
 405         }
 406     } else if (attr == 13) {
 407         access |= PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE;
 408     }
 409     return access;
 410 }
 411
 412 /*!
 413  * Convert region protection ATTR to PAGE_{READ,WRITE,EXEC} mask.
 414  * See ISA, 4.6.3.3
 415  */
 416 static unsigned region_attr_to_access(uint32_t attr)
 417 {
 418     static const unsigned access[16] = {
 419          [0] = PAGE_READ | PAGE_WRITE             | PAGE_CACHE_WT,
 420          [1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT,
 421          [2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS,
 422          [3] =                          PAGE_EXEC | PAGE_CACHE_WB,
 423          [4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
 424          [5] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
 425         [14] = PAGE_READ | PAGE_WRITE             | PAGE_CACHE_ISOLATE,
 426     };
 427
 428     return access[attr & 0xf];
 429 }
 430
 431 /*!
 432  * Convert cacheattr to PAGE_{READ,WRITE,EXEC} mask.
 433  * See ISA, A.2.14 The Cache Attribute Register
 434  */
 435 static unsigned cacheattr_attr_to_access(uint32_t attr)
 436 {
 437     static const unsigned access[16] = {
 438          [0] = PAGE_READ | PAGE_WRITE             | PAGE_CACHE_WT,
 439          [1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT,
 440          [2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS,
 441          [3] =                          PAGE_EXEC | PAGE_CACHE_WB,
 442          [4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
 443         [14] = PAGE_READ | PAGE_WRITE             | PAGE_CACHE_ISOLATE,
 444     };
 445
 446     return access[attr & 0xf];
 447 }
 448
 449 static bool is_access_granted(unsigned access, int is_write)
 450 {
 451     switch (is_write) {
 452     case 0:
 453         return access & PAGE_READ;
 454
 455     case 1:
 456         return access & PAGE_WRITE;
 457
 458     case 2:
 459         return access & PAGE_EXEC;
 460
 461     default:
 462         return 0;
 463     }
 464 }
 465
 466 static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte);
 467
 468 static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb,
 469         uint32_t vaddr, int is_write, int mmu_idx,
 470         uint32_t *paddr, uint32_t *page_size, unsigned *access,
 471         bool may_lookup_pt)
 472 {
 473     bool dtlb = is_write != 2;
 474     uint32_t wi;
 475     uint32_t ei;
 476     uint8_t ring;
 477     uint32_t vpn;
 478     uint32_t pte;
 479     const xtensa_tlb_entry *entry = NULL;
 480     xtensa_tlb_entry tmp_entry;
 481     int ret = xtensa_tlb_lookup(env, vaddr, dtlb, &wi, &ei, &ring);
 482
 483     if ((ret == INST_TLB_MISS_CAUSE || ret == LOAD_STORE_TLB_MISS_CAUSE) &&
 484             may_lookup_pt && get_pte(env, vaddr, &pte) == 0) {
 485         ring = (pte >> 4) & 0x3;
 486         wi = 0;
 487         split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, wi, &ei);
 488
 489         if (update_tlb) {
 490             wi = ++env->autorefill_idx & 0x3;
 491             xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, pte);
 492             env->sregs[EXCVADDR] = vaddr;
 493             qemu_log("%s: autorefill(%08x): %08x -> %08x\n",
 494                     __func__, vaddr, vpn, pte);
 495         } else {
 496             xtensa_tlb_set_entry_mmu(env, &tmp_entry, dtlb, wi, ei, vpn, pte);
 497             entry = &tmp_entry;
 498         }
 499         ret = 0;
 500     }
 501     if (ret != 0) {
 502         return ret;
 503     }
 504
 505     if (entry == NULL) {
 506         entry = xtensa_tlb_get_entry(env, dtlb, wi, ei);
 507     }
 508
 509     if (ring < mmu_idx) {
 510         return dtlb ?
 511             LOAD_STORE_PRIVILEGE_CAUSE :
 512             INST_FETCH_PRIVILEGE_CAUSE;
 513     }
 514
 515     *access = mmu_attr_to_access(entry->attr) &
 516         ~(dtlb ? PAGE_EXEC : PAGE_READ | PAGE_WRITE);
 517     if (!is_access_granted(*access, is_write)) {
 518         return dtlb ?
 519             (is_write ?
 520              STORE_PROHIBITED_CAUSE :
 521              LOAD_PROHIBITED_CAUSE) :
 522             INST_FETCH_PROHIBITED_CAUSE;
 523     }
 524
 525     *paddr = entry->paddr | (vaddr & ~xtensa_tlb_get_addr_mask(env, dtlb, wi));
 526     *page_size = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1;
 527
 528     return 0;
 529 }
 530
 531 static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte)
 532 {
 533     uint32_t paddr;
 534     uint32_t page_size;
 535     unsigned access;
 536     uint32_t pt_vaddr =
 537         (env->sregs[PTEVADDR] | (vaddr >> 10)) & 0xfffffffc;
 538     int ret = get_physical_addr_mmu(env, false, pt_vaddr, 0, 0,
 539             &paddr, &page_size, &access, false);
 540
 541     qemu_log("%s: trying autorefill(%08x) -> %08x\n", __func__,
 542             vaddr, ret ? ~0 : paddr);
 543
 544     if (ret == 0) {
 545         *pte = ldl_phys(paddr);
 546     }
 547     return ret;
 548 }
 549
 550 static int get_physical_addr_region(CPUXtensaState *env,
 551         uint32_t vaddr, int is_write, int mmu_idx,
 552         uint32_t *paddr, uint32_t *page_size, unsigned *access)
 553 {
 554     bool dtlb = is_write != 2;
 555     uint32_t wi = 0;
 556     uint32_t ei = (vaddr >> 29) & 0x7;
 557     const xtensa_tlb_entry *entry =
 558         xtensa_tlb_get_entry(env, dtlb, wi, ei);
 559
 560     *access = region_attr_to_access(entry->attr);
 561     if (!is_access_granted(*access, is_write)) {
 562         return dtlb ?
 563             (is_write ?
 564              STORE_PROHIBITED_CAUSE :
 565              LOAD_PROHIBITED_CAUSE) :
 566             INST_FETCH_PROHIBITED_CAUSE;
 567     }
 568
 569     *paddr = entry->paddr | (vaddr & ~REGION_PAGE_MASK);
 570     *page_size = ~REGION_PAGE_MASK + 1;
 571
 572     return 0;
 573 }
 574
 575 /*!
 576  * Convert virtual address to physical addr.
 577  * MMU may issue pagewalk and change xtensa autorefill TLB way entry.
 578  *
 579  * \return 0 if ok, exception cause code otherwise
 580  */
 581 int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
 582         uint32_t vaddr, int is_write, int mmu_idx,
 583         uint32_t *paddr, uint32_t *page_size, unsigned *access)
 584 {
 585     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 586         return get_physical_addr_mmu(env, update_tlb,
 587                 vaddr, is_write, mmu_idx, paddr, page_size, access, true);
 588     } else if (xtensa_option_bits_enabled(env->config,
 589                 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
 590                 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION))) {
 591         return get_physical_addr_region(env, vaddr, is_write, mmu_idx,
 592                 paddr, page_size, access);
 593     } else {
 594         *paddr = vaddr;
 595         *page_size = TARGET_PAGE_SIZE;
 596         *access = cacheattr_attr_to_access(
 597                 env->sregs[CACHEATTR] >> ((vaddr & 0xe0000000) >> 27));
 598         return 0;
 599     }
 600 }
 601
 602 static void dump_tlb(FILE *f, fprintf_function cpu_fprintf,
 603         CPUXtensaState *env, bool dtlb)
 604 {
 605     unsigned wi, ei;
 606     const xtensa_tlb *conf =
 607         dtlb ? &env->config->dtlb : &env->config->itlb;
 608     unsigned (*attr_to_access)(uint32_t) =
 609         xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) ?
 610         mmu_attr_to_access : region_attr_to_access;
 611
 612     for (wi = 0; wi < conf->nways; ++wi) {
 613         uint32_t sz = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1;
 614         const char *sz_text;
 615         bool print_header = true;
 616
 617         if (sz >= 0x100000) {
 618             sz >>= 20;
 619             sz_text = "MB";
 620         } else {
 621             sz >>= 10;
 622             sz_text = "KB";
 623         }
 624
 625         for (ei = 0; ei < conf->way_size[wi]; ++ei) {
 626             const xtensa_tlb_entry *entry =
 627                 xtensa_tlb_get_entry(env, dtlb, wi, ei);
 628
 629             if (entry->asid) {
 630                 static const char * const cache_text[8] = {
 631                     [PAGE_CACHE_BYPASS >> PAGE_CACHE_SHIFT] = "Bypass",
 632                     [PAGE_CACHE_WT >> PAGE_CACHE_SHIFT] = "WT",
 633                     [PAGE_CACHE_WB >> PAGE_CACHE_SHIFT] = "WB",
 634                     [PAGE_CACHE_ISOLATE >> PAGE_CACHE_SHIFT] = "Isolate",
 635                 };
 636                 unsigned access = attr_to_access(entry->attr);
 637                 unsigned cache_idx = (access & PAGE_CACHE_MASK) >>
 638                     PAGE_CACHE_SHIFT;
 639
 640                 if (print_header) {
 641                     print_header = false;
 642                     cpu_fprintf(f, "Way %u (%d %s)\n", wi, sz, sz_text);
 643                     cpu_fprintf(f,
 644                             "\tVaddr       Paddr       ASID  Attr RWX Cache\n"
 645                             "\t----------  ----------  ----  ---- --- -------\n");
 646                 }
 647                 cpu_fprintf(f,
 648                         "\t0x%08x  0x%08x  0x%02x  0x%02x %c%c%c %-7s\n",
 649                         entry->vaddr,
 650                         entry->paddr,
 651                         entry->asid,
 652                         entry->attr,
 653                         (access & PAGE_READ) ? 'R' : '-',
 654                         (access & PAGE_WRITE) ? 'W' : '-',
 655                         (access & PAGE_EXEC) ? 'X' : '-',
 656                         cache_text[cache_idx] ? cache_text[cache_idx] :
 657                             "Invalid");
 658             }
 659         }
 660     }
 661 }
 662
 663 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env)
 664 {
 665     if (xtensa_option_bits_enabled(env->config,
 666                 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
 667                 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION) |
 668                 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU))) {
 669
 670         cpu_fprintf(f, "ITLB:\n");
 671         dump_tlb(f, cpu_fprintf, env, false);
 672         cpu_fprintf(f, "\nDTLB:\n");
 673         dump_tlb(f, cpu_fprintf, env, true);
 674     } else {
 675         cpu_fprintf(f, "No TLB for this CPU core\n");
 676     }
 677 }