target-xtensa/helper.c

   1 /*
   2  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *     * Redistributions of source code must retain the above copyright
   8  *       notice, this list of conditions and the following disclaimer.
   9  *     * Redistributions in binary form must reproduce the above copyright
  10  *       notice, this list of conditions and the following disclaimer in the
  11  *       documentation and/or other materials provided with the distribution.
  12  *     * Neither the name of the Open Source and Linux Lab nor the
  13  *       names of its contributors may be used to endorse or promote products
  14  *       derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  25  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #include "cpu.h"
  29 #include "exec-all.h"
  30 #include "gdbstub.h"
  31 #include "host-utils.h"
  32 #if !defined(CONFIG_USER_ONLY)
  33 #include "hw/loader.h"
  34 #endif
  35
  36 void cpu_state_reset(CPUXtensaState *env)
  37 {
  38     cpu_reset(ENV_GET_CPU(env));
  39 }
  40
  41 static struct XtensaConfigList *xtensa_cores;
  42
  43 void xtensa_register_core(XtensaConfigList *node)
  44 {
  45     node->next = xtensa_cores;
  46     xtensa_cores = node;
  47 }
  48
  49 static uint32_t check_hw_breakpoints(CPUXtensaState *env)
  50 {
  51     unsigned i;
  52
  53     for (i = 0; i < env->config->ndbreak; ++i) {
  54         if (env->cpu_watchpoint[i] &&
  55                 env->cpu_watchpoint[i]->flags & BP_WATCHPOINT_HIT) {
  56             return DEBUGCAUSE_DB | (i << DEBUGCAUSE_DBNUM_SHIFT);
  57         }
  58     }
  59     return 0;
  60 }
  61
  62 static CPUDebugExcpHandler *prev_debug_excp_handler;
  63
  64 static void breakpoint_handler(CPUXtensaState *env)
  65 {
  66     if (env->watchpoint_hit) {
  67         if (env->watchpoint_hit->flags & BP_CPU) {
  68             uint32_t cause;
  69
  70             env->watchpoint_hit = NULL;
  71             cause = check_hw_breakpoints(env);
  72             if (cause) {
  73                 debug_exception_env(env, cause);
  74             }
  75             cpu_resume_from_signal(env, NULL);
  76         }
  77     }
  78     if (prev_debug_excp_handler) {
  79         prev_debug_excp_handler(env);
  80     }
  81 }
  82
  83 CPUXtensaState *cpu_xtensa_init(const char *cpu_model)
  84 {
  85     static int tcg_inited;
  86     static int debug_handler_inited;
  87     XtensaCPU *cpu;
  88     CPUXtensaState *env;
  89     const XtensaConfig *config = NULL;
  90     XtensaConfigList *core = xtensa_cores;
  91
  92     for (; core; core = core->next)
  93         if (strcmp(core->config->name, cpu_model) == 0) {
  94             config = core->config;
  95             break;
  96         }
  97
  98     if (config == NULL) {
  99         return NULL;
 100     }
 101
 102     cpu = XTENSA_CPU(object_new(TYPE_XTENSA_CPU));
 103     env = &cpu->env;
 104     env->config = config;
 105     cpu_exec_init(env);
 106
 107     if (!tcg_inited) {
 108         tcg_inited = 1;
 109         xtensa_translate_init();
 110     }
 111
 112     if (!debug_handler_inited && tcg_enabled()) {
 113         debug_handler_inited = 1;
 114         prev_debug_excp_handler =
 115             cpu_set_debug_excp_handler(breakpoint_handler);
 116     }
 117
 118     xtensa_irq_init(env);
 119     qemu_init_vcpu(env);
 120     return env;
 121 }
 122
 123
 124 void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf)
 125 {
 126     XtensaConfigList *core = xtensa_cores;
 127     cpu_fprintf(f, "Available CPUs:\n");
 128     for (; core; core = core->next) {
 129         cpu_fprintf(f, "  %s\n", core->config->name);
 130     }
 131 }
 132
 133 target_phys_addr_t cpu_get_phys_page_debug(CPUXtensaState *env, target_ulong addr)
 134 {
 135     uint32_t paddr;
 136     uint32_t page_size;
 137     unsigned access;
 138
 139     if (xtensa_get_physical_addr(env, addr, 0, 0,
 140                 &paddr, &page_size, &access) == 0) {
 141         return paddr;
 142     }
 143     if (xtensa_get_physical_addr(env, addr, 2, 0,
 144                 &paddr, &page_size, &access) == 0) {
 145         return paddr;
 146     }
 147     return ~0;
 148 }
 149
 150 static uint32_t relocated_vector(CPUXtensaState *env, uint32_t vector)
 151 {
 152     if (xtensa_option_enabled(env->config,
 153                 XTENSA_OPTION_RELOCATABLE_VECTOR)) {
 154         return vector - env->config->vecbase + env->sregs[VECBASE];
 155     } else {
 156         return vector;
 157     }
 158 }
 159
 160 /*!
 161  * Handle penging IRQ.
 162  * For the high priority interrupt jump to the corresponding interrupt vector.
 163  * For the level-1 interrupt convert it to either user, kernel or double
 164  * exception with the 'level-1 interrupt' exception cause.
 165  */
 166 static void handle_interrupt(CPUXtensaState *env)
 167 {
 168     int level = env->pending_irq_level;
 169
 170     if (level > xtensa_get_cintlevel(env) &&
 171             level <= env->config->nlevel &&
 172             (env->config->level_mask[level] &
 173              env->sregs[INTSET] &
 174              env->sregs[INTENABLE])) {
 175         if (level > 1) {
 176             env->sregs[EPC1 + level - 1] = env->pc;
 177             env->sregs[EPS2 + level - 2] = env->sregs[PS];
 178             env->sregs[PS] =
 179                 (env->sregs[PS] & ~PS_INTLEVEL) | level | PS_EXCM;
 180             env->pc = relocated_vector(env,
 181                     env->config->interrupt_vector[level]);
 182         } else {
 183             env->sregs[EXCCAUSE] = LEVEL1_INTERRUPT_CAUSE;
 184
 185             if (env->sregs[PS] & PS_EXCM) {
 186                 if (env->config->ndepc) {
 187                     env->sregs[DEPC] = env->pc;
 188                 } else {
 189                     env->sregs[EPC1] = env->pc;
 190                 }
 191                 env->exception_index = EXC_DOUBLE;
 192             } else {
 193                 env->sregs[EPC1] = env->pc;
 194                 env->exception_index =
 195                     (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL;
 196             }
 197             env->sregs[PS] |= PS_EXCM;
 198         }
 199         env->exception_taken = 1;
 200     }
 201 }
 202
 203 void do_interrupt(CPUXtensaState *env)
 204 {
 205     if (env->exception_index == EXC_IRQ) {
 206         qemu_log_mask(CPU_LOG_INT,
 207                 "%s(EXC_IRQ) level = %d, cintlevel = %d, "
 208                 "pc = %08x, a0 = %08x, ps = %08x, "
 209                 "intset = %08x, intenable = %08x, "
 210                 "ccount = %08x\n",
 211                 __func__, env->pending_irq_level, xtensa_get_cintlevel(env),
 212                 env->pc, env->regs[0], env->sregs[PS],
 213                 env->sregs[INTSET], env->sregs[INTENABLE],
 214                 env->sregs[CCOUNT]);
 215         handle_interrupt(env);
 216     }
 217
 218     switch (env->exception_index) {
 219     case EXC_WINDOW_OVERFLOW4:
 220     case EXC_WINDOW_UNDERFLOW4:
 221     case EXC_WINDOW_OVERFLOW8:
 222     case EXC_WINDOW_UNDERFLOW8:
 223     case EXC_WINDOW_OVERFLOW12:
 224     case EXC_WINDOW_UNDERFLOW12:
 225     case EXC_KERNEL:
 226     case EXC_USER:
 227     case EXC_DOUBLE:
 228     case EXC_DEBUG:
 229         qemu_log_mask(CPU_LOG_INT, "%s(%d) "
 230                 "pc = %08x, a0 = %08x, ps = %08x, ccount = %08x\n",
 231                 __func__, env->exception_index,
 232                 env->pc, env->regs[0], env->sregs[PS], env->sregs[CCOUNT]);
 233         if (env->config->exception_vector[env->exception_index]) {
 234             env->pc = relocated_vector(env,
 235                     env->config->exception_vector[env->exception_index]);
 236             env->exception_taken = 1;
 237         } else {
 238             qemu_log("%s(pc = %08x) bad exception_index: %d\n",
 239                     __func__, env->pc, env->exception_index);
 240         }
 241         break;
 242
 243     case EXC_IRQ:
 244         break;
 245
 246     default:
 247         qemu_log("%s(pc = %08x) unknown exception_index: %d\n",
 248                 __func__, env->pc, env->exception_index);
 249         break;
 250     }
 251     check_interrupts(env);
 252 }
 253
 254 static void reset_tlb_mmu_all_ways(CPUXtensaState *env,
 255         const xtensa_tlb *tlb, xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
 256 {
 257     unsigned wi, ei;
 258
 259     for (wi = 0; wi < tlb->nways; ++wi) {
 260         for (ei = 0; ei < tlb->way_size[wi]; ++ei) {
 261             entry[wi][ei].asid = 0;
 262             entry[wi][ei].variable = true;
 263         }
 264     }
 265 }
 266
 267 static void reset_tlb_mmu_ways56(CPUXtensaState *env,
 268         const xtensa_tlb *tlb, xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
 269 {
 270     if (!tlb->varway56) {
 271         static const xtensa_tlb_entry way5[] = {
 272             {
 273                 .vaddr = 0xd0000000,
 274                 .paddr = 0,
 275                 .asid = 1,
 276                 .attr = 7,
 277                 .variable = false,
 278             }, {
 279                 .vaddr = 0xd8000000,
 280                 .paddr = 0,
 281                 .asid = 1,
 282                 .attr = 3,
 283                 .variable = false,
 284             }
 285         };
 286         static const xtensa_tlb_entry way6[] = {
 287             {
 288                 .vaddr = 0xe0000000,
 289                 .paddr = 0xf0000000,
 290                 .asid = 1,
 291                 .attr = 7,
 292                 .variable = false,
 293             }, {
 294                 .vaddr = 0xf0000000,
 295                 .paddr = 0xf0000000,
 296                 .asid = 1,
 297                 .attr = 3,
 298                 .variable = false,
 299             }
 300         };
 301         memcpy(entry[5], way5, sizeof(way5));
 302         memcpy(entry[6], way6, sizeof(way6));
 303     } else {
 304         uint32_t ei;
 305         for (ei = 0; ei < 8; ++ei) {
 306             entry[6][ei].vaddr = ei << 29;
 307             entry[6][ei].paddr = ei << 29;
 308             entry[6][ei].asid = 1;
 309             entry[6][ei].attr = 3;
 310         }
 311     }
 312 }
 313
 314 static void reset_tlb_region_way0(CPUXtensaState *env,
 315         xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
 316 {
 317     unsigned ei;
 318
 319     for (ei = 0; ei < 8; ++ei) {
 320         entry[0][ei].vaddr = ei << 29;
 321         entry[0][ei].paddr = ei << 29;
 322         entry[0][ei].asid = 1;
 323         entry[0][ei].attr = 2;
 324         entry[0][ei].variable = true;
 325     }
 326 }
 327
 328 void reset_mmu(CPUXtensaState *env)
 329 {
 330     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 331         env->sregs[RASID] = 0x04030201;
 332         env->sregs[ITLBCFG] = 0;
 333         env->sregs[DTLBCFG] = 0;
 334         env->autorefill_idx = 0;
 335         reset_tlb_mmu_all_ways(env, &env->config->itlb, env->itlb);
 336         reset_tlb_mmu_all_ways(env, &env->config->dtlb, env->dtlb);
 337         reset_tlb_mmu_ways56(env, &env->config->itlb, env->itlb);
 338         reset_tlb_mmu_ways56(env, &env->config->dtlb, env->dtlb);
 339     } else {
 340         reset_tlb_region_way0(env, env->itlb);
 341         reset_tlb_region_way0(env, env->dtlb);
 342     }
 343 }
 344
 345 static unsigned get_ring(const CPUXtensaState *env, uint8_t asid)
 346 {
 347     unsigned i;
 348     for (i = 0; i < 4; ++i) {
 349         if (((env->sregs[RASID] >> i * 8) & 0xff) == asid) {
 350             return i;
 351         }
 352     }
 353     return 0xff;
 354 }
 355
 356 /*!
 357  * Lookup xtensa TLB for the given virtual address.
 358  * See ISA, 4.6.2.2
 359  *
 360  * \param pwi: [out] way index
 361  * \param pei: [out] entry index
 362  * \param pring: [out] access ring
 363  * \return 0 if ok, exception cause code otherwise
 364  */
 365 int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
 366         uint32_t *pwi, uint32_t *pei, uint8_t *pring)
 367 {
 368     const xtensa_tlb *tlb = dtlb ?
 369         &env->config->dtlb : &env->config->itlb;
 370     const xtensa_tlb_entry (*entry)[MAX_TLB_WAY_SIZE] = dtlb ?
 371         env->dtlb : env->itlb;
 372
 373     int nhits = 0;
 374     unsigned wi;
 375
 376     for (wi = 0; wi < tlb->nways; ++wi) {
 377         uint32_t vpn;
 378         uint32_t ei;
 379         split_tlb_entry_spec_way(env, addr, dtlb, &vpn, wi, &ei);
 380         if (entry[wi][ei].vaddr == vpn && entry[wi][ei].asid) {
 381             unsigned ring = get_ring(env, entry[wi][ei].asid);
 382             if (ring < 4) {
 383                 if (++nhits > 1) {
 384                     return dtlb ?
 385                         LOAD_STORE_TLB_MULTI_HIT_CAUSE :
 386                         INST_TLB_MULTI_HIT_CAUSE;
 387                 }
 388                 *pwi = wi;
 389                 *pei = ei;
 390                 *pring = ring;
 391             }
 392         }
 393     }
 394     return nhits ? 0 :
 395         (dtlb ? LOAD_STORE_TLB_MISS_CAUSE : INST_TLB_MISS_CAUSE);
 396 }
 397
 398 /*!
 399  * Convert MMU ATTR to PAGE_{READ,WRITE,EXEC} mask.
 400  * See ISA, 4.6.5.10
 401  */
 402 static unsigned mmu_attr_to_access(uint32_t attr)
 403 {
 404     unsigned access = 0;
 405     if (attr < 12) {
 406         access |= PAGE_READ;
 407         if (attr & 0x1) {
 408             access |= PAGE_EXEC;
 409         }
 410         if (attr & 0x2) {
 411             access |= PAGE_WRITE;
 412         }
 413     } else if (attr == 13) {
 414         access |= PAGE_READ | PAGE_WRITE;
 415     }
 416     return access;
 417 }
 418
 419 /*!
 420  * Convert region protection ATTR to PAGE_{READ,WRITE,EXEC} mask.
 421  * See ISA, 4.6.3.3
 422  */
 423 static unsigned region_attr_to_access(uint32_t attr)
 424 {
 425     unsigned access = 0;
 426     if ((attr < 6 && attr != 3) || attr == 14) {
 427         access |= PAGE_READ | PAGE_WRITE;
 428     }
 429     if (attr > 0 && attr < 6) {
 430         access |= PAGE_EXEC;
 431     }
 432     return access;
 433 }
 434
 435 static bool is_access_granted(unsigned access, int is_write)
 436 {
 437     switch (is_write) {
 438     case 0:
 439         return access & PAGE_READ;
 440
 441     case 1:
 442         return access & PAGE_WRITE;
 443
 444     case 2:
 445         return access & PAGE_EXEC;
 446
 447     default:
 448         return 0;
 449     }
 450 }
 451
 452 static int autorefill_mmu(CPUXtensaState *env, uint32_t vaddr, bool dtlb,
 453         uint32_t *wi, uint32_t *ei, uint8_t *ring);
 454
 455 static int get_physical_addr_mmu(CPUXtensaState *env,
 456         uint32_t vaddr, int is_write, int mmu_idx,
 457         uint32_t *paddr, uint32_t *page_size, unsigned *access)
 458 {
 459     bool dtlb = is_write != 2;
 460     uint32_t wi;
 461     uint32_t ei;
 462     uint8_t ring;
 463     int ret = xtensa_tlb_lookup(env, vaddr, dtlb, &wi, &ei, &ring);
 464
 465     if ((ret == INST_TLB_MISS_CAUSE || ret == LOAD_STORE_TLB_MISS_CAUSE) &&
 466             (mmu_idx != 0 || ((vaddr ^ env->sregs[PTEVADDR]) & 0xffc00000)) &&
 467             autorefill_mmu(env, vaddr, dtlb, &wi, &ei, &ring) == 0) {
 468         ret = 0;
 469     }
 470     if (ret != 0) {
 471         return ret;
 472     }
 473
 474     const xtensa_tlb_entry *entry =
 475         xtensa_tlb_get_entry(env, dtlb, wi, ei);
 476
 477     if (ring < mmu_idx) {
 478         return dtlb ?
 479             LOAD_STORE_PRIVILEGE_CAUSE :
 480             INST_FETCH_PRIVILEGE_CAUSE;
 481     }
 482
 483     *access = mmu_attr_to_access(entry->attr);
 484     if (!is_access_granted(*access, is_write)) {
 485         return dtlb ?
 486             (is_write ?
 487              STORE_PROHIBITED_CAUSE :
 488              LOAD_PROHIBITED_CAUSE) :
 489             INST_FETCH_PROHIBITED_CAUSE;
 490     }
 491
 492     *paddr = entry->paddr | (vaddr & ~xtensa_tlb_get_addr_mask(env, dtlb, wi));
 493     *page_size = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1;
 494
 495     return 0;
 496 }
 497
 498 static int autorefill_mmu(CPUXtensaState *env, uint32_t vaddr, bool dtlb,
 499         uint32_t *wi, uint32_t *ei, uint8_t *ring)
 500 {
 501     uint32_t paddr;
 502     uint32_t page_size;
 503     unsigned access;
 504     uint32_t pt_vaddr =
 505         (env->sregs[PTEVADDR] | (vaddr >> 10)) & 0xfffffffc;
 506     int ret = get_physical_addr_mmu(env, pt_vaddr, 0, 0,
 507             &paddr, &page_size, &access);
 508
 509     qemu_log("%s: trying autorefill(%08x) -> %08x\n", __func__,
 510             vaddr, ret ? ~0 : paddr);
 511
 512     if (ret == 0) {
 513         uint32_t vpn;
 514         uint32_t pte = ldl_phys(paddr);
 515
 516         *ring = (pte >> 4) & 0x3;
 517         *wi = (++env->autorefill_idx) & 0x3;
 518         split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, *wi, ei);
 519         xtensa_tlb_set_entry(env, dtlb, *wi, *ei, vpn, pte);
 520         qemu_log("%s: autorefill(%08x): %08x -> %08x\n",
 521                 __func__, vaddr, vpn, pte);
 522     }
 523     return ret;
 524 }
 525
 526 static int get_physical_addr_region(CPUXtensaState *env,
 527         uint32_t vaddr, int is_write, int mmu_idx,
 528         uint32_t *paddr, uint32_t *page_size, unsigned *access)
 529 {
 530     bool dtlb = is_write != 2;
 531     uint32_t wi = 0;
 532     uint32_t ei = (vaddr >> 29) & 0x7;
 533     const xtensa_tlb_entry *entry =
 534         xtensa_tlb_get_entry(env, dtlb, wi, ei);
 535
 536     *access = region_attr_to_access(entry->attr);
 537     if (!is_access_granted(*access, is_write)) {
 538         return dtlb ?
 539             (is_write ?
 540              STORE_PROHIBITED_CAUSE :
 541              LOAD_PROHIBITED_CAUSE) :
 542             INST_FETCH_PROHIBITED_CAUSE;
 543     }
 544
 545     *paddr = entry->paddr | (vaddr & ~REGION_PAGE_MASK);
 546     *page_size = ~REGION_PAGE_MASK + 1;
 547
 548     return 0;
 549 }
 550
 551 /*!
 552  * Convert virtual address to physical addr.
 553  * MMU may issue pagewalk and change xtensa autorefill TLB way entry.
 554  *
 555  * \return 0 if ok, exception cause code otherwise
 556  */
 557 int xtensa_get_physical_addr(CPUXtensaState *env,
 558         uint32_t vaddr, int is_write, int mmu_idx,
 559         uint32_t *paddr, uint32_t *page_size, unsigned *access)
 560 {
 561     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 562         return get_physical_addr_mmu(env, vaddr, is_write, mmu_idx,
 563                 paddr, page_size, access);
 564     } else if (xtensa_option_bits_enabled(env->config,
 565                 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
 566                 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION))) {
 567         return get_physical_addr_region(env, vaddr, is_write, mmu_idx,
 568                 paddr, page_size, access);
 569     } else {
 570         *paddr = vaddr;
 571         *page_size = TARGET_PAGE_SIZE;
 572         *access = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 573         return 0;
 574     }
 575 }
 576
 577 static void dump_tlb(FILE *f, fprintf_function cpu_fprintf,
 578         CPUXtensaState *env, bool dtlb)
 579 {
 580     unsigned wi, ei;
 581     const xtensa_tlb *conf =
 582         dtlb ? &env->config->dtlb : &env->config->itlb;
 583     unsigned (*attr_to_access)(uint32_t) =
 584         xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) ?
 585         mmu_attr_to_access : region_attr_to_access;
 586
 587     for (wi = 0; wi < conf->nways; ++wi) {
 588         uint32_t sz = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1;
 589         const char *sz_text;
 590         bool print_header = true;
 591
 592         if (sz >= 0x100000) {
 593             sz >>= 20;
 594             sz_text = "MB";
 595         } else {
 596             sz >>= 10;
 597             sz_text = "KB";
 598         }
 599
 600         for (ei = 0; ei < conf->way_size[wi]; ++ei) {
 601             const xtensa_tlb_entry *entry =
 602                 xtensa_tlb_get_entry(env, dtlb, wi, ei);
 603
 604             if (entry->asid) {
 605                 unsigned access = attr_to_access(entry->attr);
 606
 607                 if (print_header) {
 608                     print_header = false;
 609                     cpu_fprintf(f, "Way %u (%d %s)\n", wi, sz, sz_text);
 610                     cpu_fprintf(f,
 611                             "\tVaddr       Paddr       ASID  Attr RWX\n"
 612                             "\t----------  ----------  ----  ---- ---\n");
 613                 }
 614                 cpu_fprintf(f,
 615                         "\t0x%08x  0x%08x  0x%02x  0x%02x %c%c%c\n",
 616                         entry->vaddr,
 617                         entry->paddr,
 618                         entry->asid,
 619                         entry->attr,
 620                         (access & PAGE_READ) ? 'R' : '-',
 621                         (access & PAGE_WRITE) ? 'W' : '-',
 622                         (access & PAGE_EXEC) ? 'X' : '-');
 623             }
 624         }
 625     }
 626 }
 627
 628 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env)
 629 {
 630     if (xtensa_option_bits_enabled(env->config,
 631                 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
 632                 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION) |
 633                 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU))) {
 634
 635         cpu_fprintf(f, "ITLB:\n");
 636         dump_tlb(f, cpu_fprintf, env, false);
 637         cpu_fprintf(f, "\nDTLB:\n");
 638         dump_tlb(f, cpu_fprintf, env, true);
 639     } else {
 640         cpu_fprintf(f, "No TLB for this CPU core\n");
 641     }
 642 }