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target-xtensa: implement extended L32R
[qemu.git] / target-xtensa / translate.c
1 /*
2 * Xtensa ISA:
3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
4 *
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31 #include <stdio.h>
32
33 #include "cpu.h"
34 #include "exec-all.h"
35 #include "disas.h"
36 #include "tcg-op.h"
37 #include "qemu-log.h"
38
39 #include "helpers.h"
40 #define GEN_HELPER 1
41 #include "helpers.h"
42
43 typedef struct DisasContext {
44 const XtensaConfig *config;
45 TranslationBlock *tb;
46 uint32_t pc;
47 uint32_t next_pc;
48 int cring;
49 int ring;
50 uint32_t lbeg;
51 uint32_t lend;
52 TCGv_i32 litbase;
53 int is_jmp;
54 int singlestep_enabled;
55
56 bool sar_5bit;
57 bool sar_m32_5bit;
58 bool sar_m32_allocated;
59 TCGv_i32 sar_m32;
60 } DisasContext;
61
62 static TCGv_ptr cpu_env;
63 static TCGv_i32 cpu_pc;
64 static TCGv_i32 cpu_R[16];
65 static TCGv_i32 cpu_SR[256];
66 static TCGv_i32 cpu_UR[256];
67
68 #include "gen-icount.h"
69
70 static const char * const sregnames[256] = {
71 [LBEG] = "LBEG",
72 [LEND] = "LEND",
73 [LCOUNT] = "LCOUNT",
74 [SAR] = "SAR",
75 [LITBASE] = "LITBASE",
76 [SCOMPARE1] = "SCOMPARE1",
77 [WINDOW_BASE] = "WINDOW_BASE",
78 [WINDOW_START] = "WINDOW_START",
79 [EPC1] = "EPC1",
80 [DEPC] = "DEPC",
81 [EXCSAVE1] = "EXCSAVE1",
82 [PS] = "PS",
83 [EXCCAUSE] = "EXCCAUSE",
84 [EXCVADDR] = "EXCVADDR",
85 };
86
87 static const char * const uregnames[256] = {
88 [THREADPTR] = "THREADPTR",
89 [FCR] = "FCR",
90 [FSR] = "FSR",
91 };
92
93 void xtensa_translate_init(void)
94 {
95 static const char * const regnames[] = {
96 "ar0", "ar1", "ar2", "ar3",
97 "ar4", "ar5", "ar6", "ar7",
98 "ar8", "ar9", "ar10", "ar11",
99 "ar12", "ar13", "ar14", "ar15",
100 };
101 int i;
102
103 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
104 cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
105 offsetof(CPUState, pc), "pc");
106
107 for (i = 0; i < 16; i++) {
108 cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
109 offsetof(CPUState, regs[i]),
110 regnames[i]);
111 }
112
113 for (i = 0; i < 256; ++i) {
114 if (sregnames[i]) {
115 cpu_SR[i] = tcg_global_mem_new_i32(TCG_AREG0,
116 offsetof(CPUState, sregs[i]),
117 sregnames[i]);
118 }
119 }
120
121 for (i = 0; i < 256; ++i) {
122 if (uregnames[i]) {
123 cpu_UR[i] = tcg_global_mem_new_i32(TCG_AREG0,
124 offsetof(CPUState, uregs[i]),
125 uregnames[i]);
126 }
127 }
128 #define GEN_HELPER 2
129 #include "helpers.h"
130 }
131
132 static inline bool option_enabled(DisasContext *dc, int opt)
133 {
134 return xtensa_option_enabled(dc->config, opt);
135 }
136
137 static void init_litbase(DisasContext *dc)
138 {
139 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
140 dc->litbase = tcg_temp_local_new_i32();
141 tcg_gen_andi_i32(dc->litbase, cpu_SR[LITBASE], 0xfffff000);
142 }
143 }
144
145 static void reset_litbase(DisasContext *dc)
146 {
147 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
148 tcg_temp_free(dc->litbase);
149 }
150 }
151
152 static void init_sar_tracker(DisasContext *dc)
153 {
154 dc->sar_5bit = false;
155 dc->sar_m32_5bit = false;
156 dc->sar_m32_allocated = false;
157 }
158
159 static void reset_sar_tracker(DisasContext *dc)
160 {
161 if (dc->sar_m32_allocated) {
162 tcg_temp_free(dc->sar_m32);
163 }
164 }
165
166 static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa)
167 {
168 tcg_gen_andi_i32(cpu_SR[SAR], sa, 0x1f);
169 if (dc->sar_m32_5bit) {
170 tcg_gen_discard_i32(dc->sar_m32);
171 }
172 dc->sar_5bit = true;
173 dc->sar_m32_5bit = false;
174 }
175
176 static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa)
177 {
178 TCGv_i32 tmp = tcg_const_i32(32);
179 if (!dc->sar_m32_allocated) {
180 dc->sar_m32 = tcg_temp_local_new_i32();
181 dc->sar_m32_allocated = true;
182 }
183 tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f);
184 tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32);
185 dc->sar_5bit = false;
186 dc->sar_m32_5bit = true;
187 tcg_temp_free(tmp);
188 }
189
190 static void gen_exception(int excp)
191 {
192 TCGv_i32 tmp = tcg_const_i32(excp);
193 gen_helper_exception(tmp);
194 tcg_temp_free(tmp);
195 }
196
197 static void gen_exception_cause(DisasContext *dc, uint32_t cause)
198 {
199 TCGv_i32 tpc = tcg_const_i32(dc->pc);
200 TCGv_i32 tcause = tcg_const_i32(cause);
201 gen_helper_exception_cause(tpc, tcause);
202 tcg_temp_free(tpc);
203 tcg_temp_free(tcause);
204 }
205
206 static void gen_check_privilege(DisasContext *dc)
207 {
208 if (dc->cring) {
209 gen_exception_cause(dc, PRIVILEGED_CAUSE);
210 }
211 }
212
213 static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
214 {
215 tcg_gen_mov_i32(cpu_pc, dest);
216 if (dc->singlestep_enabled) {
217 gen_exception(EXCP_DEBUG);
218 } else {
219 if (slot >= 0) {
220 tcg_gen_goto_tb(slot);
221 tcg_gen_exit_tb((tcg_target_long)dc->tb + slot);
222 } else {
223 tcg_gen_exit_tb(0);
224 }
225 }
226 dc->is_jmp = DISAS_UPDATE;
227 }
228
229 static void gen_jump(DisasContext *dc, TCGv dest)
230 {
231 gen_jump_slot(dc, dest, -1);
232 }
233
234 static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
235 {
236 TCGv_i32 tmp = tcg_const_i32(dest);
237 if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
238 slot = -1;
239 }
240 gen_jump_slot(dc, tmp, slot);
241 tcg_temp_free(tmp);
242 }
243
244 static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest,
245 int slot)
246 {
247 TCGv_i32 tcallinc = tcg_const_i32(callinc);
248
249 tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS],
250 tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN);
251 tcg_temp_free(tcallinc);
252 tcg_gen_movi_i32(cpu_R[callinc << 2],
253 (callinc << 30) | (dc->next_pc & 0x3fffffff));
254 gen_jump_slot(dc, dest, slot);
255 }
256
257 static void gen_callw(DisasContext *dc, int callinc, TCGv_i32 dest)
258 {
259 gen_callw_slot(dc, callinc, dest, -1);
260 }
261
262 static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot)
263 {
264 TCGv_i32 tmp = tcg_const_i32(dest);
265 if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
266 slot = -1;
267 }
268 gen_callw_slot(dc, callinc, tmp, slot);
269 tcg_temp_free(tmp);
270 }
271
272 static bool gen_check_loop_end(DisasContext *dc, int slot)
273 {
274 if (option_enabled(dc, XTENSA_OPTION_LOOP) &&
275 !(dc->tb->flags & XTENSA_TBFLAG_EXCM) &&
276 dc->next_pc == dc->lend) {
277 int label = gen_new_label();
278
279 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label);
280 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1);
281 gen_jumpi(dc, dc->lbeg, slot);
282 gen_set_label(label);
283 gen_jumpi(dc, dc->next_pc, -1);
284 return true;
285 }
286 return false;
287 }
288
289 static void gen_jumpi_check_loop_end(DisasContext *dc, int slot)
290 {
291 if (!gen_check_loop_end(dc, slot)) {
292 gen_jumpi(dc, dc->next_pc, slot);
293 }
294 }
295
296 static void gen_brcond(DisasContext *dc, TCGCond cond,
297 TCGv_i32 t0, TCGv_i32 t1, uint32_t offset)
298 {
299 int label = gen_new_label();
300
301 tcg_gen_brcond_i32(cond, t0, t1, label);
302 gen_jumpi_check_loop_end(dc, 0);
303 gen_set_label(label);
304 gen_jumpi(dc, dc->pc + offset, 1);
305 }
306
307 static void gen_brcondi(DisasContext *dc, TCGCond cond,
308 TCGv_i32 t0, uint32_t t1, uint32_t offset)
309 {
310 TCGv_i32 tmp = tcg_const_i32(t1);
311 gen_brcond(dc, cond, t0, tmp, offset);
312 tcg_temp_free(tmp);
313 }
314
315 static void gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
316 {
317 static void (* const rsr_handler[256])(DisasContext *dc,
318 TCGv_i32 d, uint32_t sr) = {
319 };
320
321 if (sregnames[sr]) {
322 if (rsr_handler[sr]) {
323 rsr_handler[sr](dc, d, sr);
324 } else {
325 tcg_gen_mov_i32(d, cpu_SR[sr]);
326 }
327 } else {
328 qemu_log("RSR %d not implemented, ", sr);
329 }
330 }
331
332 static void gen_wsr_lbeg(DisasContext *dc, uint32_t sr, TCGv_i32 s)
333 {
334 gen_helper_wsr_lbeg(s);
335 }
336
337 static void gen_wsr_lend(DisasContext *dc, uint32_t sr, TCGv_i32 s)
338 {
339 gen_helper_wsr_lend(s);
340 }
341
342 static void gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s)
343 {
344 tcg_gen_andi_i32(cpu_SR[sr], s, 0x3f);
345 if (dc->sar_m32_5bit) {
346 tcg_gen_discard_i32(dc->sar_m32);
347 }
348 dc->sar_5bit = false;
349 dc->sar_m32_5bit = false;
350 }
351
352 static void gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s)
353 {
354 tcg_gen_andi_i32(cpu_SR[sr], s, 0xfffff001);
355 /* This can change tb->flags, so exit tb */
356 gen_jumpi_check_loop_end(dc, -1);
357 }
358
359 static void gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v)
360 {
361 gen_helper_wsr_windowbase(v);
362 }
363
364 static void gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v)
365 {
366 uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB |
367 PS_UM | PS_EXCM | PS_INTLEVEL;
368
369 if (option_enabled(dc, XTENSA_OPTION_MMU)) {
370 mask |= PS_RING;
371 }
372 tcg_gen_andi_i32(cpu_SR[sr], v, mask);
373 /* This can change mmu index, so exit tb */
374 gen_jumpi_check_loop_end(dc, -1);
375 }
376
377 static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s)
378 {
379 static void (* const wsr_handler[256])(DisasContext *dc,
380 uint32_t sr, TCGv_i32 v) = {
381 [LBEG] = gen_wsr_lbeg,
382 [LEND] = gen_wsr_lend,
383 [SAR] = gen_wsr_sar,
384 [LITBASE] = gen_wsr_litbase,
385 [WINDOW_BASE] = gen_wsr_windowbase,
386 [PS] = gen_wsr_ps,
387 };
388
389 if (sregnames[sr]) {
390 if (wsr_handler[sr]) {
391 wsr_handler[sr](dc, sr, s);
392 } else {
393 tcg_gen_mov_i32(cpu_SR[sr], s);
394 }
395 } else {
396 qemu_log("WSR %d not implemented, ", sr);
397 }
398 }
399
400 static void disas_xtensa_insn(DisasContext *dc)
401 {
402 #define HAS_OPTION(opt) do { \
403 if (!option_enabled(dc, opt)) { \
404 qemu_log("Option %d is not enabled %s:%d\n", \
405 (opt), __FILE__, __LINE__); \
406 goto invalid_opcode; \
407 } \
408 } while (0)
409
410 #define TBD() qemu_log("TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)
411 #define RESERVED() do { \
412 qemu_log("RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \
413 dc->pc, b0, b1, b2, __FILE__, __LINE__); \
414 goto invalid_opcode; \
415 } while (0)
416
417
418 #ifdef TARGET_WORDS_BIGENDIAN
419 #define OP0 (((b0) & 0xf0) >> 4)
420 #define OP1 (((b2) & 0xf0) >> 4)
421 #define OP2 ((b2) & 0xf)
422 #define RRR_R ((b1) & 0xf)
423 #define RRR_S (((b1) & 0xf0) >> 4)
424 #define RRR_T ((b0) & 0xf)
425 #else
426 #define OP0 (((b0) & 0xf))
427 #define OP1 (((b2) & 0xf))
428 #define OP2 (((b2) & 0xf0) >> 4)
429 #define RRR_R (((b1) & 0xf0) >> 4)
430 #define RRR_S (((b1) & 0xf))
431 #define RRR_T (((b0) & 0xf0) >> 4)
432 #endif
433
434 #define RRRN_R RRR_R
435 #define RRRN_S RRR_S
436 #define RRRN_T RRR_T
437
438 #define RRI8_R RRR_R
439 #define RRI8_S RRR_S
440 #define RRI8_T RRR_T
441 #define RRI8_IMM8 (b2)
442 #define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)
443
444 #ifdef TARGET_WORDS_BIGENDIAN
445 #define RI16_IMM16 (((b1) << 8) | (b2))
446 #else
447 #define RI16_IMM16 (((b2) << 8) | (b1))
448 #endif
449
450 #ifdef TARGET_WORDS_BIGENDIAN
451 #define CALL_N (((b0) & 0xc) >> 2)
452 #define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))
453 #else
454 #define CALL_N (((b0) & 0x30) >> 4)
455 #define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))
456 #endif
457 #define CALL_OFFSET_SE \
458 (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)
459
460 #define CALLX_N CALL_N
461 #ifdef TARGET_WORDS_BIGENDIAN
462 #define CALLX_M ((b0) & 0x3)
463 #else
464 #define CALLX_M (((b0) & 0xc0) >> 6)
465 #endif
466 #define CALLX_S RRR_S
467
468 #define BRI12_M CALLX_M
469 #define BRI12_S RRR_S
470 #ifdef TARGET_WORDS_BIGENDIAN
471 #define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))
472 #else
473 #define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))
474 #endif
475 #define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)
476
477 #define BRI8_M BRI12_M
478 #define BRI8_R RRI8_R
479 #define BRI8_S RRI8_S
480 #define BRI8_IMM8 RRI8_IMM8
481 #define BRI8_IMM8_SE RRI8_IMM8_SE
482
483 #define RSR_SR (b1)
484
485 uint8_t b0 = ldub_code(dc->pc);
486 uint8_t b1 = ldub_code(dc->pc + 1);
487 uint8_t b2 = ldub_code(dc->pc + 2);
488
489 static const uint32_t B4CONST[] = {
490 0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
491 };
492
493 static const uint32_t B4CONSTU[] = {
494 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
495 };
496
497 if (OP0 >= 8) {
498 dc->next_pc = dc->pc + 2;
499 HAS_OPTION(XTENSA_OPTION_CODE_DENSITY);
500 } else {
501 dc->next_pc = dc->pc + 3;
502 }
503
504 switch (OP0) {
505 case 0: /*QRST*/
506 switch (OP1) {
507 case 0: /*RST0*/
508 switch (OP2) {
509 case 0: /*ST0*/
510 if ((RRR_R & 0xc) == 0x8) {
511 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
512 }
513
514 switch (RRR_R) {
515 case 0: /*SNM0*/
516 switch (CALLX_M) {
517 case 0: /*ILL*/
518 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
519 break;
520
521 case 1: /*reserved*/
522 RESERVED();
523 break;
524
525 case 2: /*JR*/
526 switch (CALLX_N) {
527 case 0: /*RET*/
528 case 2: /*JX*/
529 gen_jump(dc, cpu_R[CALLX_S]);
530 break;
531
532 case 1: /*RETWw*/
533 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
534 {
535 TCGv_i32 tmp = tcg_const_i32(dc->pc);
536 gen_helper_retw(tmp, tmp);
537 gen_jump(dc, tmp);
538 tcg_temp_free(tmp);
539 }
540 break;
541
542 case 3: /*reserved*/
543 RESERVED();
544 break;
545 }
546 break;
547
548 case 3: /*CALLX*/
549 switch (CALLX_N) {
550 case 0: /*CALLX0*/
551 {
552 TCGv_i32 tmp = tcg_temp_new_i32();
553 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
554 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
555 gen_jump(dc, tmp);
556 tcg_temp_free(tmp);
557 }
558 break;
559
560 case 1: /*CALLX4w*/
561 case 2: /*CALLX8w*/
562 case 3: /*CALLX12w*/
563 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
564 {
565 TCGv_i32 tmp = tcg_temp_new_i32();
566
567 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
568 gen_callw(dc, CALLX_N, tmp);
569 tcg_temp_free(tmp);
570 }
571 break;
572 }
573 break;
574 }
575 break;
576
577 case 1: /*MOVSPw*/
578 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
579 {
580 TCGv_i32 pc = tcg_const_i32(dc->pc);
581 gen_helper_movsp(pc);
582 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_R[RRR_S]);
583 tcg_temp_free(pc);
584 }
585 break;
586
587 case 2: /*SYNC*/
588 switch (RRR_T) {
589 case 0: /*ISYNC*/
590 break;
591
592 case 1: /*RSYNC*/
593 break;
594
595 case 2: /*ESYNC*/
596 break;
597
598 case 3: /*DSYNC*/
599 break;
600
601 case 8: /*EXCW*/
602 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
603 break;
604
605 case 12: /*MEMW*/
606 break;
607
608 case 13: /*EXTW*/
609 break;
610
611 case 15: /*NOP*/
612 break;
613
614 default: /*reserved*/
615 RESERVED();
616 break;
617 }
618 break;
619
620 case 3: /*RFEIx*/
621 switch (RRR_T) {
622 case 0: /*RFETx*/
623 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
624 switch (RRR_S) {
625 case 0: /*RFEx*/
626 gen_check_privilege(dc);
627 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
628 gen_jump(dc, cpu_SR[EPC1]);
629 break;
630
631 case 1: /*RFUEx*/
632 RESERVED();
633 break;
634
635 case 2: /*RFDEx*/
636 gen_check_privilege(dc);
637 gen_jump(dc, cpu_SR[
638 dc->config->ndepc ? DEPC : EPC1]);
639 break;
640
641 case 4: /*RFWOw*/
642 case 5: /*RFWUw*/
643 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
644 gen_check_privilege(dc);
645 {
646 TCGv_i32 tmp = tcg_const_i32(1);
647
648 tcg_gen_andi_i32(
649 cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
650 tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]);
651
652 if (RRR_S == 4) {
653 tcg_gen_andc_i32(cpu_SR[WINDOW_START],
654 cpu_SR[WINDOW_START], tmp);
655 } else {
656 tcg_gen_or_i32(cpu_SR[WINDOW_START],
657 cpu_SR[WINDOW_START], tmp);
658 }
659
660 gen_helper_restore_owb();
661 gen_jump(dc, cpu_SR[EPC1]);
662
663 tcg_temp_free(tmp);
664 }
665 break;
666
667 default: /*reserved*/
668 RESERVED();
669 break;
670 }
671 break;
672
673 case 1: /*RFIx*/
674 HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT);
675 TBD();
676 break;
677
678 case 2: /*RFME*/
679 TBD();
680 break;
681
682 default: /*reserved*/
683 RESERVED();
684 break;
685
686 }
687 break;
688
689 case 4: /*BREAKx*/
690 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
691 TBD();
692 break;
693
694 case 5: /*SYSCALLx*/
695 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
696 switch (RRR_S) {
697 case 0: /*SYSCALLx*/
698 gen_exception_cause(dc, SYSCALL_CAUSE);
699 break;
700
701 case 1: /*SIMCALL*/
702 TBD();
703 break;
704
705 default:
706 RESERVED();
707 break;
708 }
709 break;
710
711 case 6: /*RSILx*/
712 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
713 gen_check_privilege(dc);
714 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_SR[PS]);
715 tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], RRR_S);
716 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS],
717 RRR_S | ~PS_INTLEVEL);
718 break;
719
720 case 7: /*WAITIx*/
721 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
722 TBD();
723 break;
724
725 case 8: /*ANY4p*/
726 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
727 TBD();
728 break;
729
730 case 9: /*ALL4p*/
731 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
732 TBD();
733 break;
734
735 case 10: /*ANY8p*/
736 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
737 TBD();
738 break;
739
740 case 11: /*ALL8p*/
741 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
742 TBD();
743 break;
744
745 default: /*reserved*/
746 RESERVED();
747 break;
748
749 }
750 break;
751
752 case 1: /*AND*/
753 tcg_gen_and_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
754 break;
755
756 case 2: /*OR*/
757 tcg_gen_or_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
758 break;
759
760 case 3: /*XOR*/
761 tcg_gen_xor_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
762 break;
763
764 case 4: /*ST1*/
765 switch (RRR_R) {
766 case 0: /*SSR*/
767 gen_right_shift_sar(dc, cpu_R[RRR_S]);
768 break;
769
770 case 1: /*SSL*/
771 gen_left_shift_sar(dc, cpu_R[RRR_S]);
772 break;
773
774 case 2: /*SSA8L*/
775 {
776 TCGv_i32 tmp = tcg_temp_new_i32();
777 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
778 gen_right_shift_sar(dc, tmp);
779 tcg_temp_free(tmp);
780 }
781 break;
782
783 case 3: /*SSA8B*/
784 {
785 TCGv_i32 tmp = tcg_temp_new_i32();
786 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
787 gen_left_shift_sar(dc, tmp);
788 tcg_temp_free(tmp);
789 }
790 break;
791
792 case 4: /*SSAI*/
793 {
794 TCGv_i32 tmp = tcg_const_i32(
795 RRR_S | ((RRR_T & 1) << 4));
796 gen_right_shift_sar(dc, tmp);
797 tcg_temp_free(tmp);
798 }
799 break;
800
801 case 6: /*RER*/
802 TBD();
803 break;
804
805 case 7: /*WER*/
806 TBD();
807 break;
808
809 case 8: /*ROTWw*/
810 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
811 gen_check_privilege(dc);
812 {
813 TCGv_i32 tmp = tcg_const_i32(
814 RRR_T | ((RRR_T & 8) ? 0xfffffff0 : 0));
815 gen_helper_rotw(tmp);
816 tcg_temp_free(tmp);
817 }
818 break;
819
820 case 14: /*NSAu*/
821 HAS_OPTION(XTENSA_OPTION_MISC_OP);
822 gen_helper_nsa(cpu_R[RRR_T], cpu_R[RRR_S]);
823 break;
824
825 case 15: /*NSAUu*/
826 HAS_OPTION(XTENSA_OPTION_MISC_OP);
827 gen_helper_nsau(cpu_R[RRR_T], cpu_R[RRR_S]);
828 break;
829
830 default: /*reserved*/
831 RESERVED();
832 break;
833 }
834 break;
835
836 case 5: /*TLB*/
837 TBD();
838 break;
839
840 case 6: /*RT0*/
841 switch (RRR_S) {
842 case 0: /*NEG*/
843 tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
844 break;
845
846 case 1: /*ABS*/
847 {
848 int label = gen_new_label();
849 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
850 tcg_gen_brcondi_i32(
851 TCG_COND_GE, cpu_R[RRR_R], 0, label);
852 tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
853 gen_set_label(label);
854 }
855 break;
856
857 default: /*reserved*/
858 RESERVED();
859 break;
860 }
861 break;
862
863 case 7: /*reserved*/
864 RESERVED();
865 break;
866
867 case 8: /*ADD*/
868 tcg_gen_add_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
869 break;
870
871 case 9: /*ADD**/
872 case 10:
873 case 11:
874 {
875 TCGv_i32 tmp = tcg_temp_new_i32();
876 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 8);
877 tcg_gen_add_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
878 tcg_temp_free(tmp);
879 }
880 break;
881
882 case 12: /*SUB*/
883 tcg_gen_sub_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
884 break;
885
886 case 13: /*SUB**/
887 case 14:
888 case 15:
889 {
890 TCGv_i32 tmp = tcg_temp_new_i32();
891 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 12);
892 tcg_gen_sub_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
893 tcg_temp_free(tmp);
894 }
895 break;
896 }
897 break;
898
899 case 1: /*RST1*/
900 switch (OP2) {
901 case 0: /*SLLI*/
902 case 1:
903 tcg_gen_shli_i32(cpu_R[RRR_R], cpu_R[RRR_S],
904 32 - (RRR_T | ((OP2 & 1) << 4)));
905 break;
906
907 case 2: /*SRAI*/
908 case 3:
909 tcg_gen_sari_i32(cpu_R[RRR_R], cpu_R[RRR_T],
910 RRR_S | ((OP2 & 1) << 4));
911 break;
912
913 case 4: /*SRLI*/
914 tcg_gen_shri_i32(cpu_R[RRR_R], cpu_R[RRR_T], RRR_S);
915 break;
916
917 case 6: /*XSR*/
918 {
919 TCGv_i32 tmp = tcg_temp_new_i32();
920 if (RSR_SR >= 64) {
921 gen_check_privilege(dc);
922 }
923 tcg_gen_mov_i32(tmp, cpu_R[RRR_T]);
924 gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
925 gen_wsr(dc, RSR_SR, tmp);
926 tcg_temp_free(tmp);
927 if (!sregnames[RSR_SR]) {
928 TBD();
929 }
930 }
931 break;
932
933 /*
934 * Note: 64 bit ops are used here solely because SAR values
935 * have range 0..63
936 */
937 #define gen_shift_reg(cmd, reg) do { \
938 TCGv_i64 tmp = tcg_temp_new_i64(); \
939 tcg_gen_extu_i32_i64(tmp, reg); \
940 tcg_gen_##cmd##_i64(v, v, tmp); \
941 tcg_gen_trunc_i64_i32(cpu_R[RRR_R], v); \
942 tcg_temp_free_i64(v); \
943 tcg_temp_free_i64(tmp); \
944 } while (0)
945
946 #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
947
948 case 8: /*SRC*/
949 {
950 TCGv_i64 v = tcg_temp_new_i64();
951 tcg_gen_concat_i32_i64(v, cpu_R[RRR_T], cpu_R[RRR_S]);
952 gen_shift(shr);
953 }
954 break;
955
956 case 9: /*SRL*/
957 if (dc->sar_5bit) {
958 tcg_gen_shr_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
959 } else {
960 TCGv_i64 v = tcg_temp_new_i64();
961 tcg_gen_extu_i32_i64(v, cpu_R[RRR_T]);
962 gen_shift(shr);
963 }
964 break;
965
966 case 10: /*SLL*/
967 if (dc->sar_m32_5bit) {
968 tcg_gen_shl_i32(cpu_R[RRR_R], cpu_R[RRR_S], dc->sar_m32);
969 } else {
970 TCGv_i64 v = tcg_temp_new_i64();
971 TCGv_i32 s = tcg_const_i32(32);
972 tcg_gen_sub_i32(s, s, cpu_SR[SAR]);
973 tcg_gen_andi_i32(s, s, 0x3f);
974 tcg_gen_extu_i32_i64(v, cpu_R[RRR_S]);
975 gen_shift_reg(shl, s);
976 tcg_temp_free(s);
977 }
978 break;
979
980 case 11: /*SRA*/
981 if (dc->sar_5bit) {
982 tcg_gen_sar_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
983 } else {
984 TCGv_i64 v = tcg_temp_new_i64();
985 tcg_gen_ext_i32_i64(v, cpu_R[RRR_T]);
986 gen_shift(sar);
987 }
988 break;
989 #undef gen_shift
990 #undef gen_shift_reg
991
992 case 12: /*MUL16U*/
993 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
994 {
995 TCGv_i32 v1 = tcg_temp_new_i32();
996 TCGv_i32 v2 = tcg_temp_new_i32();
997 tcg_gen_ext16u_i32(v1, cpu_R[RRR_S]);
998 tcg_gen_ext16u_i32(v2, cpu_R[RRR_T]);
999 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1000 tcg_temp_free(v2);
1001 tcg_temp_free(v1);
1002 }
1003 break;
1004
1005 case 13: /*MUL16S*/
1006 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
1007 {
1008 TCGv_i32 v1 = tcg_temp_new_i32();
1009 TCGv_i32 v2 = tcg_temp_new_i32();
1010 tcg_gen_ext16s_i32(v1, cpu_R[RRR_S]);
1011 tcg_gen_ext16s_i32(v2, cpu_R[RRR_T]);
1012 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1013 tcg_temp_free(v2);
1014 tcg_temp_free(v1);
1015 }
1016 break;
1017
1018 default: /*reserved*/
1019 RESERVED();
1020 break;
1021 }
1022 break;
1023
1024 case 2: /*RST2*/
1025 if (OP2 >= 12) {
1026 HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV);
1027 int label = gen_new_label();
1028 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0, label);
1029 gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE);
1030 gen_set_label(label);
1031 }
1032
1033 switch (OP2) {
1034 case 8: /*MULLi*/
1035 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL);
1036 tcg_gen_mul_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1037 break;
1038
1039 case 10: /*MULUHi*/
1040 case 11: /*MULSHi*/
1041 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL);
1042 {
1043 TCGv_i64 r = tcg_temp_new_i64();
1044 TCGv_i64 s = tcg_temp_new_i64();
1045 TCGv_i64 t = tcg_temp_new_i64();
1046
1047 if (OP2 == 10) {
1048 tcg_gen_extu_i32_i64(s, cpu_R[RRR_S]);
1049 tcg_gen_extu_i32_i64(t, cpu_R[RRR_T]);
1050 } else {
1051 tcg_gen_ext_i32_i64(s, cpu_R[RRR_S]);
1052 tcg_gen_ext_i32_i64(t, cpu_R[RRR_T]);
1053 }
1054 tcg_gen_mul_i64(r, s, t);
1055 tcg_gen_shri_i64(r, r, 32);
1056 tcg_gen_trunc_i64_i32(cpu_R[RRR_R], r);
1057
1058 tcg_temp_free_i64(r);
1059 tcg_temp_free_i64(s);
1060 tcg_temp_free_i64(t);
1061 }
1062 break;
1063
1064 case 12: /*QUOUi*/
1065 tcg_gen_divu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1066 break;
1067
1068 case 13: /*QUOSi*/
1069 case 15: /*REMSi*/
1070 {
1071 int label1 = gen_new_label();
1072 int label2 = gen_new_label();
1073
1074 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_S], 0x80000000,
1075 label1);
1076 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0xffffffff,
1077 label1);
1078 tcg_gen_movi_i32(cpu_R[RRR_R],
1079 OP2 == 13 ? 0x80000000 : 0);
1080 tcg_gen_br(label2);
1081 gen_set_label(label1);
1082 if (OP2 == 13) {
1083 tcg_gen_div_i32(cpu_R[RRR_R],
1084 cpu_R[RRR_S], cpu_R[RRR_T]);
1085 } else {
1086 tcg_gen_rem_i32(cpu_R[RRR_R],
1087 cpu_R[RRR_S], cpu_R[RRR_T]);
1088 }
1089 gen_set_label(label2);
1090 }
1091 break;
1092
1093 case 14: /*REMUi*/
1094 tcg_gen_remu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1095 break;
1096
1097 default: /*reserved*/
1098 RESERVED();
1099 break;
1100 }
1101 break;
1102
1103 case 3: /*RST3*/
1104 switch (OP2) {
1105 case 0: /*RSR*/
1106 if (RSR_SR >= 64) {
1107 gen_check_privilege(dc);
1108 }
1109 gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
1110 if (!sregnames[RSR_SR]) {
1111 TBD();
1112 }
1113 break;
1114
1115 case 1: /*WSR*/
1116 if (RSR_SR >= 64) {
1117 gen_check_privilege(dc);
1118 }
1119 gen_wsr(dc, RSR_SR, cpu_R[RRR_T]);
1120 if (!sregnames[RSR_SR]) {
1121 TBD();
1122 }
1123 break;
1124
1125 case 2: /*SEXTu*/
1126 HAS_OPTION(XTENSA_OPTION_MISC_OP);
1127 {
1128 int shift = 24 - RRR_T;
1129
1130 if (shift == 24) {
1131 tcg_gen_ext8s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1132 } else if (shift == 16) {
1133 tcg_gen_ext16s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1134 } else {
1135 TCGv_i32 tmp = tcg_temp_new_i32();
1136 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], shift);
1137 tcg_gen_sari_i32(cpu_R[RRR_R], tmp, shift);
1138 tcg_temp_free(tmp);
1139 }
1140 }
1141 break;
1142
1143 case 3: /*CLAMPSu*/
1144 HAS_OPTION(XTENSA_OPTION_MISC_OP);
1145 {
1146 TCGv_i32 tmp1 = tcg_temp_new_i32();
1147 TCGv_i32 tmp2 = tcg_temp_new_i32();
1148 int label = gen_new_label();
1149
1150 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 24 - RRR_T);
1151 tcg_gen_xor_i32(tmp2, tmp1, cpu_R[RRR_S]);
1152 tcg_gen_andi_i32(tmp2, tmp2, 0xffffffff << (RRR_T + 7));
1153 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1154 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp2, 0, label);
1155
1156 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 31);
1157 tcg_gen_xori_i32(cpu_R[RRR_R], tmp1,
1158 0xffffffff >> (25 - RRR_T));
1159
1160 gen_set_label(label);
1161
1162 tcg_temp_free(tmp1);
1163 tcg_temp_free(tmp2);
1164 }
1165 break;
1166
1167 case 4: /*MINu*/
1168 case 5: /*MAXu*/
1169 case 6: /*MINUu*/
1170 case 7: /*MAXUu*/
1171 HAS_OPTION(XTENSA_OPTION_MISC_OP);
1172 {
1173 static const TCGCond cond[] = {
1174 TCG_COND_LE,
1175 TCG_COND_GE,
1176 TCG_COND_LEU,
1177 TCG_COND_GEU
1178 };
1179 int label = gen_new_label();
1180
1181 if (RRR_R != RRR_T) {
1182 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1183 tcg_gen_brcond_i32(cond[OP2 - 4],
1184 cpu_R[RRR_S], cpu_R[RRR_T], label);
1185 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1186 } else {
1187 tcg_gen_brcond_i32(cond[OP2 - 4],
1188 cpu_R[RRR_T], cpu_R[RRR_S], label);
1189 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1190 }
1191 gen_set_label(label);
1192 }
1193 break;
1194
1195 case 8: /*MOVEQZ*/
1196 case 9: /*MOVNEZ*/
1197 case 10: /*MOVLTZ*/
1198 case 11: /*MOVGEZ*/
1199 {
1200 static const TCGCond cond[] = {
1201 TCG_COND_NE,
1202 TCG_COND_EQ,
1203 TCG_COND_GE,
1204 TCG_COND_LT
1205 };
1206 int label = gen_new_label();
1207 tcg_gen_brcondi_i32(cond[OP2 - 8], cpu_R[RRR_T], 0, label);
1208 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1209 gen_set_label(label);
1210 }
1211 break;
1212
1213 case 12: /*MOVFp*/
1214 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
1215 TBD();
1216 break;
1217
1218 case 13: /*MOVTp*/
1219 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
1220 TBD();
1221 break;
1222
1223 case 14: /*RUR*/
1224 {
1225 int st = (RRR_S << 4) + RRR_T;
1226 if (uregnames[st]) {
1227 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_UR[st]);
1228 } else {
1229 qemu_log("RUR %d not implemented, ", st);
1230 TBD();
1231 }
1232 }
1233 break;
1234
1235 case 15: /*WUR*/
1236 {
1237 if (uregnames[RSR_SR]) {
1238 tcg_gen_mov_i32(cpu_UR[RSR_SR], cpu_R[RRR_T]);
1239 } else {
1240 qemu_log("WUR %d not implemented, ", RSR_SR);
1241 TBD();
1242 }
1243 }
1244 break;
1245
1246 }
1247 break;
1248
1249 case 4: /*EXTUI*/
1250 case 5:
1251 {
1252 int shiftimm = RRR_S | (OP1 << 4);
1253 int maskimm = (1 << (OP2 + 1)) - 1;
1254
1255 TCGv_i32 tmp = tcg_temp_new_i32();
1256 tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm);
1257 tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm);
1258 tcg_temp_free(tmp);
1259 }
1260 break;
1261
1262 case 6: /*CUST0*/
1263 RESERVED();
1264 break;
1265
1266 case 7: /*CUST1*/
1267 RESERVED();
1268 break;
1269
1270 case 8: /*LSCXp*/
1271 HAS_OPTION(XTENSA_OPTION_COPROCESSOR);
1272 TBD();
1273 break;
1274
1275 case 9: /*LSC4*/
1276 switch (OP2) {
1277 case 0: /*L32E*/
1278 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1279 gen_check_privilege(dc);
1280 {
1281 TCGv_i32 addr = tcg_temp_new_i32();
1282 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1283 (0xffffffc0 | (RRR_R << 2)));
1284 tcg_gen_qemu_ld32u(cpu_R[RRR_T], addr, dc->ring);
1285 tcg_temp_free(addr);
1286 }
1287 break;
1288
1289 case 4: /*S32E*/
1290 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1291 gen_check_privilege(dc);
1292 {
1293 TCGv_i32 addr = tcg_temp_new_i32();
1294 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1295 (0xffffffc0 | (RRR_R << 2)));
1296 tcg_gen_qemu_st32(cpu_R[RRR_T], addr, dc->ring);
1297 tcg_temp_free(addr);
1298 }
1299 break;
1300
1301 default:
1302 RESERVED();
1303 break;
1304 }
1305 break;
1306
1307 case 10: /*FP0*/
1308 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
1309 TBD();
1310 break;
1311
1312 case 11: /*FP1*/
1313 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
1314 TBD();
1315 break;
1316
1317 default: /*reserved*/
1318 RESERVED();
1319 break;
1320 }
1321 break;
1322
1323 case 1: /*L32R*/
1324 {
1325 TCGv_i32 tmp = tcg_const_i32(
1326 ((dc->tb->flags & XTENSA_TBFLAG_LITBASE) ?
1327 0 : ((dc->pc + 3) & ~3)) +
1328 (0xfffc0000 | (RI16_IMM16 << 2)));
1329
1330 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
1331 tcg_gen_add_i32(tmp, tmp, dc->litbase);
1332 }
1333 tcg_gen_qemu_ld32u(cpu_R[RRR_T], tmp, dc->cring);
1334 tcg_temp_free(tmp);
1335 }
1336 break;
1337
1338 case 2: /*LSAI*/
1339 #define gen_load_store(type, shift) do { \
1340 TCGv_i32 addr = tcg_temp_new_i32(); \
1341 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \
1342 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
1343 tcg_temp_free(addr); \
1344 } while (0)
1345
1346 switch (RRI8_R) {
1347 case 0: /*L8UI*/
1348 gen_load_store(ld8u, 0);
1349 break;
1350
1351 case 1: /*L16UI*/
1352 gen_load_store(ld16u, 1);
1353 break;
1354
1355 case 2: /*L32I*/
1356 gen_load_store(ld32u, 2);
1357 break;
1358
1359 case 4: /*S8I*/
1360 gen_load_store(st8, 0);
1361 break;
1362
1363 case 5: /*S16I*/
1364 gen_load_store(st16, 1);
1365 break;
1366
1367 case 6: /*S32I*/
1368 gen_load_store(st32, 2);
1369 break;
1370
1371 case 7: /*CACHEc*/
1372 if (RRI8_T < 8) {
1373 HAS_OPTION(XTENSA_OPTION_DCACHE);
1374 }
1375
1376 switch (RRI8_T) {
1377 case 0: /*DPFRc*/
1378 break;
1379
1380 case 1: /*DPFWc*/
1381 break;
1382
1383 case 2: /*DPFROc*/
1384 break;
1385
1386 case 3: /*DPFWOc*/
1387 break;
1388
1389 case 4: /*DHWBc*/
1390 break;
1391
1392 case 5: /*DHWBIc*/
1393 break;
1394
1395 case 6: /*DHIc*/
1396 break;
1397
1398 case 7: /*DIIc*/
1399 break;
1400
1401 case 8: /*DCEc*/
1402 switch (OP1) {
1403 case 0: /*DPFLl*/
1404 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
1405 break;
1406
1407 case 2: /*DHUl*/
1408 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
1409 break;
1410
1411 case 3: /*DIUl*/
1412 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
1413 break;
1414
1415 case 4: /*DIWBc*/
1416 HAS_OPTION(XTENSA_OPTION_DCACHE);
1417 break;
1418
1419 case 5: /*DIWBIc*/
1420 HAS_OPTION(XTENSA_OPTION_DCACHE);
1421 break;
1422
1423 default: /*reserved*/
1424 RESERVED();
1425 break;
1426
1427 }
1428 break;
1429
1430 case 12: /*IPFc*/
1431 HAS_OPTION(XTENSA_OPTION_ICACHE);
1432 break;
1433
1434 case 13: /*ICEc*/
1435 switch (OP1) {
1436 case 0: /*IPFLl*/
1437 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
1438 break;
1439
1440 case 2: /*IHUl*/
1441 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
1442 break;
1443
1444 case 3: /*IIUl*/
1445 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
1446 break;
1447
1448 default: /*reserved*/
1449 RESERVED();
1450 break;
1451 }
1452 break;
1453
1454 case 14: /*IHIc*/
1455 HAS_OPTION(XTENSA_OPTION_ICACHE);
1456 break;
1457
1458 case 15: /*IIIc*/
1459 HAS_OPTION(XTENSA_OPTION_ICACHE);
1460 break;
1461
1462 default: /*reserved*/
1463 RESERVED();
1464 break;
1465 }
1466 break;
1467
1468 case 9: /*L16SI*/
1469 gen_load_store(ld16s, 1);
1470 break;
1471
1472 case 10: /*MOVI*/
1473 tcg_gen_movi_i32(cpu_R[RRI8_T],
1474 RRI8_IMM8 | (RRI8_S << 8) |
1475 ((RRI8_S & 0x8) ? 0xfffff000 : 0));
1476 break;
1477
1478 case 11: /*L32AIy*/
1479 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
1480 gen_load_store(ld32u, 2); /*TODO acquire?*/
1481 break;
1482
1483 case 12: /*ADDI*/
1484 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE);
1485 break;
1486
1487 case 13: /*ADDMI*/
1488 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE << 8);
1489 break;
1490
1491 case 14: /*S32C1Iy*/
1492 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
1493 {
1494 int label = gen_new_label();
1495 TCGv_i32 tmp = tcg_temp_local_new_i32();
1496 TCGv_i32 addr = tcg_temp_local_new_i32();
1497
1498 tcg_gen_mov_i32(tmp, cpu_R[RRI8_T]);
1499 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
1500 tcg_gen_qemu_ld32u(cpu_R[RRI8_T], addr, dc->cring);
1501 tcg_gen_brcond_i32(TCG_COND_NE, cpu_R[RRI8_T],
1502 cpu_SR[SCOMPARE1], label);
1503
1504 tcg_gen_qemu_st32(tmp, addr, dc->cring);
1505
1506 gen_set_label(label);
1507 tcg_temp_free(addr);
1508 tcg_temp_free(tmp);
1509 }
1510 break;
1511
1512 case 15: /*S32RIy*/
1513 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
1514 gen_load_store(st32, 2); /*TODO release?*/
1515 break;
1516
1517 default: /*reserved*/
1518 RESERVED();
1519 break;
1520 }
1521 break;
1522 #undef gen_load_store
1523
1524 case 3: /*LSCIp*/
1525 HAS_OPTION(XTENSA_OPTION_COPROCESSOR);
1526 TBD();
1527 break;
1528
1529 case 4: /*MAC16d*/
1530 HAS_OPTION(XTENSA_OPTION_MAC16);
1531 TBD();
1532 break;
1533
1534 case 5: /*CALLN*/
1535 switch (CALL_N) {
1536 case 0: /*CALL0*/
1537 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
1538 gen_jumpi(dc, (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
1539 break;
1540
1541 case 1: /*CALL4w*/
1542 case 2: /*CALL8w*/
1543 case 3: /*CALL12w*/
1544 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1545 gen_callwi(dc, CALL_N,
1546 (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
1547 break;
1548 }
1549 break;
1550
1551 case 6: /*SI*/
1552 switch (CALL_N) {
1553 case 0: /*J*/
1554 gen_jumpi(dc, dc->pc + 4 + CALL_OFFSET_SE, 0);
1555 break;
1556
1557 case 1: /*BZ*/
1558 {
1559 static const TCGCond cond[] = {
1560 TCG_COND_EQ, /*BEQZ*/
1561 TCG_COND_NE, /*BNEZ*/
1562 TCG_COND_LT, /*BLTZ*/
1563 TCG_COND_GE, /*BGEZ*/
1564 };
1565
1566 gen_brcondi(dc, cond[BRI12_M & 3], cpu_R[BRI12_S], 0,
1567 4 + BRI12_IMM12_SE);
1568 }
1569 break;
1570
1571 case 2: /*BI0*/
1572 {
1573 static const TCGCond cond[] = {
1574 TCG_COND_EQ, /*BEQI*/
1575 TCG_COND_NE, /*BNEI*/
1576 TCG_COND_LT, /*BLTI*/
1577 TCG_COND_GE, /*BGEI*/
1578 };
1579
1580 gen_brcondi(dc, cond[BRI8_M & 3],
1581 cpu_R[BRI8_S], B4CONST[BRI8_R], 4 + BRI8_IMM8_SE);
1582 }
1583 break;
1584
1585 case 3: /*BI1*/
1586 switch (BRI8_M) {
1587 case 0: /*ENTRYw*/
1588 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1589 {
1590 TCGv_i32 pc = tcg_const_i32(dc->pc);
1591 TCGv_i32 s = tcg_const_i32(BRI12_S);
1592 TCGv_i32 imm = tcg_const_i32(BRI12_IMM12);
1593 gen_helper_entry(pc, s, imm);
1594 tcg_temp_free(imm);
1595 tcg_temp_free(s);
1596 tcg_temp_free(pc);
1597 }
1598 break;
1599
1600 case 1: /*B1*/
1601 switch (BRI8_R) {
1602 case 0: /*BFp*/
1603 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
1604 TBD();
1605 break;
1606
1607 case 1: /*BTp*/
1608 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
1609 TBD();
1610 break;
1611
1612 case 8: /*LOOP*/
1613 case 9: /*LOOPNEZ*/
1614 case 10: /*LOOPGTZ*/
1615 HAS_OPTION(XTENSA_OPTION_LOOP);
1616 {
1617 uint32_t lend = dc->pc + RRI8_IMM8 + 4;
1618 TCGv_i32 tmp = tcg_const_i32(lend);
1619
1620 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[RRI8_S], 1);
1621 tcg_gen_movi_i32(cpu_SR[LBEG], dc->next_pc);
1622 gen_wsr_lend(dc, LEND, tmp);
1623 tcg_temp_free(tmp);
1624
1625 if (BRI8_R > 8) {
1626 int label = gen_new_label();
1627 tcg_gen_brcondi_i32(
1628 BRI8_R == 9 ? TCG_COND_NE : TCG_COND_GT,
1629 cpu_R[RRI8_S], 0, label);
1630 gen_jumpi(dc, lend, 1);
1631 gen_set_label(label);
1632 }
1633
1634 gen_jumpi(dc, dc->next_pc, 0);
1635 }
1636 break;
1637
1638 default: /*reserved*/
1639 RESERVED();
1640 break;
1641
1642 }
1643 break;
1644
1645 case 2: /*BLTUI*/
1646 case 3: /*BGEUI*/
1647 gen_brcondi(dc, BRI8_M == 2 ? TCG_COND_LTU : TCG_COND_GEU,
1648 cpu_R[BRI8_S], B4CONSTU[BRI8_R], 4 + BRI8_IMM8_SE);
1649 break;
1650 }
1651 break;
1652
1653 }
1654 break;
1655
1656 case 7: /*B*/
1657 {
1658 TCGCond eq_ne = (RRI8_R & 8) ? TCG_COND_NE : TCG_COND_EQ;
1659
1660 switch (RRI8_R & 7) {
1661 case 0: /*BNONE*/ /*BANY*/
1662 {
1663 TCGv_i32 tmp = tcg_temp_new_i32();
1664 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
1665 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
1666 tcg_temp_free(tmp);
1667 }
1668 break;
1669
1670 case 1: /*BEQ*/ /*BNE*/
1671 case 2: /*BLT*/ /*BGE*/
1672 case 3: /*BLTU*/ /*BGEU*/
1673 {
1674 static const TCGCond cond[] = {
1675 [1] = TCG_COND_EQ,
1676 [2] = TCG_COND_LT,
1677 [3] = TCG_COND_LTU,
1678 [9] = TCG_COND_NE,
1679 [10] = TCG_COND_GE,
1680 [11] = TCG_COND_GEU,
1681 };
1682 gen_brcond(dc, cond[RRI8_R], cpu_R[RRI8_S], cpu_R[RRI8_T],
1683 4 + RRI8_IMM8_SE);
1684 }
1685 break;
1686
1687 case 4: /*BALL*/ /*BNALL*/
1688 {
1689 TCGv_i32 tmp = tcg_temp_new_i32();
1690 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
1691 gen_brcond(dc, eq_ne, tmp, cpu_R[RRI8_T],
1692 4 + RRI8_IMM8_SE);
1693 tcg_temp_free(tmp);
1694 }
1695 break;
1696
1697 case 5: /*BBC*/ /*BBS*/
1698 {
1699 TCGv_i32 bit = tcg_const_i32(1);
1700 TCGv_i32 tmp = tcg_temp_new_i32();
1701 tcg_gen_andi_i32(tmp, cpu_R[RRI8_T], 0x1f);
1702 tcg_gen_shl_i32(bit, bit, tmp);
1703 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], bit);
1704 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
1705 tcg_temp_free(tmp);
1706 tcg_temp_free(bit);
1707 }
1708 break;
1709
1710 case 6: /*BBCI*/ /*BBSI*/
1711 case 7:
1712 {
1713 TCGv_i32 tmp = tcg_temp_new_i32();
1714 tcg_gen_andi_i32(tmp, cpu_R[RRI8_S],
1715 1 << (((RRI8_R & 1) << 4) | RRI8_T));
1716 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
1717 tcg_temp_free(tmp);
1718 }
1719 break;
1720
1721 }
1722 }
1723 break;
1724
1725 #define gen_narrow_load_store(type) do { \
1726 TCGv_i32 addr = tcg_temp_new_i32(); \
1727 tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
1728 tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, dc->cring); \
1729 tcg_temp_free(addr); \
1730 } while (0)
1731
1732 case 8: /*L32I.Nn*/
1733 gen_narrow_load_store(ld32u);
1734 break;
1735
1736 case 9: /*S32I.Nn*/
1737 gen_narrow_load_store(st32);
1738 break;
1739 #undef gen_narrow_load_store
1740
1741 case 10: /*ADD.Nn*/
1742 tcg_gen_add_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], cpu_R[RRRN_T]);
1743 break;
1744
1745 case 11: /*ADDI.Nn*/
1746 tcg_gen_addi_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], RRRN_T ? RRRN_T : -1);
1747 break;
1748
1749 case 12: /*ST2n*/
1750 if (RRRN_T < 8) { /*MOVI.Nn*/
1751 tcg_gen_movi_i32(cpu_R[RRRN_S],
1752 RRRN_R | (RRRN_T << 4) |
1753 ((RRRN_T & 6) == 6 ? 0xffffff80 : 0));
1754 } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/
1755 TCGCond eq_ne = (RRRN_T & 4) ? TCG_COND_NE : TCG_COND_EQ;
1756
1757 gen_brcondi(dc, eq_ne, cpu_R[RRRN_S], 0,
1758 4 + (RRRN_R | ((RRRN_T & 3) << 4)));
1759 }
1760 break;
1761
1762 case 13: /*ST3n*/
1763 switch (RRRN_R) {
1764 case 0: /*MOV.Nn*/
1765 tcg_gen_mov_i32(cpu_R[RRRN_T], cpu_R[RRRN_S]);
1766 break;
1767
1768 case 15: /*S3*/
1769 switch (RRRN_T) {
1770 case 0: /*RET.Nn*/
1771 gen_jump(dc, cpu_R[0]);
1772 break;
1773
1774 case 1: /*RETW.Nn*/
1775 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1776 {
1777 TCGv_i32 tmp = tcg_const_i32(dc->pc);
1778 gen_helper_retw(tmp, tmp);
1779 gen_jump(dc, tmp);
1780 tcg_temp_free(tmp);
1781 }
1782 break;
1783
1784 case 2: /*BREAK.Nn*/
1785 TBD();
1786 break;
1787
1788 case 3: /*NOP.Nn*/
1789 break;
1790
1791 case 6: /*ILL.Nn*/
1792 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1793 break;
1794
1795 default: /*reserved*/
1796 RESERVED();
1797 break;
1798 }
1799 break;
1800
1801 default: /*reserved*/
1802 RESERVED();
1803 break;
1804 }
1805 break;
1806
1807 default: /*reserved*/
1808 RESERVED();
1809 break;
1810 }
1811
1812 gen_check_loop_end(dc, 0);
1813 dc->pc = dc->next_pc;
1814
1815 return;
1816
1817 invalid_opcode:
1818 qemu_log("INVALID(pc = %08x)\n", dc->pc);
1819 dc->pc = dc->next_pc;
1820 #undef HAS_OPTION
1821 }
1822
1823 static void check_breakpoint(CPUState *env, DisasContext *dc)
1824 {
1825 CPUBreakpoint *bp;
1826
1827 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
1828 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
1829 if (bp->pc == dc->pc) {
1830 tcg_gen_movi_i32(cpu_pc, dc->pc);
1831 gen_exception(EXCP_DEBUG);
1832 dc->is_jmp = DISAS_UPDATE;
1833 }
1834 }
1835 }
1836 }
1837
1838 static void gen_intermediate_code_internal(
1839 CPUState *env, TranslationBlock *tb, int search_pc)
1840 {
1841 DisasContext dc;
1842 int insn_count = 0;
1843 int j, lj = -1;
1844 uint16_t *gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
1845 int max_insns = tb->cflags & CF_COUNT_MASK;
1846 uint32_t pc_start = tb->pc;
1847 uint32_t next_page_start =
1848 (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
1849
1850 if (max_insns == 0) {
1851 max_insns = CF_COUNT_MASK;
1852 }
1853
1854 dc.config = env->config;
1855 dc.singlestep_enabled = env->singlestep_enabled;
1856 dc.tb = tb;
1857 dc.pc = pc_start;
1858 dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK;
1859 dc.cring = (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc.ring;
1860 dc.lbeg = env->sregs[LBEG];
1861 dc.lend = env->sregs[LEND];
1862 dc.is_jmp = DISAS_NEXT;
1863
1864 init_litbase(&dc);
1865 init_sar_tracker(&dc);
1866
1867 gen_icount_start();
1868
1869 if (env->singlestep_enabled && env->exception_taken) {
1870 env->exception_taken = 0;
1871 tcg_gen_movi_i32(cpu_pc, dc.pc);
1872 gen_exception(EXCP_DEBUG);
1873 }
1874
1875 do {
1876 check_breakpoint(env, &dc);
1877
1878 if (search_pc) {
1879 j = gen_opc_ptr - gen_opc_buf;
1880 if (lj < j) {
1881 lj++;
1882 while (lj < j) {
1883 gen_opc_instr_start[lj++] = 0;
1884 }
1885 }
1886 gen_opc_pc[lj] = dc.pc;
1887 gen_opc_instr_start[lj] = 1;
1888 gen_opc_icount[lj] = insn_count;
1889 }
1890
1891 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
1892 tcg_gen_debug_insn_start(dc.pc);
1893 }
1894
1895 disas_xtensa_insn(&dc);
1896 ++insn_count;
1897 if (env->singlestep_enabled) {
1898 tcg_gen_movi_i32(cpu_pc, dc.pc);
1899 gen_exception(EXCP_DEBUG);
1900 break;
1901 }
1902 } while (dc.is_jmp == DISAS_NEXT &&
1903 insn_count < max_insns &&
1904 dc.pc < next_page_start &&
1905 gen_opc_ptr < gen_opc_end);
1906
1907 reset_litbase(&dc);
1908 reset_sar_tracker(&dc);
1909
1910 if (dc.is_jmp == DISAS_NEXT) {
1911 gen_jumpi(&dc, dc.pc, 0);
1912 }
1913 gen_icount_end(tb, insn_count);
1914 *gen_opc_ptr = INDEX_op_end;
1915
1916 if (!search_pc) {
1917 tb->size = dc.pc - pc_start;
1918 tb->icount = insn_count;
1919 }
1920 }
1921
1922 void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
1923 {
1924 gen_intermediate_code_internal(env, tb, 0);
1925 }
1926
1927 void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
1928 {
1929 gen_intermediate_code_internal(env, tb, 1);
1930 }
1931
1932 void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
1933 int flags)
1934 {
1935 int i, j;
1936
1937 cpu_fprintf(f, "PC=%08x\n\n", env->pc);
1938
1939 for (i = j = 0; i < 256; ++i) {
1940 if (sregnames[i]) {
1941 cpu_fprintf(f, "%s=%08x%c", sregnames[i], env->sregs[i],
1942 (j++ % 4) == 3 ? '\n' : ' ');
1943 }
1944 }
1945
1946 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
1947
1948 for (i = j = 0; i < 256; ++i) {
1949 if (uregnames[i]) {
1950 cpu_fprintf(f, "%s=%08x%c", uregnames[i], env->uregs[i],
1951 (j++ % 4) == 3 ? '\n' : ' ');
1952 }
1953 }
1954
1955 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
1956
1957 for (i = 0; i < 16; ++i) {
1958 cpu_fprintf(f, "A%02d=%08x%c", i, env->regs[i],
1959 (i % 4) == 3 ? '\n' : ' ');
1960 }
1961
1962 cpu_fprintf(f, "\n");
1963
1964 for (i = 0; i < env->config->nareg; ++i) {
1965 cpu_fprintf(f, "AR%02d=%08x%c", i, env->phys_regs[i],
1966 (i % 4) == 3 ? '\n' : ' ');
1967 }
1968 }
1969
1970 void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
1971 {
1972 env->pc = gen_opc_pc[pc_pos];
1973 }
Qemu copy for testing