3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 typedef struct DisasContext
{
44 const XtensaConfig
*config
;
49 int singlestep_enabled
;
53 bool sar_m32_allocated
;
57 static TCGv_ptr cpu_env
;
58 static TCGv_i32 cpu_pc
;
59 static TCGv_i32 cpu_R
[16];
60 static TCGv_i32 cpu_SR
[256];
61 static TCGv_i32 cpu_UR
[256];
63 #include "gen-icount.h"
65 static const char * const sregnames
[256] = {
67 [SCOMPARE1
] = "SCOMPARE1",
70 static const char * const uregnames
[256] = {
71 [THREADPTR
] = "THREADPTR",
76 void xtensa_translate_init(void)
78 static const char * const regnames
[] = {
79 "ar0", "ar1", "ar2", "ar3",
80 "ar4", "ar5", "ar6", "ar7",
81 "ar8", "ar9", "ar10", "ar11",
82 "ar12", "ar13", "ar14", "ar15",
86 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
87 cpu_pc
= tcg_global_mem_new_i32(TCG_AREG0
,
88 offsetof(CPUState
, pc
), "pc");
90 for (i
= 0; i
< 16; i
++) {
91 cpu_R
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
92 offsetof(CPUState
, regs
[i
]),
96 for (i
= 0; i
< 256; ++i
) {
98 cpu_SR
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
99 offsetof(CPUState
, sregs
[i
]),
104 for (i
= 0; i
< 256; ++i
) {
106 cpu_UR
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
107 offsetof(CPUState
, uregs
[i
]),
115 static inline bool option_enabled(DisasContext
*dc
, int opt
)
117 return xtensa_option_enabled(dc
->config
, opt
);
120 static void init_sar_tracker(DisasContext
*dc
)
122 dc
->sar_5bit
= false;
123 dc
->sar_m32_5bit
= false;
124 dc
->sar_m32_allocated
= false;
127 static void reset_sar_tracker(DisasContext
*dc
)
129 if (dc
->sar_m32_allocated
) {
130 tcg_temp_free(dc
->sar_m32
);
134 static void gen_right_shift_sar(DisasContext
*dc
, TCGv_i32 sa
)
136 tcg_gen_andi_i32(cpu_SR
[SAR
], sa
, 0x1f);
137 if (dc
->sar_m32_5bit
) {
138 tcg_gen_discard_i32(dc
->sar_m32
);
141 dc
->sar_m32_5bit
= false;
144 static void gen_left_shift_sar(DisasContext
*dc
, TCGv_i32 sa
)
146 TCGv_i32 tmp
= tcg_const_i32(32);
147 if (!dc
->sar_m32_allocated
) {
148 dc
->sar_m32
= tcg_temp_local_new_i32();
149 dc
->sar_m32_allocated
= true;
151 tcg_gen_andi_i32(dc
->sar_m32
, sa
, 0x1f);
152 tcg_gen_sub_i32(cpu_SR
[SAR
], tmp
, dc
->sar_m32
);
153 dc
->sar_5bit
= false;
154 dc
->sar_m32_5bit
= true;
158 static void gen_exception(int excp
)
160 TCGv_i32 tmp
= tcg_const_i32(excp
);
161 gen_helper_exception(tmp
);
165 static void gen_jump_slot(DisasContext
*dc
, TCGv dest
, int slot
)
167 tcg_gen_mov_i32(cpu_pc
, dest
);
168 if (dc
->singlestep_enabled
) {
169 gen_exception(EXCP_DEBUG
);
172 tcg_gen_goto_tb(slot
);
173 tcg_gen_exit_tb((tcg_target_long
)dc
->tb
+ slot
);
178 dc
->is_jmp
= DISAS_UPDATE
;
181 static void gen_jump(DisasContext
*dc
, TCGv dest
)
183 gen_jump_slot(dc
, dest
, -1);
186 static void gen_jumpi(DisasContext
*dc
, uint32_t dest
, int slot
)
188 TCGv_i32 tmp
= tcg_const_i32(dest
);
189 if (((dc
->pc
^ dest
) & TARGET_PAGE_MASK
) != 0) {
192 gen_jump_slot(dc
, tmp
, slot
);
196 static void gen_brcond(DisasContext
*dc
, TCGCond cond
,
197 TCGv_i32 t0
, TCGv_i32 t1
, uint32_t offset
)
199 int label
= gen_new_label();
201 tcg_gen_brcond_i32(cond
, t0
, t1
, label
);
202 gen_jumpi(dc
, dc
->next_pc
, 0);
203 gen_set_label(label
);
204 gen_jumpi(dc
, dc
->pc
+ offset
, 1);
207 static void gen_brcondi(DisasContext
*dc
, TCGCond cond
,
208 TCGv_i32 t0
, uint32_t t1
, uint32_t offset
)
210 TCGv_i32 tmp
= tcg_const_i32(t1
);
211 gen_brcond(dc
, cond
, t0
, tmp
, offset
);
215 static void gen_rsr(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
217 static void (* const rsr_handler
[256])(DisasContext
*dc
,
218 TCGv_i32 d
, uint32_t sr
) = {
222 if (rsr_handler
[sr
]) {
223 rsr_handler
[sr
](dc
, d
, sr
);
225 tcg_gen_mov_i32(d
, cpu_SR
[sr
]);
228 qemu_log("RSR %d not implemented, ", sr
);
232 static void gen_wsr_sar(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
234 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0x3f);
235 if (dc
->sar_m32_5bit
) {
236 tcg_gen_discard_i32(dc
->sar_m32
);
238 dc
->sar_5bit
= false;
239 dc
->sar_m32_5bit
= false;
242 static void gen_wsr(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
244 static void (* const wsr_handler
[256])(DisasContext
*dc
,
245 uint32_t sr
, TCGv_i32 v
) = {
250 if (wsr_handler
[sr
]) {
251 wsr_handler
[sr
](dc
, sr
, s
);
253 tcg_gen_mov_i32(cpu_SR
[sr
], s
);
256 qemu_log("WSR %d not implemented, ", sr
);
260 static void disas_xtensa_insn(DisasContext
*dc
)
262 #define HAS_OPTION(opt) do { \
263 if (!option_enabled(dc, opt)) { \
264 qemu_log("Option %d is not enabled %s:%d\n", \
265 (opt), __FILE__, __LINE__); \
266 goto invalid_opcode; \
270 #define TBD() qemu_log("TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)
271 #define RESERVED() do { \
272 qemu_log("RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \
273 dc->pc, b0, b1, b2, __FILE__, __LINE__); \
274 goto invalid_opcode; \
278 #ifdef TARGET_WORDS_BIGENDIAN
279 #define OP0 (((b0) & 0xf0) >> 4)
280 #define OP1 (((b2) & 0xf0) >> 4)
281 #define OP2 ((b2) & 0xf)
282 #define RRR_R ((b1) & 0xf)
283 #define RRR_S (((b1) & 0xf0) >> 4)
284 #define RRR_T ((b0) & 0xf)
286 #define OP0 (((b0) & 0xf))
287 #define OP1 (((b2) & 0xf))
288 #define OP2 (((b2) & 0xf0) >> 4)
289 #define RRR_R (((b1) & 0xf0) >> 4)
290 #define RRR_S (((b1) & 0xf))
291 #define RRR_T (((b0) & 0xf0) >> 4)
301 #define RRI8_IMM8 (b2)
302 #define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)
304 #ifdef TARGET_WORDS_BIGENDIAN
305 #define RI16_IMM16 (((b1) << 8) | (b2))
307 #define RI16_IMM16 (((b2) << 8) | (b1))
310 #ifdef TARGET_WORDS_BIGENDIAN
311 #define CALL_N (((b0) & 0xc) >> 2)
312 #define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))
314 #define CALL_N (((b0) & 0x30) >> 4)
315 #define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))
317 #define CALL_OFFSET_SE \
318 (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)
320 #define CALLX_N CALL_N
321 #ifdef TARGET_WORDS_BIGENDIAN
322 #define CALLX_M ((b0) & 0x3)
324 #define CALLX_M (((b0) & 0xc0) >> 6)
326 #define CALLX_S RRR_S
328 #define BRI12_M CALLX_M
329 #define BRI12_S RRR_S
330 #ifdef TARGET_WORDS_BIGENDIAN
331 #define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))
333 #define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))
335 #define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)
337 #define BRI8_M BRI12_M
338 #define BRI8_R RRI8_R
339 #define BRI8_S RRI8_S
340 #define BRI8_IMM8 RRI8_IMM8
341 #define BRI8_IMM8_SE RRI8_IMM8_SE
345 uint8_t b0
= ldub_code(dc
->pc
);
346 uint8_t b1
= ldub_code(dc
->pc
+ 1);
347 uint8_t b2
= ldub_code(dc
->pc
+ 2);
349 static const uint32_t B4CONST
[] = {
350 0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
353 static const uint32_t B4CONSTU
[] = {
354 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
358 dc
->next_pc
= dc
->pc
+ 2;
359 HAS_OPTION(XTENSA_OPTION_CODE_DENSITY
);
361 dc
->next_pc
= dc
->pc
+ 3;
370 if ((RRR_R
& 0xc) == 0x8) {
371 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
389 gen_jump(dc
, cpu_R
[CALLX_S
]);
393 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
407 TCGv_i32 tmp
= tcg_temp_new_i32();
408 tcg_gen_mov_i32(tmp
, cpu_R
[CALLX_S
]);
409 tcg_gen_movi_i32(cpu_R
[0], dc
->next_pc
);
418 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
427 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
440 HAS_OPTION(XTENSA_OPTION_EXCEPTION
);
445 HAS_OPTION(XTENSA_OPTION_EXCEPTION
);
450 HAS_OPTION(XTENSA_OPTION_INTERRUPT
);
455 HAS_OPTION(XTENSA_OPTION_INTERRUPT
);
460 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
465 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
470 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
475 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
479 default: /*reserved*/
487 tcg_gen_and_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
491 tcg_gen_or_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
495 tcg_gen_xor_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
501 gen_right_shift_sar(dc
, cpu_R
[RRR_S
]);
505 gen_left_shift_sar(dc
, cpu_R
[RRR_S
]);
510 TCGv_i32 tmp
= tcg_temp_new_i32();
511 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], 3);
512 gen_right_shift_sar(dc
, tmp
);
519 TCGv_i32 tmp
= tcg_temp_new_i32();
520 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], 3);
521 gen_left_shift_sar(dc
, tmp
);
528 TCGv_i32 tmp
= tcg_const_i32(
529 RRR_S
| ((RRR_T
& 1) << 4));
530 gen_right_shift_sar(dc
, tmp
);
544 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
549 HAS_OPTION(XTENSA_OPTION_MISC_OP
);
550 gen_helper_nsa(cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
554 HAS_OPTION(XTENSA_OPTION_MISC_OP
);
555 gen_helper_nsau(cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
558 default: /*reserved*/
571 tcg_gen_neg_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
576 int label
= gen_new_label();
577 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
579 TCG_COND_GE
, cpu_R
[RRR_R
], 0, label
);
580 tcg_gen_neg_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
581 gen_set_label(label
);
585 default: /*reserved*/
596 tcg_gen_add_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
603 TCGv_i32 tmp
= tcg_temp_new_i32();
604 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], OP2
- 8);
605 tcg_gen_add_i32(cpu_R
[RRR_R
], tmp
, cpu_R
[RRR_T
]);
611 tcg_gen_sub_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
618 TCGv_i32 tmp
= tcg_temp_new_i32();
619 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], OP2
- 12);
620 tcg_gen_sub_i32(cpu_R
[RRR_R
], tmp
, cpu_R
[RRR_T
]);
631 tcg_gen_shli_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
],
632 32 - (RRR_T
| ((OP2
& 1) << 4)));
637 tcg_gen_sari_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
],
638 RRR_S
| ((OP2
& 1) << 4));
642 tcg_gen_shri_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
], RRR_S
);
647 TCGv_i32 tmp
= tcg_temp_new_i32();
648 tcg_gen_mov_i32(tmp
, cpu_R
[RRR_T
]);
649 gen_rsr(dc
, cpu_R
[RRR_T
], RSR_SR
);
650 gen_wsr(dc
, RSR_SR
, tmp
);
652 if (!sregnames
[RSR_SR
]) {
659 * Note: 64 bit ops are used here solely because SAR values
662 #define gen_shift_reg(cmd, reg) do { \
663 TCGv_i64 tmp = tcg_temp_new_i64(); \
664 tcg_gen_extu_i32_i64(tmp, reg); \
665 tcg_gen_##cmd##_i64(v, v, tmp); \
666 tcg_gen_trunc_i64_i32(cpu_R[RRR_R], v); \
667 tcg_temp_free_i64(v); \
668 tcg_temp_free_i64(tmp); \
671 #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
675 TCGv_i64 v
= tcg_temp_new_i64();
676 tcg_gen_concat_i32_i64(v
, cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
683 tcg_gen_shr_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
], cpu_SR
[SAR
]);
685 TCGv_i64 v
= tcg_temp_new_i64();
686 tcg_gen_extu_i32_i64(v
, cpu_R
[RRR_T
]);
692 if (dc
->sar_m32_5bit
) {
693 tcg_gen_shl_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], dc
->sar_m32
);
695 TCGv_i64 v
= tcg_temp_new_i64();
696 TCGv_i32 s
= tcg_const_i32(32);
697 tcg_gen_sub_i32(s
, s
, cpu_SR
[SAR
]);
698 tcg_gen_andi_i32(s
, s
, 0x3f);
699 tcg_gen_extu_i32_i64(v
, cpu_R
[RRR_S
]);
700 gen_shift_reg(shl
, s
);
707 tcg_gen_sar_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
], cpu_SR
[SAR
]);
709 TCGv_i64 v
= tcg_temp_new_i64();
710 tcg_gen_ext_i32_i64(v
, cpu_R
[RRR_T
]);
718 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL
);
720 TCGv_i32 v1
= tcg_temp_new_i32();
721 TCGv_i32 v2
= tcg_temp_new_i32();
722 tcg_gen_ext16u_i32(v1
, cpu_R
[RRR_S
]);
723 tcg_gen_ext16u_i32(v2
, cpu_R
[RRR_T
]);
724 tcg_gen_mul_i32(cpu_R
[RRR_R
], v1
, v2
);
731 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL
);
733 TCGv_i32 v1
= tcg_temp_new_i32();
734 TCGv_i32 v2
= tcg_temp_new_i32();
735 tcg_gen_ext16s_i32(v1
, cpu_R
[RRR_S
]);
736 tcg_gen_ext16s_i32(v2
, cpu_R
[RRR_T
]);
737 tcg_gen_mul_i32(cpu_R
[RRR_R
], v1
, v2
);
743 default: /*reserved*/
756 gen_rsr(dc
, cpu_R
[RRR_T
], RSR_SR
);
757 if (!sregnames
[RSR_SR
]) {
763 gen_wsr(dc
, RSR_SR
, cpu_R
[RRR_T
]);
764 if (!sregnames
[RSR_SR
]) {
770 HAS_OPTION(XTENSA_OPTION_MISC_OP
);
772 int shift
= 24 - RRR_T
;
775 tcg_gen_ext8s_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
776 } else if (shift
== 16) {
777 tcg_gen_ext16s_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
779 TCGv_i32 tmp
= tcg_temp_new_i32();
780 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], shift
);
781 tcg_gen_sari_i32(cpu_R
[RRR_R
], tmp
, shift
);
788 HAS_OPTION(XTENSA_OPTION_MISC_OP
);
790 TCGv_i32 tmp1
= tcg_temp_new_i32();
791 TCGv_i32 tmp2
= tcg_temp_new_i32();
792 int label
= gen_new_label();
794 tcg_gen_sari_i32(tmp1
, cpu_R
[RRR_S
], 24 - RRR_T
);
795 tcg_gen_xor_i32(tmp2
, tmp1
, cpu_R
[RRR_S
]);
796 tcg_gen_andi_i32(tmp2
, tmp2
, 0xffffffff << (RRR_T
+ 7));
797 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
798 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp2
, 0, label
);
800 tcg_gen_sari_i32(tmp1
, cpu_R
[RRR_S
], 31);
801 tcg_gen_xori_i32(cpu_R
[RRR_R
], tmp1
,
802 0xffffffff >> (25 - RRR_T
));
804 gen_set_label(label
);
815 HAS_OPTION(XTENSA_OPTION_MISC_OP
);
817 static const TCGCond cond
[] = {
823 int label
= gen_new_label();
825 if (RRR_R
!= RRR_T
) {
826 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
827 tcg_gen_brcond_i32(cond
[OP2
- 4],
828 cpu_R
[RRR_S
], cpu_R
[RRR_T
], label
);
829 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
831 tcg_gen_brcond_i32(cond
[OP2
- 4],
832 cpu_R
[RRR_T
], cpu_R
[RRR_S
], label
);
833 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
835 gen_set_label(label
);
844 static const TCGCond cond
[] = {
850 int label
= gen_new_label();
851 tcg_gen_brcondi_i32(cond
[OP2
- 8], cpu_R
[RRR_T
], 0, label
);
852 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
853 gen_set_label(label
);
858 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
863 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
869 int st
= (RRR_S
<< 4) + RRR_T
;
871 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_UR
[st
]);
873 qemu_log("RUR %d not implemented, ", st
);
881 if (uregnames
[RSR_SR
]) {
882 tcg_gen_mov_i32(cpu_UR
[RSR_SR
], cpu_R
[RRR_T
]);
884 qemu_log("WUR %d not implemented, ", RSR_SR
);
896 int shiftimm
= RRR_S
| (OP1
<< 4);
897 int maskimm
= (1 << (OP2
+ 1)) - 1;
899 TCGv_i32 tmp
= tcg_temp_new_i32();
900 tcg_gen_shri_i32(tmp
, cpu_R
[RRR_T
], shiftimm
);
901 tcg_gen_andi_i32(cpu_R
[RRR_R
], tmp
, maskimm
);
915 HAS_OPTION(XTENSA_OPTION_COPROCESSOR
);
924 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR
);
929 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR
);
933 default: /*reserved*/
941 TCGv_i32 tmp
= tcg_const_i32(
942 (0xfffc0000 | (RI16_IMM16
<< 2)) +
943 ((dc
->pc
+ 3) & ~3));
947 tcg_gen_qemu_ld32u(cpu_R
[RRR_T
], tmp
, 0);
953 #define gen_load_store(type, shift) do { \
954 TCGv_i32 addr = tcg_temp_new_i32(); \
955 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \
956 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, 0); \
957 tcg_temp_free(addr); \
962 gen_load_store(ld8u
, 0);
966 gen_load_store(ld16u
, 1);
970 gen_load_store(ld32u
, 2);
974 gen_load_store(st8
, 0);
978 gen_load_store(st16
, 1);
982 gen_load_store(st32
, 2);
990 gen_load_store(ld16s
, 1);
994 tcg_gen_movi_i32(cpu_R
[RRI8_T
],
995 RRI8_IMM8
| (RRI8_S
<< 8) |
996 ((RRI8_S
& 0x8) ? 0xfffff000 : 0));
1000 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO
);
1001 gen_load_store(ld32u
, 2); /*TODO acquire?*/
1005 tcg_gen_addi_i32(cpu_R
[RRI8_T
], cpu_R
[RRI8_S
], RRI8_IMM8_SE
);
1009 tcg_gen_addi_i32(cpu_R
[RRI8_T
], cpu_R
[RRI8_S
], RRI8_IMM8_SE
<< 8);
1012 case 14: /*S32C1Iy*/
1013 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO
);
1015 int label
= gen_new_label();
1016 TCGv_i32 tmp
= tcg_temp_local_new_i32();
1017 TCGv_i32 addr
= tcg_temp_local_new_i32();
1019 tcg_gen_mov_i32(tmp
, cpu_R
[RRI8_T
]);
1020 tcg_gen_addi_i32(addr
, cpu_R
[RRI8_S
], RRI8_IMM8
<< 2);
1021 tcg_gen_qemu_ld32u(cpu_R
[RRI8_T
], addr
, 0);
1022 tcg_gen_brcond_i32(TCG_COND_NE
, cpu_R
[RRI8_T
],
1023 cpu_SR
[SCOMPARE1
], label
);
1025 tcg_gen_qemu_st32(tmp
, addr
, 0);
1027 gen_set_label(label
);
1028 tcg_temp_free(addr
);
1034 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO
);
1035 gen_load_store(st32
, 2); /*TODO release?*/
1038 default: /*reserved*/
1043 #undef gen_load_store
1046 HAS_OPTION(XTENSA_OPTION_COPROCESSOR
);
1051 HAS_OPTION(XTENSA_OPTION_MAC16
);
1058 tcg_gen_movi_i32(cpu_R
[0], dc
->next_pc
);
1059 gen_jumpi(dc
, (dc
->pc
& ~3) + (CALL_OFFSET_SE
<< 2) + 4, 0);
1065 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1074 gen_jumpi(dc
, dc
->pc
+ 4 + CALL_OFFSET_SE
, 0);
1079 static const TCGCond cond
[] = {
1080 TCG_COND_EQ
, /*BEQZ*/
1081 TCG_COND_NE
, /*BNEZ*/
1082 TCG_COND_LT
, /*BLTZ*/
1083 TCG_COND_GE
, /*BGEZ*/
1086 gen_brcondi(dc
, cond
[BRI12_M
& 3], cpu_R
[BRI12_S
], 0,
1087 4 + BRI12_IMM12_SE
);
1093 static const TCGCond cond
[] = {
1094 TCG_COND_EQ
, /*BEQI*/
1095 TCG_COND_NE
, /*BNEI*/
1096 TCG_COND_LT
, /*BLTI*/
1097 TCG_COND_GE
, /*BGEI*/
1100 gen_brcondi(dc
, cond
[BRI8_M
& 3],
1101 cpu_R
[BRI8_S
], B4CONST
[BRI8_R
], 4 + BRI8_IMM8_SE
);
1108 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1115 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
1120 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
1132 case 10: /*LOOPGTZ*/
1136 default: /*reserved*/
1145 gen_brcondi(dc
, BRI8_M
== 2 ? TCG_COND_LTU
: TCG_COND_GEU
,
1146 cpu_R
[BRI8_S
], B4CONSTU
[BRI8_R
], 4 + BRI8_IMM8_SE
);
1156 TCGCond eq_ne
= (RRI8_R
& 8) ? TCG_COND_NE
: TCG_COND_EQ
;
1158 switch (RRI8_R
& 7) {
1159 case 0: /*BNONE*/ /*BANY*/
1161 TCGv_i32 tmp
= tcg_temp_new_i32();
1162 tcg_gen_and_i32(tmp
, cpu_R
[RRI8_S
], cpu_R
[RRI8_T
]);
1163 gen_brcondi(dc
, eq_ne
, tmp
, 0, 4 + RRI8_IMM8_SE
);
1168 case 1: /*BEQ*/ /*BNE*/
1169 case 2: /*BLT*/ /*BGE*/
1170 case 3: /*BLTU*/ /*BGEU*/
1172 static const TCGCond cond
[] = {
1178 [11] = TCG_COND_GEU
,
1180 gen_brcond(dc
, cond
[RRI8_R
], cpu_R
[RRI8_S
], cpu_R
[RRI8_T
],
1185 case 4: /*BALL*/ /*BNALL*/
1187 TCGv_i32 tmp
= tcg_temp_new_i32();
1188 tcg_gen_and_i32(tmp
, cpu_R
[RRI8_S
], cpu_R
[RRI8_T
]);
1189 gen_brcond(dc
, eq_ne
, tmp
, cpu_R
[RRI8_T
],
1195 case 5: /*BBC*/ /*BBS*/
1197 TCGv_i32 bit
= tcg_const_i32(1);
1198 TCGv_i32 tmp
= tcg_temp_new_i32();
1199 tcg_gen_andi_i32(tmp
, cpu_R
[RRI8_T
], 0x1f);
1200 tcg_gen_shl_i32(bit
, bit
, tmp
);
1201 tcg_gen_and_i32(tmp
, cpu_R
[RRI8_S
], bit
);
1202 gen_brcondi(dc
, eq_ne
, tmp
, 0, 4 + RRI8_IMM8_SE
);
1208 case 6: /*BBCI*/ /*BBSI*/
1211 TCGv_i32 tmp
= tcg_temp_new_i32();
1212 tcg_gen_andi_i32(tmp
, cpu_R
[RRI8_S
],
1213 1 << (((RRI8_R
& 1) << 4) | RRI8_T
));
1214 gen_brcondi(dc
, eq_ne
, tmp
, 0, 4 + RRI8_IMM8_SE
);
1223 #define gen_narrow_load_store(type) do { \
1224 TCGv_i32 addr = tcg_temp_new_i32(); \
1225 tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
1226 tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, 0); \
1227 tcg_temp_free(addr); \
1231 gen_narrow_load_store(ld32u
);
1235 gen_narrow_load_store(st32
);
1237 #undef gen_narrow_load_store
1240 tcg_gen_add_i32(cpu_R
[RRRN_R
], cpu_R
[RRRN_S
], cpu_R
[RRRN_T
]);
1243 case 11: /*ADDI.Nn*/
1244 tcg_gen_addi_i32(cpu_R
[RRRN_R
], cpu_R
[RRRN_S
], RRRN_T
? RRRN_T
: -1);
1248 if (RRRN_T
< 8) { /*MOVI.Nn*/
1249 tcg_gen_movi_i32(cpu_R
[RRRN_S
],
1250 RRRN_R
| (RRRN_T
<< 4) |
1251 ((RRRN_T
& 6) == 6 ? 0xffffff80 : 0));
1252 } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/
1253 TCGCond eq_ne
= (RRRN_T
& 4) ? TCG_COND_NE
: TCG_COND_EQ
;
1255 gen_brcondi(dc
, eq_ne
, cpu_R
[RRRN_S
], 0,
1256 4 + (RRRN_R
| ((RRRN_T
& 3) << 4)));
1263 tcg_gen_mov_i32(cpu_R
[RRRN_T
], cpu_R
[RRRN_S
]);
1269 gen_jump(dc
, cpu_R
[0]);
1273 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1277 case 2: /*BREAK.Nn*/
1288 default: /*reserved*/
1294 default: /*reserved*/
1300 default: /*reserved*/
1305 dc
->pc
= dc
->next_pc
;
1309 qemu_log("INVALID(pc = %08x)\n", dc
->pc
);
1310 dc
->pc
= dc
->next_pc
;
1314 static void check_breakpoint(CPUState
*env
, DisasContext
*dc
)
1318 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
1319 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
1320 if (bp
->pc
== dc
->pc
) {
1321 tcg_gen_movi_i32(cpu_pc
, dc
->pc
);
1322 gen_exception(EXCP_DEBUG
);
1323 dc
->is_jmp
= DISAS_UPDATE
;
1329 static void gen_intermediate_code_internal(
1330 CPUState
*env
, TranslationBlock
*tb
, int search_pc
)
1335 uint16_t *gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
1336 int max_insns
= tb
->cflags
& CF_COUNT_MASK
;
1337 uint32_t pc_start
= tb
->pc
;
1338 uint32_t next_page_start
=
1339 (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
1341 if (max_insns
== 0) {
1342 max_insns
= CF_COUNT_MASK
;
1345 dc
.config
= env
->config
;
1346 dc
.singlestep_enabled
= env
->singlestep_enabled
;
1349 dc
.is_jmp
= DISAS_NEXT
;
1351 init_sar_tracker(&dc
);
1356 check_breakpoint(env
, &dc
);
1359 j
= gen_opc_ptr
- gen_opc_buf
;
1363 gen_opc_instr_start
[lj
++] = 0;
1366 gen_opc_pc
[lj
] = dc
.pc
;
1367 gen_opc_instr_start
[lj
] = 1;
1368 gen_opc_icount
[lj
] = insn_count
;
1371 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
))) {
1372 tcg_gen_debug_insn_start(dc
.pc
);
1375 disas_xtensa_insn(&dc
);
1377 if (env
->singlestep_enabled
) {
1378 tcg_gen_movi_i32(cpu_pc
, dc
.pc
);
1379 gen_exception(EXCP_DEBUG
);
1382 } while (dc
.is_jmp
== DISAS_NEXT
&&
1383 insn_count
< max_insns
&&
1384 dc
.pc
< next_page_start
&&
1385 gen_opc_ptr
< gen_opc_end
);
1387 reset_sar_tracker(&dc
);
1389 if (dc
.is_jmp
== DISAS_NEXT
) {
1390 gen_jumpi(&dc
, dc
.pc
, 0);
1392 gen_icount_end(tb
, insn_count
);
1393 *gen_opc_ptr
= INDEX_op_end
;
1396 tb
->size
= dc
.pc
- pc_start
;
1397 tb
->icount
= insn_count
;
1401 void gen_intermediate_code(CPUState
*env
, TranslationBlock
*tb
)
1403 gen_intermediate_code_internal(env
, tb
, 0);
1406 void gen_intermediate_code_pc(CPUState
*env
, TranslationBlock
*tb
)
1408 gen_intermediate_code_internal(env
, tb
, 1);
1411 void cpu_dump_state(CPUState
*env
, FILE *f
, fprintf_function cpu_fprintf
,
1416 cpu_fprintf(f
, "PC=%08x\n\n", env
->pc
);
1418 for (i
= j
= 0; i
< 256; ++i
) {
1420 cpu_fprintf(f
, "%s=%08x%c", sregnames
[i
], env
->sregs
[i
],
1421 (j
++ % 4) == 3 ? '\n' : ' ');
1425 cpu_fprintf(f
, (j
% 4) == 0 ? "\n" : "\n\n");
1427 for (i
= j
= 0; i
< 256; ++i
) {
1429 cpu_fprintf(f
, "%s=%08x%c", uregnames
[i
], env
->uregs
[i
],
1430 (j
++ % 4) == 3 ? '\n' : ' ');
1434 cpu_fprintf(f
, (j
% 4) == 0 ? "\n" : "\n\n");
1436 for (i
= 0; i
< 16; ++i
) {
1437 cpu_fprintf(f
, "A%02d=%08x%c", i
, env
->regs
[i
],
1438 (i
% 4) == 3 ? '\n' : ' ');
1442 void restore_state_to_opc(CPUState
*env
, TranslationBlock
*tb
, int pc_pos
)
1444 env
->pc
= gen_opc_pc
[pc_pos
];