3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 typedef struct DisasContext
{
45 const XtensaConfig
*config
;
55 int singlestep_enabled
;
59 bool sar_m32_allocated
;
62 uint32_t ccount_delta
;
70 static TCGv_ptr cpu_env
;
71 static TCGv_i32 cpu_pc
;
72 static TCGv_i32 cpu_R
[16];
73 static TCGv_i32 cpu_SR
[256];
74 static TCGv_i32 cpu_UR
[256];
76 #include "gen-icount.h"
78 static const char * const sregnames
[256] = {
84 [LITBASE
] = "LITBASE",
85 [SCOMPARE1
] = "SCOMPARE1",
92 [WINDOW_BASE
] = "WINDOW_BASE",
93 [WINDOW_START
] = "WINDOW_START",
94 [PTEVADDR
] = "PTEVADDR",
96 [ITLBCFG
] = "ITLBCFG",
97 [DTLBCFG
] = "DTLBCFG",
98 [IBREAKENABLE
] = "IBREAKENABLE",
99 [IBREAKA
] = "IBREAKA0",
100 [IBREAKA
+ 1] = "IBREAKA1",
101 [DBREAKA
] = "DBREAKA0",
102 [DBREAKA
+ 1] = "DBREAKA1",
103 [DBREAKC
] = "DBREAKC0",
104 [DBREAKC
+ 1] = "DBREAKC1",
119 [EXCSAVE1
] = "EXCSAVE1",
120 [EXCSAVE1
+ 1] = "EXCSAVE2",
121 [EXCSAVE1
+ 2] = "EXCSAVE3",
122 [EXCSAVE1
+ 3] = "EXCSAVE4",
123 [EXCSAVE1
+ 4] = "EXCSAVE5",
124 [EXCSAVE1
+ 5] = "EXCSAVE6",
125 [EXCSAVE1
+ 6] = "EXCSAVE7",
126 [CPENABLE
] = "CPENABLE",
128 [INTCLEAR
] = "INTCLEAR",
129 [INTENABLE
] = "INTENABLE",
131 [VECBASE
] = "VECBASE",
132 [EXCCAUSE
] = "EXCCAUSE",
133 [DEBUGCAUSE
] = "DEBUGCAUSE",
137 [ICOUNTLEVEL
] = "ICOUNTLEVEL",
138 [EXCVADDR
] = "EXCVADDR",
139 [CCOMPARE
] = "CCOMPARE0",
140 [CCOMPARE
+ 1] = "CCOMPARE1",
141 [CCOMPARE
+ 2] = "CCOMPARE2",
144 static const char * const uregnames
[256] = {
145 [THREADPTR
] = "THREADPTR",
150 void xtensa_translate_init(void)
152 static const char * const regnames
[] = {
153 "ar0", "ar1", "ar2", "ar3",
154 "ar4", "ar5", "ar6", "ar7",
155 "ar8", "ar9", "ar10", "ar11",
156 "ar12", "ar13", "ar14", "ar15",
160 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
161 cpu_pc
= tcg_global_mem_new_i32(TCG_AREG0
,
162 offsetof(CPUState
, pc
), "pc");
164 for (i
= 0; i
< 16; i
++) {
165 cpu_R
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
166 offsetof(CPUState
, regs
[i
]),
170 for (i
= 0; i
< 256; ++i
) {
172 cpu_SR
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
173 offsetof(CPUState
, sregs
[i
]),
178 for (i
= 0; i
< 256; ++i
) {
180 cpu_UR
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
181 offsetof(CPUState
, uregs
[i
]),
189 static inline bool option_bits_enabled(DisasContext
*dc
, uint64_t opt
)
191 return xtensa_option_bits_enabled(dc
->config
, opt
);
194 static inline bool option_enabled(DisasContext
*dc
, int opt
)
196 return xtensa_option_enabled(dc
->config
, opt
);
199 static void init_litbase(DisasContext
*dc
)
201 if (dc
->tb
->flags
& XTENSA_TBFLAG_LITBASE
) {
202 dc
->litbase
= tcg_temp_local_new_i32();
203 tcg_gen_andi_i32(dc
->litbase
, cpu_SR
[LITBASE
], 0xfffff000);
207 static void reset_litbase(DisasContext
*dc
)
209 if (dc
->tb
->flags
& XTENSA_TBFLAG_LITBASE
) {
210 tcg_temp_free(dc
->litbase
);
214 static void init_sar_tracker(DisasContext
*dc
)
216 dc
->sar_5bit
= false;
217 dc
->sar_m32_5bit
= false;
218 dc
->sar_m32_allocated
= false;
221 static void reset_sar_tracker(DisasContext
*dc
)
223 if (dc
->sar_m32_allocated
) {
224 tcg_temp_free(dc
->sar_m32
);
228 static void gen_right_shift_sar(DisasContext
*dc
, TCGv_i32 sa
)
230 tcg_gen_andi_i32(cpu_SR
[SAR
], sa
, 0x1f);
231 if (dc
->sar_m32_5bit
) {
232 tcg_gen_discard_i32(dc
->sar_m32
);
235 dc
->sar_m32_5bit
= false;
238 static void gen_left_shift_sar(DisasContext
*dc
, TCGv_i32 sa
)
240 TCGv_i32 tmp
= tcg_const_i32(32);
241 if (!dc
->sar_m32_allocated
) {
242 dc
->sar_m32
= tcg_temp_local_new_i32();
243 dc
->sar_m32_allocated
= true;
245 tcg_gen_andi_i32(dc
->sar_m32
, sa
, 0x1f);
246 tcg_gen_sub_i32(cpu_SR
[SAR
], tmp
, dc
->sar_m32
);
247 dc
->sar_5bit
= false;
248 dc
->sar_m32_5bit
= true;
252 static void gen_advance_ccount(DisasContext
*dc
)
254 if (dc
->ccount_delta
> 0) {
255 TCGv_i32 tmp
= tcg_const_i32(dc
->ccount_delta
);
256 dc
->ccount_delta
= 0;
257 gen_helper_advance_ccount(tmp
);
262 static void reset_used_window(DisasContext
*dc
)
267 static void gen_exception(DisasContext
*dc
, int excp
)
269 TCGv_i32 tmp
= tcg_const_i32(excp
);
270 gen_advance_ccount(dc
);
271 gen_helper_exception(tmp
);
275 static void gen_exception_cause(DisasContext
*dc
, uint32_t cause
)
277 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
278 TCGv_i32 tcause
= tcg_const_i32(cause
);
279 gen_advance_ccount(dc
);
280 gen_helper_exception_cause(tpc
, tcause
);
282 tcg_temp_free(tcause
);
283 if (cause
== ILLEGAL_INSTRUCTION_CAUSE
||
284 cause
== SYSCALL_CAUSE
) {
285 dc
->is_jmp
= DISAS_UPDATE
;
289 static void gen_exception_cause_vaddr(DisasContext
*dc
, uint32_t cause
,
292 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
293 TCGv_i32 tcause
= tcg_const_i32(cause
);
294 gen_advance_ccount(dc
);
295 gen_helper_exception_cause_vaddr(tpc
, tcause
, vaddr
);
297 tcg_temp_free(tcause
);
300 static void gen_debug_exception(DisasContext
*dc
, uint32_t cause
)
302 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
303 TCGv_i32 tcause
= tcg_const_i32(cause
);
304 gen_advance_ccount(dc
);
305 gen_helper_debug_exception(tpc
, tcause
);
307 tcg_temp_free(tcause
);
308 if (cause
& (DEBUGCAUSE_IB
| DEBUGCAUSE_BI
| DEBUGCAUSE_BN
)) {
309 dc
->is_jmp
= DISAS_UPDATE
;
313 static void gen_check_privilege(DisasContext
*dc
)
316 gen_exception_cause(dc
, PRIVILEGED_CAUSE
);
317 dc
->is_jmp
= DISAS_UPDATE
;
321 static void gen_jump_slot(DisasContext
*dc
, TCGv dest
, int slot
)
323 tcg_gen_mov_i32(cpu_pc
, dest
);
324 gen_advance_ccount(dc
);
326 tcg_gen_mov_i32(cpu_SR
[ICOUNT
], dc
->next_icount
);
328 if (dc
->singlestep_enabled
) {
329 gen_exception(dc
, EXCP_DEBUG
);
332 tcg_gen_goto_tb(slot
);
333 tcg_gen_exit_tb((tcg_target_long
)dc
->tb
+ slot
);
338 dc
->is_jmp
= DISAS_UPDATE
;
341 static void gen_jump(DisasContext
*dc
, TCGv dest
)
343 gen_jump_slot(dc
, dest
, -1);
346 static void gen_jumpi(DisasContext
*dc
, uint32_t dest
, int slot
)
348 TCGv_i32 tmp
= tcg_const_i32(dest
);
349 if (((dc
->pc
^ dest
) & TARGET_PAGE_MASK
) != 0) {
352 gen_jump_slot(dc
, tmp
, slot
);
356 static void gen_callw_slot(DisasContext
*dc
, int callinc
, TCGv_i32 dest
,
359 TCGv_i32 tcallinc
= tcg_const_i32(callinc
);
361 tcg_gen_deposit_i32(cpu_SR
[PS
], cpu_SR
[PS
],
362 tcallinc
, PS_CALLINC_SHIFT
, PS_CALLINC_LEN
);
363 tcg_temp_free(tcallinc
);
364 tcg_gen_movi_i32(cpu_R
[callinc
<< 2],
365 (callinc
<< 30) | (dc
->next_pc
& 0x3fffffff));
366 gen_jump_slot(dc
, dest
, slot
);
369 static void gen_callw(DisasContext
*dc
, int callinc
, TCGv_i32 dest
)
371 gen_callw_slot(dc
, callinc
, dest
, -1);
374 static void gen_callwi(DisasContext
*dc
, int callinc
, uint32_t dest
, int slot
)
376 TCGv_i32 tmp
= tcg_const_i32(dest
);
377 if (((dc
->pc
^ dest
) & TARGET_PAGE_MASK
) != 0) {
380 gen_callw_slot(dc
, callinc
, tmp
, slot
);
384 static bool gen_check_loop_end(DisasContext
*dc
, int slot
)
386 if (option_enabled(dc
, XTENSA_OPTION_LOOP
) &&
387 !(dc
->tb
->flags
& XTENSA_TBFLAG_EXCM
) &&
388 dc
->next_pc
== dc
->lend
) {
389 int label
= gen_new_label();
391 tcg_gen_brcondi_i32(TCG_COND_EQ
, cpu_SR
[LCOUNT
], 0, label
);
392 tcg_gen_subi_i32(cpu_SR
[LCOUNT
], cpu_SR
[LCOUNT
], 1);
393 gen_jumpi(dc
, dc
->lbeg
, slot
);
394 gen_set_label(label
);
395 gen_jumpi(dc
, dc
->next_pc
, -1);
401 static void gen_jumpi_check_loop_end(DisasContext
*dc
, int slot
)
403 if (!gen_check_loop_end(dc
, slot
)) {
404 gen_jumpi(dc
, dc
->next_pc
, slot
);
408 static void gen_brcond(DisasContext
*dc
, TCGCond cond
,
409 TCGv_i32 t0
, TCGv_i32 t1
, uint32_t offset
)
411 int label
= gen_new_label();
413 tcg_gen_brcond_i32(cond
, t0
, t1
, label
);
414 gen_jumpi_check_loop_end(dc
, 0);
415 gen_set_label(label
);
416 gen_jumpi(dc
, dc
->pc
+ offset
, 1);
419 static void gen_brcondi(DisasContext
*dc
, TCGCond cond
,
420 TCGv_i32 t0
, uint32_t t1
, uint32_t offset
)
422 TCGv_i32 tmp
= tcg_const_i32(t1
);
423 gen_brcond(dc
, cond
, t0
, tmp
, offset
);
427 static void gen_rsr_ccount(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
429 gen_advance_ccount(dc
);
430 tcg_gen_mov_i32(d
, cpu_SR
[sr
]);
433 static void gen_rsr_ptevaddr(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
435 tcg_gen_shri_i32(d
, cpu_SR
[EXCVADDR
], 10);
436 tcg_gen_or_i32(d
, d
, cpu_SR
[sr
]);
437 tcg_gen_andi_i32(d
, d
, 0xfffffffc);
440 static void gen_rsr(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
442 static void (* const rsr_handler
[256])(DisasContext
*dc
,
443 TCGv_i32 d
, uint32_t sr
) = {
444 [CCOUNT
] = gen_rsr_ccount
,
445 [PTEVADDR
] = gen_rsr_ptevaddr
,
449 if (rsr_handler
[sr
]) {
450 rsr_handler
[sr
](dc
, d
, sr
);
452 tcg_gen_mov_i32(d
, cpu_SR
[sr
]);
455 qemu_log("RSR %d not implemented, ", sr
);
459 static void gen_wsr_lbeg(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
461 gen_helper_wsr_lbeg(s
);
464 static void gen_wsr_lend(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
466 gen_helper_wsr_lend(s
);
469 static void gen_wsr_sar(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
471 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0x3f);
472 if (dc
->sar_m32_5bit
) {
473 tcg_gen_discard_i32(dc
->sar_m32
);
475 dc
->sar_5bit
= false;
476 dc
->sar_m32_5bit
= false;
479 static void gen_wsr_br(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
481 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0xffff);
484 static void gen_wsr_litbase(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
486 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0xfffff001);
487 /* This can change tb->flags, so exit tb */
488 gen_jumpi_check_loop_end(dc
, -1);
491 static void gen_wsr_acchi(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
493 tcg_gen_ext8s_i32(cpu_SR
[sr
], s
);
496 static void gen_wsr_windowbase(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
498 gen_helper_wsr_windowbase(v
);
499 reset_used_window(dc
);
502 static void gen_wsr_windowstart(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
504 tcg_gen_andi_i32(cpu_SR
[sr
], v
, (1 << dc
->config
->nareg
/ 4) - 1);
505 reset_used_window(dc
);
508 static void gen_wsr_ptevaddr(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
510 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0xffc00000);
513 static void gen_wsr_rasid(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
515 gen_helper_wsr_rasid(v
);
516 /* This can change tb->flags, so exit tb */
517 gen_jumpi_check_loop_end(dc
, -1);
520 static void gen_wsr_tlbcfg(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
522 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0x01130000);
525 static void gen_wsr_ibreakenable(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
527 gen_helper_wsr_ibreakenable(v
);
528 gen_jumpi_check_loop_end(dc
, 0);
531 static void gen_wsr_ibreaka(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
533 unsigned id
= sr
- IBREAKA
;
535 if (id
< dc
->config
->nibreak
) {
536 TCGv_i32 tmp
= tcg_const_i32(id
);
537 gen_helper_wsr_ibreaka(tmp
, v
);
539 gen_jumpi_check_loop_end(dc
, 0);
543 static void gen_wsr_dbreaka(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
545 unsigned id
= sr
- DBREAKA
;
547 if (id
< dc
->config
->ndbreak
) {
548 TCGv_i32 tmp
= tcg_const_i32(id
);
549 gen_helper_wsr_dbreaka(tmp
, v
);
554 static void gen_wsr_dbreakc(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
556 unsigned id
= sr
- DBREAKC
;
558 if (id
< dc
->config
->ndbreak
) {
559 TCGv_i32 tmp
= tcg_const_i32(id
);
560 gen_helper_wsr_dbreakc(tmp
, v
);
565 static void gen_wsr_intset(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
567 tcg_gen_andi_i32(cpu_SR
[sr
], v
,
568 dc
->config
->inttype_mask
[INTTYPE_SOFTWARE
]);
569 gen_helper_check_interrupts(cpu_env
);
570 gen_jumpi_check_loop_end(dc
, 0);
573 static void gen_wsr_intclear(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
575 TCGv_i32 tmp
= tcg_temp_new_i32();
577 tcg_gen_andi_i32(tmp
, v
,
578 dc
->config
->inttype_mask
[INTTYPE_EDGE
] |
579 dc
->config
->inttype_mask
[INTTYPE_NMI
] |
580 dc
->config
->inttype_mask
[INTTYPE_SOFTWARE
]);
581 tcg_gen_andc_i32(cpu_SR
[INTSET
], cpu_SR
[INTSET
], tmp
);
583 gen_helper_check_interrupts(cpu_env
);
586 static void gen_wsr_intenable(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
588 tcg_gen_mov_i32(cpu_SR
[sr
], v
);
589 gen_helper_check_interrupts(cpu_env
);
590 gen_jumpi_check_loop_end(dc
, 0);
593 static void gen_wsr_ps(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
595 uint32_t mask
= PS_WOE
| PS_CALLINC
| PS_OWB
|
596 PS_UM
| PS_EXCM
| PS_INTLEVEL
;
598 if (option_enabled(dc
, XTENSA_OPTION_MMU
)) {
601 tcg_gen_andi_i32(cpu_SR
[sr
], v
, mask
);
602 reset_used_window(dc
);
603 gen_helper_check_interrupts(cpu_env
);
604 /* This can change mmu index and tb->flags, so exit tb */
605 gen_jumpi_check_loop_end(dc
, -1);
608 static void gen_wsr_debugcause(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
612 static void gen_wsr_prid(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
616 static void gen_wsr_icount(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
619 tcg_gen_mov_i32(dc
->next_icount
, v
);
621 tcg_gen_mov_i32(cpu_SR
[sr
], v
);
625 static void gen_wsr_icountlevel(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
627 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0xf);
628 /* This can change tb->flags, so exit tb */
629 gen_jumpi_check_loop_end(dc
, -1);
632 static void gen_wsr_ccompare(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
634 uint32_t id
= sr
- CCOMPARE
;
635 if (id
< dc
->config
->nccompare
) {
636 uint32_t int_bit
= 1 << dc
->config
->timerint
[id
];
637 gen_advance_ccount(dc
);
638 tcg_gen_mov_i32(cpu_SR
[sr
], v
);
639 tcg_gen_andi_i32(cpu_SR
[INTSET
], cpu_SR
[INTSET
], ~int_bit
);
640 gen_helper_check_interrupts(cpu_env
);
644 static void gen_wsr(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
646 static void (* const wsr_handler
[256])(DisasContext
*dc
,
647 uint32_t sr
, TCGv_i32 v
) = {
648 [LBEG
] = gen_wsr_lbeg
,
649 [LEND
] = gen_wsr_lend
,
652 [LITBASE
] = gen_wsr_litbase
,
653 [ACCHI
] = gen_wsr_acchi
,
654 [WINDOW_BASE
] = gen_wsr_windowbase
,
655 [WINDOW_START
] = gen_wsr_windowstart
,
656 [PTEVADDR
] = gen_wsr_ptevaddr
,
657 [RASID
] = gen_wsr_rasid
,
658 [ITLBCFG
] = gen_wsr_tlbcfg
,
659 [DTLBCFG
] = gen_wsr_tlbcfg
,
660 [IBREAKENABLE
] = gen_wsr_ibreakenable
,
661 [IBREAKA
] = gen_wsr_ibreaka
,
662 [IBREAKA
+ 1] = gen_wsr_ibreaka
,
663 [DBREAKA
] = gen_wsr_dbreaka
,
664 [DBREAKA
+ 1] = gen_wsr_dbreaka
,
665 [DBREAKC
] = gen_wsr_dbreakc
,
666 [DBREAKC
+ 1] = gen_wsr_dbreakc
,
667 [INTSET
] = gen_wsr_intset
,
668 [INTCLEAR
] = gen_wsr_intclear
,
669 [INTENABLE
] = gen_wsr_intenable
,
671 [DEBUGCAUSE
] = gen_wsr_debugcause
,
672 [PRID
] = gen_wsr_prid
,
673 [ICOUNT
] = gen_wsr_icount
,
674 [ICOUNTLEVEL
] = gen_wsr_icountlevel
,
675 [CCOMPARE
] = gen_wsr_ccompare
,
676 [CCOMPARE
+ 1] = gen_wsr_ccompare
,
677 [CCOMPARE
+ 2] = gen_wsr_ccompare
,
681 if (wsr_handler
[sr
]) {
682 wsr_handler
[sr
](dc
, sr
, s
);
684 tcg_gen_mov_i32(cpu_SR
[sr
], s
);
687 qemu_log("WSR %d not implemented, ", sr
);
691 static void gen_load_store_alignment(DisasContext
*dc
, int shift
,
692 TCGv_i32 addr
, bool no_hw_alignment
)
694 if (!option_enabled(dc
, XTENSA_OPTION_UNALIGNED_EXCEPTION
)) {
695 tcg_gen_andi_i32(addr
, addr
, ~0 << shift
);
696 } else if (option_enabled(dc
, XTENSA_OPTION_HW_ALIGNMENT
) &&
698 int label
= gen_new_label();
699 TCGv_i32 tmp
= tcg_temp_new_i32();
700 tcg_gen_andi_i32(tmp
, addr
, ~(~0 << shift
));
701 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
702 gen_exception_cause_vaddr(dc
, LOAD_STORE_ALIGNMENT_CAUSE
, addr
);
703 gen_set_label(label
);
708 static void gen_waiti(DisasContext
*dc
, uint32_t imm4
)
710 TCGv_i32 pc
= tcg_const_i32(dc
->next_pc
);
711 TCGv_i32 intlevel
= tcg_const_i32(imm4
);
712 gen_advance_ccount(dc
);
713 gen_helper_waiti(pc
, intlevel
);
715 tcg_temp_free(intlevel
);
718 static void gen_window_check1(DisasContext
*dc
, unsigned r1
)
720 if (dc
->tb
->flags
& XTENSA_TBFLAG_EXCM
) {
723 if (option_enabled(dc
, XTENSA_OPTION_WINDOWED_REGISTER
) &&
724 r1
/ 4 > dc
->used_window
) {
725 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
726 TCGv_i32 w
= tcg_const_i32(r1
/ 4);
728 dc
->used_window
= r1
/ 4;
729 gen_advance_ccount(dc
);
730 gen_helper_window_check(pc
, w
);
737 static void gen_window_check2(DisasContext
*dc
, unsigned r1
, unsigned r2
)
739 gen_window_check1(dc
, r1
> r2
? r1
: r2
);
742 static void gen_window_check3(DisasContext
*dc
, unsigned r1
, unsigned r2
,
745 gen_window_check2(dc
, r1
, r2
> r3
? r2
: r3
);
748 static TCGv_i32
gen_mac16_m(TCGv_i32 v
, bool hi
, bool is_unsigned
)
750 TCGv_i32 m
= tcg_temp_new_i32();
753 (is_unsigned
? tcg_gen_shri_i32
: tcg_gen_sari_i32
)(m
, v
, 16);
755 (is_unsigned
? tcg_gen_ext16u_i32
: tcg_gen_ext16s_i32
)(m
, v
);
760 static void disas_xtensa_insn(DisasContext
*dc
)
762 #define HAS_OPTION_BITS(opt) do { \
763 if (!option_bits_enabled(dc, opt)) { \
764 qemu_log("Option is not enabled %s:%d\n", \
765 __FILE__, __LINE__); \
766 goto invalid_opcode; \
770 #define HAS_OPTION(opt) HAS_OPTION_BITS(XTENSA_OPTION_BIT(opt))
772 #define TBD() qemu_log("TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)
773 #define RESERVED() do { \
774 qemu_log("RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \
775 dc->pc, b0, b1, b2, __FILE__, __LINE__); \
776 goto invalid_opcode; \
780 #ifdef TARGET_WORDS_BIGENDIAN
781 #define OP0 (((b0) & 0xf0) >> 4)
782 #define OP1 (((b2) & 0xf0) >> 4)
783 #define OP2 ((b2) & 0xf)
784 #define RRR_R ((b1) & 0xf)
785 #define RRR_S (((b1) & 0xf0) >> 4)
786 #define RRR_T ((b0) & 0xf)
788 #define OP0 (((b0) & 0xf))
789 #define OP1 (((b2) & 0xf))
790 #define OP2 (((b2) & 0xf0) >> 4)
791 #define RRR_R (((b1) & 0xf0) >> 4)
792 #define RRR_S (((b1) & 0xf))
793 #define RRR_T (((b0) & 0xf0) >> 4)
795 #define RRR_X ((RRR_R & 0x4) >> 2)
796 #define RRR_Y ((RRR_T & 0x4) >> 2)
797 #define RRR_W (RRR_R & 0x3)
806 #define RRI8_IMM8 (b2)
807 #define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)
809 #ifdef TARGET_WORDS_BIGENDIAN
810 #define RI16_IMM16 (((b1) << 8) | (b2))
812 #define RI16_IMM16 (((b2) << 8) | (b1))
815 #ifdef TARGET_WORDS_BIGENDIAN
816 #define CALL_N (((b0) & 0xc) >> 2)
817 #define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))
819 #define CALL_N (((b0) & 0x30) >> 4)
820 #define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))
822 #define CALL_OFFSET_SE \
823 (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)
825 #define CALLX_N CALL_N
826 #ifdef TARGET_WORDS_BIGENDIAN
827 #define CALLX_M ((b0) & 0x3)
829 #define CALLX_M (((b0) & 0xc0) >> 6)
831 #define CALLX_S RRR_S
833 #define BRI12_M CALLX_M
834 #define BRI12_S RRR_S
835 #ifdef TARGET_WORDS_BIGENDIAN
836 #define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))
838 #define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))
840 #define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)
842 #define BRI8_M BRI12_M
843 #define BRI8_R RRI8_R
844 #define BRI8_S RRI8_S
845 #define BRI8_IMM8 RRI8_IMM8
846 #define BRI8_IMM8_SE RRI8_IMM8_SE
850 uint8_t b0
= ldub_code(dc
->pc
);
851 uint8_t b1
= ldub_code(dc
->pc
+ 1);
854 static const uint32_t B4CONST
[] = {
855 0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
858 static const uint32_t B4CONSTU
[] = {
859 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
863 dc
->next_pc
= dc
->pc
+ 2;
864 HAS_OPTION(XTENSA_OPTION_CODE_DENSITY
);
866 dc
->next_pc
= dc
->pc
+ 3;
867 b2
= ldub_code(dc
->pc
+ 2);
876 if ((RRR_R
& 0xc) == 0x8) {
877 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
884 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
895 gen_window_check1(dc
, CALLX_S
);
896 gen_jump(dc
, cpu_R
[CALLX_S
]);
900 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
902 TCGv_i32 tmp
= tcg_const_i32(dc
->pc
);
903 gen_advance_ccount(dc
);
904 gen_helper_retw(tmp
, tmp
);
917 gen_window_check2(dc
, CALLX_S
, CALLX_N
<< 2);
921 TCGv_i32 tmp
= tcg_temp_new_i32();
922 tcg_gen_mov_i32(tmp
, cpu_R
[CALLX_S
]);
923 tcg_gen_movi_i32(cpu_R
[0], dc
->next_pc
);
932 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
934 TCGv_i32 tmp
= tcg_temp_new_i32();
936 tcg_gen_mov_i32(tmp
, cpu_R
[CALLX_S
]);
937 gen_callw(dc
, CALLX_N
, tmp
);
947 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
948 gen_window_check2(dc
, RRR_T
, RRR_S
);
950 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
951 gen_advance_ccount(dc
);
952 gen_helper_movsp(pc
);
953 tcg_gen_mov_i32(cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
973 HAS_OPTION(XTENSA_OPTION_EXCEPTION
);
985 default: /*reserved*/
994 HAS_OPTION(XTENSA_OPTION_EXCEPTION
);
997 gen_check_privilege(dc
);
998 tcg_gen_andi_i32(cpu_SR
[PS
], cpu_SR
[PS
], ~PS_EXCM
);
999 gen_helper_check_interrupts(cpu_env
);
1000 gen_jump(dc
, cpu_SR
[EPC1
]);
1008 gen_check_privilege(dc
);
1009 gen_jump(dc
, cpu_SR
[
1010 dc
->config
->ndepc
? DEPC
: EPC1
]);
1015 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1016 gen_check_privilege(dc
);
1018 TCGv_i32 tmp
= tcg_const_i32(1);
1021 cpu_SR
[PS
], cpu_SR
[PS
], ~PS_EXCM
);
1022 tcg_gen_shl_i32(tmp
, tmp
, cpu_SR
[WINDOW_BASE
]);
1025 tcg_gen_andc_i32(cpu_SR
[WINDOW_START
],
1026 cpu_SR
[WINDOW_START
], tmp
);
1028 tcg_gen_or_i32(cpu_SR
[WINDOW_START
],
1029 cpu_SR
[WINDOW_START
], tmp
);
1032 gen_helper_restore_owb();
1033 gen_helper_check_interrupts(cpu_env
);
1034 gen_jump(dc
, cpu_SR
[EPC1
]);
1040 default: /*reserved*/
1047 HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
);
1048 if (RRR_S
>= 2 && RRR_S
<= dc
->config
->nlevel
) {
1049 gen_check_privilege(dc
);
1050 tcg_gen_mov_i32(cpu_SR
[PS
],
1051 cpu_SR
[EPS2
+ RRR_S
- 2]);
1052 gen_helper_check_interrupts(cpu_env
);
1053 gen_jump(dc
, cpu_SR
[EPC1
+ RRR_S
- 1]);
1055 qemu_log("RFI %d is illegal\n", RRR_S
);
1056 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
1064 default: /*reserved*/
1072 HAS_OPTION(XTENSA_OPTION_DEBUG
);
1074 gen_debug_exception(dc
, DEBUGCAUSE_BI
);
1078 case 5: /*SYSCALLx*/
1079 HAS_OPTION(XTENSA_OPTION_EXCEPTION
);
1081 case 0: /*SYSCALLx*/
1082 gen_exception_cause(dc
, SYSCALL_CAUSE
);
1086 if (semihosting_enabled
) {
1087 gen_check_privilege(dc
);
1088 gen_helper_simcall(cpu_env
);
1090 qemu_log("SIMCALL but semihosting is disabled\n");
1091 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
1102 HAS_OPTION(XTENSA_OPTION_INTERRUPT
);
1103 gen_check_privilege(dc
);
1104 gen_window_check1(dc
, RRR_T
);
1105 tcg_gen_mov_i32(cpu_R
[RRR_T
], cpu_SR
[PS
]);
1106 tcg_gen_andi_i32(cpu_SR
[PS
], cpu_SR
[PS
], ~PS_INTLEVEL
);
1107 tcg_gen_ori_i32(cpu_SR
[PS
], cpu_SR
[PS
], RRR_S
);
1108 gen_helper_check_interrupts(cpu_env
);
1109 gen_jumpi_check_loop_end(dc
, 0);
1113 HAS_OPTION(XTENSA_OPTION_INTERRUPT
);
1114 gen_check_privilege(dc
);
1115 gen_waiti(dc
, RRR_S
);
1122 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
1124 const unsigned shift
= (RRR_R
& 2) ? 8 : 4;
1125 TCGv_i32 mask
= tcg_const_i32(
1126 ((1 << shift
) - 1) << RRR_S
);
1127 TCGv_i32 tmp
= tcg_temp_new_i32();
1129 tcg_gen_and_i32(tmp
, cpu_SR
[BR
], mask
);
1130 if (RRR_R
& 1) { /*ALL*/
1131 tcg_gen_addi_i32(tmp
, tmp
, 1 << RRR_S
);
1133 tcg_gen_add_i32(tmp
, tmp
, mask
);
1135 tcg_gen_shri_i32(tmp
, tmp
, RRR_S
+ shift
);
1136 tcg_gen_deposit_i32(cpu_SR
[BR
], cpu_SR
[BR
],
1138 tcg_temp_free(mask
);
1143 default: /*reserved*/
1151 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1152 tcg_gen_and_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1156 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1157 tcg_gen_or_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1161 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1162 tcg_gen_xor_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1168 gen_window_check1(dc
, RRR_S
);
1169 gen_right_shift_sar(dc
, cpu_R
[RRR_S
]);
1173 gen_window_check1(dc
, RRR_S
);
1174 gen_left_shift_sar(dc
, cpu_R
[RRR_S
]);
1178 gen_window_check1(dc
, RRR_S
);
1180 TCGv_i32 tmp
= tcg_temp_new_i32();
1181 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], 3);
1182 gen_right_shift_sar(dc
, tmp
);
1188 gen_window_check1(dc
, RRR_S
);
1190 TCGv_i32 tmp
= tcg_temp_new_i32();
1191 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], 3);
1192 gen_left_shift_sar(dc
, tmp
);
1199 TCGv_i32 tmp
= tcg_const_i32(
1200 RRR_S
| ((RRR_T
& 1) << 4));
1201 gen_right_shift_sar(dc
, tmp
);
1215 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1216 gen_check_privilege(dc
);
1218 TCGv_i32 tmp
= tcg_const_i32(
1219 RRR_T
| ((RRR_T
& 8) ? 0xfffffff0 : 0));
1220 gen_helper_rotw(tmp
);
1222 reset_used_window(dc
);
1227 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA
);
1228 gen_window_check2(dc
, RRR_S
, RRR_T
);
1229 gen_helper_nsa(cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
1233 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA
);
1234 gen_window_check2(dc
, RRR_S
, RRR_T
);
1235 gen_helper_nsau(cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
1238 default: /*reserved*/
1246 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU
) |
1247 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION
) |
1248 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION
));
1249 gen_check_privilege(dc
);
1250 gen_window_check2(dc
, RRR_S
, RRR_T
);
1252 TCGv_i32 dtlb
= tcg_const_i32((RRR_R
& 8) != 0);
1254 switch (RRR_R
& 7) {
1255 case 3: /*RITLB0*/ /*RDTLB0*/
1256 gen_helper_rtlb0(cpu_R
[RRR_T
], cpu_R
[RRR_S
], dtlb
);
1259 case 4: /*IITLB*/ /*IDTLB*/
1260 gen_helper_itlb(cpu_R
[RRR_S
], dtlb
);
1261 /* This could change memory mapping, so exit tb */
1262 gen_jumpi_check_loop_end(dc
, -1);
1265 case 5: /*PITLB*/ /*PDTLB*/
1266 tcg_gen_movi_i32(cpu_pc
, dc
->pc
);
1267 gen_helper_ptlb(cpu_R
[RRR_T
], cpu_R
[RRR_S
], dtlb
);
1270 case 6: /*WITLB*/ /*WDTLB*/
1271 gen_helper_wtlb(cpu_R
[RRR_T
], cpu_R
[RRR_S
], dtlb
);
1272 /* This could change memory mapping, so exit tb */
1273 gen_jumpi_check_loop_end(dc
, -1);
1276 case 7: /*RITLB1*/ /*RDTLB1*/
1277 gen_helper_rtlb1(cpu_R
[RRR_T
], cpu_R
[RRR_S
], dtlb
);
1281 tcg_temp_free(dtlb
);
1285 tcg_temp_free(dtlb
);
1290 gen_window_check2(dc
, RRR_R
, RRR_T
);
1293 tcg_gen_neg_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
1298 int label
= gen_new_label();
1299 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
1300 tcg_gen_brcondi_i32(
1301 TCG_COND_GE
, cpu_R
[RRR_R
], 0, label
);
1302 tcg_gen_neg_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
1303 gen_set_label(label
);
1307 default: /*reserved*/
1313 case 7: /*reserved*/
1318 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1319 tcg_gen_add_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1325 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1327 TCGv_i32 tmp
= tcg_temp_new_i32();
1328 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], OP2
- 8);
1329 tcg_gen_add_i32(cpu_R
[RRR_R
], tmp
, cpu_R
[RRR_T
]);
1335 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1336 tcg_gen_sub_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1342 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1344 TCGv_i32 tmp
= tcg_temp_new_i32();
1345 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], OP2
- 12);
1346 tcg_gen_sub_i32(cpu_R
[RRR_R
], tmp
, cpu_R
[RRR_T
]);
1357 gen_window_check2(dc
, RRR_R
, RRR_S
);
1358 tcg_gen_shli_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
],
1359 32 - (RRR_T
| ((OP2
& 1) << 4)));
1364 gen_window_check2(dc
, RRR_R
, RRR_T
);
1365 tcg_gen_sari_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
],
1366 RRR_S
| ((OP2
& 1) << 4));
1370 gen_window_check2(dc
, RRR_R
, RRR_T
);
1371 tcg_gen_shri_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
], RRR_S
);
1376 TCGv_i32 tmp
= tcg_temp_new_i32();
1378 gen_check_privilege(dc
);
1380 gen_window_check1(dc
, RRR_T
);
1381 tcg_gen_mov_i32(tmp
, cpu_R
[RRR_T
]);
1382 gen_rsr(dc
, cpu_R
[RRR_T
], RSR_SR
);
1383 gen_wsr(dc
, RSR_SR
, tmp
);
1385 if (!sregnames
[RSR_SR
]) {
1392 * Note: 64 bit ops are used here solely because SAR values
1395 #define gen_shift_reg(cmd, reg) do { \
1396 TCGv_i64 tmp = tcg_temp_new_i64(); \
1397 tcg_gen_extu_i32_i64(tmp, reg); \
1398 tcg_gen_##cmd##_i64(v, v, tmp); \
1399 tcg_gen_trunc_i64_i32(cpu_R[RRR_R], v); \
1400 tcg_temp_free_i64(v); \
1401 tcg_temp_free_i64(tmp); \
1404 #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
1407 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1409 TCGv_i64 v
= tcg_temp_new_i64();
1410 tcg_gen_concat_i32_i64(v
, cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
1416 gen_window_check2(dc
, RRR_R
, RRR_T
);
1418 tcg_gen_shr_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
], cpu_SR
[SAR
]);
1420 TCGv_i64 v
= tcg_temp_new_i64();
1421 tcg_gen_extu_i32_i64(v
, cpu_R
[RRR_T
]);
1427 gen_window_check2(dc
, RRR_R
, RRR_S
);
1428 if (dc
->sar_m32_5bit
) {
1429 tcg_gen_shl_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], dc
->sar_m32
);
1431 TCGv_i64 v
= tcg_temp_new_i64();
1432 TCGv_i32 s
= tcg_const_i32(32);
1433 tcg_gen_sub_i32(s
, s
, cpu_SR
[SAR
]);
1434 tcg_gen_andi_i32(s
, s
, 0x3f);
1435 tcg_gen_extu_i32_i64(v
, cpu_R
[RRR_S
]);
1436 gen_shift_reg(shl
, s
);
1442 gen_window_check2(dc
, RRR_R
, RRR_T
);
1444 tcg_gen_sar_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
], cpu_SR
[SAR
]);
1446 TCGv_i64 v
= tcg_temp_new_i64();
1447 tcg_gen_ext_i32_i64(v
, cpu_R
[RRR_T
]);
1452 #undef gen_shift_reg
1455 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL
);
1456 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1458 TCGv_i32 v1
= tcg_temp_new_i32();
1459 TCGv_i32 v2
= tcg_temp_new_i32();
1460 tcg_gen_ext16u_i32(v1
, cpu_R
[RRR_S
]);
1461 tcg_gen_ext16u_i32(v2
, cpu_R
[RRR_T
]);
1462 tcg_gen_mul_i32(cpu_R
[RRR_R
], v1
, v2
);
1469 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL
);
1470 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1472 TCGv_i32 v1
= tcg_temp_new_i32();
1473 TCGv_i32 v2
= tcg_temp_new_i32();
1474 tcg_gen_ext16s_i32(v1
, cpu_R
[RRR_S
]);
1475 tcg_gen_ext16s_i32(v2
, cpu_R
[RRR_T
]);
1476 tcg_gen_mul_i32(cpu_R
[RRR_R
], v1
, v2
);
1482 default: /*reserved*/
1490 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1494 HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV
);
1495 int label
= gen_new_label();
1496 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[RRR_T
], 0, label
);
1497 gen_exception_cause(dc
, INTEGER_DIVIDE_BY_ZERO_CAUSE
);
1498 gen_set_label(label
);
1502 #define BOOLEAN_LOGIC(fn, r, s, t) \
1504 HAS_OPTION(XTENSA_OPTION_BOOLEAN); \
1505 TCGv_i32 tmp1 = tcg_temp_new_i32(); \
1506 TCGv_i32 tmp2 = tcg_temp_new_i32(); \
1508 tcg_gen_shri_i32(tmp1, cpu_SR[BR], s); \
1509 tcg_gen_shri_i32(tmp2, cpu_SR[BR], t); \
1510 tcg_gen_##fn##_i32(tmp1, tmp1, tmp2); \
1511 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, r, 1); \
1512 tcg_temp_free(tmp1); \
1513 tcg_temp_free(tmp2); \
1517 BOOLEAN_LOGIC(and, RRR_R
, RRR_S
, RRR_T
);
1521 BOOLEAN_LOGIC(andc
, RRR_R
, RRR_S
, RRR_T
);
1525 BOOLEAN_LOGIC(or, RRR_R
, RRR_S
, RRR_T
);
1529 BOOLEAN_LOGIC(orc
, RRR_R
, RRR_S
, RRR_T
);
1533 BOOLEAN_LOGIC(xor, RRR_R
, RRR_S
, RRR_T
);
1536 #undef BOOLEAN_LOGIC
1539 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL
);
1540 tcg_gen_mul_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1545 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL_HIGH
);
1547 TCGv_i64 r
= tcg_temp_new_i64();
1548 TCGv_i64 s
= tcg_temp_new_i64();
1549 TCGv_i64 t
= tcg_temp_new_i64();
1552 tcg_gen_extu_i32_i64(s
, cpu_R
[RRR_S
]);
1553 tcg_gen_extu_i32_i64(t
, cpu_R
[RRR_T
]);
1555 tcg_gen_ext_i32_i64(s
, cpu_R
[RRR_S
]);
1556 tcg_gen_ext_i32_i64(t
, cpu_R
[RRR_T
]);
1558 tcg_gen_mul_i64(r
, s
, t
);
1559 tcg_gen_shri_i64(r
, r
, 32);
1560 tcg_gen_trunc_i64_i32(cpu_R
[RRR_R
], r
);
1562 tcg_temp_free_i64(r
);
1563 tcg_temp_free_i64(s
);
1564 tcg_temp_free_i64(t
);
1569 tcg_gen_divu_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1575 int label1
= gen_new_label();
1576 int label2
= gen_new_label();
1578 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[RRR_S
], 0x80000000,
1580 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[RRR_T
], 0xffffffff,
1582 tcg_gen_movi_i32(cpu_R
[RRR_R
],
1583 OP2
== 13 ? 0x80000000 : 0);
1585 gen_set_label(label1
);
1587 tcg_gen_div_i32(cpu_R
[RRR_R
],
1588 cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1590 tcg_gen_rem_i32(cpu_R
[RRR_R
],
1591 cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1593 gen_set_label(label2
);
1598 tcg_gen_remu_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1601 default: /*reserved*/
1611 gen_check_privilege(dc
);
1613 gen_window_check1(dc
, RRR_T
);
1614 gen_rsr(dc
, cpu_R
[RRR_T
], RSR_SR
);
1615 if (!sregnames
[RSR_SR
]) {
1622 gen_check_privilege(dc
);
1624 gen_window_check1(dc
, RRR_T
);
1625 gen_wsr(dc
, RSR_SR
, cpu_R
[RRR_T
]);
1626 if (!sregnames
[RSR_SR
]) {
1632 HAS_OPTION(XTENSA_OPTION_MISC_OP_SEXT
);
1633 gen_window_check2(dc
, RRR_R
, RRR_S
);
1635 int shift
= 24 - RRR_T
;
1638 tcg_gen_ext8s_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1639 } else if (shift
== 16) {
1640 tcg_gen_ext16s_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1642 TCGv_i32 tmp
= tcg_temp_new_i32();
1643 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], shift
);
1644 tcg_gen_sari_i32(cpu_R
[RRR_R
], tmp
, shift
);
1651 HAS_OPTION(XTENSA_OPTION_MISC_OP_CLAMPS
);
1652 gen_window_check2(dc
, RRR_R
, RRR_S
);
1654 TCGv_i32 tmp1
= tcg_temp_new_i32();
1655 TCGv_i32 tmp2
= tcg_temp_new_i32();
1656 int label
= gen_new_label();
1658 tcg_gen_sari_i32(tmp1
, cpu_R
[RRR_S
], 24 - RRR_T
);
1659 tcg_gen_xor_i32(tmp2
, tmp1
, cpu_R
[RRR_S
]);
1660 tcg_gen_andi_i32(tmp2
, tmp2
, 0xffffffff << (RRR_T
+ 7));
1661 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1662 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp2
, 0, label
);
1664 tcg_gen_sari_i32(tmp1
, cpu_R
[RRR_S
], 31);
1665 tcg_gen_xori_i32(cpu_R
[RRR_R
], tmp1
,
1666 0xffffffff >> (25 - RRR_T
));
1668 gen_set_label(label
);
1670 tcg_temp_free(tmp1
);
1671 tcg_temp_free(tmp2
);
1679 HAS_OPTION(XTENSA_OPTION_MISC_OP_MINMAX
);
1680 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1682 static const TCGCond cond
[] = {
1688 int label
= gen_new_label();
1690 if (RRR_R
!= RRR_T
) {
1691 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1692 tcg_gen_brcond_i32(cond
[OP2
- 4],
1693 cpu_R
[RRR_S
], cpu_R
[RRR_T
], label
);
1694 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
1696 tcg_gen_brcond_i32(cond
[OP2
- 4],
1697 cpu_R
[RRR_T
], cpu_R
[RRR_S
], label
);
1698 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1700 gen_set_label(label
);
1708 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1710 static const TCGCond cond
[] = {
1716 int label
= gen_new_label();
1717 tcg_gen_brcondi_i32(cond
[OP2
- 8], cpu_R
[RRR_T
], 0, label
);
1718 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1719 gen_set_label(label
);
1725 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
1726 gen_window_check2(dc
, RRR_R
, RRR_S
);
1728 int label
= gen_new_label();
1729 TCGv_i32 tmp
= tcg_temp_new_i32();
1731 tcg_gen_andi_i32(tmp
, cpu_SR
[BR
], 1 << RRR_T
);
1732 tcg_gen_brcondi_i32(
1733 OP2
& 1 ? TCG_COND_EQ
: TCG_COND_NE
,
1735 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1736 gen_set_label(label
);
1742 gen_window_check1(dc
, RRR_R
);
1744 int st
= (RRR_S
<< 4) + RRR_T
;
1745 if (uregnames
[st
]) {
1746 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_UR
[st
]);
1748 qemu_log("RUR %d not implemented, ", st
);
1755 gen_window_check1(dc
, RRR_T
);
1757 if (uregnames
[RSR_SR
]) {
1758 tcg_gen_mov_i32(cpu_UR
[RSR_SR
], cpu_R
[RRR_T
]);
1760 qemu_log("WUR %d not implemented, ", RSR_SR
);
1771 gen_window_check2(dc
, RRR_R
, RRR_T
);
1773 int shiftimm
= RRR_S
| (OP1
<< 4);
1774 int maskimm
= (1 << (OP2
+ 1)) - 1;
1776 TCGv_i32 tmp
= tcg_temp_new_i32();
1777 tcg_gen_shri_i32(tmp
, cpu_R
[RRR_T
], shiftimm
);
1778 tcg_gen_andi_i32(cpu_R
[RRR_R
], tmp
, maskimm
);
1792 HAS_OPTION(XTENSA_OPTION_COPROCESSOR
);
1797 gen_window_check2(dc
, RRR_S
, RRR_T
);
1800 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1801 gen_check_privilege(dc
);
1803 TCGv_i32 addr
= tcg_temp_new_i32();
1804 tcg_gen_addi_i32(addr
, cpu_R
[RRR_S
],
1805 (0xffffffc0 | (RRR_R
<< 2)));
1806 tcg_gen_qemu_ld32u(cpu_R
[RRR_T
], addr
, dc
->ring
);
1807 tcg_temp_free(addr
);
1812 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1813 gen_check_privilege(dc
);
1815 TCGv_i32 addr
= tcg_temp_new_i32();
1816 tcg_gen_addi_i32(addr
, cpu_R
[RRR_S
],
1817 (0xffffffc0 | (RRR_R
<< 2)));
1818 tcg_gen_qemu_st32(cpu_R
[RRR_T
], addr
, dc
->ring
);
1819 tcg_temp_free(addr
);
1830 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR
);
1835 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR
);
1839 default: /*reserved*/
1846 gen_window_check1(dc
, RRR_T
);
1848 TCGv_i32 tmp
= tcg_const_i32(
1849 ((dc
->tb
->flags
& XTENSA_TBFLAG_LITBASE
) ?
1850 0 : ((dc
->pc
+ 3) & ~3)) +
1851 (0xfffc0000 | (RI16_IMM16
<< 2)));
1853 if (dc
->tb
->flags
& XTENSA_TBFLAG_LITBASE
) {
1854 tcg_gen_add_i32(tmp
, tmp
, dc
->litbase
);
1856 tcg_gen_qemu_ld32u(cpu_R
[RRR_T
], tmp
, dc
->cring
);
1862 #define gen_load_store(type, shift) do { \
1863 TCGv_i32 addr = tcg_temp_new_i32(); \
1864 gen_window_check2(dc, RRI8_S, RRI8_T); \
1865 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \
1867 gen_load_store_alignment(dc, shift, addr, false); \
1869 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
1870 tcg_temp_free(addr); \
1875 gen_load_store(ld8u
, 0);
1879 gen_load_store(ld16u
, 1);
1883 gen_load_store(ld32u
, 2);
1887 gen_load_store(st8
, 0);
1891 gen_load_store(st16
, 1);
1895 gen_load_store(st32
, 2);
1900 HAS_OPTION(XTENSA_OPTION_DCACHE
);
1931 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK
);
1935 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK
);
1939 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK
);
1943 HAS_OPTION(XTENSA_OPTION_DCACHE
);
1947 HAS_OPTION(XTENSA_OPTION_DCACHE
);
1950 default: /*reserved*/
1958 HAS_OPTION(XTENSA_OPTION_ICACHE
);
1964 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK
);
1968 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK
);
1972 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK
);
1975 default: /*reserved*/
1982 HAS_OPTION(XTENSA_OPTION_ICACHE
);
1986 HAS_OPTION(XTENSA_OPTION_ICACHE
);
1989 default: /*reserved*/
1996 gen_load_store(ld16s
, 1);
1998 #undef gen_load_store
2001 gen_window_check1(dc
, RRI8_T
);
2002 tcg_gen_movi_i32(cpu_R
[RRI8_T
],
2003 RRI8_IMM8
| (RRI8_S
<< 8) |
2004 ((RRI8_S
& 0x8) ? 0xfffff000 : 0));
2007 #define gen_load_store_no_hw_align(type) do { \
2008 TCGv_i32 addr = tcg_temp_local_new_i32(); \
2009 gen_window_check2(dc, RRI8_S, RRI8_T); \
2010 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); \
2011 gen_load_store_alignment(dc, 2, addr, true); \
2012 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
2013 tcg_temp_free(addr); \
2017 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO
);
2018 gen_load_store_no_hw_align(ld32u
); /*TODO acquire?*/
2022 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2023 tcg_gen_addi_i32(cpu_R
[RRI8_T
], cpu_R
[RRI8_S
], RRI8_IMM8_SE
);
2027 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2028 tcg_gen_addi_i32(cpu_R
[RRI8_T
], cpu_R
[RRI8_S
], RRI8_IMM8_SE
<< 8);
2031 case 14: /*S32C1Iy*/
2032 HAS_OPTION(XTENSA_OPTION_CONDITIONAL_STORE
);
2033 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2035 int label
= gen_new_label();
2036 TCGv_i32 tmp
= tcg_temp_local_new_i32();
2037 TCGv_i32 addr
= tcg_temp_local_new_i32();
2039 tcg_gen_mov_i32(tmp
, cpu_R
[RRI8_T
]);
2040 tcg_gen_addi_i32(addr
, cpu_R
[RRI8_S
], RRI8_IMM8
<< 2);
2041 gen_load_store_alignment(dc
, 2, addr
, true);
2042 tcg_gen_qemu_ld32u(cpu_R
[RRI8_T
], addr
, dc
->cring
);
2043 tcg_gen_brcond_i32(TCG_COND_NE
, cpu_R
[RRI8_T
],
2044 cpu_SR
[SCOMPARE1
], label
);
2046 tcg_gen_qemu_st32(tmp
, addr
, dc
->cring
);
2048 gen_set_label(label
);
2049 tcg_temp_free(addr
);
2055 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO
);
2056 gen_load_store_no_hw_align(st32
); /*TODO release?*/
2058 #undef gen_load_store_no_hw_align
2060 default: /*reserved*/
2067 HAS_OPTION(XTENSA_OPTION_COPROCESSOR
);
2072 HAS_OPTION(XTENSA_OPTION_MAC16
);
2081 bool is_m1_sr
= (OP2
& 0x3) == 2;
2082 bool is_m2_sr
= (OP2
& 0xc) == 0;
2083 uint32_t ld_offset
= 0;
2090 case 0: /*MACI?/MACC?*/
2092 ld_offset
= (OP2
& 1) ? -4 : 4;
2094 if (OP2
>= 8) { /*MACI/MACC*/
2095 if (OP1
== 0) { /*LDINC/LDDEC*/
2100 } else if (op
!= MAC16_MULA
) { /*MULA.*.*.LDINC/LDDEC*/
2105 case 2: /*MACD?/MACA?*/
2106 if (op
== MAC16_UMUL
&& OP2
!= 7) { /*UMUL only in MACAA*/
2112 if (op
!= MAC16_NONE
) {
2114 gen_window_check1(dc
, RRR_S
);
2117 gen_window_check1(dc
, RRR_T
);
2122 TCGv_i32 vaddr
= tcg_temp_new_i32();
2123 TCGv_i32 mem32
= tcg_temp_new_i32();
2126 gen_window_check1(dc
, RRR_S
);
2127 tcg_gen_addi_i32(vaddr
, cpu_R
[RRR_S
], ld_offset
);
2128 gen_load_store_alignment(dc
, 2, vaddr
, false);
2129 tcg_gen_qemu_ld32u(mem32
, vaddr
, dc
->cring
);
2131 if (op
!= MAC16_NONE
) {
2132 TCGv_i32 m1
= gen_mac16_m(
2133 is_m1_sr
? cpu_SR
[MR
+ RRR_X
] : cpu_R
[RRR_S
],
2134 OP1
& 1, op
== MAC16_UMUL
);
2135 TCGv_i32 m2
= gen_mac16_m(
2136 is_m2_sr
? cpu_SR
[MR
+ 2 + RRR_Y
] : cpu_R
[RRR_T
],
2137 OP1
& 2, op
== MAC16_UMUL
);
2139 if (op
== MAC16_MUL
|| op
== MAC16_UMUL
) {
2140 tcg_gen_mul_i32(cpu_SR
[ACCLO
], m1
, m2
);
2141 if (op
== MAC16_UMUL
) {
2142 tcg_gen_movi_i32(cpu_SR
[ACCHI
], 0);
2144 tcg_gen_sari_i32(cpu_SR
[ACCHI
], cpu_SR
[ACCLO
], 31);
2147 TCGv_i32 res
= tcg_temp_new_i32();
2148 TCGv_i64 res64
= tcg_temp_new_i64();
2149 TCGv_i64 tmp
= tcg_temp_new_i64();
2151 tcg_gen_mul_i32(res
, m1
, m2
);
2152 tcg_gen_ext_i32_i64(res64
, res
);
2153 tcg_gen_concat_i32_i64(tmp
,
2154 cpu_SR
[ACCLO
], cpu_SR
[ACCHI
]);
2155 if (op
== MAC16_MULA
) {
2156 tcg_gen_add_i64(tmp
, tmp
, res64
);
2158 tcg_gen_sub_i64(tmp
, tmp
, res64
);
2160 tcg_gen_trunc_i64_i32(cpu_SR
[ACCLO
], tmp
);
2161 tcg_gen_shri_i64(tmp
, tmp
, 32);
2162 tcg_gen_trunc_i64_i32(cpu_SR
[ACCHI
], tmp
);
2163 tcg_gen_ext8s_i32(cpu_SR
[ACCHI
], cpu_SR
[ACCHI
]);
2166 tcg_temp_free_i64(res64
);
2167 tcg_temp_free_i64(tmp
);
2173 tcg_gen_mov_i32(cpu_R
[RRR_S
], vaddr
);
2174 tcg_gen_mov_i32(cpu_SR
[MR
+ RRR_W
], mem32
);
2176 tcg_temp_free(vaddr
);
2177 tcg_temp_free(mem32
);
2185 tcg_gen_movi_i32(cpu_R
[0], dc
->next_pc
);
2186 gen_jumpi(dc
, (dc
->pc
& ~3) + (CALL_OFFSET_SE
<< 2) + 4, 0);
2192 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
2193 gen_window_check1(dc
, CALL_N
<< 2);
2194 gen_callwi(dc
, CALL_N
,
2195 (dc
->pc
& ~3) + (CALL_OFFSET_SE
<< 2) + 4, 0);
2203 gen_jumpi(dc
, dc
->pc
+ 4 + CALL_OFFSET_SE
, 0);
2207 gen_window_check1(dc
, BRI12_S
);
2209 static const TCGCond cond
[] = {
2210 TCG_COND_EQ
, /*BEQZ*/
2211 TCG_COND_NE
, /*BNEZ*/
2212 TCG_COND_LT
, /*BLTZ*/
2213 TCG_COND_GE
, /*BGEZ*/
2216 gen_brcondi(dc
, cond
[BRI12_M
& 3], cpu_R
[BRI12_S
], 0,
2217 4 + BRI12_IMM12_SE
);
2222 gen_window_check1(dc
, BRI8_S
);
2224 static const TCGCond cond
[] = {
2225 TCG_COND_EQ
, /*BEQI*/
2226 TCG_COND_NE
, /*BNEI*/
2227 TCG_COND_LT
, /*BLTI*/
2228 TCG_COND_GE
, /*BGEI*/
2231 gen_brcondi(dc
, cond
[BRI8_M
& 3],
2232 cpu_R
[BRI8_S
], B4CONST
[BRI8_R
], 4 + BRI8_IMM8_SE
);
2239 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
2241 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
2242 TCGv_i32 s
= tcg_const_i32(BRI12_S
);
2243 TCGv_i32 imm
= tcg_const_i32(BRI12_IMM12
);
2244 gen_advance_ccount(dc
);
2245 gen_helper_entry(pc
, s
, imm
);
2249 reset_used_window(dc
);
2257 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
2259 TCGv_i32 tmp
= tcg_temp_new_i32();
2260 tcg_gen_andi_i32(tmp
, cpu_SR
[BR
], 1 << RRI8_S
);
2262 BRI8_R
== 1 ? TCG_COND_NE
: TCG_COND_EQ
,
2263 tmp
, 0, 4 + RRI8_IMM8_SE
);
2270 case 10: /*LOOPGTZ*/
2271 HAS_OPTION(XTENSA_OPTION_LOOP
);
2272 gen_window_check1(dc
, RRI8_S
);
2274 uint32_t lend
= dc
->pc
+ RRI8_IMM8
+ 4;
2275 TCGv_i32 tmp
= tcg_const_i32(lend
);
2277 tcg_gen_subi_i32(cpu_SR
[LCOUNT
], cpu_R
[RRI8_S
], 1);
2278 tcg_gen_movi_i32(cpu_SR
[LBEG
], dc
->next_pc
);
2279 gen_wsr_lend(dc
, LEND
, tmp
);
2283 int label
= gen_new_label();
2284 tcg_gen_brcondi_i32(
2285 BRI8_R
== 9 ? TCG_COND_NE
: TCG_COND_GT
,
2286 cpu_R
[RRI8_S
], 0, label
);
2287 gen_jumpi(dc
, lend
, 1);
2288 gen_set_label(label
);
2291 gen_jumpi(dc
, dc
->next_pc
, 0);
2295 default: /*reserved*/
2304 gen_window_check1(dc
, BRI8_S
);
2305 gen_brcondi(dc
, BRI8_M
== 2 ? TCG_COND_LTU
: TCG_COND_GEU
,
2306 cpu_R
[BRI8_S
], B4CONSTU
[BRI8_R
], 4 + BRI8_IMM8_SE
);
2316 TCGCond eq_ne
= (RRI8_R
& 8) ? TCG_COND_NE
: TCG_COND_EQ
;
2318 switch (RRI8_R
& 7) {
2319 case 0: /*BNONE*/ /*BANY*/
2320 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2322 TCGv_i32 tmp
= tcg_temp_new_i32();
2323 tcg_gen_and_i32(tmp
, cpu_R
[RRI8_S
], cpu_R
[RRI8_T
]);
2324 gen_brcondi(dc
, eq_ne
, tmp
, 0, 4 + RRI8_IMM8_SE
);
2329 case 1: /*BEQ*/ /*BNE*/
2330 case 2: /*BLT*/ /*BGE*/
2331 case 3: /*BLTU*/ /*BGEU*/
2332 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2334 static const TCGCond cond
[] = {
2340 [11] = TCG_COND_GEU
,
2342 gen_brcond(dc
, cond
[RRI8_R
], cpu_R
[RRI8_S
], cpu_R
[RRI8_T
],
2347 case 4: /*BALL*/ /*BNALL*/
2348 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2350 TCGv_i32 tmp
= tcg_temp_new_i32();
2351 tcg_gen_and_i32(tmp
, cpu_R
[RRI8_S
], cpu_R
[RRI8_T
]);
2352 gen_brcond(dc
, eq_ne
, tmp
, cpu_R
[RRI8_T
],
2358 case 5: /*BBC*/ /*BBS*/
2359 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2361 TCGv_i32 bit
= tcg_const_i32(1);
2362 TCGv_i32 tmp
= tcg_temp_new_i32();
2363 tcg_gen_andi_i32(tmp
, cpu_R
[RRI8_T
], 0x1f);
2364 tcg_gen_shl_i32(bit
, bit
, tmp
);
2365 tcg_gen_and_i32(tmp
, cpu_R
[RRI8_S
], bit
);
2366 gen_brcondi(dc
, eq_ne
, tmp
, 0, 4 + RRI8_IMM8_SE
);
2372 case 6: /*BBCI*/ /*BBSI*/
2374 gen_window_check1(dc
, RRI8_S
);
2376 TCGv_i32 tmp
= tcg_temp_new_i32();
2377 tcg_gen_andi_i32(tmp
, cpu_R
[RRI8_S
],
2378 1 << (((RRI8_R
& 1) << 4) | RRI8_T
));
2379 gen_brcondi(dc
, eq_ne
, tmp
, 0, 4 + RRI8_IMM8_SE
);
2388 #define gen_narrow_load_store(type) do { \
2389 TCGv_i32 addr = tcg_temp_new_i32(); \
2390 gen_window_check2(dc, RRRN_S, RRRN_T); \
2391 tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
2392 gen_load_store_alignment(dc, 2, addr, false); \
2393 tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, dc->cring); \
2394 tcg_temp_free(addr); \
2398 gen_narrow_load_store(ld32u
);
2402 gen_narrow_load_store(st32
);
2404 #undef gen_narrow_load_store
2407 gen_window_check3(dc
, RRRN_R
, RRRN_S
, RRRN_T
);
2408 tcg_gen_add_i32(cpu_R
[RRRN_R
], cpu_R
[RRRN_S
], cpu_R
[RRRN_T
]);
2411 case 11: /*ADDI.Nn*/
2412 gen_window_check2(dc
, RRRN_R
, RRRN_S
);
2413 tcg_gen_addi_i32(cpu_R
[RRRN_R
], cpu_R
[RRRN_S
], RRRN_T
? RRRN_T
: -1);
2417 gen_window_check1(dc
, RRRN_S
);
2418 if (RRRN_T
< 8) { /*MOVI.Nn*/
2419 tcg_gen_movi_i32(cpu_R
[RRRN_S
],
2420 RRRN_R
| (RRRN_T
<< 4) |
2421 ((RRRN_T
& 6) == 6 ? 0xffffff80 : 0));
2422 } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/
2423 TCGCond eq_ne
= (RRRN_T
& 4) ? TCG_COND_NE
: TCG_COND_EQ
;
2425 gen_brcondi(dc
, eq_ne
, cpu_R
[RRRN_S
], 0,
2426 4 + (RRRN_R
| ((RRRN_T
& 3) << 4)));
2433 gen_window_check2(dc
, RRRN_S
, RRRN_T
);
2434 tcg_gen_mov_i32(cpu_R
[RRRN_T
], cpu_R
[RRRN_S
]);
2440 gen_jump(dc
, cpu_R
[0]);
2444 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
2446 TCGv_i32 tmp
= tcg_const_i32(dc
->pc
);
2447 gen_advance_ccount(dc
);
2448 gen_helper_retw(tmp
, tmp
);
2454 case 2: /*BREAK.Nn*/
2455 HAS_OPTION(XTENSA_OPTION_DEBUG
);
2457 gen_debug_exception(dc
, DEBUGCAUSE_BN
);
2465 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
2468 default: /*reserved*/
2474 default: /*reserved*/
2480 default: /*reserved*/
2485 gen_check_loop_end(dc
, 0);
2486 dc
->pc
= dc
->next_pc
;
2491 qemu_log("INVALID(pc = %08x)\n", dc
->pc
);
2492 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
2496 static void check_breakpoint(CPUState
*env
, DisasContext
*dc
)
2500 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
2501 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
2502 if (bp
->pc
== dc
->pc
) {
2503 tcg_gen_movi_i32(cpu_pc
, dc
->pc
);
2504 gen_exception(dc
, EXCP_DEBUG
);
2505 dc
->is_jmp
= DISAS_UPDATE
;
2511 static void gen_ibreak_check(CPUState
*env
, DisasContext
*dc
)
2515 for (i
= 0; i
< dc
->config
->nibreak
; ++i
) {
2516 if ((env
->sregs
[IBREAKENABLE
] & (1 << i
)) &&
2517 env
->sregs
[IBREAKA
+ i
] == dc
->pc
) {
2518 gen_debug_exception(dc
, DEBUGCAUSE_IB
);
2524 static void gen_intermediate_code_internal(
2525 CPUState
*env
, TranslationBlock
*tb
, int search_pc
)
2530 uint16_t *gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
2531 int max_insns
= tb
->cflags
& CF_COUNT_MASK
;
2532 uint32_t pc_start
= tb
->pc
;
2533 uint32_t next_page_start
=
2534 (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
2536 if (max_insns
== 0) {
2537 max_insns
= CF_COUNT_MASK
;
2540 dc
.config
= env
->config
;
2541 dc
.singlestep_enabled
= env
->singlestep_enabled
;
2544 dc
.ring
= tb
->flags
& XTENSA_TBFLAG_RING_MASK
;
2545 dc
.cring
= (tb
->flags
& XTENSA_TBFLAG_EXCM
) ? 0 : dc
.ring
;
2546 dc
.lbeg
= env
->sregs
[LBEG
];
2547 dc
.lend
= env
->sregs
[LEND
];
2548 dc
.is_jmp
= DISAS_NEXT
;
2549 dc
.ccount_delta
= 0;
2550 dc
.debug
= tb
->flags
& XTENSA_TBFLAG_DEBUG
;
2551 dc
.icount
= tb
->flags
& XTENSA_TBFLAG_ICOUNT
;
2554 init_sar_tracker(&dc
);
2555 reset_used_window(&dc
);
2557 dc
.next_icount
= tcg_temp_local_new_i32();
2562 if (env
->singlestep_enabled
&& env
->exception_taken
) {
2563 env
->exception_taken
= 0;
2564 tcg_gen_movi_i32(cpu_pc
, dc
.pc
);
2565 gen_exception(&dc
, EXCP_DEBUG
);
2569 check_breakpoint(env
, &dc
);
2572 j
= gen_opc_ptr
- gen_opc_buf
;
2576 gen_opc_instr_start
[lj
++] = 0;
2579 gen_opc_pc
[lj
] = dc
.pc
;
2580 gen_opc_instr_start
[lj
] = 1;
2581 gen_opc_icount
[lj
] = insn_count
;
2584 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
))) {
2585 tcg_gen_debug_insn_start(dc
.pc
);
2590 if (insn_count
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
2595 int label
= gen_new_label();
2597 tcg_gen_addi_i32(dc
.next_icount
, cpu_SR
[ICOUNT
], 1);
2598 tcg_gen_brcondi_i32(TCG_COND_NE
, dc
.next_icount
, 0, label
);
2599 tcg_gen_mov_i32(dc
.next_icount
, cpu_SR
[ICOUNT
]);
2601 gen_debug_exception(&dc
, DEBUGCAUSE_IC
);
2603 gen_set_label(label
);
2607 gen_ibreak_check(env
, &dc
);
2610 disas_xtensa_insn(&dc
);
2613 tcg_gen_mov_i32(cpu_SR
[ICOUNT
], dc
.next_icount
);
2615 if (env
->singlestep_enabled
) {
2616 tcg_gen_movi_i32(cpu_pc
, dc
.pc
);
2617 gen_exception(&dc
, EXCP_DEBUG
);
2620 } while (dc
.is_jmp
== DISAS_NEXT
&&
2621 insn_count
< max_insns
&&
2622 dc
.pc
< next_page_start
&&
2623 gen_opc_ptr
< gen_opc_end
);
2626 reset_sar_tracker(&dc
);
2628 tcg_temp_free(dc
.next_icount
);
2631 if (tb
->cflags
& CF_LAST_IO
) {
2635 if (dc
.is_jmp
== DISAS_NEXT
) {
2636 gen_jumpi(&dc
, dc
.pc
, 0);
2638 gen_icount_end(tb
, insn_count
);
2639 *gen_opc_ptr
= INDEX_op_end
;
2642 tb
->size
= dc
.pc
- pc_start
;
2643 tb
->icount
= insn_count
;
2647 void gen_intermediate_code(CPUState
*env
, TranslationBlock
*tb
)
2649 gen_intermediate_code_internal(env
, tb
, 0);
2652 void gen_intermediate_code_pc(CPUState
*env
, TranslationBlock
*tb
)
2654 gen_intermediate_code_internal(env
, tb
, 1);
2657 void cpu_dump_state(CPUState
*env
, FILE *f
, fprintf_function cpu_fprintf
,
2662 cpu_fprintf(f
, "PC=%08x\n\n", env
->pc
);
2664 for (i
= j
= 0; i
< 256; ++i
) {
2666 cpu_fprintf(f
, "%s=%08x%c", sregnames
[i
], env
->sregs
[i
],
2667 (j
++ % 4) == 3 ? '\n' : ' ');
2671 cpu_fprintf(f
, (j
% 4) == 0 ? "\n" : "\n\n");
2673 for (i
= j
= 0; i
< 256; ++i
) {
2675 cpu_fprintf(f
, "%s=%08x%c", uregnames
[i
], env
->uregs
[i
],
2676 (j
++ % 4) == 3 ? '\n' : ' ');
2680 cpu_fprintf(f
, (j
% 4) == 0 ? "\n" : "\n\n");
2682 for (i
= 0; i
< 16; ++i
) {
2683 cpu_fprintf(f
, "A%02d=%08x%c", i
, env
->regs
[i
],
2684 (i
% 4) == 3 ? '\n' : ' ');
2687 cpu_fprintf(f
, "\n");
2689 for (i
= 0; i
< env
->config
->nareg
; ++i
) {
2690 cpu_fprintf(f
, "AR%02d=%08x%c", i
, env
->phys_regs
[i
],
2691 (i
% 4) == 3 ? '\n' : ' ');
2695 void restore_state_to_opc(CPUState
*env
, TranslationBlock
*tb
, int pc_pos
)
2697 env
->pc
= gen_opc_pc
[pc_pos
];