3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 typedef struct DisasContext
{
45 const XtensaConfig
*config
;
55 int singlestep_enabled
;
59 bool sar_m32_allocated
;
62 uint32_t ccount_delta
;
70 static TCGv_ptr cpu_env
;
71 static TCGv_i32 cpu_pc
;
72 static TCGv_i32 cpu_R
[16];
73 static TCGv_i32 cpu_SR
[256];
74 static TCGv_i32 cpu_UR
[256];
76 #include "gen-icount.h"
78 static const char * const sregnames
[256] = {
84 [LITBASE
] = "LITBASE",
85 [SCOMPARE1
] = "SCOMPARE1",
92 [WINDOW_BASE
] = "WINDOW_BASE",
93 [WINDOW_START
] = "WINDOW_START",
94 [PTEVADDR
] = "PTEVADDR",
96 [ITLBCFG
] = "ITLBCFG",
97 [DTLBCFG
] = "DTLBCFG",
98 [IBREAKENABLE
] = "IBREAKENABLE",
99 [IBREAKA
] = "IBREAKA0",
100 [IBREAKA
+ 1] = "IBREAKA1",
101 [DBREAKA
] = "DBREAKA0",
102 [DBREAKA
+ 1] = "DBREAKA1",
103 [DBREAKC
] = "DBREAKC0",
104 [DBREAKC
+ 1] = "DBREAKC1",
119 [EXCSAVE1
] = "EXCSAVE1",
120 [EXCSAVE1
+ 1] = "EXCSAVE2",
121 [EXCSAVE1
+ 2] = "EXCSAVE3",
122 [EXCSAVE1
+ 3] = "EXCSAVE4",
123 [EXCSAVE1
+ 4] = "EXCSAVE5",
124 [EXCSAVE1
+ 5] = "EXCSAVE6",
125 [EXCSAVE1
+ 6] = "EXCSAVE7",
126 [CPENABLE
] = "CPENABLE",
128 [INTCLEAR
] = "INTCLEAR",
129 [INTENABLE
] = "INTENABLE",
131 [VECBASE
] = "VECBASE",
132 [EXCCAUSE
] = "EXCCAUSE",
133 [DEBUGCAUSE
] = "DEBUGCAUSE",
137 [ICOUNTLEVEL
] = "ICOUNTLEVEL",
138 [EXCVADDR
] = "EXCVADDR",
139 [CCOMPARE
] = "CCOMPARE0",
140 [CCOMPARE
+ 1] = "CCOMPARE1",
141 [CCOMPARE
+ 2] = "CCOMPARE2",
144 static const char * const uregnames
[256] = {
145 [THREADPTR
] = "THREADPTR",
150 void xtensa_translate_init(void)
152 static const char * const regnames
[] = {
153 "ar0", "ar1", "ar2", "ar3",
154 "ar4", "ar5", "ar6", "ar7",
155 "ar8", "ar9", "ar10", "ar11",
156 "ar12", "ar13", "ar14", "ar15",
160 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
161 cpu_pc
= tcg_global_mem_new_i32(TCG_AREG0
,
162 offsetof(CPUXtensaState
, pc
), "pc");
164 for (i
= 0; i
< 16; i
++) {
165 cpu_R
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
166 offsetof(CPUXtensaState
, regs
[i
]),
170 for (i
= 0; i
< 256; ++i
) {
172 cpu_SR
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
173 offsetof(CPUXtensaState
, sregs
[i
]),
178 for (i
= 0; i
< 256; ++i
) {
180 cpu_UR
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
181 offsetof(CPUXtensaState
, uregs
[i
]),
189 static inline bool option_bits_enabled(DisasContext
*dc
, uint64_t opt
)
191 return xtensa_option_bits_enabled(dc
->config
, opt
);
194 static inline bool option_enabled(DisasContext
*dc
, int opt
)
196 return xtensa_option_enabled(dc
->config
, opt
);
199 static void init_litbase(DisasContext
*dc
)
201 if (dc
->tb
->flags
& XTENSA_TBFLAG_LITBASE
) {
202 dc
->litbase
= tcg_temp_local_new_i32();
203 tcg_gen_andi_i32(dc
->litbase
, cpu_SR
[LITBASE
], 0xfffff000);
207 static void reset_litbase(DisasContext
*dc
)
209 if (dc
->tb
->flags
& XTENSA_TBFLAG_LITBASE
) {
210 tcg_temp_free(dc
->litbase
);
214 static void init_sar_tracker(DisasContext
*dc
)
216 dc
->sar_5bit
= false;
217 dc
->sar_m32_5bit
= false;
218 dc
->sar_m32_allocated
= false;
221 static void reset_sar_tracker(DisasContext
*dc
)
223 if (dc
->sar_m32_allocated
) {
224 tcg_temp_free(dc
->sar_m32
);
228 static void gen_right_shift_sar(DisasContext
*dc
, TCGv_i32 sa
)
230 tcg_gen_andi_i32(cpu_SR
[SAR
], sa
, 0x1f);
231 if (dc
->sar_m32_5bit
) {
232 tcg_gen_discard_i32(dc
->sar_m32
);
235 dc
->sar_m32_5bit
= false;
238 static void gen_left_shift_sar(DisasContext
*dc
, TCGv_i32 sa
)
240 TCGv_i32 tmp
= tcg_const_i32(32);
241 if (!dc
->sar_m32_allocated
) {
242 dc
->sar_m32
= tcg_temp_local_new_i32();
243 dc
->sar_m32_allocated
= true;
245 tcg_gen_andi_i32(dc
->sar_m32
, sa
, 0x1f);
246 tcg_gen_sub_i32(cpu_SR
[SAR
], tmp
, dc
->sar_m32
);
247 dc
->sar_5bit
= false;
248 dc
->sar_m32_5bit
= true;
252 static void gen_advance_ccount(DisasContext
*dc
)
254 if (dc
->ccount_delta
> 0) {
255 TCGv_i32 tmp
= tcg_const_i32(dc
->ccount_delta
);
256 dc
->ccount_delta
= 0;
257 gen_helper_advance_ccount(tmp
);
262 static void reset_used_window(DisasContext
*dc
)
267 static void gen_exception(DisasContext
*dc
, int excp
)
269 TCGv_i32 tmp
= tcg_const_i32(excp
);
270 gen_advance_ccount(dc
);
271 gen_helper_exception(tmp
);
275 static void gen_exception_cause(DisasContext
*dc
, uint32_t cause
)
277 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
278 TCGv_i32 tcause
= tcg_const_i32(cause
);
279 gen_advance_ccount(dc
);
280 gen_helper_exception_cause(tpc
, tcause
);
282 tcg_temp_free(tcause
);
283 if (cause
== ILLEGAL_INSTRUCTION_CAUSE
||
284 cause
== SYSCALL_CAUSE
) {
285 dc
->is_jmp
= DISAS_UPDATE
;
289 static void gen_exception_cause_vaddr(DisasContext
*dc
, uint32_t cause
,
292 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
293 TCGv_i32 tcause
= tcg_const_i32(cause
);
294 gen_advance_ccount(dc
);
295 gen_helper_exception_cause_vaddr(tpc
, tcause
, vaddr
);
297 tcg_temp_free(tcause
);
300 static void gen_debug_exception(DisasContext
*dc
, uint32_t cause
)
302 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
303 TCGv_i32 tcause
= tcg_const_i32(cause
);
304 gen_advance_ccount(dc
);
305 gen_helper_debug_exception(tpc
, tcause
);
307 tcg_temp_free(tcause
);
308 if (cause
& (DEBUGCAUSE_IB
| DEBUGCAUSE_BI
| DEBUGCAUSE_BN
)) {
309 dc
->is_jmp
= DISAS_UPDATE
;
313 static void gen_check_privilege(DisasContext
*dc
)
316 gen_exception_cause(dc
, PRIVILEGED_CAUSE
);
317 dc
->is_jmp
= DISAS_UPDATE
;
321 static void gen_jump_slot(DisasContext
*dc
, TCGv dest
, int slot
)
323 tcg_gen_mov_i32(cpu_pc
, dest
);
324 gen_advance_ccount(dc
);
326 tcg_gen_mov_i32(cpu_SR
[ICOUNT
], dc
->next_icount
);
328 if (dc
->singlestep_enabled
) {
329 gen_exception(dc
, EXCP_DEBUG
);
332 tcg_gen_goto_tb(slot
);
333 tcg_gen_exit_tb((tcg_target_long
)dc
->tb
+ slot
);
338 dc
->is_jmp
= DISAS_UPDATE
;
341 static void gen_jump(DisasContext
*dc
, TCGv dest
)
343 gen_jump_slot(dc
, dest
, -1);
346 static void gen_jumpi(DisasContext
*dc
, uint32_t dest
, int slot
)
348 TCGv_i32 tmp
= tcg_const_i32(dest
);
349 if (((dc
->pc
^ dest
) & TARGET_PAGE_MASK
) != 0) {
352 gen_jump_slot(dc
, tmp
, slot
);
356 static void gen_callw_slot(DisasContext
*dc
, int callinc
, TCGv_i32 dest
,
359 TCGv_i32 tcallinc
= tcg_const_i32(callinc
);
361 tcg_gen_deposit_i32(cpu_SR
[PS
], cpu_SR
[PS
],
362 tcallinc
, PS_CALLINC_SHIFT
, PS_CALLINC_LEN
);
363 tcg_temp_free(tcallinc
);
364 tcg_gen_movi_i32(cpu_R
[callinc
<< 2],
365 (callinc
<< 30) | (dc
->next_pc
& 0x3fffffff));
366 gen_jump_slot(dc
, dest
, slot
);
369 static void gen_callw(DisasContext
*dc
, int callinc
, TCGv_i32 dest
)
371 gen_callw_slot(dc
, callinc
, dest
, -1);
374 static void gen_callwi(DisasContext
*dc
, int callinc
, uint32_t dest
, int slot
)
376 TCGv_i32 tmp
= tcg_const_i32(dest
);
377 if (((dc
->pc
^ dest
) & TARGET_PAGE_MASK
) != 0) {
380 gen_callw_slot(dc
, callinc
, tmp
, slot
);
384 static bool gen_check_loop_end(DisasContext
*dc
, int slot
)
386 if (option_enabled(dc
, XTENSA_OPTION_LOOP
) &&
387 !(dc
->tb
->flags
& XTENSA_TBFLAG_EXCM
) &&
388 dc
->next_pc
== dc
->lend
) {
389 int label
= gen_new_label();
391 tcg_gen_brcondi_i32(TCG_COND_EQ
, cpu_SR
[LCOUNT
], 0, label
);
392 tcg_gen_subi_i32(cpu_SR
[LCOUNT
], cpu_SR
[LCOUNT
], 1);
393 gen_jumpi(dc
, dc
->lbeg
, slot
);
394 gen_set_label(label
);
395 gen_jumpi(dc
, dc
->next_pc
, -1);
401 static void gen_jumpi_check_loop_end(DisasContext
*dc
, int slot
)
403 if (!gen_check_loop_end(dc
, slot
)) {
404 gen_jumpi(dc
, dc
->next_pc
, slot
);
408 static void gen_brcond(DisasContext
*dc
, TCGCond cond
,
409 TCGv_i32 t0
, TCGv_i32 t1
, uint32_t offset
)
411 int label
= gen_new_label();
413 tcg_gen_brcond_i32(cond
, t0
, t1
, label
);
414 gen_jumpi_check_loop_end(dc
, 0);
415 gen_set_label(label
);
416 gen_jumpi(dc
, dc
->pc
+ offset
, 1);
419 static void gen_brcondi(DisasContext
*dc
, TCGCond cond
,
420 TCGv_i32 t0
, uint32_t t1
, uint32_t offset
)
422 TCGv_i32 tmp
= tcg_const_i32(t1
);
423 gen_brcond(dc
, cond
, t0
, tmp
, offset
);
427 static void gen_rsr_ccount(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
429 gen_advance_ccount(dc
);
430 tcg_gen_mov_i32(d
, cpu_SR
[sr
]);
433 static void gen_rsr_ptevaddr(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
435 tcg_gen_shri_i32(d
, cpu_SR
[EXCVADDR
], 10);
436 tcg_gen_or_i32(d
, d
, cpu_SR
[sr
]);
437 tcg_gen_andi_i32(d
, d
, 0xfffffffc);
440 static void gen_rsr(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
442 static void (* const rsr_handler
[256])(DisasContext
*dc
,
443 TCGv_i32 d
, uint32_t sr
) = {
444 [CCOUNT
] = gen_rsr_ccount
,
445 [PTEVADDR
] = gen_rsr_ptevaddr
,
449 if (rsr_handler
[sr
]) {
450 rsr_handler
[sr
](dc
, d
, sr
);
452 tcg_gen_mov_i32(d
, cpu_SR
[sr
]);
455 qemu_log("RSR %d not implemented, ", sr
);
459 static void gen_wsr_lbeg(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
461 gen_helper_wsr_lbeg(s
);
462 gen_jumpi_check_loop_end(dc
, 0);
465 static void gen_wsr_lend(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
467 gen_helper_wsr_lend(s
);
468 gen_jumpi_check_loop_end(dc
, 0);
471 static void gen_wsr_sar(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
473 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0x3f);
474 if (dc
->sar_m32_5bit
) {
475 tcg_gen_discard_i32(dc
->sar_m32
);
477 dc
->sar_5bit
= false;
478 dc
->sar_m32_5bit
= false;
481 static void gen_wsr_br(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
483 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0xffff);
486 static void gen_wsr_litbase(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
488 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0xfffff001);
489 /* This can change tb->flags, so exit tb */
490 gen_jumpi_check_loop_end(dc
, -1);
493 static void gen_wsr_acchi(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
495 tcg_gen_ext8s_i32(cpu_SR
[sr
], s
);
498 static void gen_wsr_windowbase(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
500 gen_helper_wsr_windowbase(v
);
501 reset_used_window(dc
);
504 static void gen_wsr_windowstart(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
506 tcg_gen_andi_i32(cpu_SR
[sr
], v
, (1 << dc
->config
->nareg
/ 4) - 1);
507 reset_used_window(dc
);
510 static void gen_wsr_ptevaddr(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
512 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0xffc00000);
515 static void gen_wsr_rasid(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
517 gen_helper_wsr_rasid(v
);
518 /* This can change tb->flags, so exit tb */
519 gen_jumpi_check_loop_end(dc
, -1);
522 static void gen_wsr_tlbcfg(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
524 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0x01130000);
527 static void gen_wsr_ibreakenable(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
529 gen_helper_wsr_ibreakenable(v
);
530 gen_jumpi_check_loop_end(dc
, 0);
533 static void gen_wsr_ibreaka(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
535 unsigned id
= sr
- IBREAKA
;
537 if (id
< dc
->config
->nibreak
) {
538 TCGv_i32 tmp
= tcg_const_i32(id
);
539 gen_helper_wsr_ibreaka(tmp
, v
);
541 gen_jumpi_check_loop_end(dc
, 0);
545 static void gen_wsr_dbreaka(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
547 unsigned id
= sr
- DBREAKA
;
549 if (id
< dc
->config
->ndbreak
) {
550 TCGv_i32 tmp
= tcg_const_i32(id
);
551 gen_helper_wsr_dbreaka(tmp
, v
);
556 static void gen_wsr_dbreakc(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
558 unsigned id
= sr
- DBREAKC
;
560 if (id
< dc
->config
->ndbreak
) {
561 TCGv_i32 tmp
= tcg_const_i32(id
);
562 gen_helper_wsr_dbreakc(tmp
, v
);
567 static void gen_wsr_intset(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
569 tcg_gen_andi_i32(cpu_SR
[sr
], v
,
570 dc
->config
->inttype_mask
[INTTYPE_SOFTWARE
]);
571 gen_helper_check_interrupts(cpu_env
);
572 gen_jumpi_check_loop_end(dc
, 0);
575 static void gen_wsr_intclear(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
577 TCGv_i32 tmp
= tcg_temp_new_i32();
579 tcg_gen_andi_i32(tmp
, v
,
580 dc
->config
->inttype_mask
[INTTYPE_EDGE
] |
581 dc
->config
->inttype_mask
[INTTYPE_NMI
] |
582 dc
->config
->inttype_mask
[INTTYPE_SOFTWARE
]);
583 tcg_gen_andc_i32(cpu_SR
[INTSET
], cpu_SR
[INTSET
], tmp
);
585 gen_helper_check_interrupts(cpu_env
);
588 static void gen_wsr_intenable(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
590 tcg_gen_mov_i32(cpu_SR
[sr
], v
);
591 gen_helper_check_interrupts(cpu_env
);
592 gen_jumpi_check_loop_end(dc
, 0);
595 static void gen_wsr_ps(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
597 uint32_t mask
= PS_WOE
| PS_CALLINC
| PS_OWB
|
598 PS_UM
| PS_EXCM
| PS_INTLEVEL
;
600 if (option_enabled(dc
, XTENSA_OPTION_MMU
)) {
603 tcg_gen_andi_i32(cpu_SR
[sr
], v
, mask
);
604 reset_used_window(dc
);
605 gen_helper_check_interrupts(cpu_env
);
606 /* This can change mmu index and tb->flags, so exit tb */
607 gen_jumpi_check_loop_end(dc
, -1);
610 static void gen_wsr_debugcause(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
614 static void gen_wsr_prid(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
618 static void gen_wsr_icount(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
621 tcg_gen_mov_i32(dc
->next_icount
, v
);
623 tcg_gen_mov_i32(cpu_SR
[sr
], v
);
627 static void gen_wsr_icountlevel(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
629 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0xf);
630 /* This can change tb->flags, so exit tb */
631 gen_jumpi_check_loop_end(dc
, -1);
634 static void gen_wsr_ccompare(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
636 uint32_t id
= sr
- CCOMPARE
;
637 if (id
< dc
->config
->nccompare
) {
638 uint32_t int_bit
= 1 << dc
->config
->timerint
[id
];
639 gen_advance_ccount(dc
);
640 tcg_gen_mov_i32(cpu_SR
[sr
], v
);
641 tcg_gen_andi_i32(cpu_SR
[INTSET
], cpu_SR
[INTSET
], ~int_bit
);
642 gen_helper_check_interrupts(cpu_env
);
646 static void gen_wsr(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
648 static void (* const wsr_handler
[256])(DisasContext
*dc
,
649 uint32_t sr
, TCGv_i32 v
) = {
650 [LBEG
] = gen_wsr_lbeg
,
651 [LEND
] = gen_wsr_lend
,
654 [LITBASE
] = gen_wsr_litbase
,
655 [ACCHI
] = gen_wsr_acchi
,
656 [WINDOW_BASE
] = gen_wsr_windowbase
,
657 [WINDOW_START
] = gen_wsr_windowstart
,
658 [PTEVADDR
] = gen_wsr_ptevaddr
,
659 [RASID
] = gen_wsr_rasid
,
660 [ITLBCFG
] = gen_wsr_tlbcfg
,
661 [DTLBCFG
] = gen_wsr_tlbcfg
,
662 [IBREAKENABLE
] = gen_wsr_ibreakenable
,
663 [IBREAKA
] = gen_wsr_ibreaka
,
664 [IBREAKA
+ 1] = gen_wsr_ibreaka
,
665 [DBREAKA
] = gen_wsr_dbreaka
,
666 [DBREAKA
+ 1] = gen_wsr_dbreaka
,
667 [DBREAKC
] = gen_wsr_dbreakc
,
668 [DBREAKC
+ 1] = gen_wsr_dbreakc
,
669 [INTSET
] = gen_wsr_intset
,
670 [INTCLEAR
] = gen_wsr_intclear
,
671 [INTENABLE
] = gen_wsr_intenable
,
673 [DEBUGCAUSE
] = gen_wsr_debugcause
,
674 [PRID
] = gen_wsr_prid
,
675 [ICOUNT
] = gen_wsr_icount
,
676 [ICOUNTLEVEL
] = gen_wsr_icountlevel
,
677 [CCOMPARE
] = gen_wsr_ccompare
,
678 [CCOMPARE
+ 1] = gen_wsr_ccompare
,
679 [CCOMPARE
+ 2] = gen_wsr_ccompare
,
683 if (wsr_handler
[sr
]) {
684 wsr_handler
[sr
](dc
, sr
, s
);
686 tcg_gen_mov_i32(cpu_SR
[sr
], s
);
689 qemu_log("WSR %d not implemented, ", sr
);
693 static void gen_load_store_alignment(DisasContext
*dc
, int shift
,
694 TCGv_i32 addr
, bool no_hw_alignment
)
696 if (!option_enabled(dc
, XTENSA_OPTION_UNALIGNED_EXCEPTION
)) {
697 tcg_gen_andi_i32(addr
, addr
, ~0 << shift
);
698 } else if (option_enabled(dc
, XTENSA_OPTION_HW_ALIGNMENT
) &&
700 int label
= gen_new_label();
701 TCGv_i32 tmp
= tcg_temp_new_i32();
702 tcg_gen_andi_i32(tmp
, addr
, ~(~0 << shift
));
703 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
704 gen_exception_cause_vaddr(dc
, LOAD_STORE_ALIGNMENT_CAUSE
, addr
);
705 gen_set_label(label
);
710 static void gen_waiti(DisasContext
*dc
, uint32_t imm4
)
712 TCGv_i32 pc
= tcg_const_i32(dc
->next_pc
);
713 TCGv_i32 intlevel
= tcg_const_i32(imm4
);
714 gen_advance_ccount(dc
);
715 gen_helper_waiti(pc
, intlevel
);
717 tcg_temp_free(intlevel
);
720 static void gen_window_check1(DisasContext
*dc
, unsigned r1
)
722 if (dc
->tb
->flags
& XTENSA_TBFLAG_EXCM
) {
725 if (option_enabled(dc
, XTENSA_OPTION_WINDOWED_REGISTER
) &&
726 r1
/ 4 > dc
->used_window
) {
727 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
728 TCGv_i32 w
= tcg_const_i32(r1
/ 4);
730 dc
->used_window
= r1
/ 4;
731 gen_advance_ccount(dc
);
732 gen_helper_window_check(pc
, w
);
739 static void gen_window_check2(DisasContext
*dc
, unsigned r1
, unsigned r2
)
741 gen_window_check1(dc
, r1
> r2
? r1
: r2
);
744 static void gen_window_check3(DisasContext
*dc
, unsigned r1
, unsigned r2
,
747 gen_window_check2(dc
, r1
, r2
> r3
? r2
: r3
);
750 static TCGv_i32
gen_mac16_m(TCGv_i32 v
, bool hi
, bool is_unsigned
)
752 TCGv_i32 m
= tcg_temp_new_i32();
755 (is_unsigned
? tcg_gen_shri_i32
: tcg_gen_sari_i32
)(m
, v
, 16);
757 (is_unsigned
? tcg_gen_ext16u_i32
: tcg_gen_ext16s_i32
)(m
, v
);
762 static void disas_xtensa_insn(DisasContext
*dc
)
764 #define HAS_OPTION_BITS(opt) do { \
765 if (!option_bits_enabled(dc, opt)) { \
766 qemu_log("Option is not enabled %s:%d\n", \
767 __FILE__, __LINE__); \
768 goto invalid_opcode; \
772 #define HAS_OPTION(opt) HAS_OPTION_BITS(XTENSA_OPTION_BIT(opt))
774 #define TBD() qemu_log("TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)
775 #define RESERVED() do { \
776 qemu_log("RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \
777 dc->pc, b0, b1, b2, __FILE__, __LINE__); \
778 goto invalid_opcode; \
782 #ifdef TARGET_WORDS_BIGENDIAN
783 #define OP0 (((b0) & 0xf0) >> 4)
784 #define OP1 (((b2) & 0xf0) >> 4)
785 #define OP2 ((b2) & 0xf)
786 #define RRR_R ((b1) & 0xf)
787 #define RRR_S (((b1) & 0xf0) >> 4)
788 #define RRR_T ((b0) & 0xf)
790 #define OP0 (((b0) & 0xf))
791 #define OP1 (((b2) & 0xf))
792 #define OP2 (((b2) & 0xf0) >> 4)
793 #define RRR_R (((b1) & 0xf0) >> 4)
794 #define RRR_S (((b1) & 0xf))
795 #define RRR_T (((b0) & 0xf0) >> 4)
797 #define RRR_X ((RRR_R & 0x4) >> 2)
798 #define RRR_Y ((RRR_T & 0x4) >> 2)
799 #define RRR_W (RRR_R & 0x3)
808 #define RRI8_IMM8 (b2)
809 #define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)
811 #ifdef TARGET_WORDS_BIGENDIAN
812 #define RI16_IMM16 (((b1) << 8) | (b2))
814 #define RI16_IMM16 (((b2) << 8) | (b1))
817 #ifdef TARGET_WORDS_BIGENDIAN
818 #define CALL_N (((b0) & 0xc) >> 2)
819 #define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))
821 #define CALL_N (((b0) & 0x30) >> 4)
822 #define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))
824 #define CALL_OFFSET_SE \
825 (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)
827 #define CALLX_N CALL_N
828 #ifdef TARGET_WORDS_BIGENDIAN
829 #define CALLX_M ((b0) & 0x3)
831 #define CALLX_M (((b0) & 0xc0) >> 6)
833 #define CALLX_S RRR_S
835 #define BRI12_M CALLX_M
836 #define BRI12_S RRR_S
837 #ifdef TARGET_WORDS_BIGENDIAN
838 #define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))
840 #define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))
842 #define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)
844 #define BRI8_M BRI12_M
845 #define BRI8_R RRI8_R
846 #define BRI8_S RRI8_S
847 #define BRI8_IMM8 RRI8_IMM8
848 #define BRI8_IMM8_SE RRI8_IMM8_SE
852 uint8_t b0
= ldub_code(dc
->pc
);
853 uint8_t b1
= ldub_code(dc
->pc
+ 1);
856 static const uint32_t B4CONST
[] = {
857 0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
860 static const uint32_t B4CONSTU
[] = {
861 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
865 dc
->next_pc
= dc
->pc
+ 2;
866 HAS_OPTION(XTENSA_OPTION_CODE_DENSITY
);
868 dc
->next_pc
= dc
->pc
+ 3;
869 b2
= ldub_code(dc
->pc
+ 2);
878 if ((RRR_R
& 0xc) == 0x8) {
879 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
886 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
897 gen_window_check1(dc
, CALLX_S
);
898 gen_jump(dc
, cpu_R
[CALLX_S
]);
902 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
904 TCGv_i32 tmp
= tcg_const_i32(dc
->pc
);
905 gen_advance_ccount(dc
);
906 gen_helper_retw(tmp
, tmp
);
919 gen_window_check2(dc
, CALLX_S
, CALLX_N
<< 2);
923 TCGv_i32 tmp
= tcg_temp_new_i32();
924 tcg_gen_mov_i32(tmp
, cpu_R
[CALLX_S
]);
925 tcg_gen_movi_i32(cpu_R
[0], dc
->next_pc
);
934 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
936 TCGv_i32 tmp
= tcg_temp_new_i32();
938 tcg_gen_mov_i32(tmp
, cpu_R
[CALLX_S
]);
939 gen_callw(dc
, CALLX_N
, tmp
);
949 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
950 gen_window_check2(dc
, RRR_T
, RRR_S
);
952 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
953 gen_advance_ccount(dc
);
954 gen_helper_movsp(pc
);
955 tcg_gen_mov_i32(cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
975 HAS_OPTION(XTENSA_OPTION_EXCEPTION
);
987 default: /*reserved*/
996 HAS_OPTION(XTENSA_OPTION_EXCEPTION
);
999 gen_check_privilege(dc
);
1000 tcg_gen_andi_i32(cpu_SR
[PS
], cpu_SR
[PS
], ~PS_EXCM
);
1001 gen_helper_check_interrupts(cpu_env
);
1002 gen_jump(dc
, cpu_SR
[EPC1
]);
1010 gen_check_privilege(dc
);
1011 gen_jump(dc
, cpu_SR
[
1012 dc
->config
->ndepc
? DEPC
: EPC1
]);
1017 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1018 gen_check_privilege(dc
);
1020 TCGv_i32 tmp
= tcg_const_i32(1);
1023 cpu_SR
[PS
], cpu_SR
[PS
], ~PS_EXCM
);
1024 tcg_gen_shl_i32(tmp
, tmp
, cpu_SR
[WINDOW_BASE
]);
1027 tcg_gen_andc_i32(cpu_SR
[WINDOW_START
],
1028 cpu_SR
[WINDOW_START
], tmp
);
1030 tcg_gen_or_i32(cpu_SR
[WINDOW_START
],
1031 cpu_SR
[WINDOW_START
], tmp
);
1034 gen_helper_restore_owb();
1035 gen_helper_check_interrupts(cpu_env
);
1036 gen_jump(dc
, cpu_SR
[EPC1
]);
1042 default: /*reserved*/
1049 HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
);
1050 if (RRR_S
>= 2 && RRR_S
<= dc
->config
->nlevel
) {
1051 gen_check_privilege(dc
);
1052 tcg_gen_mov_i32(cpu_SR
[PS
],
1053 cpu_SR
[EPS2
+ RRR_S
- 2]);
1054 gen_helper_check_interrupts(cpu_env
);
1055 gen_jump(dc
, cpu_SR
[EPC1
+ RRR_S
- 1]);
1057 qemu_log("RFI %d is illegal\n", RRR_S
);
1058 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
1066 default: /*reserved*/
1074 HAS_OPTION(XTENSA_OPTION_DEBUG
);
1076 gen_debug_exception(dc
, DEBUGCAUSE_BI
);
1080 case 5: /*SYSCALLx*/
1081 HAS_OPTION(XTENSA_OPTION_EXCEPTION
);
1083 case 0: /*SYSCALLx*/
1084 gen_exception_cause(dc
, SYSCALL_CAUSE
);
1088 if (semihosting_enabled
) {
1089 gen_check_privilege(dc
);
1090 gen_helper_simcall(cpu_env
);
1092 qemu_log("SIMCALL but semihosting is disabled\n");
1093 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
1104 HAS_OPTION(XTENSA_OPTION_INTERRUPT
);
1105 gen_check_privilege(dc
);
1106 gen_window_check1(dc
, RRR_T
);
1107 tcg_gen_mov_i32(cpu_R
[RRR_T
], cpu_SR
[PS
]);
1108 tcg_gen_andi_i32(cpu_SR
[PS
], cpu_SR
[PS
], ~PS_INTLEVEL
);
1109 tcg_gen_ori_i32(cpu_SR
[PS
], cpu_SR
[PS
], RRR_S
);
1110 gen_helper_check_interrupts(cpu_env
);
1111 gen_jumpi_check_loop_end(dc
, 0);
1115 HAS_OPTION(XTENSA_OPTION_INTERRUPT
);
1116 gen_check_privilege(dc
);
1117 gen_waiti(dc
, RRR_S
);
1124 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
1126 const unsigned shift
= (RRR_R
& 2) ? 8 : 4;
1127 TCGv_i32 mask
= tcg_const_i32(
1128 ((1 << shift
) - 1) << RRR_S
);
1129 TCGv_i32 tmp
= tcg_temp_new_i32();
1131 tcg_gen_and_i32(tmp
, cpu_SR
[BR
], mask
);
1132 if (RRR_R
& 1) { /*ALL*/
1133 tcg_gen_addi_i32(tmp
, tmp
, 1 << RRR_S
);
1135 tcg_gen_add_i32(tmp
, tmp
, mask
);
1137 tcg_gen_shri_i32(tmp
, tmp
, RRR_S
+ shift
);
1138 tcg_gen_deposit_i32(cpu_SR
[BR
], cpu_SR
[BR
],
1140 tcg_temp_free(mask
);
1145 default: /*reserved*/
1153 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1154 tcg_gen_and_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1158 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1159 tcg_gen_or_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1163 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1164 tcg_gen_xor_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1170 gen_window_check1(dc
, RRR_S
);
1171 gen_right_shift_sar(dc
, cpu_R
[RRR_S
]);
1175 gen_window_check1(dc
, RRR_S
);
1176 gen_left_shift_sar(dc
, cpu_R
[RRR_S
]);
1180 gen_window_check1(dc
, RRR_S
);
1182 TCGv_i32 tmp
= tcg_temp_new_i32();
1183 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], 3);
1184 gen_right_shift_sar(dc
, tmp
);
1190 gen_window_check1(dc
, RRR_S
);
1192 TCGv_i32 tmp
= tcg_temp_new_i32();
1193 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], 3);
1194 gen_left_shift_sar(dc
, tmp
);
1201 TCGv_i32 tmp
= tcg_const_i32(
1202 RRR_S
| ((RRR_T
& 1) << 4));
1203 gen_right_shift_sar(dc
, tmp
);
1217 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1218 gen_check_privilege(dc
);
1220 TCGv_i32 tmp
= tcg_const_i32(
1221 RRR_T
| ((RRR_T
& 8) ? 0xfffffff0 : 0));
1222 gen_helper_rotw(tmp
);
1224 reset_used_window(dc
);
1229 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA
);
1230 gen_window_check2(dc
, RRR_S
, RRR_T
);
1231 gen_helper_nsa(cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
1235 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA
);
1236 gen_window_check2(dc
, RRR_S
, RRR_T
);
1237 gen_helper_nsau(cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
1240 default: /*reserved*/
1248 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU
) |
1249 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION
) |
1250 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION
));
1251 gen_check_privilege(dc
);
1252 gen_window_check2(dc
, RRR_S
, RRR_T
);
1254 TCGv_i32 dtlb
= tcg_const_i32((RRR_R
& 8) != 0);
1256 switch (RRR_R
& 7) {
1257 case 3: /*RITLB0*/ /*RDTLB0*/
1258 gen_helper_rtlb0(cpu_R
[RRR_T
], cpu_R
[RRR_S
], dtlb
);
1261 case 4: /*IITLB*/ /*IDTLB*/
1262 gen_helper_itlb(cpu_R
[RRR_S
], dtlb
);
1263 /* This could change memory mapping, so exit tb */
1264 gen_jumpi_check_loop_end(dc
, -1);
1267 case 5: /*PITLB*/ /*PDTLB*/
1268 tcg_gen_movi_i32(cpu_pc
, dc
->pc
);
1269 gen_helper_ptlb(cpu_R
[RRR_T
], cpu_R
[RRR_S
], dtlb
);
1272 case 6: /*WITLB*/ /*WDTLB*/
1273 gen_helper_wtlb(cpu_R
[RRR_T
], cpu_R
[RRR_S
], dtlb
);
1274 /* This could change memory mapping, so exit tb */
1275 gen_jumpi_check_loop_end(dc
, -1);
1278 case 7: /*RITLB1*/ /*RDTLB1*/
1279 gen_helper_rtlb1(cpu_R
[RRR_T
], cpu_R
[RRR_S
], dtlb
);
1283 tcg_temp_free(dtlb
);
1287 tcg_temp_free(dtlb
);
1292 gen_window_check2(dc
, RRR_R
, RRR_T
);
1295 tcg_gen_neg_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
1300 int label
= gen_new_label();
1301 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
1302 tcg_gen_brcondi_i32(
1303 TCG_COND_GE
, cpu_R
[RRR_R
], 0, label
);
1304 tcg_gen_neg_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
1305 gen_set_label(label
);
1309 default: /*reserved*/
1315 case 7: /*reserved*/
1320 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1321 tcg_gen_add_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1327 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1329 TCGv_i32 tmp
= tcg_temp_new_i32();
1330 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], OP2
- 8);
1331 tcg_gen_add_i32(cpu_R
[RRR_R
], tmp
, cpu_R
[RRR_T
]);
1337 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1338 tcg_gen_sub_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1344 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1346 TCGv_i32 tmp
= tcg_temp_new_i32();
1347 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], OP2
- 12);
1348 tcg_gen_sub_i32(cpu_R
[RRR_R
], tmp
, cpu_R
[RRR_T
]);
1359 gen_window_check2(dc
, RRR_R
, RRR_S
);
1360 tcg_gen_shli_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
],
1361 32 - (RRR_T
| ((OP2
& 1) << 4)));
1366 gen_window_check2(dc
, RRR_R
, RRR_T
);
1367 tcg_gen_sari_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
],
1368 RRR_S
| ((OP2
& 1) << 4));
1372 gen_window_check2(dc
, RRR_R
, RRR_T
);
1373 tcg_gen_shri_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
], RRR_S
);
1378 TCGv_i32 tmp
= tcg_temp_new_i32();
1380 gen_check_privilege(dc
);
1382 gen_window_check1(dc
, RRR_T
);
1383 tcg_gen_mov_i32(tmp
, cpu_R
[RRR_T
]);
1384 gen_rsr(dc
, cpu_R
[RRR_T
], RSR_SR
);
1385 gen_wsr(dc
, RSR_SR
, tmp
);
1387 if (!sregnames
[RSR_SR
]) {
1394 * Note: 64 bit ops are used here solely because SAR values
1397 #define gen_shift_reg(cmd, reg) do { \
1398 TCGv_i64 tmp = tcg_temp_new_i64(); \
1399 tcg_gen_extu_i32_i64(tmp, reg); \
1400 tcg_gen_##cmd##_i64(v, v, tmp); \
1401 tcg_gen_trunc_i64_i32(cpu_R[RRR_R], v); \
1402 tcg_temp_free_i64(v); \
1403 tcg_temp_free_i64(tmp); \
1406 #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
1409 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1411 TCGv_i64 v
= tcg_temp_new_i64();
1412 tcg_gen_concat_i32_i64(v
, cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
1418 gen_window_check2(dc
, RRR_R
, RRR_T
);
1420 tcg_gen_shr_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
], cpu_SR
[SAR
]);
1422 TCGv_i64 v
= tcg_temp_new_i64();
1423 tcg_gen_extu_i32_i64(v
, cpu_R
[RRR_T
]);
1429 gen_window_check2(dc
, RRR_R
, RRR_S
);
1430 if (dc
->sar_m32_5bit
) {
1431 tcg_gen_shl_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], dc
->sar_m32
);
1433 TCGv_i64 v
= tcg_temp_new_i64();
1434 TCGv_i32 s
= tcg_const_i32(32);
1435 tcg_gen_sub_i32(s
, s
, cpu_SR
[SAR
]);
1436 tcg_gen_andi_i32(s
, s
, 0x3f);
1437 tcg_gen_extu_i32_i64(v
, cpu_R
[RRR_S
]);
1438 gen_shift_reg(shl
, s
);
1444 gen_window_check2(dc
, RRR_R
, RRR_T
);
1446 tcg_gen_sar_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
], cpu_SR
[SAR
]);
1448 TCGv_i64 v
= tcg_temp_new_i64();
1449 tcg_gen_ext_i32_i64(v
, cpu_R
[RRR_T
]);
1454 #undef gen_shift_reg
1457 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL
);
1458 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1460 TCGv_i32 v1
= tcg_temp_new_i32();
1461 TCGv_i32 v2
= tcg_temp_new_i32();
1462 tcg_gen_ext16u_i32(v1
, cpu_R
[RRR_S
]);
1463 tcg_gen_ext16u_i32(v2
, cpu_R
[RRR_T
]);
1464 tcg_gen_mul_i32(cpu_R
[RRR_R
], v1
, v2
);
1471 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL
);
1472 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1474 TCGv_i32 v1
= tcg_temp_new_i32();
1475 TCGv_i32 v2
= tcg_temp_new_i32();
1476 tcg_gen_ext16s_i32(v1
, cpu_R
[RRR_S
]);
1477 tcg_gen_ext16s_i32(v2
, cpu_R
[RRR_T
]);
1478 tcg_gen_mul_i32(cpu_R
[RRR_R
], v1
, v2
);
1484 default: /*reserved*/
1492 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1496 HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV
);
1497 int label
= gen_new_label();
1498 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[RRR_T
], 0, label
);
1499 gen_exception_cause(dc
, INTEGER_DIVIDE_BY_ZERO_CAUSE
);
1500 gen_set_label(label
);
1504 #define BOOLEAN_LOGIC(fn, r, s, t) \
1506 HAS_OPTION(XTENSA_OPTION_BOOLEAN); \
1507 TCGv_i32 tmp1 = tcg_temp_new_i32(); \
1508 TCGv_i32 tmp2 = tcg_temp_new_i32(); \
1510 tcg_gen_shri_i32(tmp1, cpu_SR[BR], s); \
1511 tcg_gen_shri_i32(tmp2, cpu_SR[BR], t); \
1512 tcg_gen_##fn##_i32(tmp1, tmp1, tmp2); \
1513 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, r, 1); \
1514 tcg_temp_free(tmp1); \
1515 tcg_temp_free(tmp2); \
1519 BOOLEAN_LOGIC(and, RRR_R
, RRR_S
, RRR_T
);
1523 BOOLEAN_LOGIC(andc
, RRR_R
, RRR_S
, RRR_T
);
1527 BOOLEAN_LOGIC(or, RRR_R
, RRR_S
, RRR_T
);
1531 BOOLEAN_LOGIC(orc
, RRR_R
, RRR_S
, RRR_T
);
1535 BOOLEAN_LOGIC(xor, RRR_R
, RRR_S
, RRR_T
);
1538 #undef BOOLEAN_LOGIC
1541 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL
);
1542 tcg_gen_mul_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1547 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL_HIGH
);
1549 TCGv_i64 r
= tcg_temp_new_i64();
1550 TCGv_i64 s
= tcg_temp_new_i64();
1551 TCGv_i64 t
= tcg_temp_new_i64();
1554 tcg_gen_extu_i32_i64(s
, cpu_R
[RRR_S
]);
1555 tcg_gen_extu_i32_i64(t
, cpu_R
[RRR_T
]);
1557 tcg_gen_ext_i32_i64(s
, cpu_R
[RRR_S
]);
1558 tcg_gen_ext_i32_i64(t
, cpu_R
[RRR_T
]);
1560 tcg_gen_mul_i64(r
, s
, t
);
1561 tcg_gen_shri_i64(r
, r
, 32);
1562 tcg_gen_trunc_i64_i32(cpu_R
[RRR_R
], r
);
1564 tcg_temp_free_i64(r
);
1565 tcg_temp_free_i64(s
);
1566 tcg_temp_free_i64(t
);
1571 tcg_gen_divu_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1577 int label1
= gen_new_label();
1578 int label2
= gen_new_label();
1580 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[RRR_S
], 0x80000000,
1582 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[RRR_T
], 0xffffffff,
1584 tcg_gen_movi_i32(cpu_R
[RRR_R
],
1585 OP2
== 13 ? 0x80000000 : 0);
1587 gen_set_label(label1
);
1589 tcg_gen_div_i32(cpu_R
[RRR_R
],
1590 cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1592 tcg_gen_rem_i32(cpu_R
[RRR_R
],
1593 cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1595 gen_set_label(label2
);
1600 tcg_gen_remu_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1603 default: /*reserved*/
1613 gen_check_privilege(dc
);
1615 gen_window_check1(dc
, RRR_T
);
1616 gen_rsr(dc
, cpu_R
[RRR_T
], RSR_SR
);
1617 if (!sregnames
[RSR_SR
]) {
1624 gen_check_privilege(dc
);
1626 gen_window_check1(dc
, RRR_T
);
1627 gen_wsr(dc
, RSR_SR
, cpu_R
[RRR_T
]);
1628 if (!sregnames
[RSR_SR
]) {
1634 HAS_OPTION(XTENSA_OPTION_MISC_OP_SEXT
);
1635 gen_window_check2(dc
, RRR_R
, RRR_S
);
1637 int shift
= 24 - RRR_T
;
1640 tcg_gen_ext8s_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1641 } else if (shift
== 16) {
1642 tcg_gen_ext16s_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1644 TCGv_i32 tmp
= tcg_temp_new_i32();
1645 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], shift
);
1646 tcg_gen_sari_i32(cpu_R
[RRR_R
], tmp
, shift
);
1653 HAS_OPTION(XTENSA_OPTION_MISC_OP_CLAMPS
);
1654 gen_window_check2(dc
, RRR_R
, RRR_S
);
1656 TCGv_i32 tmp1
= tcg_temp_new_i32();
1657 TCGv_i32 tmp2
= tcg_temp_new_i32();
1658 int label
= gen_new_label();
1660 tcg_gen_sari_i32(tmp1
, cpu_R
[RRR_S
], 24 - RRR_T
);
1661 tcg_gen_xor_i32(tmp2
, tmp1
, cpu_R
[RRR_S
]);
1662 tcg_gen_andi_i32(tmp2
, tmp2
, 0xffffffff << (RRR_T
+ 7));
1663 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1664 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp2
, 0, label
);
1666 tcg_gen_sari_i32(tmp1
, cpu_R
[RRR_S
], 31);
1667 tcg_gen_xori_i32(cpu_R
[RRR_R
], tmp1
,
1668 0xffffffff >> (25 - RRR_T
));
1670 gen_set_label(label
);
1672 tcg_temp_free(tmp1
);
1673 tcg_temp_free(tmp2
);
1681 HAS_OPTION(XTENSA_OPTION_MISC_OP_MINMAX
);
1682 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1684 static const TCGCond cond
[] = {
1690 int label
= gen_new_label();
1692 if (RRR_R
!= RRR_T
) {
1693 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1694 tcg_gen_brcond_i32(cond
[OP2
- 4],
1695 cpu_R
[RRR_S
], cpu_R
[RRR_T
], label
);
1696 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
1698 tcg_gen_brcond_i32(cond
[OP2
- 4],
1699 cpu_R
[RRR_T
], cpu_R
[RRR_S
], label
);
1700 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1702 gen_set_label(label
);
1710 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1712 static const TCGCond cond
[] = {
1718 int label
= gen_new_label();
1719 tcg_gen_brcondi_i32(cond
[OP2
- 8], cpu_R
[RRR_T
], 0, label
);
1720 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1721 gen_set_label(label
);
1727 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
1728 gen_window_check2(dc
, RRR_R
, RRR_S
);
1730 int label
= gen_new_label();
1731 TCGv_i32 tmp
= tcg_temp_new_i32();
1733 tcg_gen_andi_i32(tmp
, cpu_SR
[BR
], 1 << RRR_T
);
1734 tcg_gen_brcondi_i32(
1735 OP2
& 1 ? TCG_COND_EQ
: TCG_COND_NE
,
1737 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1738 gen_set_label(label
);
1744 gen_window_check1(dc
, RRR_R
);
1746 int st
= (RRR_S
<< 4) + RRR_T
;
1747 if (uregnames
[st
]) {
1748 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_UR
[st
]);
1750 qemu_log("RUR %d not implemented, ", st
);
1757 gen_window_check1(dc
, RRR_T
);
1759 if (uregnames
[RSR_SR
]) {
1760 tcg_gen_mov_i32(cpu_UR
[RSR_SR
], cpu_R
[RRR_T
]);
1762 qemu_log("WUR %d not implemented, ", RSR_SR
);
1773 gen_window_check2(dc
, RRR_R
, RRR_T
);
1775 int shiftimm
= RRR_S
| (OP1
<< 4);
1776 int maskimm
= (1 << (OP2
+ 1)) - 1;
1778 TCGv_i32 tmp
= tcg_temp_new_i32();
1779 tcg_gen_shri_i32(tmp
, cpu_R
[RRR_T
], shiftimm
);
1780 tcg_gen_andi_i32(cpu_R
[RRR_R
], tmp
, maskimm
);
1794 HAS_OPTION(XTENSA_OPTION_COPROCESSOR
);
1799 gen_window_check2(dc
, RRR_S
, RRR_T
);
1802 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1803 gen_check_privilege(dc
);
1805 TCGv_i32 addr
= tcg_temp_new_i32();
1806 tcg_gen_addi_i32(addr
, cpu_R
[RRR_S
],
1807 (0xffffffc0 | (RRR_R
<< 2)));
1808 tcg_gen_qemu_ld32u(cpu_R
[RRR_T
], addr
, dc
->ring
);
1809 tcg_temp_free(addr
);
1814 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1815 gen_check_privilege(dc
);
1817 TCGv_i32 addr
= tcg_temp_new_i32();
1818 tcg_gen_addi_i32(addr
, cpu_R
[RRR_S
],
1819 (0xffffffc0 | (RRR_R
<< 2)));
1820 tcg_gen_qemu_st32(cpu_R
[RRR_T
], addr
, dc
->ring
);
1821 tcg_temp_free(addr
);
1832 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR
);
1837 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR
);
1841 default: /*reserved*/
1848 gen_window_check1(dc
, RRR_T
);
1850 TCGv_i32 tmp
= tcg_const_i32(
1851 ((dc
->tb
->flags
& XTENSA_TBFLAG_LITBASE
) ?
1852 0 : ((dc
->pc
+ 3) & ~3)) +
1853 (0xfffc0000 | (RI16_IMM16
<< 2)));
1855 if (dc
->tb
->flags
& XTENSA_TBFLAG_LITBASE
) {
1856 tcg_gen_add_i32(tmp
, tmp
, dc
->litbase
);
1858 tcg_gen_qemu_ld32u(cpu_R
[RRR_T
], tmp
, dc
->cring
);
1864 #define gen_load_store(type, shift) do { \
1865 TCGv_i32 addr = tcg_temp_new_i32(); \
1866 gen_window_check2(dc, RRI8_S, RRI8_T); \
1867 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \
1869 gen_load_store_alignment(dc, shift, addr, false); \
1871 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
1872 tcg_temp_free(addr); \
1877 gen_load_store(ld8u
, 0);
1881 gen_load_store(ld16u
, 1);
1885 gen_load_store(ld32u
, 2);
1889 gen_load_store(st8
, 0);
1893 gen_load_store(st16
, 1);
1897 gen_load_store(st32
, 2);
1902 HAS_OPTION(XTENSA_OPTION_DCACHE
);
1933 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK
);
1937 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK
);
1941 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK
);
1945 HAS_OPTION(XTENSA_OPTION_DCACHE
);
1949 HAS_OPTION(XTENSA_OPTION_DCACHE
);
1952 default: /*reserved*/
1960 HAS_OPTION(XTENSA_OPTION_ICACHE
);
1966 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK
);
1970 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK
);
1974 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK
);
1977 default: /*reserved*/
1984 HAS_OPTION(XTENSA_OPTION_ICACHE
);
1988 HAS_OPTION(XTENSA_OPTION_ICACHE
);
1991 default: /*reserved*/
1998 gen_load_store(ld16s
, 1);
2000 #undef gen_load_store
2003 gen_window_check1(dc
, RRI8_T
);
2004 tcg_gen_movi_i32(cpu_R
[RRI8_T
],
2005 RRI8_IMM8
| (RRI8_S
<< 8) |
2006 ((RRI8_S
& 0x8) ? 0xfffff000 : 0));
2009 #define gen_load_store_no_hw_align(type) do { \
2010 TCGv_i32 addr = tcg_temp_local_new_i32(); \
2011 gen_window_check2(dc, RRI8_S, RRI8_T); \
2012 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); \
2013 gen_load_store_alignment(dc, 2, addr, true); \
2014 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
2015 tcg_temp_free(addr); \
2019 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO
);
2020 gen_load_store_no_hw_align(ld32u
); /*TODO acquire?*/
2024 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2025 tcg_gen_addi_i32(cpu_R
[RRI8_T
], cpu_R
[RRI8_S
], RRI8_IMM8_SE
);
2029 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2030 tcg_gen_addi_i32(cpu_R
[RRI8_T
], cpu_R
[RRI8_S
], RRI8_IMM8_SE
<< 8);
2033 case 14: /*S32C1Iy*/
2034 HAS_OPTION(XTENSA_OPTION_CONDITIONAL_STORE
);
2035 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2037 int label
= gen_new_label();
2038 TCGv_i32 tmp
= tcg_temp_local_new_i32();
2039 TCGv_i32 addr
= tcg_temp_local_new_i32();
2041 tcg_gen_mov_i32(tmp
, cpu_R
[RRI8_T
]);
2042 tcg_gen_addi_i32(addr
, cpu_R
[RRI8_S
], RRI8_IMM8
<< 2);
2043 gen_load_store_alignment(dc
, 2, addr
, true);
2044 tcg_gen_qemu_ld32u(cpu_R
[RRI8_T
], addr
, dc
->cring
);
2045 tcg_gen_brcond_i32(TCG_COND_NE
, cpu_R
[RRI8_T
],
2046 cpu_SR
[SCOMPARE1
], label
);
2048 tcg_gen_qemu_st32(tmp
, addr
, dc
->cring
);
2050 gen_set_label(label
);
2051 tcg_temp_free(addr
);
2057 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO
);
2058 gen_load_store_no_hw_align(st32
); /*TODO release?*/
2060 #undef gen_load_store_no_hw_align
2062 default: /*reserved*/
2069 HAS_OPTION(XTENSA_OPTION_COPROCESSOR
);
2074 HAS_OPTION(XTENSA_OPTION_MAC16
);
2083 bool is_m1_sr
= (OP2
& 0x3) == 2;
2084 bool is_m2_sr
= (OP2
& 0xc) == 0;
2085 uint32_t ld_offset
= 0;
2092 case 0: /*MACI?/MACC?*/
2094 ld_offset
= (OP2
& 1) ? -4 : 4;
2096 if (OP2
>= 8) { /*MACI/MACC*/
2097 if (OP1
== 0) { /*LDINC/LDDEC*/
2102 } else if (op
!= MAC16_MULA
) { /*MULA.*.*.LDINC/LDDEC*/
2107 case 2: /*MACD?/MACA?*/
2108 if (op
== MAC16_UMUL
&& OP2
!= 7) { /*UMUL only in MACAA*/
2114 if (op
!= MAC16_NONE
) {
2116 gen_window_check1(dc
, RRR_S
);
2119 gen_window_check1(dc
, RRR_T
);
2124 TCGv_i32 vaddr
= tcg_temp_new_i32();
2125 TCGv_i32 mem32
= tcg_temp_new_i32();
2128 gen_window_check1(dc
, RRR_S
);
2129 tcg_gen_addi_i32(vaddr
, cpu_R
[RRR_S
], ld_offset
);
2130 gen_load_store_alignment(dc
, 2, vaddr
, false);
2131 tcg_gen_qemu_ld32u(mem32
, vaddr
, dc
->cring
);
2133 if (op
!= MAC16_NONE
) {
2134 TCGv_i32 m1
= gen_mac16_m(
2135 is_m1_sr
? cpu_SR
[MR
+ RRR_X
] : cpu_R
[RRR_S
],
2136 OP1
& 1, op
== MAC16_UMUL
);
2137 TCGv_i32 m2
= gen_mac16_m(
2138 is_m2_sr
? cpu_SR
[MR
+ 2 + RRR_Y
] : cpu_R
[RRR_T
],
2139 OP1
& 2, op
== MAC16_UMUL
);
2141 if (op
== MAC16_MUL
|| op
== MAC16_UMUL
) {
2142 tcg_gen_mul_i32(cpu_SR
[ACCLO
], m1
, m2
);
2143 if (op
== MAC16_UMUL
) {
2144 tcg_gen_movi_i32(cpu_SR
[ACCHI
], 0);
2146 tcg_gen_sari_i32(cpu_SR
[ACCHI
], cpu_SR
[ACCLO
], 31);
2149 TCGv_i32 res
= tcg_temp_new_i32();
2150 TCGv_i64 res64
= tcg_temp_new_i64();
2151 TCGv_i64 tmp
= tcg_temp_new_i64();
2153 tcg_gen_mul_i32(res
, m1
, m2
);
2154 tcg_gen_ext_i32_i64(res64
, res
);
2155 tcg_gen_concat_i32_i64(tmp
,
2156 cpu_SR
[ACCLO
], cpu_SR
[ACCHI
]);
2157 if (op
== MAC16_MULA
) {
2158 tcg_gen_add_i64(tmp
, tmp
, res64
);
2160 tcg_gen_sub_i64(tmp
, tmp
, res64
);
2162 tcg_gen_trunc_i64_i32(cpu_SR
[ACCLO
], tmp
);
2163 tcg_gen_shri_i64(tmp
, tmp
, 32);
2164 tcg_gen_trunc_i64_i32(cpu_SR
[ACCHI
], tmp
);
2165 tcg_gen_ext8s_i32(cpu_SR
[ACCHI
], cpu_SR
[ACCHI
]);
2168 tcg_temp_free_i64(res64
);
2169 tcg_temp_free_i64(tmp
);
2175 tcg_gen_mov_i32(cpu_R
[RRR_S
], vaddr
);
2176 tcg_gen_mov_i32(cpu_SR
[MR
+ RRR_W
], mem32
);
2178 tcg_temp_free(vaddr
);
2179 tcg_temp_free(mem32
);
2187 tcg_gen_movi_i32(cpu_R
[0], dc
->next_pc
);
2188 gen_jumpi(dc
, (dc
->pc
& ~3) + (CALL_OFFSET_SE
<< 2) + 4, 0);
2194 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
2195 gen_window_check1(dc
, CALL_N
<< 2);
2196 gen_callwi(dc
, CALL_N
,
2197 (dc
->pc
& ~3) + (CALL_OFFSET_SE
<< 2) + 4, 0);
2205 gen_jumpi(dc
, dc
->pc
+ 4 + CALL_OFFSET_SE
, 0);
2209 gen_window_check1(dc
, BRI12_S
);
2211 static const TCGCond cond
[] = {
2212 TCG_COND_EQ
, /*BEQZ*/
2213 TCG_COND_NE
, /*BNEZ*/
2214 TCG_COND_LT
, /*BLTZ*/
2215 TCG_COND_GE
, /*BGEZ*/
2218 gen_brcondi(dc
, cond
[BRI12_M
& 3], cpu_R
[BRI12_S
], 0,
2219 4 + BRI12_IMM12_SE
);
2224 gen_window_check1(dc
, BRI8_S
);
2226 static const TCGCond cond
[] = {
2227 TCG_COND_EQ
, /*BEQI*/
2228 TCG_COND_NE
, /*BNEI*/
2229 TCG_COND_LT
, /*BLTI*/
2230 TCG_COND_GE
, /*BGEI*/
2233 gen_brcondi(dc
, cond
[BRI8_M
& 3],
2234 cpu_R
[BRI8_S
], B4CONST
[BRI8_R
], 4 + BRI8_IMM8_SE
);
2241 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
2243 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
2244 TCGv_i32 s
= tcg_const_i32(BRI12_S
);
2245 TCGv_i32 imm
= tcg_const_i32(BRI12_IMM12
);
2246 gen_advance_ccount(dc
);
2247 gen_helper_entry(pc
, s
, imm
);
2251 reset_used_window(dc
);
2259 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
2261 TCGv_i32 tmp
= tcg_temp_new_i32();
2262 tcg_gen_andi_i32(tmp
, cpu_SR
[BR
], 1 << RRI8_S
);
2264 BRI8_R
== 1 ? TCG_COND_NE
: TCG_COND_EQ
,
2265 tmp
, 0, 4 + RRI8_IMM8_SE
);
2272 case 10: /*LOOPGTZ*/
2273 HAS_OPTION(XTENSA_OPTION_LOOP
);
2274 gen_window_check1(dc
, RRI8_S
);
2276 uint32_t lend
= dc
->pc
+ RRI8_IMM8
+ 4;
2277 TCGv_i32 tmp
= tcg_const_i32(lend
);
2279 tcg_gen_subi_i32(cpu_SR
[LCOUNT
], cpu_R
[RRI8_S
], 1);
2280 tcg_gen_movi_i32(cpu_SR
[LBEG
], dc
->next_pc
);
2281 gen_helper_wsr_lend(tmp
);
2285 int label
= gen_new_label();
2286 tcg_gen_brcondi_i32(
2287 BRI8_R
== 9 ? TCG_COND_NE
: TCG_COND_GT
,
2288 cpu_R
[RRI8_S
], 0, label
);
2289 gen_jumpi(dc
, lend
, 1);
2290 gen_set_label(label
);
2293 gen_jumpi(dc
, dc
->next_pc
, 0);
2297 default: /*reserved*/
2306 gen_window_check1(dc
, BRI8_S
);
2307 gen_brcondi(dc
, BRI8_M
== 2 ? TCG_COND_LTU
: TCG_COND_GEU
,
2308 cpu_R
[BRI8_S
], B4CONSTU
[BRI8_R
], 4 + BRI8_IMM8_SE
);
2318 TCGCond eq_ne
= (RRI8_R
& 8) ? TCG_COND_NE
: TCG_COND_EQ
;
2320 switch (RRI8_R
& 7) {
2321 case 0: /*BNONE*/ /*BANY*/
2322 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2324 TCGv_i32 tmp
= tcg_temp_new_i32();
2325 tcg_gen_and_i32(tmp
, cpu_R
[RRI8_S
], cpu_R
[RRI8_T
]);
2326 gen_brcondi(dc
, eq_ne
, tmp
, 0, 4 + RRI8_IMM8_SE
);
2331 case 1: /*BEQ*/ /*BNE*/
2332 case 2: /*BLT*/ /*BGE*/
2333 case 3: /*BLTU*/ /*BGEU*/
2334 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2336 static const TCGCond cond
[] = {
2342 [11] = TCG_COND_GEU
,
2344 gen_brcond(dc
, cond
[RRI8_R
], cpu_R
[RRI8_S
], cpu_R
[RRI8_T
],
2349 case 4: /*BALL*/ /*BNALL*/
2350 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2352 TCGv_i32 tmp
= tcg_temp_new_i32();
2353 tcg_gen_and_i32(tmp
, cpu_R
[RRI8_S
], cpu_R
[RRI8_T
]);
2354 gen_brcond(dc
, eq_ne
, tmp
, cpu_R
[RRI8_T
],
2360 case 5: /*BBC*/ /*BBS*/
2361 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2363 TCGv_i32 bit
= tcg_const_i32(1);
2364 TCGv_i32 tmp
= tcg_temp_new_i32();
2365 tcg_gen_andi_i32(tmp
, cpu_R
[RRI8_T
], 0x1f);
2366 tcg_gen_shl_i32(bit
, bit
, tmp
);
2367 tcg_gen_and_i32(tmp
, cpu_R
[RRI8_S
], bit
);
2368 gen_brcondi(dc
, eq_ne
, tmp
, 0, 4 + RRI8_IMM8_SE
);
2374 case 6: /*BBCI*/ /*BBSI*/
2376 gen_window_check1(dc
, RRI8_S
);
2378 TCGv_i32 tmp
= tcg_temp_new_i32();
2379 tcg_gen_andi_i32(tmp
, cpu_R
[RRI8_S
],
2380 1 << (((RRI8_R
& 1) << 4) | RRI8_T
));
2381 gen_brcondi(dc
, eq_ne
, tmp
, 0, 4 + RRI8_IMM8_SE
);
2390 #define gen_narrow_load_store(type) do { \
2391 TCGv_i32 addr = tcg_temp_new_i32(); \
2392 gen_window_check2(dc, RRRN_S, RRRN_T); \
2393 tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
2394 gen_load_store_alignment(dc, 2, addr, false); \
2395 tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, dc->cring); \
2396 tcg_temp_free(addr); \
2400 gen_narrow_load_store(ld32u
);
2404 gen_narrow_load_store(st32
);
2406 #undef gen_narrow_load_store
2409 gen_window_check3(dc
, RRRN_R
, RRRN_S
, RRRN_T
);
2410 tcg_gen_add_i32(cpu_R
[RRRN_R
], cpu_R
[RRRN_S
], cpu_R
[RRRN_T
]);
2413 case 11: /*ADDI.Nn*/
2414 gen_window_check2(dc
, RRRN_R
, RRRN_S
);
2415 tcg_gen_addi_i32(cpu_R
[RRRN_R
], cpu_R
[RRRN_S
], RRRN_T
? RRRN_T
: -1);
2419 gen_window_check1(dc
, RRRN_S
);
2420 if (RRRN_T
< 8) { /*MOVI.Nn*/
2421 tcg_gen_movi_i32(cpu_R
[RRRN_S
],
2422 RRRN_R
| (RRRN_T
<< 4) |
2423 ((RRRN_T
& 6) == 6 ? 0xffffff80 : 0));
2424 } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/
2425 TCGCond eq_ne
= (RRRN_T
& 4) ? TCG_COND_NE
: TCG_COND_EQ
;
2427 gen_brcondi(dc
, eq_ne
, cpu_R
[RRRN_S
], 0,
2428 4 + (RRRN_R
| ((RRRN_T
& 3) << 4)));
2435 gen_window_check2(dc
, RRRN_S
, RRRN_T
);
2436 tcg_gen_mov_i32(cpu_R
[RRRN_T
], cpu_R
[RRRN_S
]);
2442 gen_jump(dc
, cpu_R
[0]);
2446 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
2448 TCGv_i32 tmp
= tcg_const_i32(dc
->pc
);
2449 gen_advance_ccount(dc
);
2450 gen_helper_retw(tmp
, tmp
);
2456 case 2: /*BREAK.Nn*/
2457 HAS_OPTION(XTENSA_OPTION_DEBUG
);
2459 gen_debug_exception(dc
, DEBUGCAUSE_BN
);
2467 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
2470 default: /*reserved*/
2476 default: /*reserved*/
2482 default: /*reserved*/
2487 gen_check_loop_end(dc
, 0);
2488 dc
->pc
= dc
->next_pc
;
2493 qemu_log("INVALID(pc = %08x)\n", dc
->pc
);
2494 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
2498 static void check_breakpoint(CPUXtensaState
*env
, DisasContext
*dc
)
2502 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
2503 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
2504 if (bp
->pc
== dc
->pc
) {
2505 tcg_gen_movi_i32(cpu_pc
, dc
->pc
);
2506 gen_exception(dc
, EXCP_DEBUG
);
2507 dc
->is_jmp
= DISAS_UPDATE
;
2513 static void gen_ibreak_check(CPUXtensaState
*env
, DisasContext
*dc
)
2517 for (i
= 0; i
< dc
->config
->nibreak
; ++i
) {
2518 if ((env
->sregs
[IBREAKENABLE
] & (1 << i
)) &&
2519 env
->sregs
[IBREAKA
+ i
] == dc
->pc
) {
2520 gen_debug_exception(dc
, DEBUGCAUSE_IB
);
2526 static void gen_intermediate_code_internal(
2527 CPUXtensaState
*env
, TranslationBlock
*tb
, int search_pc
)
2532 uint16_t *gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
2533 int max_insns
= tb
->cflags
& CF_COUNT_MASK
;
2534 uint32_t pc_start
= tb
->pc
;
2535 uint32_t next_page_start
=
2536 (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
2538 if (max_insns
== 0) {
2539 max_insns
= CF_COUNT_MASK
;
2542 dc
.config
= env
->config
;
2543 dc
.singlestep_enabled
= env
->singlestep_enabled
;
2546 dc
.ring
= tb
->flags
& XTENSA_TBFLAG_RING_MASK
;
2547 dc
.cring
= (tb
->flags
& XTENSA_TBFLAG_EXCM
) ? 0 : dc
.ring
;
2548 dc
.lbeg
= env
->sregs
[LBEG
];
2549 dc
.lend
= env
->sregs
[LEND
];
2550 dc
.is_jmp
= DISAS_NEXT
;
2551 dc
.ccount_delta
= 0;
2552 dc
.debug
= tb
->flags
& XTENSA_TBFLAG_DEBUG
;
2553 dc
.icount
= tb
->flags
& XTENSA_TBFLAG_ICOUNT
;
2556 init_sar_tracker(&dc
);
2557 reset_used_window(&dc
);
2559 dc
.next_icount
= tcg_temp_local_new_i32();
2564 if (env
->singlestep_enabled
&& env
->exception_taken
) {
2565 env
->exception_taken
= 0;
2566 tcg_gen_movi_i32(cpu_pc
, dc
.pc
);
2567 gen_exception(&dc
, EXCP_DEBUG
);
2571 check_breakpoint(env
, &dc
);
2574 j
= gen_opc_ptr
- gen_opc_buf
;
2578 gen_opc_instr_start
[lj
++] = 0;
2581 gen_opc_pc
[lj
] = dc
.pc
;
2582 gen_opc_instr_start
[lj
] = 1;
2583 gen_opc_icount
[lj
] = insn_count
;
2586 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
))) {
2587 tcg_gen_debug_insn_start(dc
.pc
);
2592 if (insn_count
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
2597 int label
= gen_new_label();
2599 tcg_gen_addi_i32(dc
.next_icount
, cpu_SR
[ICOUNT
], 1);
2600 tcg_gen_brcondi_i32(TCG_COND_NE
, dc
.next_icount
, 0, label
);
2601 tcg_gen_mov_i32(dc
.next_icount
, cpu_SR
[ICOUNT
]);
2603 gen_debug_exception(&dc
, DEBUGCAUSE_IC
);
2605 gen_set_label(label
);
2609 gen_ibreak_check(env
, &dc
);
2612 disas_xtensa_insn(&dc
);
2615 tcg_gen_mov_i32(cpu_SR
[ICOUNT
], dc
.next_icount
);
2617 if (env
->singlestep_enabled
) {
2618 tcg_gen_movi_i32(cpu_pc
, dc
.pc
);
2619 gen_exception(&dc
, EXCP_DEBUG
);
2622 } while (dc
.is_jmp
== DISAS_NEXT
&&
2623 insn_count
< max_insns
&&
2624 dc
.pc
< next_page_start
&&
2625 gen_opc_ptr
< gen_opc_end
);
2628 reset_sar_tracker(&dc
);
2630 tcg_temp_free(dc
.next_icount
);
2633 if (tb
->cflags
& CF_LAST_IO
) {
2637 if (dc
.is_jmp
== DISAS_NEXT
) {
2638 gen_jumpi(&dc
, dc
.pc
, 0);
2640 gen_icount_end(tb
, insn_count
);
2641 *gen_opc_ptr
= INDEX_op_end
;
2644 tb
->size
= dc
.pc
- pc_start
;
2645 tb
->icount
= insn_count
;
2649 void gen_intermediate_code(CPUXtensaState
*env
, TranslationBlock
*tb
)
2651 gen_intermediate_code_internal(env
, tb
, 0);
2654 void gen_intermediate_code_pc(CPUXtensaState
*env
, TranslationBlock
*tb
)
2656 gen_intermediate_code_internal(env
, tb
, 1);
2659 void cpu_dump_state(CPUXtensaState
*env
, FILE *f
, fprintf_function cpu_fprintf
,
2664 cpu_fprintf(f
, "PC=%08x\n\n", env
->pc
);
2666 for (i
= j
= 0; i
< 256; ++i
) {
2668 cpu_fprintf(f
, "%s=%08x%c", sregnames
[i
], env
->sregs
[i
],
2669 (j
++ % 4) == 3 ? '\n' : ' ');
2673 cpu_fprintf(f
, (j
% 4) == 0 ? "\n" : "\n\n");
2675 for (i
= j
= 0; i
< 256; ++i
) {
2677 cpu_fprintf(f
, "%s=%08x%c", uregnames
[i
], env
->uregs
[i
],
2678 (j
++ % 4) == 3 ? '\n' : ' ');
2682 cpu_fprintf(f
, (j
% 4) == 0 ? "\n" : "\n\n");
2684 for (i
= 0; i
< 16; ++i
) {
2685 cpu_fprintf(f
, "A%02d=%08x%c", i
, env
->regs
[i
],
2686 (i
% 4) == 3 ? '\n' : ' ');
2689 cpu_fprintf(f
, "\n");
2691 for (i
= 0; i
< env
->config
->nareg
; ++i
) {
2692 cpu_fprintf(f
, "AR%02d=%08x%c", i
, env
->phys_regs
[i
],
2693 (i
% 4) == 3 ? '\n' : ' ');
2697 void restore_state_to_opc(CPUXtensaState
*env
, TranslationBlock
*tb
, int pc_pos
)
2699 env
->pc
= gen_opc_pc
[pc_pos
];