3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 typedef struct DisasContext
{
45 const XtensaConfig
*config
;
55 int singlestep_enabled
;
59 bool sar_m32_allocated
;
62 uint32_t ccount_delta
;
70 static TCGv_ptr cpu_env
;
71 static TCGv_i32 cpu_pc
;
72 static TCGv_i32 cpu_R
[16];
73 static TCGv_i32 cpu_FR
[16];
74 static TCGv_i32 cpu_SR
[256];
75 static TCGv_i32 cpu_UR
[256];
77 #include "gen-icount.h"
79 static const char * const sregnames
[256] = {
85 [LITBASE
] = "LITBASE",
86 [SCOMPARE1
] = "SCOMPARE1",
93 [WINDOW_BASE
] = "WINDOW_BASE",
94 [WINDOW_START
] = "WINDOW_START",
95 [PTEVADDR
] = "PTEVADDR",
97 [ITLBCFG
] = "ITLBCFG",
98 [DTLBCFG
] = "DTLBCFG",
99 [IBREAKENABLE
] = "IBREAKENABLE",
100 [IBREAKA
] = "IBREAKA0",
101 [IBREAKA
+ 1] = "IBREAKA1",
102 [DBREAKA
] = "DBREAKA0",
103 [DBREAKA
+ 1] = "DBREAKA1",
104 [DBREAKC
] = "DBREAKC0",
105 [DBREAKC
+ 1] = "DBREAKC1",
120 [EXCSAVE1
] = "EXCSAVE1",
121 [EXCSAVE1
+ 1] = "EXCSAVE2",
122 [EXCSAVE1
+ 2] = "EXCSAVE3",
123 [EXCSAVE1
+ 3] = "EXCSAVE4",
124 [EXCSAVE1
+ 4] = "EXCSAVE5",
125 [EXCSAVE1
+ 5] = "EXCSAVE6",
126 [EXCSAVE1
+ 6] = "EXCSAVE7",
127 [CPENABLE
] = "CPENABLE",
129 [INTCLEAR
] = "INTCLEAR",
130 [INTENABLE
] = "INTENABLE",
132 [VECBASE
] = "VECBASE",
133 [EXCCAUSE
] = "EXCCAUSE",
134 [DEBUGCAUSE
] = "DEBUGCAUSE",
138 [ICOUNTLEVEL
] = "ICOUNTLEVEL",
139 [EXCVADDR
] = "EXCVADDR",
140 [CCOMPARE
] = "CCOMPARE0",
141 [CCOMPARE
+ 1] = "CCOMPARE1",
142 [CCOMPARE
+ 2] = "CCOMPARE2",
145 static const char * const uregnames
[256] = {
146 [THREADPTR
] = "THREADPTR",
151 void xtensa_translate_init(void)
153 static const char * const regnames
[] = {
154 "ar0", "ar1", "ar2", "ar3",
155 "ar4", "ar5", "ar6", "ar7",
156 "ar8", "ar9", "ar10", "ar11",
157 "ar12", "ar13", "ar14", "ar15",
159 static const char * const fregnames
[] = {
160 "f0", "f1", "f2", "f3",
161 "f4", "f5", "f6", "f7",
162 "f8", "f9", "f10", "f11",
163 "f12", "f13", "f14", "f15",
167 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
168 cpu_pc
= tcg_global_mem_new_i32(TCG_AREG0
,
169 offsetof(CPUXtensaState
, pc
), "pc");
171 for (i
= 0; i
< 16; i
++) {
172 cpu_R
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
173 offsetof(CPUXtensaState
, regs
[i
]),
177 for (i
= 0; i
< 16; i
++) {
178 cpu_FR
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
179 offsetof(CPUXtensaState
, fregs
[i
]),
183 for (i
= 0; i
< 256; ++i
) {
185 cpu_SR
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
186 offsetof(CPUXtensaState
, sregs
[i
]),
191 for (i
= 0; i
< 256; ++i
) {
193 cpu_UR
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
194 offsetof(CPUXtensaState
, uregs
[i
]),
202 static inline bool option_bits_enabled(DisasContext
*dc
, uint64_t opt
)
204 return xtensa_option_bits_enabled(dc
->config
, opt
);
207 static inline bool option_enabled(DisasContext
*dc
, int opt
)
209 return xtensa_option_enabled(dc
->config
, opt
);
212 static void init_litbase(DisasContext
*dc
)
214 if (dc
->tb
->flags
& XTENSA_TBFLAG_LITBASE
) {
215 dc
->litbase
= tcg_temp_local_new_i32();
216 tcg_gen_andi_i32(dc
->litbase
, cpu_SR
[LITBASE
], 0xfffff000);
220 static void reset_litbase(DisasContext
*dc
)
222 if (dc
->tb
->flags
& XTENSA_TBFLAG_LITBASE
) {
223 tcg_temp_free(dc
->litbase
);
227 static void init_sar_tracker(DisasContext
*dc
)
229 dc
->sar_5bit
= false;
230 dc
->sar_m32_5bit
= false;
231 dc
->sar_m32_allocated
= false;
234 static void reset_sar_tracker(DisasContext
*dc
)
236 if (dc
->sar_m32_allocated
) {
237 tcg_temp_free(dc
->sar_m32
);
241 static void gen_right_shift_sar(DisasContext
*dc
, TCGv_i32 sa
)
243 tcg_gen_andi_i32(cpu_SR
[SAR
], sa
, 0x1f);
244 if (dc
->sar_m32_5bit
) {
245 tcg_gen_discard_i32(dc
->sar_m32
);
248 dc
->sar_m32_5bit
= false;
251 static void gen_left_shift_sar(DisasContext
*dc
, TCGv_i32 sa
)
253 TCGv_i32 tmp
= tcg_const_i32(32);
254 if (!dc
->sar_m32_allocated
) {
255 dc
->sar_m32
= tcg_temp_local_new_i32();
256 dc
->sar_m32_allocated
= true;
258 tcg_gen_andi_i32(dc
->sar_m32
, sa
, 0x1f);
259 tcg_gen_sub_i32(cpu_SR
[SAR
], tmp
, dc
->sar_m32
);
260 dc
->sar_5bit
= false;
261 dc
->sar_m32_5bit
= true;
265 static void gen_advance_ccount(DisasContext
*dc
)
267 if (dc
->ccount_delta
> 0) {
268 TCGv_i32 tmp
= tcg_const_i32(dc
->ccount_delta
);
269 dc
->ccount_delta
= 0;
270 gen_helper_advance_ccount(cpu_env
, tmp
);
275 static void reset_used_window(DisasContext
*dc
)
280 static void gen_exception(DisasContext
*dc
, int excp
)
282 TCGv_i32 tmp
= tcg_const_i32(excp
);
283 gen_advance_ccount(dc
);
284 gen_helper_exception(cpu_env
, tmp
);
288 static void gen_exception_cause(DisasContext
*dc
, uint32_t cause
)
290 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
291 TCGv_i32 tcause
= tcg_const_i32(cause
);
292 gen_advance_ccount(dc
);
293 gen_helper_exception_cause(cpu_env
, tpc
, tcause
);
295 tcg_temp_free(tcause
);
296 if (cause
== ILLEGAL_INSTRUCTION_CAUSE
||
297 cause
== SYSCALL_CAUSE
) {
298 dc
->is_jmp
= DISAS_UPDATE
;
302 static void gen_exception_cause_vaddr(DisasContext
*dc
, uint32_t cause
,
305 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
306 TCGv_i32 tcause
= tcg_const_i32(cause
);
307 gen_advance_ccount(dc
);
308 gen_helper_exception_cause_vaddr(cpu_env
, tpc
, tcause
, vaddr
);
310 tcg_temp_free(tcause
);
313 static void gen_debug_exception(DisasContext
*dc
, uint32_t cause
)
315 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
316 TCGv_i32 tcause
= tcg_const_i32(cause
);
317 gen_advance_ccount(dc
);
318 gen_helper_debug_exception(cpu_env
, tpc
, tcause
);
320 tcg_temp_free(tcause
);
321 if (cause
& (DEBUGCAUSE_IB
| DEBUGCAUSE_BI
| DEBUGCAUSE_BN
)) {
322 dc
->is_jmp
= DISAS_UPDATE
;
326 static void gen_check_privilege(DisasContext
*dc
)
329 gen_exception_cause(dc
, PRIVILEGED_CAUSE
);
330 dc
->is_jmp
= DISAS_UPDATE
;
334 static void gen_jump_slot(DisasContext
*dc
, TCGv dest
, int slot
)
336 tcg_gen_mov_i32(cpu_pc
, dest
);
337 gen_advance_ccount(dc
);
339 tcg_gen_mov_i32(cpu_SR
[ICOUNT
], dc
->next_icount
);
341 if (dc
->singlestep_enabled
) {
342 gen_exception(dc
, EXCP_DEBUG
);
345 tcg_gen_goto_tb(slot
);
346 tcg_gen_exit_tb((tcg_target_long
)dc
->tb
+ slot
);
351 dc
->is_jmp
= DISAS_UPDATE
;
354 static void gen_jump(DisasContext
*dc
, TCGv dest
)
356 gen_jump_slot(dc
, dest
, -1);
359 static void gen_jumpi(DisasContext
*dc
, uint32_t dest
, int slot
)
361 TCGv_i32 tmp
= tcg_const_i32(dest
);
362 if (((dc
->pc
^ dest
) & TARGET_PAGE_MASK
) != 0) {
365 gen_jump_slot(dc
, tmp
, slot
);
369 static void gen_callw_slot(DisasContext
*dc
, int callinc
, TCGv_i32 dest
,
372 TCGv_i32 tcallinc
= tcg_const_i32(callinc
);
374 tcg_gen_deposit_i32(cpu_SR
[PS
], cpu_SR
[PS
],
375 tcallinc
, PS_CALLINC_SHIFT
, PS_CALLINC_LEN
);
376 tcg_temp_free(tcallinc
);
377 tcg_gen_movi_i32(cpu_R
[callinc
<< 2],
378 (callinc
<< 30) | (dc
->next_pc
& 0x3fffffff));
379 gen_jump_slot(dc
, dest
, slot
);
382 static void gen_callw(DisasContext
*dc
, int callinc
, TCGv_i32 dest
)
384 gen_callw_slot(dc
, callinc
, dest
, -1);
387 static void gen_callwi(DisasContext
*dc
, int callinc
, uint32_t dest
, int slot
)
389 TCGv_i32 tmp
= tcg_const_i32(dest
);
390 if (((dc
->pc
^ dest
) & TARGET_PAGE_MASK
) != 0) {
393 gen_callw_slot(dc
, callinc
, tmp
, slot
);
397 static bool gen_check_loop_end(DisasContext
*dc
, int slot
)
399 if (option_enabled(dc
, XTENSA_OPTION_LOOP
) &&
400 !(dc
->tb
->flags
& XTENSA_TBFLAG_EXCM
) &&
401 dc
->next_pc
== dc
->lend
) {
402 int label
= gen_new_label();
404 gen_advance_ccount(dc
);
405 tcg_gen_brcondi_i32(TCG_COND_EQ
, cpu_SR
[LCOUNT
], 0, label
);
406 tcg_gen_subi_i32(cpu_SR
[LCOUNT
], cpu_SR
[LCOUNT
], 1);
407 gen_jumpi(dc
, dc
->lbeg
, slot
);
408 gen_set_label(label
);
409 gen_jumpi(dc
, dc
->next_pc
, -1);
415 static void gen_jumpi_check_loop_end(DisasContext
*dc
, int slot
)
417 if (!gen_check_loop_end(dc
, slot
)) {
418 gen_jumpi(dc
, dc
->next_pc
, slot
);
422 static void gen_brcond(DisasContext
*dc
, TCGCond cond
,
423 TCGv_i32 t0
, TCGv_i32 t1
, uint32_t offset
)
425 int label
= gen_new_label();
427 gen_advance_ccount(dc
);
428 tcg_gen_brcond_i32(cond
, t0
, t1
, label
);
429 gen_jumpi_check_loop_end(dc
, 0);
430 gen_set_label(label
);
431 gen_jumpi(dc
, dc
->pc
+ offset
, 1);
434 static void gen_brcondi(DisasContext
*dc
, TCGCond cond
,
435 TCGv_i32 t0
, uint32_t t1
, uint32_t offset
)
437 TCGv_i32 tmp
= tcg_const_i32(t1
);
438 gen_brcond(dc
, cond
, t0
, tmp
, offset
);
442 static void gen_rsr_ccount(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
444 gen_advance_ccount(dc
);
445 tcg_gen_mov_i32(d
, cpu_SR
[sr
]);
448 static void gen_rsr_ptevaddr(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
450 tcg_gen_shri_i32(d
, cpu_SR
[EXCVADDR
], 10);
451 tcg_gen_or_i32(d
, d
, cpu_SR
[sr
]);
452 tcg_gen_andi_i32(d
, d
, 0xfffffffc);
455 static void gen_rsr(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
457 static void (* const rsr_handler
[256])(DisasContext
*dc
,
458 TCGv_i32 d
, uint32_t sr
) = {
459 [CCOUNT
] = gen_rsr_ccount
,
460 [PTEVADDR
] = gen_rsr_ptevaddr
,
464 if (rsr_handler
[sr
]) {
465 rsr_handler
[sr
](dc
, d
, sr
);
467 tcg_gen_mov_i32(d
, cpu_SR
[sr
]);
470 qemu_log("RSR %d not implemented, ", sr
);
474 static void gen_wsr_lbeg(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
476 gen_helper_wsr_lbeg(cpu_env
, s
);
477 gen_jumpi_check_loop_end(dc
, 0);
480 static void gen_wsr_lend(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
482 gen_helper_wsr_lend(cpu_env
, s
);
483 gen_jumpi_check_loop_end(dc
, 0);
486 static void gen_wsr_sar(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
488 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0x3f);
489 if (dc
->sar_m32_5bit
) {
490 tcg_gen_discard_i32(dc
->sar_m32
);
492 dc
->sar_5bit
= false;
493 dc
->sar_m32_5bit
= false;
496 static void gen_wsr_br(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
498 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0xffff);
501 static void gen_wsr_litbase(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
503 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0xfffff001);
504 /* This can change tb->flags, so exit tb */
505 gen_jumpi_check_loop_end(dc
, -1);
508 static void gen_wsr_acchi(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
510 tcg_gen_ext8s_i32(cpu_SR
[sr
], s
);
513 static void gen_wsr_windowbase(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
515 gen_helper_wsr_windowbase(cpu_env
, v
);
516 reset_used_window(dc
);
519 static void gen_wsr_windowstart(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
521 tcg_gen_andi_i32(cpu_SR
[sr
], v
, (1 << dc
->config
->nareg
/ 4) - 1);
522 reset_used_window(dc
);
525 static void gen_wsr_ptevaddr(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
527 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0xffc00000);
530 static void gen_wsr_rasid(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
532 gen_helper_wsr_rasid(cpu_env
, v
);
533 /* This can change tb->flags, so exit tb */
534 gen_jumpi_check_loop_end(dc
, -1);
537 static void gen_wsr_tlbcfg(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
539 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0x01130000);
542 static void gen_wsr_ibreakenable(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
544 gen_helper_wsr_ibreakenable(cpu_env
, v
);
545 gen_jumpi_check_loop_end(dc
, 0);
548 static void gen_wsr_ibreaka(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
550 unsigned id
= sr
- IBREAKA
;
552 if (id
< dc
->config
->nibreak
) {
553 TCGv_i32 tmp
= tcg_const_i32(id
);
554 gen_helper_wsr_ibreaka(cpu_env
, tmp
, v
);
556 gen_jumpi_check_loop_end(dc
, 0);
560 static void gen_wsr_dbreaka(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
562 unsigned id
= sr
- DBREAKA
;
564 if (id
< dc
->config
->ndbreak
) {
565 TCGv_i32 tmp
= tcg_const_i32(id
);
566 gen_helper_wsr_dbreaka(cpu_env
, tmp
, v
);
571 static void gen_wsr_dbreakc(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
573 unsigned id
= sr
- DBREAKC
;
575 if (id
< dc
->config
->ndbreak
) {
576 TCGv_i32 tmp
= tcg_const_i32(id
);
577 gen_helper_wsr_dbreakc(cpu_env
, tmp
, v
);
582 static void gen_wsr_intset(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
584 tcg_gen_andi_i32(cpu_SR
[sr
], v
,
585 dc
->config
->inttype_mask
[INTTYPE_SOFTWARE
]);
586 gen_helper_check_interrupts(cpu_env
);
587 gen_jumpi_check_loop_end(dc
, 0);
590 static void gen_wsr_intclear(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
592 TCGv_i32 tmp
= tcg_temp_new_i32();
594 tcg_gen_andi_i32(tmp
, v
,
595 dc
->config
->inttype_mask
[INTTYPE_EDGE
] |
596 dc
->config
->inttype_mask
[INTTYPE_NMI
] |
597 dc
->config
->inttype_mask
[INTTYPE_SOFTWARE
]);
598 tcg_gen_andc_i32(cpu_SR
[INTSET
], cpu_SR
[INTSET
], tmp
);
600 gen_helper_check_interrupts(cpu_env
);
603 static void gen_wsr_intenable(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
605 tcg_gen_mov_i32(cpu_SR
[sr
], v
);
606 gen_helper_check_interrupts(cpu_env
);
607 gen_jumpi_check_loop_end(dc
, 0);
610 static void gen_wsr_ps(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
612 uint32_t mask
= PS_WOE
| PS_CALLINC
| PS_OWB
|
613 PS_UM
| PS_EXCM
| PS_INTLEVEL
;
615 if (option_enabled(dc
, XTENSA_OPTION_MMU
)) {
618 tcg_gen_andi_i32(cpu_SR
[sr
], v
, mask
);
619 reset_used_window(dc
);
620 gen_helper_check_interrupts(cpu_env
);
621 /* This can change mmu index and tb->flags, so exit tb */
622 gen_jumpi_check_loop_end(dc
, -1);
625 static void gen_wsr_debugcause(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
629 static void gen_wsr_prid(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
633 static void gen_wsr_icount(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
636 tcg_gen_mov_i32(dc
->next_icount
, v
);
638 tcg_gen_mov_i32(cpu_SR
[sr
], v
);
642 static void gen_wsr_icountlevel(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
644 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0xf);
645 /* This can change tb->flags, so exit tb */
646 gen_jumpi_check_loop_end(dc
, -1);
649 static void gen_wsr_ccompare(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
651 uint32_t id
= sr
- CCOMPARE
;
652 if (id
< dc
->config
->nccompare
) {
653 uint32_t int_bit
= 1 << dc
->config
->timerint
[id
];
654 gen_advance_ccount(dc
);
655 tcg_gen_mov_i32(cpu_SR
[sr
], v
);
656 tcg_gen_andi_i32(cpu_SR
[INTSET
], cpu_SR
[INTSET
], ~int_bit
);
657 gen_helper_check_interrupts(cpu_env
);
661 static void gen_wsr(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
663 static void (* const wsr_handler
[256])(DisasContext
*dc
,
664 uint32_t sr
, TCGv_i32 v
) = {
665 [LBEG
] = gen_wsr_lbeg
,
666 [LEND
] = gen_wsr_lend
,
669 [LITBASE
] = gen_wsr_litbase
,
670 [ACCHI
] = gen_wsr_acchi
,
671 [WINDOW_BASE
] = gen_wsr_windowbase
,
672 [WINDOW_START
] = gen_wsr_windowstart
,
673 [PTEVADDR
] = gen_wsr_ptevaddr
,
674 [RASID
] = gen_wsr_rasid
,
675 [ITLBCFG
] = gen_wsr_tlbcfg
,
676 [DTLBCFG
] = gen_wsr_tlbcfg
,
677 [IBREAKENABLE
] = gen_wsr_ibreakenable
,
678 [IBREAKA
] = gen_wsr_ibreaka
,
679 [IBREAKA
+ 1] = gen_wsr_ibreaka
,
680 [DBREAKA
] = gen_wsr_dbreaka
,
681 [DBREAKA
+ 1] = gen_wsr_dbreaka
,
682 [DBREAKC
] = gen_wsr_dbreakc
,
683 [DBREAKC
+ 1] = gen_wsr_dbreakc
,
684 [INTSET
] = gen_wsr_intset
,
685 [INTCLEAR
] = gen_wsr_intclear
,
686 [INTENABLE
] = gen_wsr_intenable
,
688 [DEBUGCAUSE
] = gen_wsr_debugcause
,
689 [PRID
] = gen_wsr_prid
,
690 [ICOUNT
] = gen_wsr_icount
,
691 [ICOUNTLEVEL
] = gen_wsr_icountlevel
,
692 [CCOMPARE
] = gen_wsr_ccompare
,
693 [CCOMPARE
+ 1] = gen_wsr_ccompare
,
694 [CCOMPARE
+ 2] = gen_wsr_ccompare
,
698 if (wsr_handler
[sr
]) {
699 wsr_handler
[sr
](dc
, sr
, s
);
701 tcg_gen_mov_i32(cpu_SR
[sr
], s
);
704 qemu_log("WSR %d not implemented, ", sr
);
708 static void gen_wur(uint32_t ur
, TCGv_i32 s
)
712 gen_helper_wur_fcr(cpu_env
, s
);
716 tcg_gen_andi_i32(cpu_UR
[ur
], s
, 0xffffff80);
720 tcg_gen_mov_i32(cpu_UR
[ur
], s
);
725 static void gen_load_store_alignment(DisasContext
*dc
, int shift
,
726 TCGv_i32 addr
, bool no_hw_alignment
)
728 if (!option_enabled(dc
, XTENSA_OPTION_UNALIGNED_EXCEPTION
)) {
729 tcg_gen_andi_i32(addr
, addr
, ~0 << shift
);
730 } else if (option_enabled(dc
, XTENSA_OPTION_HW_ALIGNMENT
) &&
732 int label
= gen_new_label();
733 TCGv_i32 tmp
= tcg_temp_new_i32();
734 tcg_gen_andi_i32(tmp
, addr
, ~(~0 << shift
));
735 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
736 gen_exception_cause_vaddr(dc
, LOAD_STORE_ALIGNMENT_CAUSE
, addr
);
737 gen_set_label(label
);
742 static void gen_waiti(DisasContext
*dc
, uint32_t imm4
)
744 TCGv_i32 pc
= tcg_const_i32(dc
->next_pc
);
745 TCGv_i32 intlevel
= tcg_const_i32(imm4
);
746 gen_advance_ccount(dc
);
747 gen_helper_waiti(cpu_env
, pc
, intlevel
);
749 tcg_temp_free(intlevel
);
752 static void gen_window_check1(DisasContext
*dc
, unsigned r1
)
754 if (dc
->tb
->flags
& XTENSA_TBFLAG_EXCM
) {
757 if (option_enabled(dc
, XTENSA_OPTION_WINDOWED_REGISTER
) &&
758 r1
/ 4 > dc
->used_window
) {
759 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
760 TCGv_i32 w
= tcg_const_i32(r1
/ 4);
762 dc
->used_window
= r1
/ 4;
763 gen_advance_ccount(dc
);
764 gen_helper_window_check(cpu_env
, pc
, w
);
771 static void gen_window_check2(DisasContext
*dc
, unsigned r1
, unsigned r2
)
773 gen_window_check1(dc
, r1
> r2
? r1
: r2
);
776 static void gen_window_check3(DisasContext
*dc
, unsigned r1
, unsigned r2
,
779 gen_window_check2(dc
, r1
, r2
> r3
? r2
: r3
);
782 static TCGv_i32
gen_mac16_m(TCGv_i32 v
, bool hi
, bool is_unsigned
)
784 TCGv_i32 m
= tcg_temp_new_i32();
787 (is_unsigned
? tcg_gen_shri_i32
: tcg_gen_sari_i32
)(m
, v
, 16);
789 (is_unsigned
? tcg_gen_ext16u_i32
: tcg_gen_ext16s_i32
)(m
, v
);
794 static void disas_xtensa_insn(DisasContext
*dc
)
796 #define HAS_OPTION_BITS(opt) do { \
797 if (!option_bits_enabled(dc, opt)) { \
798 qemu_log("Option is not enabled %s:%d\n", \
799 __FILE__, __LINE__); \
800 goto invalid_opcode; \
804 #define HAS_OPTION(opt) HAS_OPTION_BITS(XTENSA_OPTION_BIT(opt))
806 #define TBD() qemu_log("TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)
807 #define RESERVED() do { \
808 qemu_log("RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \
809 dc->pc, b0, b1, b2, __FILE__, __LINE__); \
810 goto invalid_opcode; \
814 #ifdef TARGET_WORDS_BIGENDIAN
815 #define OP0 (((b0) & 0xf0) >> 4)
816 #define OP1 (((b2) & 0xf0) >> 4)
817 #define OP2 ((b2) & 0xf)
818 #define RRR_R ((b1) & 0xf)
819 #define RRR_S (((b1) & 0xf0) >> 4)
820 #define RRR_T ((b0) & 0xf)
822 #define OP0 (((b0) & 0xf))
823 #define OP1 (((b2) & 0xf))
824 #define OP2 (((b2) & 0xf0) >> 4)
825 #define RRR_R (((b1) & 0xf0) >> 4)
826 #define RRR_S (((b1) & 0xf))
827 #define RRR_T (((b0) & 0xf0) >> 4)
829 #define RRR_X ((RRR_R & 0x4) >> 2)
830 #define RRR_Y ((RRR_T & 0x4) >> 2)
831 #define RRR_W (RRR_R & 0x3)
840 #define RRI8_IMM8 (b2)
841 #define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)
843 #ifdef TARGET_WORDS_BIGENDIAN
844 #define RI16_IMM16 (((b1) << 8) | (b2))
846 #define RI16_IMM16 (((b2) << 8) | (b1))
849 #ifdef TARGET_WORDS_BIGENDIAN
850 #define CALL_N (((b0) & 0xc) >> 2)
851 #define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))
853 #define CALL_N (((b0) & 0x30) >> 4)
854 #define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))
856 #define CALL_OFFSET_SE \
857 (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)
859 #define CALLX_N CALL_N
860 #ifdef TARGET_WORDS_BIGENDIAN
861 #define CALLX_M ((b0) & 0x3)
863 #define CALLX_M (((b0) & 0xc0) >> 6)
865 #define CALLX_S RRR_S
867 #define BRI12_M CALLX_M
868 #define BRI12_S RRR_S
869 #ifdef TARGET_WORDS_BIGENDIAN
870 #define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))
872 #define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))
874 #define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)
876 #define BRI8_M BRI12_M
877 #define BRI8_R RRI8_R
878 #define BRI8_S RRI8_S
879 #define BRI8_IMM8 RRI8_IMM8
880 #define BRI8_IMM8_SE RRI8_IMM8_SE
884 uint8_t b0
= cpu_ldub_code(cpu_single_env
, dc
->pc
);
885 uint8_t b1
= cpu_ldub_code(cpu_single_env
, dc
->pc
+ 1);
888 static const uint32_t B4CONST
[] = {
889 0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
892 static const uint32_t B4CONSTU
[] = {
893 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
897 dc
->next_pc
= dc
->pc
+ 2;
898 HAS_OPTION(XTENSA_OPTION_CODE_DENSITY
);
900 dc
->next_pc
= dc
->pc
+ 3;
901 b2
= cpu_ldub_code(cpu_single_env
, dc
->pc
+ 2);
910 if ((RRR_R
& 0xc) == 0x8) {
911 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
918 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
929 gen_window_check1(dc
, CALLX_S
);
930 gen_jump(dc
, cpu_R
[CALLX_S
]);
934 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
936 TCGv_i32 tmp
= tcg_const_i32(dc
->pc
);
937 gen_advance_ccount(dc
);
938 gen_helper_retw(tmp
, cpu_env
, tmp
);
951 gen_window_check2(dc
, CALLX_S
, CALLX_N
<< 2);
955 TCGv_i32 tmp
= tcg_temp_new_i32();
956 tcg_gen_mov_i32(tmp
, cpu_R
[CALLX_S
]);
957 tcg_gen_movi_i32(cpu_R
[0], dc
->next_pc
);
966 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
968 TCGv_i32 tmp
= tcg_temp_new_i32();
970 tcg_gen_mov_i32(tmp
, cpu_R
[CALLX_S
]);
971 gen_callw(dc
, CALLX_N
, tmp
);
981 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
982 gen_window_check2(dc
, RRR_T
, RRR_S
);
984 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
985 gen_advance_ccount(dc
);
986 gen_helper_movsp(cpu_env
, pc
);
987 tcg_gen_mov_i32(cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
1007 HAS_OPTION(XTENSA_OPTION_EXCEPTION
);
1019 default: /*reserved*/
1028 HAS_OPTION(XTENSA_OPTION_EXCEPTION
);
1031 gen_check_privilege(dc
);
1032 tcg_gen_andi_i32(cpu_SR
[PS
], cpu_SR
[PS
], ~PS_EXCM
);
1033 gen_helper_check_interrupts(cpu_env
);
1034 gen_jump(dc
, cpu_SR
[EPC1
]);
1042 gen_check_privilege(dc
);
1043 gen_jump(dc
, cpu_SR
[
1044 dc
->config
->ndepc
? DEPC
: EPC1
]);
1049 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1050 gen_check_privilege(dc
);
1052 TCGv_i32 tmp
= tcg_const_i32(1);
1055 cpu_SR
[PS
], cpu_SR
[PS
], ~PS_EXCM
);
1056 tcg_gen_shl_i32(tmp
, tmp
, cpu_SR
[WINDOW_BASE
]);
1059 tcg_gen_andc_i32(cpu_SR
[WINDOW_START
],
1060 cpu_SR
[WINDOW_START
], tmp
);
1062 tcg_gen_or_i32(cpu_SR
[WINDOW_START
],
1063 cpu_SR
[WINDOW_START
], tmp
);
1066 gen_helper_restore_owb(cpu_env
);
1067 gen_helper_check_interrupts(cpu_env
);
1068 gen_jump(dc
, cpu_SR
[EPC1
]);
1074 default: /*reserved*/
1081 HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
);
1082 if (RRR_S
>= 2 && RRR_S
<= dc
->config
->nlevel
) {
1083 gen_check_privilege(dc
);
1084 tcg_gen_mov_i32(cpu_SR
[PS
],
1085 cpu_SR
[EPS2
+ RRR_S
- 2]);
1086 gen_helper_check_interrupts(cpu_env
);
1087 gen_jump(dc
, cpu_SR
[EPC1
+ RRR_S
- 1]);
1089 qemu_log("RFI %d is illegal\n", RRR_S
);
1090 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
1098 default: /*reserved*/
1106 HAS_OPTION(XTENSA_OPTION_DEBUG
);
1108 gen_debug_exception(dc
, DEBUGCAUSE_BI
);
1112 case 5: /*SYSCALLx*/
1113 HAS_OPTION(XTENSA_OPTION_EXCEPTION
);
1115 case 0: /*SYSCALLx*/
1116 gen_exception_cause(dc
, SYSCALL_CAUSE
);
1120 if (semihosting_enabled
) {
1121 gen_check_privilege(dc
);
1122 gen_helper_simcall(cpu_env
);
1124 qemu_log("SIMCALL but semihosting is disabled\n");
1125 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
1136 HAS_OPTION(XTENSA_OPTION_INTERRUPT
);
1137 gen_check_privilege(dc
);
1138 gen_window_check1(dc
, RRR_T
);
1139 tcg_gen_mov_i32(cpu_R
[RRR_T
], cpu_SR
[PS
]);
1140 tcg_gen_andi_i32(cpu_SR
[PS
], cpu_SR
[PS
], ~PS_INTLEVEL
);
1141 tcg_gen_ori_i32(cpu_SR
[PS
], cpu_SR
[PS
], RRR_S
);
1142 gen_helper_check_interrupts(cpu_env
);
1143 gen_jumpi_check_loop_end(dc
, 0);
1147 HAS_OPTION(XTENSA_OPTION_INTERRUPT
);
1148 gen_check_privilege(dc
);
1149 gen_waiti(dc
, RRR_S
);
1156 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
1158 const unsigned shift
= (RRR_R
& 2) ? 8 : 4;
1159 TCGv_i32 mask
= tcg_const_i32(
1160 ((1 << shift
) - 1) << RRR_S
);
1161 TCGv_i32 tmp
= tcg_temp_new_i32();
1163 tcg_gen_and_i32(tmp
, cpu_SR
[BR
], mask
);
1164 if (RRR_R
& 1) { /*ALL*/
1165 tcg_gen_addi_i32(tmp
, tmp
, 1 << RRR_S
);
1167 tcg_gen_add_i32(tmp
, tmp
, mask
);
1169 tcg_gen_shri_i32(tmp
, tmp
, RRR_S
+ shift
);
1170 tcg_gen_deposit_i32(cpu_SR
[BR
], cpu_SR
[BR
],
1172 tcg_temp_free(mask
);
1177 default: /*reserved*/
1185 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1186 tcg_gen_and_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1190 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1191 tcg_gen_or_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1195 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1196 tcg_gen_xor_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1202 gen_window_check1(dc
, RRR_S
);
1203 gen_right_shift_sar(dc
, cpu_R
[RRR_S
]);
1207 gen_window_check1(dc
, RRR_S
);
1208 gen_left_shift_sar(dc
, cpu_R
[RRR_S
]);
1212 gen_window_check1(dc
, RRR_S
);
1214 TCGv_i32 tmp
= tcg_temp_new_i32();
1215 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], 3);
1216 gen_right_shift_sar(dc
, tmp
);
1222 gen_window_check1(dc
, RRR_S
);
1224 TCGv_i32 tmp
= tcg_temp_new_i32();
1225 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], 3);
1226 gen_left_shift_sar(dc
, tmp
);
1233 TCGv_i32 tmp
= tcg_const_i32(
1234 RRR_S
| ((RRR_T
& 1) << 4));
1235 gen_right_shift_sar(dc
, tmp
);
1249 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1250 gen_check_privilege(dc
);
1252 TCGv_i32 tmp
= tcg_const_i32(
1253 RRR_T
| ((RRR_T
& 8) ? 0xfffffff0 : 0));
1254 gen_helper_rotw(cpu_env
, tmp
);
1256 reset_used_window(dc
);
1261 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA
);
1262 gen_window_check2(dc
, RRR_S
, RRR_T
);
1263 gen_helper_nsa(cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
1267 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA
);
1268 gen_window_check2(dc
, RRR_S
, RRR_T
);
1269 gen_helper_nsau(cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
1272 default: /*reserved*/
1280 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU
) |
1281 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION
) |
1282 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION
));
1283 gen_check_privilege(dc
);
1284 gen_window_check2(dc
, RRR_S
, RRR_T
);
1286 TCGv_i32 dtlb
= tcg_const_i32((RRR_R
& 8) != 0);
1288 switch (RRR_R
& 7) {
1289 case 3: /*RITLB0*/ /*RDTLB0*/
1290 gen_helper_rtlb0(cpu_R
[RRR_T
],
1291 cpu_env
, cpu_R
[RRR_S
], dtlb
);
1294 case 4: /*IITLB*/ /*IDTLB*/
1295 gen_helper_itlb(cpu_env
, cpu_R
[RRR_S
], dtlb
);
1296 /* This could change memory mapping, so exit tb */
1297 gen_jumpi_check_loop_end(dc
, -1);
1300 case 5: /*PITLB*/ /*PDTLB*/
1301 tcg_gen_movi_i32(cpu_pc
, dc
->pc
);
1302 gen_helper_ptlb(cpu_R
[RRR_T
],
1303 cpu_env
, cpu_R
[RRR_S
], dtlb
);
1306 case 6: /*WITLB*/ /*WDTLB*/
1308 cpu_env
, cpu_R
[RRR_T
], cpu_R
[RRR_S
], dtlb
);
1309 /* This could change memory mapping, so exit tb */
1310 gen_jumpi_check_loop_end(dc
, -1);
1313 case 7: /*RITLB1*/ /*RDTLB1*/
1314 gen_helper_rtlb1(cpu_R
[RRR_T
],
1315 cpu_env
, cpu_R
[RRR_S
], dtlb
);
1319 tcg_temp_free(dtlb
);
1323 tcg_temp_free(dtlb
);
1328 gen_window_check2(dc
, RRR_R
, RRR_T
);
1331 tcg_gen_neg_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
1336 int label
= gen_new_label();
1337 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
1338 tcg_gen_brcondi_i32(
1339 TCG_COND_GE
, cpu_R
[RRR_R
], 0, label
);
1340 tcg_gen_neg_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
1341 gen_set_label(label
);
1345 default: /*reserved*/
1351 case 7: /*reserved*/
1356 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1357 tcg_gen_add_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1363 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1365 TCGv_i32 tmp
= tcg_temp_new_i32();
1366 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], OP2
- 8);
1367 tcg_gen_add_i32(cpu_R
[RRR_R
], tmp
, cpu_R
[RRR_T
]);
1373 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1374 tcg_gen_sub_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1380 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1382 TCGv_i32 tmp
= tcg_temp_new_i32();
1383 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], OP2
- 12);
1384 tcg_gen_sub_i32(cpu_R
[RRR_R
], tmp
, cpu_R
[RRR_T
]);
1395 gen_window_check2(dc
, RRR_R
, RRR_S
);
1396 tcg_gen_shli_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
],
1397 32 - (RRR_T
| ((OP2
& 1) << 4)));
1402 gen_window_check2(dc
, RRR_R
, RRR_T
);
1403 tcg_gen_sari_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
],
1404 RRR_S
| ((OP2
& 1) << 4));
1408 gen_window_check2(dc
, RRR_R
, RRR_T
);
1409 tcg_gen_shri_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
], RRR_S
);
1414 TCGv_i32 tmp
= tcg_temp_new_i32();
1416 gen_check_privilege(dc
);
1418 gen_window_check1(dc
, RRR_T
);
1419 tcg_gen_mov_i32(tmp
, cpu_R
[RRR_T
]);
1420 gen_rsr(dc
, cpu_R
[RRR_T
], RSR_SR
);
1421 gen_wsr(dc
, RSR_SR
, tmp
);
1423 if (!sregnames
[RSR_SR
]) {
1430 * Note: 64 bit ops are used here solely because SAR values
1433 #define gen_shift_reg(cmd, reg) do { \
1434 TCGv_i64 tmp = tcg_temp_new_i64(); \
1435 tcg_gen_extu_i32_i64(tmp, reg); \
1436 tcg_gen_##cmd##_i64(v, v, tmp); \
1437 tcg_gen_trunc_i64_i32(cpu_R[RRR_R], v); \
1438 tcg_temp_free_i64(v); \
1439 tcg_temp_free_i64(tmp); \
1442 #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
1445 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1447 TCGv_i64 v
= tcg_temp_new_i64();
1448 tcg_gen_concat_i32_i64(v
, cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
1454 gen_window_check2(dc
, RRR_R
, RRR_T
);
1456 tcg_gen_shr_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
], cpu_SR
[SAR
]);
1458 TCGv_i64 v
= tcg_temp_new_i64();
1459 tcg_gen_extu_i32_i64(v
, cpu_R
[RRR_T
]);
1465 gen_window_check2(dc
, RRR_R
, RRR_S
);
1466 if (dc
->sar_m32_5bit
) {
1467 tcg_gen_shl_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], dc
->sar_m32
);
1469 TCGv_i64 v
= tcg_temp_new_i64();
1470 TCGv_i32 s
= tcg_const_i32(32);
1471 tcg_gen_sub_i32(s
, s
, cpu_SR
[SAR
]);
1472 tcg_gen_andi_i32(s
, s
, 0x3f);
1473 tcg_gen_extu_i32_i64(v
, cpu_R
[RRR_S
]);
1474 gen_shift_reg(shl
, s
);
1480 gen_window_check2(dc
, RRR_R
, RRR_T
);
1482 tcg_gen_sar_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
], cpu_SR
[SAR
]);
1484 TCGv_i64 v
= tcg_temp_new_i64();
1485 tcg_gen_ext_i32_i64(v
, cpu_R
[RRR_T
]);
1490 #undef gen_shift_reg
1493 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL
);
1494 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1496 TCGv_i32 v1
= tcg_temp_new_i32();
1497 TCGv_i32 v2
= tcg_temp_new_i32();
1498 tcg_gen_ext16u_i32(v1
, cpu_R
[RRR_S
]);
1499 tcg_gen_ext16u_i32(v2
, cpu_R
[RRR_T
]);
1500 tcg_gen_mul_i32(cpu_R
[RRR_R
], v1
, v2
);
1507 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL
);
1508 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1510 TCGv_i32 v1
= tcg_temp_new_i32();
1511 TCGv_i32 v2
= tcg_temp_new_i32();
1512 tcg_gen_ext16s_i32(v1
, cpu_R
[RRR_S
]);
1513 tcg_gen_ext16s_i32(v2
, cpu_R
[RRR_T
]);
1514 tcg_gen_mul_i32(cpu_R
[RRR_R
], v1
, v2
);
1520 default: /*reserved*/
1528 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1532 HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV
);
1533 int label
= gen_new_label();
1534 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[RRR_T
], 0, label
);
1535 gen_exception_cause(dc
, INTEGER_DIVIDE_BY_ZERO_CAUSE
);
1536 gen_set_label(label
);
1540 #define BOOLEAN_LOGIC(fn, r, s, t) \
1542 HAS_OPTION(XTENSA_OPTION_BOOLEAN); \
1543 TCGv_i32 tmp1 = tcg_temp_new_i32(); \
1544 TCGv_i32 tmp2 = tcg_temp_new_i32(); \
1546 tcg_gen_shri_i32(tmp1, cpu_SR[BR], s); \
1547 tcg_gen_shri_i32(tmp2, cpu_SR[BR], t); \
1548 tcg_gen_##fn##_i32(tmp1, tmp1, tmp2); \
1549 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, r, 1); \
1550 tcg_temp_free(tmp1); \
1551 tcg_temp_free(tmp2); \
1555 BOOLEAN_LOGIC(and, RRR_R
, RRR_S
, RRR_T
);
1559 BOOLEAN_LOGIC(andc
, RRR_R
, RRR_S
, RRR_T
);
1563 BOOLEAN_LOGIC(or, RRR_R
, RRR_S
, RRR_T
);
1567 BOOLEAN_LOGIC(orc
, RRR_R
, RRR_S
, RRR_T
);
1571 BOOLEAN_LOGIC(xor, RRR_R
, RRR_S
, RRR_T
);
1574 #undef BOOLEAN_LOGIC
1577 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL
);
1578 tcg_gen_mul_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1583 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL_HIGH
);
1585 TCGv_i64 r
= tcg_temp_new_i64();
1586 TCGv_i64 s
= tcg_temp_new_i64();
1587 TCGv_i64 t
= tcg_temp_new_i64();
1590 tcg_gen_extu_i32_i64(s
, cpu_R
[RRR_S
]);
1591 tcg_gen_extu_i32_i64(t
, cpu_R
[RRR_T
]);
1593 tcg_gen_ext_i32_i64(s
, cpu_R
[RRR_S
]);
1594 tcg_gen_ext_i32_i64(t
, cpu_R
[RRR_T
]);
1596 tcg_gen_mul_i64(r
, s
, t
);
1597 tcg_gen_shri_i64(r
, r
, 32);
1598 tcg_gen_trunc_i64_i32(cpu_R
[RRR_R
], r
);
1600 tcg_temp_free_i64(r
);
1601 tcg_temp_free_i64(s
);
1602 tcg_temp_free_i64(t
);
1607 tcg_gen_divu_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1613 int label1
= gen_new_label();
1614 int label2
= gen_new_label();
1616 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[RRR_S
], 0x80000000,
1618 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[RRR_T
], 0xffffffff,
1620 tcg_gen_movi_i32(cpu_R
[RRR_R
],
1621 OP2
== 13 ? 0x80000000 : 0);
1623 gen_set_label(label1
);
1625 tcg_gen_div_i32(cpu_R
[RRR_R
],
1626 cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1628 tcg_gen_rem_i32(cpu_R
[RRR_R
],
1629 cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1631 gen_set_label(label2
);
1636 tcg_gen_remu_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1639 default: /*reserved*/
1649 gen_check_privilege(dc
);
1651 gen_window_check1(dc
, RRR_T
);
1652 gen_rsr(dc
, cpu_R
[RRR_T
], RSR_SR
);
1653 if (!sregnames
[RSR_SR
]) {
1660 gen_check_privilege(dc
);
1662 gen_window_check1(dc
, RRR_T
);
1663 gen_wsr(dc
, RSR_SR
, cpu_R
[RRR_T
]);
1664 if (!sregnames
[RSR_SR
]) {
1670 HAS_OPTION(XTENSA_OPTION_MISC_OP_SEXT
);
1671 gen_window_check2(dc
, RRR_R
, RRR_S
);
1673 int shift
= 24 - RRR_T
;
1676 tcg_gen_ext8s_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1677 } else if (shift
== 16) {
1678 tcg_gen_ext16s_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1680 TCGv_i32 tmp
= tcg_temp_new_i32();
1681 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], shift
);
1682 tcg_gen_sari_i32(cpu_R
[RRR_R
], tmp
, shift
);
1689 HAS_OPTION(XTENSA_OPTION_MISC_OP_CLAMPS
);
1690 gen_window_check2(dc
, RRR_R
, RRR_S
);
1692 TCGv_i32 tmp1
= tcg_temp_new_i32();
1693 TCGv_i32 tmp2
= tcg_temp_new_i32();
1694 int label
= gen_new_label();
1696 tcg_gen_sari_i32(tmp1
, cpu_R
[RRR_S
], 24 - RRR_T
);
1697 tcg_gen_xor_i32(tmp2
, tmp1
, cpu_R
[RRR_S
]);
1698 tcg_gen_andi_i32(tmp2
, tmp2
, 0xffffffff << (RRR_T
+ 7));
1699 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1700 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp2
, 0, label
);
1702 tcg_gen_sari_i32(tmp1
, cpu_R
[RRR_S
], 31);
1703 tcg_gen_xori_i32(cpu_R
[RRR_R
], tmp1
,
1704 0xffffffff >> (25 - RRR_T
));
1706 gen_set_label(label
);
1708 tcg_temp_free(tmp1
);
1709 tcg_temp_free(tmp2
);
1717 HAS_OPTION(XTENSA_OPTION_MISC_OP_MINMAX
);
1718 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1720 static const TCGCond cond
[] = {
1726 int label
= gen_new_label();
1728 if (RRR_R
!= RRR_T
) {
1729 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1730 tcg_gen_brcond_i32(cond
[OP2
- 4],
1731 cpu_R
[RRR_S
], cpu_R
[RRR_T
], label
);
1732 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
1734 tcg_gen_brcond_i32(cond
[OP2
- 4],
1735 cpu_R
[RRR_T
], cpu_R
[RRR_S
], label
);
1736 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1738 gen_set_label(label
);
1746 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1748 static const TCGCond cond
[] = {
1754 int label
= gen_new_label();
1755 tcg_gen_brcondi_i32(cond
[OP2
- 8], cpu_R
[RRR_T
], 0, label
);
1756 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1757 gen_set_label(label
);
1763 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
1764 gen_window_check2(dc
, RRR_R
, RRR_S
);
1766 int label
= gen_new_label();
1767 TCGv_i32 tmp
= tcg_temp_new_i32();
1769 tcg_gen_andi_i32(tmp
, cpu_SR
[BR
], 1 << RRR_T
);
1770 tcg_gen_brcondi_i32(
1771 OP2
& 1 ? TCG_COND_EQ
: TCG_COND_NE
,
1773 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1774 gen_set_label(label
);
1780 gen_window_check1(dc
, RRR_R
);
1782 int st
= (RRR_S
<< 4) + RRR_T
;
1783 if (uregnames
[st
]) {
1784 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_UR
[st
]);
1786 qemu_log("RUR %d not implemented, ", st
);
1793 gen_window_check1(dc
, RRR_T
);
1794 if (uregnames
[RSR_SR
]) {
1795 gen_wur(RSR_SR
, cpu_R
[RRR_T
]);
1797 qemu_log("WUR %d not implemented, ", RSR_SR
);
1807 gen_window_check2(dc
, RRR_R
, RRR_T
);
1809 int shiftimm
= RRR_S
| ((OP1
& 1) << 4);
1810 int maskimm
= (1 << (OP2
+ 1)) - 1;
1812 TCGv_i32 tmp
= tcg_temp_new_i32();
1815 tcg_gen_shri_i32(tmp
, cpu_R
[RRR_T
], shiftimm
);
1817 tcg_gen_mov_i32(tmp
, cpu_R
[RRR_T
]);
1822 tcg_gen_ext8u_i32(cpu_R
[RRR_R
], tmp
);
1826 tcg_gen_ext16u_i32(cpu_R
[RRR_R
], tmp
);
1830 tcg_gen_andi_i32(cpu_R
[RRR_R
], tmp
, maskimm
);
1851 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR
);
1852 gen_window_check2(dc
, RRR_S
, RRR_T
);
1854 TCGv_i32 addr
= tcg_temp_new_i32();
1855 tcg_gen_add_i32(addr
, cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1856 gen_load_store_alignment(dc
, 2, addr
, false);
1858 tcg_gen_qemu_st32(cpu_FR
[RRR_R
], addr
, dc
->cring
);
1860 tcg_gen_qemu_ld32u(cpu_FR
[RRR_R
], addr
, dc
->cring
);
1863 tcg_gen_mov_i32(cpu_R
[RRR_S
], addr
);
1865 tcg_temp_free(addr
);
1869 default: /*reserved*/
1876 gen_window_check2(dc
, RRR_S
, RRR_T
);
1879 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1880 gen_check_privilege(dc
);
1882 TCGv_i32 addr
= tcg_temp_new_i32();
1883 tcg_gen_addi_i32(addr
, cpu_R
[RRR_S
],
1884 (0xffffffc0 | (RRR_R
<< 2)));
1885 tcg_gen_qemu_ld32u(cpu_R
[RRR_T
], addr
, dc
->ring
);
1886 tcg_temp_free(addr
);
1891 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1892 gen_check_privilege(dc
);
1894 TCGv_i32 addr
= tcg_temp_new_i32();
1895 tcg_gen_addi_i32(addr
, cpu_R
[RRR_S
],
1896 (0xffffffc0 | (RRR_R
<< 2)));
1897 tcg_gen_qemu_st32(cpu_R
[RRR_T
], addr
, dc
->ring
);
1898 tcg_temp_free(addr
);
1909 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR
);
1912 gen_helper_add_s(cpu_FR
[RRR_R
], cpu_env
,
1913 cpu_FR
[RRR_S
], cpu_FR
[RRR_T
]);
1917 gen_helper_sub_s(cpu_FR
[RRR_R
], cpu_env
,
1918 cpu_FR
[RRR_S
], cpu_FR
[RRR_T
]);
1922 gen_helper_mul_s(cpu_FR
[RRR_R
], cpu_env
,
1923 cpu_FR
[RRR_S
], cpu_FR
[RRR_T
]);
1927 gen_helper_madd_s(cpu_FR
[RRR_R
], cpu_env
,
1928 cpu_FR
[RRR_R
], cpu_FR
[RRR_S
], cpu_FR
[RRR_T
]);
1932 gen_helper_msub_s(cpu_FR
[RRR_R
], cpu_env
,
1933 cpu_FR
[RRR_R
], cpu_FR
[RRR_S
], cpu_FR
[RRR_T
]);
1936 case 8: /*ROUND.Sf*/
1937 case 9: /*TRUNC.Sf*/
1938 case 10: /*FLOOR.Sf*/
1939 case 11: /*CEIL.Sf*/
1940 case 14: /*UTRUNC.Sf*/
1941 gen_window_check1(dc
, RRR_R
);
1943 static const unsigned rounding_mode_const
[] = {
1944 float_round_nearest_even
,
1945 float_round_to_zero
,
1948 [6] = float_round_to_zero
,
1950 TCGv_i32 rounding_mode
= tcg_const_i32(
1951 rounding_mode_const
[OP2
& 7]);
1952 TCGv_i32 scale
= tcg_const_i32(RRR_T
);
1955 gen_helper_ftoui(cpu_R
[RRR_R
], cpu_FR
[RRR_S
],
1956 rounding_mode
, scale
);
1958 gen_helper_ftoi(cpu_R
[RRR_R
], cpu_FR
[RRR_S
],
1959 rounding_mode
, scale
);
1962 tcg_temp_free(rounding_mode
);
1963 tcg_temp_free(scale
);
1967 case 12: /*FLOAT.Sf*/
1968 case 13: /*UFLOAT.Sf*/
1969 gen_window_check1(dc
, RRR_S
);
1971 TCGv_i32 scale
= tcg_const_i32(-RRR_T
);
1974 gen_helper_uitof(cpu_FR
[RRR_R
], cpu_env
,
1975 cpu_R
[RRR_S
], scale
);
1977 gen_helper_itof(cpu_FR
[RRR_R
], cpu_env
,
1978 cpu_R
[RRR_S
], scale
);
1980 tcg_temp_free(scale
);
1987 tcg_gen_mov_i32(cpu_FR
[RRR_R
], cpu_FR
[RRR_S
]);
1991 gen_helper_abs_s(cpu_FR
[RRR_R
], cpu_FR
[RRR_S
]);
1995 gen_window_check1(dc
, RRR_R
);
1996 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_FR
[RRR_S
]);
2000 gen_window_check1(dc
, RRR_S
);
2001 tcg_gen_mov_i32(cpu_FR
[RRR_R
], cpu_R
[RRR_S
]);
2005 gen_helper_neg_s(cpu_FR
[RRR_R
], cpu_FR
[RRR_S
]);
2008 default: /*reserved*/
2014 default: /*reserved*/
2021 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR
);
2023 #define gen_compare(rel, br, a, b) \
2025 TCGv_i32 bit = tcg_const_i32(1 << br); \
2027 gen_helper_##rel(cpu_env, bit, cpu_FR[a], cpu_FR[b]); \
2028 tcg_temp_free(bit); \
2033 gen_compare(un_s
, RRR_R
, RRR_S
, RRR_T
);
2037 gen_compare(oeq_s
, RRR_R
, RRR_S
, RRR_T
);
2041 gen_compare(ueq_s
, RRR_R
, RRR_S
, RRR_T
);
2045 gen_compare(olt_s
, RRR_R
, RRR_S
, RRR_T
);
2049 gen_compare(ult_s
, RRR_R
, RRR_S
, RRR_T
);
2053 gen_compare(ole_s
, RRR_R
, RRR_S
, RRR_T
);
2057 gen_compare(ule_s
, RRR_R
, RRR_S
, RRR_T
);
2062 case 8: /*MOVEQZ.Sf*/
2063 case 9: /*MOVNEZ.Sf*/
2064 case 10: /*MOVLTZ.Sf*/
2065 case 11: /*MOVGEZ.Sf*/
2066 gen_window_check1(dc
, RRR_T
);
2068 static const TCGCond cond
[] = {
2074 int label
= gen_new_label();
2075 tcg_gen_brcondi_i32(cond
[OP2
- 8], cpu_R
[RRR_T
], 0, label
);
2076 tcg_gen_mov_i32(cpu_FR
[RRR_R
], cpu_FR
[RRR_S
]);
2077 gen_set_label(label
);
2081 case 12: /*MOVF.Sf*/
2082 case 13: /*MOVT.Sf*/
2083 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
2085 int label
= gen_new_label();
2086 TCGv_i32 tmp
= tcg_temp_new_i32();
2088 tcg_gen_andi_i32(tmp
, cpu_SR
[BR
], 1 << RRR_T
);
2089 tcg_gen_brcondi_i32(
2090 OP2
& 1 ? TCG_COND_EQ
: TCG_COND_NE
,
2092 tcg_gen_mov_i32(cpu_FR
[RRR_R
], cpu_FR
[RRR_S
]);
2093 gen_set_label(label
);
2098 default: /*reserved*/
2104 default: /*reserved*/
2111 gen_window_check1(dc
, RRR_T
);
2113 TCGv_i32 tmp
= tcg_const_i32(
2114 ((dc
->tb
->flags
& XTENSA_TBFLAG_LITBASE
) ?
2115 0 : ((dc
->pc
+ 3) & ~3)) +
2116 (0xfffc0000 | (RI16_IMM16
<< 2)));
2118 if (dc
->tb
->flags
& XTENSA_TBFLAG_LITBASE
) {
2119 tcg_gen_add_i32(tmp
, tmp
, dc
->litbase
);
2121 tcg_gen_qemu_ld32u(cpu_R
[RRR_T
], tmp
, dc
->cring
);
2127 #define gen_load_store(type, shift) do { \
2128 TCGv_i32 addr = tcg_temp_new_i32(); \
2129 gen_window_check2(dc, RRI8_S, RRI8_T); \
2130 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \
2132 gen_load_store_alignment(dc, shift, addr, false); \
2134 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
2135 tcg_temp_free(addr); \
2140 gen_load_store(ld8u
, 0);
2144 gen_load_store(ld16u
, 1);
2148 gen_load_store(ld32u
, 2);
2152 gen_load_store(st8
, 0);
2156 gen_load_store(st16
, 1);
2160 gen_load_store(st32
, 2);
2165 HAS_OPTION(XTENSA_OPTION_DCACHE
);
2196 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK
);
2200 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK
);
2204 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK
);
2208 HAS_OPTION(XTENSA_OPTION_DCACHE
);
2212 HAS_OPTION(XTENSA_OPTION_DCACHE
);
2215 default: /*reserved*/
2223 HAS_OPTION(XTENSA_OPTION_ICACHE
);
2229 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK
);
2233 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK
);
2237 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK
);
2240 default: /*reserved*/
2247 HAS_OPTION(XTENSA_OPTION_ICACHE
);
2251 HAS_OPTION(XTENSA_OPTION_ICACHE
);
2254 default: /*reserved*/
2261 gen_load_store(ld16s
, 1);
2263 #undef gen_load_store
2266 gen_window_check1(dc
, RRI8_T
);
2267 tcg_gen_movi_i32(cpu_R
[RRI8_T
],
2268 RRI8_IMM8
| (RRI8_S
<< 8) |
2269 ((RRI8_S
& 0x8) ? 0xfffff000 : 0));
2272 #define gen_load_store_no_hw_align(type) do { \
2273 TCGv_i32 addr = tcg_temp_local_new_i32(); \
2274 gen_window_check2(dc, RRI8_S, RRI8_T); \
2275 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); \
2276 gen_load_store_alignment(dc, 2, addr, true); \
2277 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
2278 tcg_temp_free(addr); \
2282 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO
);
2283 gen_load_store_no_hw_align(ld32u
); /*TODO acquire?*/
2287 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2288 tcg_gen_addi_i32(cpu_R
[RRI8_T
], cpu_R
[RRI8_S
], RRI8_IMM8_SE
);
2292 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2293 tcg_gen_addi_i32(cpu_R
[RRI8_T
], cpu_R
[RRI8_S
], RRI8_IMM8_SE
<< 8);
2296 case 14: /*S32C1Iy*/
2297 HAS_OPTION(XTENSA_OPTION_CONDITIONAL_STORE
);
2298 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2300 int label
= gen_new_label();
2301 TCGv_i32 tmp
= tcg_temp_local_new_i32();
2302 TCGv_i32 addr
= tcg_temp_local_new_i32();
2304 tcg_gen_mov_i32(tmp
, cpu_R
[RRI8_T
]);
2305 tcg_gen_addi_i32(addr
, cpu_R
[RRI8_S
], RRI8_IMM8
<< 2);
2306 gen_load_store_alignment(dc
, 2, addr
, true);
2307 tcg_gen_qemu_ld32u(cpu_R
[RRI8_T
], addr
, dc
->cring
);
2308 tcg_gen_brcond_i32(TCG_COND_NE
, cpu_R
[RRI8_T
],
2309 cpu_SR
[SCOMPARE1
], label
);
2311 tcg_gen_qemu_st32(tmp
, addr
, dc
->cring
);
2313 gen_set_label(label
);
2314 tcg_temp_free(addr
);
2320 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO
);
2321 gen_load_store_no_hw_align(st32
); /*TODO release?*/
2323 #undef gen_load_store_no_hw_align
2325 default: /*reserved*/
2337 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR
);
2338 gen_window_check1(dc
, RRI8_S
);
2340 TCGv_i32 addr
= tcg_temp_new_i32();
2341 tcg_gen_addi_i32(addr
, cpu_R
[RRI8_S
], RRI8_IMM8
<< 2);
2342 gen_load_store_alignment(dc
, 2, addr
, false);
2344 tcg_gen_qemu_st32(cpu_FR
[RRI8_T
], addr
, dc
->cring
);
2346 tcg_gen_qemu_ld32u(cpu_FR
[RRI8_T
], addr
, dc
->cring
);
2349 tcg_gen_mov_i32(cpu_R
[RRI8_S
], addr
);
2351 tcg_temp_free(addr
);
2355 default: /*reserved*/
2362 HAS_OPTION(XTENSA_OPTION_MAC16
);
2371 bool is_m1_sr
= (OP2
& 0x3) == 2;
2372 bool is_m2_sr
= (OP2
& 0xc) == 0;
2373 uint32_t ld_offset
= 0;
2380 case 0: /*MACI?/MACC?*/
2382 ld_offset
= (OP2
& 1) ? -4 : 4;
2384 if (OP2
>= 8) { /*MACI/MACC*/
2385 if (OP1
== 0) { /*LDINC/LDDEC*/
2390 } else if (op
!= MAC16_MULA
) { /*MULA.*.*.LDINC/LDDEC*/
2395 case 2: /*MACD?/MACA?*/
2396 if (op
== MAC16_UMUL
&& OP2
!= 7) { /*UMUL only in MACAA*/
2402 if (op
!= MAC16_NONE
) {
2404 gen_window_check1(dc
, RRR_S
);
2407 gen_window_check1(dc
, RRR_T
);
2412 TCGv_i32 vaddr
= tcg_temp_new_i32();
2413 TCGv_i32 mem32
= tcg_temp_new_i32();
2416 gen_window_check1(dc
, RRR_S
);
2417 tcg_gen_addi_i32(vaddr
, cpu_R
[RRR_S
], ld_offset
);
2418 gen_load_store_alignment(dc
, 2, vaddr
, false);
2419 tcg_gen_qemu_ld32u(mem32
, vaddr
, dc
->cring
);
2421 if (op
!= MAC16_NONE
) {
2422 TCGv_i32 m1
= gen_mac16_m(
2423 is_m1_sr
? cpu_SR
[MR
+ RRR_X
] : cpu_R
[RRR_S
],
2424 OP1
& 1, op
== MAC16_UMUL
);
2425 TCGv_i32 m2
= gen_mac16_m(
2426 is_m2_sr
? cpu_SR
[MR
+ 2 + RRR_Y
] : cpu_R
[RRR_T
],
2427 OP1
& 2, op
== MAC16_UMUL
);
2429 if (op
== MAC16_MUL
|| op
== MAC16_UMUL
) {
2430 tcg_gen_mul_i32(cpu_SR
[ACCLO
], m1
, m2
);
2431 if (op
== MAC16_UMUL
) {
2432 tcg_gen_movi_i32(cpu_SR
[ACCHI
], 0);
2434 tcg_gen_sari_i32(cpu_SR
[ACCHI
], cpu_SR
[ACCLO
], 31);
2437 TCGv_i32 res
= tcg_temp_new_i32();
2438 TCGv_i64 res64
= tcg_temp_new_i64();
2439 TCGv_i64 tmp
= tcg_temp_new_i64();
2441 tcg_gen_mul_i32(res
, m1
, m2
);
2442 tcg_gen_ext_i32_i64(res64
, res
);
2443 tcg_gen_concat_i32_i64(tmp
,
2444 cpu_SR
[ACCLO
], cpu_SR
[ACCHI
]);
2445 if (op
== MAC16_MULA
) {
2446 tcg_gen_add_i64(tmp
, tmp
, res64
);
2448 tcg_gen_sub_i64(tmp
, tmp
, res64
);
2450 tcg_gen_trunc_i64_i32(cpu_SR
[ACCLO
], tmp
);
2451 tcg_gen_shri_i64(tmp
, tmp
, 32);
2452 tcg_gen_trunc_i64_i32(cpu_SR
[ACCHI
], tmp
);
2453 tcg_gen_ext8s_i32(cpu_SR
[ACCHI
], cpu_SR
[ACCHI
]);
2456 tcg_temp_free_i64(res64
);
2457 tcg_temp_free_i64(tmp
);
2463 tcg_gen_mov_i32(cpu_R
[RRR_S
], vaddr
);
2464 tcg_gen_mov_i32(cpu_SR
[MR
+ RRR_W
], mem32
);
2466 tcg_temp_free(vaddr
);
2467 tcg_temp_free(mem32
);
2475 tcg_gen_movi_i32(cpu_R
[0], dc
->next_pc
);
2476 gen_jumpi(dc
, (dc
->pc
& ~3) + (CALL_OFFSET_SE
<< 2) + 4, 0);
2482 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
2483 gen_window_check1(dc
, CALL_N
<< 2);
2484 gen_callwi(dc
, CALL_N
,
2485 (dc
->pc
& ~3) + (CALL_OFFSET_SE
<< 2) + 4, 0);
2493 gen_jumpi(dc
, dc
->pc
+ 4 + CALL_OFFSET_SE
, 0);
2497 gen_window_check1(dc
, BRI12_S
);
2499 static const TCGCond cond
[] = {
2500 TCG_COND_EQ
, /*BEQZ*/
2501 TCG_COND_NE
, /*BNEZ*/
2502 TCG_COND_LT
, /*BLTZ*/
2503 TCG_COND_GE
, /*BGEZ*/
2506 gen_brcondi(dc
, cond
[BRI12_M
& 3], cpu_R
[BRI12_S
], 0,
2507 4 + BRI12_IMM12_SE
);
2512 gen_window_check1(dc
, BRI8_S
);
2514 static const TCGCond cond
[] = {
2515 TCG_COND_EQ
, /*BEQI*/
2516 TCG_COND_NE
, /*BNEI*/
2517 TCG_COND_LT
, /*BLTI*/
2518 TCG_COND_GE
, /*BGEI*/
2521 gen_brcondi(dc
, cond
[BRI8_M
& 3],
2522 cpu_R
[BRI8_S
], B4CONST
[BRI8_R
], 4 + BRI8_IMM8_SE
);
2529 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
2531 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
2532 TCGv_i32 s
= tcg_const_i32(BRI12_S
);
2533 TCGv_i32 imm
= tcg_const_i32(BRI12_IMM12
);
2534 gen_advance_ccount(dc
);
2535 gen_helper_entry(cpu_env
, pc
, s
, imm
);
2539 reset_used_window(dc
);
2547 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
2549 TCGv_i32 tmp
= tcg_temp_new_i32();
2550 tcg_gen_andi_i32(tmp
, cpu_SR
[BR
], 1 << RRI8_S
);
2552 BRI8_R
== 1 ? TCG_COND_NE
: TCG_COND_EQ
,
2553 tmp
, 0, 4 + RRI8_IMM8_SE
);
2560 case 10: /*LOOPGTZ*/
2561 HAS_OPTION(XTENSA_OPTION_LOOP
);
2562 gen_window_check1(dc
, RRI8_S
);
2564 uint32_t lend
= dc
->pc
+ RRI8_IMM8
+ 4;
2565 TCGv_i32 tmp
= tcg_const_i32(lend
);
2567 tcg_gen_subi_i32(cpu_SR
[LCOUNT
], cpu_R
[RRI8_S
], 1);
2568 tcg_gen_movi_i32(cpu_SR
[LBEG
], dc
->next_pc
);
2569 gen_helper_wsr_lend(cpu_env
, tmp
);
2573 int label
= gen_new_label();
2574 tcg_gen_brcondi_i32(
2575 BRI8_R
== 9 ? TCG_COND_NE
: TCG_COND_GT
,
2576 cpu_R
[RRI8_S
], 0, label
);
2577 gen_jumpi(dc
, lend
, 1);
2578 gen_set_label(label
);
2581 gen_jumpi(dc
, dc
->next_pc
, 0);
2585 default: /*reserved*/
2594 gen_window_check1(dc
, BRI8_S
);
2595 gen_brcondi(dc
, BRI8_M
== 2 ? TCG_COND_LTU
: TCG_COND_GEU
,
2596 cpu_R
[BRI8_S
], B4CONSTU
[BRI8_R
], 4 + BRI8_IMM8_SE
);
2606 TCGCond eq_ne
= (RRI8_R
& 8) ? TCG_COND_NE
: TCG_COND_EQ
;
2608 switch (RRI8_R
& 7) {
2609 case 0: /*BNONE*/ /*BANY*/
2610 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2612 TCGv_i32 tmp
= tcg_temp_new_i32();
2613 tcg_gen_and_i32(tmp
, cpu_R
[RRI8_S
], cpu_R
[RRI8_T
]);
2614 gen_brcondi(dc
, eq_ne
, tmp
, 0, 4 + RRI8_IMM8_SE
);
2619 case 1: /*BEQ*/ /*BNE*/
2620 case 2: /*BLT*/ /*BGE*/
2621 case 3: /*BLTU*/ /*BGEU*/
2622 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2624 static const TCGCond cond
[] = {
2630 [11] = TCG_COND_GEU
,
2632 gen_brcond(dc
, cond
[RRI8_R
], cpu_R
[RRI8_S
], cpu_R
[RRI8_T
],
2637 case 4: /*BALL*/ /*BNALL*/
2638 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2640 TCGv_i32 tmp
= tcg_temp_new_i32();
2641 tcg_gen_and_i32(tmp
, cpu_R
[RRI8_S
], cpu_R
[RRI8_T
]);
2642 gen_brcond(dc
, eq_ne
, tmp
, cpu_R
[RRI8_T
],
2648 case 5: /*BBC*/ /*BBS*/
2649 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2651 #ifdef TARGET_WORDS_BIGENDIAN
2652 TCGv_i32 bit
= tcg_const_i32(0x80000000);
2654 TCGv_i32 bit
= tcg_const_i32(0x00000001);
2656 TCGv_i32 tmp
= tcg_temp_new_i32();
2657 tcg_gen_andi_i32(tmp
, cpu_R
[RRI8_T
], 0x1f);
2658 #ifdef TARGET_WORDS_BIGENDIAN
2659 tcg_gen_shr_i32(bit
, bit
, tmp
);
2661 tcg_gen_shl_i32(bit
, bit
, tmp
);
2663 tcg_gen_and_i32(tmp
, cpu_R
[RRI8_S
], bit
);
2664 gen_brcondi(dc
, eq_ne
, tmp
, 0, 4 + RRI8_IMM8_SE
);
2670 case 6: /*BBCI*/ /*BBSI*/
2672 gen_window_check1(dc
, RRI8_S
);
2674 TCGv_i32 tmp
= tcg_temp_new_i32();
2675 tcg_gen_andi_i32(tmp
, cpu_R
[RRI8_S
],
2676 #ifdef TARGET_WORDS_BIGENDIAN
2677 0x80000000 >> (((RRI8_R
& 1) << 4) | RRI8_T
));
2679 0x00000001 << (((RRI8_R
& 1) << 4) | RRI8_T
));
2681 gen_brcondi(dc
, eq_ne
, tmp
, 0, 4 + RRI8_IMM8_SE
);
2690 #define gen_narrow_load_store(type) do { \
2691 TCGv_i32 addr = tcg_temp_new_i32(); \
2692 gen_window_check2(dc, RRRN_S, RRRN_T); \
2693 tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
2694 gen_load_store_alignment(dc, 2, addr, false); \
2695 tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, dc->cring); \
2696 tcg_temp_free(addr); \
2700 gen_narrow_load_store(ld32u
);
2704 gen_narrow_load_store(st32
);
2706 #undef gen_narrow_load_store
2709 gen_window_check3(dc
, RRRN_R
, RRRN_S
, RRRN_T
);
2710 tcg_gen_add_i32(cpu_R
[RRRN_R
], cpu_R
[RRRN_S
], cpu_R
[RRRN_T
]);
2713 case 11: /*ADDI.Nn*/
2714 gen_window_check2(dc
, RRRN_R
, RRRN_S
);
2715 tcg_gen_addi_i32(cpu_R
[RRRN_R
], cpu_R
[RRRN_S
], RRRN_T
? RRRN_T
: -1);
2719 gen_window_check1(dc
, RRRN_S
);
2720 if (RRRN_T
< 8) { /*MOVI.Nn*/
2721 tcg_gen_movi_i32(cpu_R
[RRRN_S
],
2722 RRRN_R
| (RRRN_T
<< 4) |
2723 ((RRRN_T
& 6) == 6 ? 0xffffff80 : 0));
2724 } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/
2725 TCGCond eq_ne
= (RRRN_T
& 4) ? TCG_COND_NE
: TCG_COND_EQ
;
2727 gen_brcondi(dc
, eq_ne
, cpu_R
[RRRN_S
], 0,
2728 4 + (RRRN_R
| ((RRRN_T
& 3) << 4)));
2735 gen_window_check2(dc
, RRRN_S
, RRRN_T
);
2736 tcg_gen_mov_i32(cpu_R
[RRRN_T
], cpu_R
[RRRN_S
]);
2742 gen_jump(dc
, cpu_R
[0]);
2746 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
2748 TCGv_i32 tmp
= tcg_const_i32(dc
->pc
);
2749 gen_advance_ccount(dc
);
2750 gen_helper_retw(tmp
, cpu_env
, tmp
);
2756 case 2: /*BREAK.Nn*/
2757 HAS_OPTION(XTENSA_OPTION_DEBUG
);
2759 gen_debug_exception(dc
, DEBUGCAUSE_BN
);
2767 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
2770 default: /*reserved*/
2776 default: /*reserved*/
2782 default: /*reserved*/
2787 if (dc
->is_jmp
== DISAS_NEXT
) {
2788 gen_check_loop_end(dc
, 0);
2790 dc
->pc
= dc
->next_pc
;
2795 qemu_log("INVALID(pc = %08x)\n", dc
->pc
);
2796 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
2800 static void check_breakpoint(CPUXtensaState
*env
, DisasContext
*dc
)
2804 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
2805 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
2806 if (bp
->pc
== dc
->pc
) {
2807 tcg_gen_movi_i32(cpu_pc
, dc
->pc
);
2808 gen_exception(dc
, EXCP_DEBUG
);
2809 dc
->is_jmp
= DISAS_UPDATE
;
2815 static void gen_ibreak_check(CPUXtensaState
*env
, DisasContext
*dc
)
2819 for (i
= 0; i
< dc
->config
->nibreak
; ++i
) {
2820 if ((env
->sregs
[IBREAKENABLE
] & (1 << i
)) &&
2821 env
->sregs
[IBREAKA
+ i
] == dc
->pc
) {
2822 gen_debug_exception(dc
, DEBUGCAUSE_IB
);
2828 static void gen_intermediate_code_internal(
2829 CPUXtensaState
*env
, TranslationBlock
*tb
, int search_pc
)
2834 uint16_t *gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
2835 int max_insns
= tb
->cflags
& CF_COUNT_MASK
;
2836 uint32_t pc_start
= tb
->pc
;
2837 uint32_t next_page_start
=
2838 (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
2840 if (max_insns
== 0) {
2841 max_insns
= CF_COUNT_MASK
;
2844 dc
.config
= env
->config
;
2845 dc
.singlestep_enabled
= env
->singlestep_enabled
;
2848 dc
.ring
= tb
->flags
& XTENSA_TBFLAG_RING_MASK
;
2849 dc
.cring
= (tb
->flags
& XTENSA_TBFLAG_EXCM
) ? 0 : dc
.ring
;
2850 dc
.lbeg
= env
->sregs
[LBEG
];
2851 dc
.lend
= env
->sregs
[LEND
];
2852 dc
.is_jmp
= DISAS_NEXT
;
2853 dc
.ccount_delta
= 0;
2854 dc
.debug
= tb
->flags
& XTENSA_TBFLAG_DEBUG
;
2855 dc
.icount
= tb
->flags
& XTENSA_TBFLAG_ICOUNT
;
2858 init_sar_tracker(&dc
);
2859 reset_used_window(&dc
);
2861 dc
.next_icount
= tcg_temp_local_new_i32();
2866 if (env
->singlestep_enabled
&& env
->exception_taken
) {
2867 env
->exception_taken
= 0;
2868 tcg_gen_movi_i32(cpu_pc
, dc
.pc
);
2869 gen_exception(&dc
, EXCP_DEBUG
);
2873 check_breakpoint(env
, &dc
);
2876 j
= gen_opc_ptr
- gen_opc_buf
;
2880 gen_opc_instr_start
[lj
++] = 0;
2883 gen_opc_pc
[lj
] = dc
.pc
;
2884 gen_opc_instr_start
[lj
] = 1;
2885 gen_opc_icount
[lj
] = insn_count
;
2888 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
))) {
2889 tcg_gen_debug_insn_start(dc
.pc
);
2894 if (insn_count
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
2899 int label
= gen_new_label();
2901 tcg_gen_addi_i32(dc
.next_icount
, cpu_SR
[ICOUNT
], 1);
2902 tcg_gen_brcondi_i32(TCG_COND_NE
, dc
.next_icount
, 0, label
);
2903 tcg_gen_mov_i32(dc
.next_icount
, cpu_SR
[ICOUNT
]);
2905 gen_debug_exception(&dc
, DEBUGCAUSE_IC
);
2907 gen_set_label(label
);
2911 gen_ibreak_check(env
, &dc
);
2914 disas_xtensa_insn(&dc
);
2917 tcg_gen_mov_i32(cpu_SR
[ICOUNT
], dc
.next_icount
);
2919 if (env
->singlestep_enabled
) {
2920 tcg_gen_movi_i32(cpu_pc
, dc
.pc
);
2921 gen_exception(&dc
, EXCP_DEBUG
);
2924 } while (dc
.is_jmp
== DISAS_NEXT
&&
2925 insn_count
< max_insns
&&
2926 dc
.pc
< next_page_start
&&
2927 gen_opc_ptr
< gen_opc_end
);
2930 reset_sar_tracker(&dc
);
2932 tcg_temp_free(dc
.next_icount
);
2935 if (tb
->cflags
& CF_LAST_IO
) {
2939 if (dc
.is_jmp
== DISAS_NEXT
) {
2940 gen_jumpi(&dc
, dc
.pc
, 0);
2942 gen_icount_end(tb
, insn_count
);
2943 *gen_opc_ptr
= INDEX_op_end
;
2946 tb
->size
= dc
.pc
- pc_start
;
2947 tb
->icount
= insn_count
;
2951 void gen_intermediate_code(CPUXtensaState
*env
, TranslationBlock
*tb
)
2953 gen_intermediate_code_internal(env
, tb
, 0);
2956 void gen_intermediate_code_pc(CPUXtensaState
*env
, TranslationBlock
*tb
)
2958 gen_intermediate_code_internal(env
, tb
, 1);
2961 void cpu_dump_state(CPUXtensaState
*env
, FILE *f
, fprintf_function cpu_fprintf
,
2966 cpu_fprintf(f
, "PC=%08x\n\n", env
->pc
);
2968 for (i
= j
= 0; i
< 256; ++i
) {
2970 cpu_fprintf(f
, "%s=%08x%c", sregnames
[i
], env
->sregs
[i
],
2971 (j
++ % 4) == 3 ? '\n' : ' ');
2975 cpu_fprintf(f
, (j
% 4) == 0 ? "\n" : "\n\n");
2977 for (i
= j
= 0; i
< 256; ++i
) {
2979 cpu_fprintf(f
, "%s=%08x%c", uregnames
[i
], env
->uregs
[i
],
2980 (j
++ % 4) == 3 ? '\n' : ' ');
2984 cpu_fprintf(f
, (j
% 4) == 0 ? "\n" : "\n\n");
2986 for (i
= 0; i
< 16; ++i
) {
2987 cpu_fprintf(f
, "A%02d=%08x%c", i
, env
->regs
[i
],
2988 (i
% 4) == 3 ? '\n' : ' ');
2991 cpu_fprintf(f
, "\n");
2993 for (i
= 0; i
< env
->config
->nareg
; ++i
) {
2994 cpu_fprintf(f
, "AR%02d=%08x%c", i
, env
->phys_regs
[i
],
2995 (i
% 4) == 3 ? '\n' : ' ');
2998 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_FP_COPROCESSOR
)) {
2999 cpu_fprintf(f
, "\n");
3001 for (i
= 0; i
< 16; ++i
) {
3002 cpu_fprintf(f
, "F%02d=%08x (%+10.8e)%c", i
,
3003 float32_val(env
->fregs
[i
]),
3004 *(float *)&env
->fregs
[i
], (i
% 2) == 1 ? '\n' : ' ');
3009 void restore_state_to_opc(CPUXtensaState
*env
, TranslationBlock
*tb
, int pc_pos
)
3011 env
->pc
= gen_opc_pc
[pc_pos
];