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tcg-arm: Use bic to implement and with constant
[qemu.git] / tcg / arm / tcg-target.c
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Andrzej Zaborowski
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #if defined(__ARM_ARCH_7__) || \
26 defined(__ARM_ARCH_7A__) || \
27 defined(__ARM_ARCH_7EM__) || \
28 defined(__ARM_ARCH_7M__) || \
29 defined(__ARM_ARCH_7R__)
30 #define USE_ARMV7_INSTRUCTIONS
31 #endif
32
33 #if defined(USE_ARMV7_INSTRUCTIONS) || \
34 defined(__ARM_ARCH_6J__) || \
35 defined(__ARM_ARCH_6K__) || \
36 defined(__ARM_ARCH_6T2__) || \
37 defined(__ARM_ARCH_6Z__) || \
38 defined(__ARM_ARCH_6ZK__)
39 #define USE_ARMV6_INSTRUCTIONS
40 #endif
41
42 #if defined(USE_ARMV6_INSTRUCTIONS) || \
43 defined(__ARM_ARCH_5T__) || \
44 defined(__ARM_ARCH_5TE__) || \
45 defined(__ARM_ARCH_5TEJ__)
46 #define USE_ARMV5_INSTRUCTIONS
47 #endif
48
49 #ifdef USE_ARMV5_INSTRUCTIONS
50 static const int use_armv5_instructions = 1;
51 #else
52 static const int use_armv5_instructions = 0;
53 #endif
54 #undef USE_ARMV5_INSTRUCTIONS
55
56 #ifdef USE_ARMV6_INSTRUCTIONS
57 static const int use_armv6_instructions = 1;
58 #else
59 static const int use_armv6_instructions = 0;
60 #endif
61 #undef USE_ARMV6_INSTRUCTIONS
62
63 #ifdef USE_ARMV7_INSTRUCTIONS
64 static const int use_armv7_instructions = 1;
65 #else
66 static const int use_armv7_instructions = 0;
67 #endif
68 #undef USE_ARMV7_INSTRUCTIONS
69
70 #ifndef NDEBUG
71 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
72 "%r0",
73 "%r1",
74 "%r2",
75 "%r3",
76 "%r4",
77 "%r5",
78 "%r6",
79 "%r7",
80 "%r8",
81 "%r9",
82 "%r10",
83 "%r11",
84 "%r12",
85 "%r13",
86 "%r14",
87 "%pc",
88 };
89 #endif
90
91 static const int tcg_target_reg_alloc_order[] = {
92 TCG_REG_R4,
93 TCG_REG_R5,
94 TCG_REG_R6,
95 TCG_REG_R7,
96 TCG_REG_R8,
97 TCG_REG_R9,
98 TCG_REG_R10,
99 TCG_REG_R11,
100 TCG_REG_R13,
101 TCG_REG_R0,
102 TCG_REG_R1,
103 TCG_REG_R2,
104 TCG_REG_R3,
105 TCG_REG_R12,
106 TCG_REG_R14,
107 };
108
109 static const int tcg_target_call_iarg_regs[4] = {
110 TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3
111 };
112 static const int tcg_target_call_oarg_regs[2] = {
113 TCG_REG_R0, TCG_REG_R1
114 };
115
116 static inline void reloc_abs32(void *code_ptr, tcg_target_long target)
117 {
118 *(uint32_t *) code_ptr = target;
119 }
120
121 static inline void reloc_pc24(void *code_ptr, tcg_target_long target)
122 {
123 uint32_t offset = ((target - ((tcg_target_long) code_ptr + 8)) >> 2);
124
125 *(uint32_t *) code_ptr = ((*(uint32_t *) code_ptr) & ~0xffffff)
126 | (offset & 0xffffff);
127 }
128
129 static void patch_reloc(uint8_t *code_ptr, int type,
130 tcg_target_long value, tcg_target_long addend)
131 {
132 switch (type) {
133 case R_ARM_ABS32:
134 reloc_abs32(code_ptr, value);
135 break;
136
137 case R_ARM_CALL:
138 case R_ARM_JUMP24:
139 default:
140 tcg_abort();
141
142 case R_ARM_PC24:
143 reloc_pc24(code_ptr, value);
144 break;
145 }
146 }
147
148 #define TCG_CT_CONST_ARM 0x100
149 #define TCG_CT_CONST_INV 0x200
150
151 /* parse target specific constraints */
152 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
153 {
154 const char *ct_str;
155
156 ct_str = *pct_str;
157 switch (ct_str[0]) {
158 case 'I':
159 ct->ct |= TCG_CT_CONST_ARM;
160 break;
161 case 'K':
162 ct->ct |= TCG_CT_CONST_INV;
163 break;
164
165 case 'r':
166 ct->ct |= TCG_CT_REG;
167 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
168 break;
169
170 /* qemu_ld address */
171 case 'l':
172 ct->ct |= TCG_CT_REG;
173 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
174 #ifdef CONFIG_SOFTMMU
175 /* r0 and r1 will be overwritten when reading the tlb entry,
176 so don't use these. */
177 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
178 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
179 #if TARGET_LONG_BITS == 64
180 /* If we're passing env to the helper as r0 and need a regpair
181 * for the address then r2 will be overwritten as we're setting
182 * up the args to the helper.
183 */
184 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
185 #endif
186 #endif
187 break;
188 case 'L':
189 ct->ct |= TCG_CT_REG;
190 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
191 #ifdef CONFIG_SOFTMMU
192 /* r1 is still needed to load data_reg or data_reg2,
193 so don't use it. */
194 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
195 #endif
196 break;
197
198 /* qemu_st address & data_reg */
199 case 's':
200 ct->ct |= TCG_CT_REG;
201 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
202 /* r0 and r1 will be overwritten when reading the tlb entry
203 (softmmu only) and doing the byte swapping, so don't
204 use these. */
205 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
206 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
207 #if defined(CONFIG_SOFTMMU) && (TARGET_LONG_BITS == 64)
208 /* Avoid clashes with registers being used for helper args */
209 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
210 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
211 #endif
212 break;
213 /* qemu_st64 data_reg2 */
214 case 'S':
215 ct->ct |= TCG_CT_REG;
216 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
217 /* r0 and r1 will be overwritten when reading the tlb entry
218 (softmmu only) and doing the byte swapping, so don't
219 use these. */
220 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
221 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
222 #ifdef CONFIG_SOFTMMU
223 /* r2 is still needed to load data_reg, so don't use it. */
224 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
225 #if TARGET_LONG_BITS == 64
226 /* Avoid clashes with registers being used for helper args */
227 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
228 #endif
229 #endif
230 break;
231
232 default:
233 return -1;
234 }
235 ct_str++;
236 *pct_str = ct_str;
237
238 return 0;
239 }
240
241 static inline uint32_t rotl(uint32_t val, int n)
242 {
243 return (val << n) | (val >> (32 - n));
244 }
245
246 /* ARM immediates for ALU instructions are made of an unsigned 8-bit
247 right-rotated by an even amount between 0 and 30. */
248 static inline int encode_imm(uint32_t imm)
249 {
250 int shift;
251
252 /* simple case, only lower bits */
253 if ((imm & ~0xff) == 0)
254 return 0;
255 /* then try a simple even shift */
256 shift = ctz32(imm) & ~1;
257 if (((imm >> shift) & ~0xff) == 0)
258 return 32 - shift;
259 /* now try harder with rotations */
260 if ((rotl(imm, 2) & ~0xff) == 0)
261 return 2;
262 if ((rotl(imm, 4) & ~0xff) == 0)
263 return 4;
264 if ((rotl(imm, 6) & ~0xff) == 0)
265 return 6;
266 /* imm can't be encoded */
267 return -1;
268 }
269
270 static inline int check_fit_imm(uint32_t imm)
271 {
272 return encode_imm(imm) >= 0;
273 }
274
275 /* Test if a constant matches the constraint.
276 * TODO: define constraints for:
277 *
278 * ldr/str offset: between -0xfff and 0xfff
279 * ldrh/strh offset: between -0xff and 0xff
280 * mov operand2: values represented with x << (2 * y), x < 0x100
281 * add, sub, eor...: ditto
282 */
283 static inline int tcg_target_const_match(tcg_target_long val,
284 const TCGArgConstraint *arg_ct)
285 {
286 int ct;
287 ct = arg_ct->ct;
288 if (ct & TCG_CT_CONST) {
289 return 1;
290 } else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val)) {
291 return 1;
292 } else if ((ct & TCG_CT_CONST_INV) && check_fit_imm(~val)) {
293 return 1;
294 } else {
295 return 0;
296 }
297 }
298
299 enum arm_data_opc_e {
300 ARITH_AND = 0x0,
301 ARITH_EOR = 0x1,
302 ARITH_SUB = 0x2,
303 ARITH_RSB = 0x3,
304 ARITH_ADD = 0x4,
305 ARITH_ADC = 0x5,
306 ARITH_SBC = 0x6,
307 ARITH_RSC = 0x7,
308 ARITH_TST = 0x8,
309 ARITH_CMP = 0xa,
310 ARITH_CMN = 0xb,
311 ARITH_ORR = 0xc,
312 ARITH_MOV = 0xd,
313 ARITH_BIC = 0xe,
314 ARITH_MVN = 0xf,
315 };
316
317 #define TO_CPSR(opc) \
318 ((opc == ARITH_CMP || opc == ARITH_CMN || opc == ARITH_TST) << 20)
319
320 #define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00)
321 #define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20)
322 #define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40)
323 #define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60)
324 #define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10)
325 #define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30)
326 #define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50)
327 #define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70)
328
329 enum arm_cond_code_e {
330 COND_EQ = 0x0,
331 COND_NE = 0x1,
332 COND_CS = 0x2, /* Unsigned greater or equal */
333 COND_CC = 0x3, /* Unsigned less than */
334 COND_MI = 0x4, /* Negative */
335 COND_PL = 0x5, /* Zero or greater */
336 COND_VS = 0x6, /* Overflow */
337 COND_VC = 0x7, /* No overflow */
338 COND_HI = 0x8, /* Unsigned greater than */
339 COND_LS = 0x9, /* Unsigned less or equal */
340 COND_GE = 0xa,
341 COND_LT = 0xb,
342 COND_GT = 0xc,
343 COND_LE = 0xd,
344 COND_AL = 0xe,
345 };
346
347 static const uint8_t tcg_cond_to_arm_cond[] = {
348 [TCG_COND_EQ] = COND_EQ,
349 [TCG_COND_NE] = COND_NE,
350 [TCG_COND_LT] = COND_LT,
351 [TCG_COND_GE] = COND_GE,
352 [TCG_COND_LE] = COND_LE,
353 [TCG_COND_GT] = COND_GT,
354 /* unsigned */
355 [TCG_COND_LTU] = COND_CC,
356 [TCG_COND_GEU] = COND_CS,
357 [TCG_COND_LEU] = COND_LS,
358 [TCG_COND_GTU] = COND_HI,
359 };
360
361 static inline void tcg_out_bx(TCGContext *s, int cond, int rn)
362 {
363 tcg_out32(s, (cond << 28) | 0x012fff10 | rn);
364 }
365
366 static inline void tcg_out_b(TCGContext *s, int cond, int32_t offset)
367 {
368 tcg_out32(s, (cond << 28) | 0x0a000000 |
369 (((offset - 8) >> 2) & 0x00ffffff));
370 }
371
372 static inline void tcg_out_b_noaddr(TCGContext *s, int cond)
373 {
374 /* We pay attention here to not modify the branch target by skipping
375 the corresponding bytes. This ensure that caches and memory are
376 kept coherent during retranslation. */
377 #ifdef HOST_WORDS_BIGENDIAN
378 tcg_out8(s, (cond << 4) | 0x0a);
379 s->code_ptr += 3;
380 #else
381 s->code_ptr += 3;
382 tcg_out8(s, (cond << 4) | 0x0a);
383 #endif
384 }
385
386 static inline void tcg_out_bl(TCGContext *s, int cond, int32_t offset)
387 {
388 tcg_out32(s, (cond << 28) | 0x0b000000 |
389 (((offset - 8) >> 2) & 0x00ffffff));
390 }
391
392 static inline void tcg_out_blx(TCGContext *s, int cond, int rn)
393 {
394 tcg_out32(s, (cond << 28) | 0x012fff30 | rn);
395 }
396
397 static inline void tcg_out_blx_imm(TCGContext *s, int32_t offset)
398 {
399 tcg_out32(s, 0xfa000000 | ((offset & 2) << 23) |
400 (((offset - 8) >> 2) & 0x00ffffff));
401 }
402
403 static inline void tcg_out_dat_reg(TCGContext *s,
404 int cond, int opc, int rd, int rn, int rm, int shift)
405 {
406 tcg_out32(s, (cond << 28) | (0 << 25) | (opc << 21) | TO_CPSR(opc) |
407 (rn << 16) | (rd << 12) | shift | rm);
408 }
409
410 static inline void tcg_out_mov_reg(TCGContext *s, int cond, int rd, int rm)
411 {
412 /* Simple reg-reg move, optimising out the 'do nothing' case */
413 if (rd != rm) {
414 tcg_out_dat_reg(s, cond, ARITH_MOV, rd, 0, rm, SHIFT_IMM_LSL(0));
415 }
416 }
417
418 static inline void tcg_out_dat_reg2(TCGContext *s,
419 int cond, int opc0, int opc1, int rd0, int rd1,
420 int rn0, int rn1, int rm0, int rm1, int shift)
421 {
422 if (rd0 == rn1 || rd0 == rm1) {
423 tcg_out32(s, (cond << 28) | (0 << 25) | (opc0 << 21) | (1 << 20) |
424 (rn0 << 16) | (8 << 12) | shift | rm0);
425 tcg_out32(s, (cond << 28) | (0 << 25) | (opc1 << 21) |
426 (rn1 << 16) | (rd1 << 12) | shift | rm1);
427 tcg_out_dat_reg(s, cond, ARITH_MOV,
428 rd0, 0, TCG_REG_R8, SHIFT_IMM_LSL(0));
429 } else {
430 tcg_out32(s, (cond << 28) | (0 << 25) | (opc0 << 21) | (1 << 20) |
431 (rn0 << 16) | (rd0 << 12) | shift | rm0);
432 tcg_out32(s, (cond << 28) | (0 << 25) | (opc1 << 21) |
433 (rn1 << 16) | (rd1 << 12) | shift | rm1);
434 }
435 }
436
437 static inline void tcg_out_dat_imm(TCGContext *s,
438 int cond, int opc, int rd, int rn, int im)
439 {
440 tcg_out32(s, (cond << 28) | (1 << 25) | (opc << 21) | TO_CPSR(opc) |
441 (rn << 16) | (rd << 12) | im);
442 }
443
444 static inline void tcg_out_movi32(TCGContext *s,
445 int cond, int rd, uint32_t arg)
446 {
447 /* TODO: This is very suboptimal, we can easily have a constant
448 * pool somewhere after all the instructions. */
449 if ((int)arg < 0 && (int)arg >= -0x100) {
450 tcg_out_dat_imm(s, cond, ARITH_MVN, rd, 0, (~arg) & 0xff);
451 } else if (use_armv7_instructions) {
452 /* use movw/movt */
453 /* movw */
454 tcg_out32(s, (cond << 28) | 0x03000000 | (rd << 12)
455 | ((arg << 4) & 0x000f0000) | (arg & 0xfff));
456 if (arg & 0xffff0000) {
457 /* movt */
458 tcg_out32(s, (cond << 28) | 0x03400000 | (rd << 12)
459 | ((arg >> 12) & 0x000f0000) | ((arg >> 16) & 0xfff));
460 }
461 } else {
462 int opc = ARITH_MOV;
463 int rn = 0;
464
465 do {
466 int i, rot;
467
468 i = ctz32(arg) & ~1;
469 rot = ((32 - i) << 7) & 0xf00;
470 tcg_out_dat_imm(s, cond, opc, rd, rn, ((arg >> i) & 0xff) | rot);
471 arg &= ~(0xff << i);
472
473 opc = ARITH_ORR;
474 rn = rd;
475 } while (arg);
476 }
477 }
478
479 static inline void tcg_out_dat_rI(TCGContext *s, int cond, int opc, TCGArg dst,
480 TCGArg lhs, TCGArg rhs, int rhs_is_const)
481 {
482 /* Emit either the reg,imm or reg,reg form of a data-processing insn.
483 * rhs must satisfy the "rI" constraint.
484 */
485 if (rhs_is_const) {
486 int rot = encode_imm(rhs);
487 assert(rot >= 0);
488 tcg_out_dat_imm(s, cond, opc, dst, lhs, rotl(rhs, rot) | (rot << 7));
489 } else {
490 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0));
491 }
492 }
493
494 static void tcg_out_dat_rIK(TCGContext *s, int cond, int opc, int opinv,
495 TCGReg dst, TCGReg lhs, TCGArg rhs,
496 bool rhs_is_const)
497 {
498 /* Emit either the reg,imm or reg,reg form of a data-processing insn.
499 * rhs must satisfy the "rIK" constraint.
500 */
501 if (rhs_is_const) {
502 int rot = encode_imm(rhs);
503 if (rot < 0) {
504 rhs = ~rhs;
505 rot = encode_imm(rhs);
506 assert(rot >= 0);
507 opc = opinv;
508 }
509 tcg_out_dat_imm(s, cond, opc, dst, lhs, rotl(rhs, rot) | (rot << 7));
510 } else {
511 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0));
512 }
513 }
514
515 static inline void tcg_out_mul32(TCGContext *s,
516 int cond, int rd, int rs, int rm)
517 {
518 if (rd != rm)
519 tcg_out32(s, (cond << 28) | (rd << 16) | (0 << 12) |
520 (rs << 8) | 0x90 | rm);
521 else if (rd != rs)
522 tcg_out32(s, (cond << 28) | (rd << 16) | (0 << 12) |
523 (rm << 8) | 0x90 | rs);
524 else {
525 tcg_out32(s, (cond << 28) | ( 8 << 16) | (0 << 12) |
526 (rs << 8) | 0x90 | rm);
527 tcg_out_dat_reg(s, cond, ARITH_MOV,
528 rd, 0, TCG_REG_R8, SHIFT_IMM_LSL(0));
529 }
530 }
531
532 static inline void tcg_out_umull32(TCGContext *s,
533 int cond, int rd0, int rd1, int rs, int rm)
534 {
535 if (rd0 != rm && rd1 != rm)
536 tcg_out32(s, (cond << 28) | 0x800090 |
537 (rd1 << 16) | (rd0 << 12) | (rs << 8) | rm);
538 else if (rd0 != rs && rd1 != rs)
539 tcg_out32(s, (cond << 28) | 0x800090 |
540 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rs);
541 else {
542 tcg_out_dat_reg(s, cond, ARITH_MOV,
543 TCG_REG_R8, 0, rm, SHIFT_IMM_LSL(0));
544 tcg_out32(s, (cond << 28) | 0x800098 |
545 (rd1 << 16) | (rd0 << 12) | (rs << 8));
546 }
547 }
548
549 static inline void tcg_out_smull32(TCGContext *s,
550 int cond, int rd0, int rd1, int rs, int rm)
551 {
552 if (rd0 != rm && rd1 != rm)
553 tcg_out32(s, (cond << 28) | 0xc00090 |
554 (rd1 << 16) | (rd0 << 12) | (rs << 8) | rm);
555 else if (rd0 != rs && rd1 != rs)
556 tcg_out32(s, (cond << 28) | 0xc00090 |
557 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rs);
558 else {
559 tcg_out_dat_reg(s, cond, ARITH_MOV,
560 TCG_REG_R8, 0, rm, SHIFT_IMM_LSL(0));
561 tcg_out32(s, (cond << 28) | 0xc00098 |
562 (rd1 << 16) | (rd0 << 12) | (rs << 8));
563 }
564 }
565
566 static inline void tcg_out_ext8s(TCGContext *s, int cond,
567 int rd, int rn)
568 {
569 if (use_armv6_instructions) {
570 /* sxtb */
571 tcg_out32(s, 0x06af0070 | (cond << 28) | (rd << 12) | rn);
572 } else {
573 tcg_out_dat_reg(s, cond, ARITH_MOV,
574 rd, 0, rn, SHIFT_IMM_LSL(24));
575 tcg_out_dat_reg(s, cond, ARITH_MOV,
576 rd, 0, rd, SHIFT_IMM_ASR(24));
577 }
578 }
579
580 static inline void tcg_out_ext8u(TCGContext *s, int cond,
581 int rd, int rn)
582 {
583 tcg_out_dat_imm(s, cond, ARITH_AND, rd, rn, 0xff);
584 }
585
586 static inline void tcg_out_ext16s(TCGContext *s, int cond,
587 int rd, int rn)
588 {
589 if (use_armv6_instructions) {
590 /* sxth */
591 tcg_out32(s, 0x06bf0070 | (cond << 28) | (rd << 12) | rn);
592 } else {
593 tcg_out_dat_reg(s, cond, ARITH_MOV,
594 rd, 0, rn, SHIFT_IMM_LSL(16));
595 tcg_out_dat_reg(s, cond, ARITH_MOV,
596 rd, 0, rd, SHIFT_IMM_ASR(16));
597 }
598 }
599
600 static inline void tcg_out_ext16u(TCGContext *s, int cond,
601 int rd, int rn)
602 {
603 if (use_armv6_instructions) {
604 /* uxth */
605 tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | rn);
606 } else {
607 tcg_out_dat_reg(s, cond, ARITH_MOV,
608 rd, 0, rn, SHIFT_IMM_LSL(16));
609 tcg_out_dat_reg(s, cond, ARITH_MOV,
610 rd, 0, rd, SHIFT_IMM_LSR(16));
611 }
612 }
613
614 static inline void tcg_out_bswap16s(TCGContext *s, int cond, int rd, int rn)
615 {
616 if (use_armv6_instructions) {
617 /* revsh */
618 tcg_out32(s, 0x06ff0fb0 | (cond << 28) | (rd << 12) | rn);
619 } else {
620 tcg_out_dat_reg(s, cond, ARITH_MOV,
621 TCG_REG_R8, 0, rn, SHIFT_IMM_LSL(24));
622 tcg_out_dat_reg(s, cond, ARITH_MOV,
623 TCG_REG_R8, 0, TCG_REG_R8, SHIFT_IMM_ASR(16));
624 tcg_out_dat_reg(s, cond, ARITH_ORR,
625 rd, TCG_REG_R8, rn, SHIFT_IMM_LSR(8));
626 }
627 }
628
629 static inline void tcg_out_bswap16(TCGContext *s, int cond, int rd, int rn)
630 {
631 if (use_armv6_instructions) {
632 /* rev16 */
633 tcg_out32(s, 0x06bf0fb0 | (cond << 28) | (rd << 12) | rn);
634 } else {
635 tcg_out_dat_reg(s, cond, ARITH_MOV,
636 TCG_REG_R8, 0, rn, SHIFT_IMM_LSL(24));
637 tcg_out_dat_reg(s, cond, ARITH_MOV,
638 TCG_REG_R8, 0, TCG_REG_R8, SHIFT_IMM_LSR(16));
639 tcg_out_dat_reg(s, cond, ARITH_ORR,
640 rd, TCG_REG_R8, rn, SHIFT_IMM_LSR(8));
641 }
642 }
643
644 /* swap the two low bytes assuming that the two high input bytes and the
645 two high output bit can hold any value. */
646 static inline void tcg_out_bswap16st(TCGContext *s, int cond, int rd, int rn)
647 {
648 if (use_armv6_instructions) {
649 /* rev16 */
650 tcg_out32(s, 0x06bf0fb0 | (cond << 28) | (rd << 12) | rn);
651 } else {
652 tcg_out_dat_reg(s, cond, ARITH_MOV,
653 TCG_REG_R8, 0, rn, SHIFT_IMM_LSR(8));
654 tcg_out_dat_imm(s, cond, ARITH_AND, TCG_REG_R8, TCG_REG_R8, 0xff);
655 tcg_out_dat_reg(s, cond, ARITH_ORR,
656 rd, TCG_REG_R8, rn, SHIFT_IMM_LSL(8));
657 }
658 }
659
660 static inline void tcg_out_bswap32(TCGContext *s, int cond, int rd, int rn)
661 {
662 if (use_armv6_instructions) {
663 /* rev */
664 tcg_out32(s, 0x06bf0f30 | (cond << 28) | (rd << 12) | rn);
665 } else {
666 tcg_out_dat_reg(s, cond, ARITH_EOR,
667 TCG_REG_R8, rn, rn, SHIFT_IMM_ROR(16));
668 tcg_out_dat_imm(s, cond, ARITH_BIC,
669 TCG_REG_R8, TCG_REG_R8, 0xff | 0x800);
670 tcg_out_dat_reg(s, cond, ARITH_MOV,
671 rd, 0, rn, SHIFT_IMM_ROR(8));
672 tcg_out_dat_reg(s, cond, ARITH_EOR,
673 rd, rd, TCG_REG_R8, SHIFT_IMM_LSR(8));
674 }
675 }
676
677 static inline void tcg_out_ld32_12(TCGContext *s, int cond,
678 int rd, int rn, tcg_target_long im)
679 {
680 if (im >= 0)
681 tcg_out32(s, (cond << 28) | 0x05900000 |
682 (rn << 16) | (rd << 12) | (im & 0xfff));
683 else
684 tcg_out32(s, (cond << 28) | 0x05100000 |
685 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
686 }
687
688 /* Offset pre-increment with base writeback. */
689 static inline void tcg_out_ld32_12wb(TCGContext *s, int cond,
690 int rd, int rn, tcg_target_long im)
691 {
692 /* ldr with writeback and both register equals is UNPREDICTABLE */
693 assert(rd != rn);
694
695 if (im >= 0) {
696 tcg_out32(s, (cond << 28) | 0x05b00000 |
697 (rn << 16) | (rd << 12) | (im & 0xfff));
698 } else {
699 tcg_out32(s, (cond << 28) | 0x05300000 |
700 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
701 }
702 }
703
704 static inline void tcg_out_st32_12(TCGContext *s, int cond,
705 int rd, int rn, tcg_target_long im)
706 {
707 if (im >= 0)
708 tcg_out32(s, (cond << 28) | 0x05800000 |
709 (rn << 16) | (rd << 12) | (im & 0xfff));
710 else
711 tcg_out32(s, (cond << 28) | 0x05000000 |
712 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
713 }
714
715 static inline void tcg_out_ld32_r(TCGContext *s, int cond,
716 int rd, int rn, int rm)
717 {
718 tcg_out32(s, (cond << 28) | 0x07900000 |
719 (rn << 16) | (rd << 12) | rm);
720 }
721
722 static inline void tcg_out_st32_r(TCGContext *s, int cond,
723 int rd, int rn, int rm)
724 {
725 tcg_out32(s, (cond << 28) | 0x07800000 |
726 (rn << 16) | (rd << 12) | rm);
727 }
728
729 /* Register pre-increment with base writeback. */
730 static inline void tcg_out_ld32_rwb(TCGContext *s, int cond,
731 int rd, int rn, int rm)
732 {
733 tcg_out32(s, (cond << 28) | 0x07b00000 |
734 (rn << 16) | (rd << 12) | rm);
735 }
736
737 static inline void tcg_out_st32_rwb(TCGContext *s, int cond,
738 int rd, int rn, int rm)
739 {
740 tcg_out32(s, (cond << 28) | 0x07a00000 |
741 (rn << 16) | (rd << 12) | rm);
742 }
743
744 static inline void tcg_out_ld16u_8(TCGContext *s, int cond,
745 int rd, int rn, tcg_target_long im)
746 {
747 if (im >= 0)
748 tcg_out32(s, (cond << 28) | 0x01d000b0 |
749 (rn << 16) | (rd << 12) |
750 ((im & 0xf0) << 4) | (im & 0xf));
751 else
752 tcg_out32(s, (cond << 28) | 0x015000b0 |
753 (rn << 16) | (rd << 12) |
754 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
755 }
756
757 static inline void tcg_out_st16_8(TCGContext *s, int cond,
758 int rd, int rn, tcg_target_long im)
759 {
760 if (im >= 0)
761 tcg_out32(s, (cond << 28) | 0x01c000b0 |
762 (rn << 16) | (rd << 12) |
763 ((im & 0xf0) << 4) | (im & 0xf));
764 else
765 tcg_out32(s, (cond << 28) | 0x014000b0 |
766 (rn << 16) | (rd << 12) |
767 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
768 }
769
770 static inline void tcg_out_ld16u_r(TCGContext *s, int cond,
771 int rd, int rn, int rm)
772 {
773 tcg_out32(s, (cond << 28) | 0x019000b0 |
774 (rn << 16) | (rd << 12) | rm);
775 }
776
777 static inline void tcg_out_st16_r(TCGContext *s, int cond,
778 int rd, int rn, int rm)
779 {
780 tcg_out32(s, (cond << 28) | 0x018000b0 |
781 (rn << 16) | (rd << 12) | rm);
782 }
783
784 static inline void tcg_out_ld16s_8(TCGContext *s, int cond,
785 int rd, int rn, tcg_target_long im)
786 {
787 if (im >= 0)
788 tcg_out32(s, (cond << 28) | 0x01d000f0 |
789 (rn << 16) | (rd << 12) |
790 ((im & 0xf0) << 4) | (im & 0xf));
791 else
792 tcg_out32(s, (cond << 28) | 0x015000f0 |
793 (rn << 16) | (rd << 12) |
794 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
795 }
796
797 static inline void tcg_out_ld16s_r(TCGContext *s, int cond,
798 int rd, int rn, int rm)
799 {
800 tcg_out32(s, (cond << 28) | 0x019000f0 |
801 (rn << 16) | (rd << 12) | rm);
802 }
803
804 static inline void tcg_out_ld8_12(TCGContext *s, int cond,
805 int rd, int rn, tcg_target_long im)
806 {
807 if (im >= 0)
808 tcg_out32(s, (cond << 28) | 0x05d00000 |
809 (rn << 16) | (rd << 12) | (im & 0xfff));
810 else
811 tcg_out32(s, (cond << 28) | 0x05500000 |
812 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
813 }
814
815 static inline void tcg_out_st8_12(TCGContext *s, int cond,
816 int rd, int rn, tcg_target_long im)
817 {
818 if (im >= 0)
819 tcg_out32(s, (cond << 28) | 0x05c00000 |
820 (rn << 16) | (rd << 12) | (im & 0xfff));
821 else
822 tcg_out32(s, (cond << 28) | 0x05400000 |
823 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
824 }
825
826 static inline void tcg_out_ld8_r(TCGContext *s, int cond,
827 int rd, int rn, int rm)
828 {
829 tcg_out32(s, (cond << 28) | 0x07d00000 |
830 (rn << 16) | (rd << 12) | rm);
831 }
832
833 static inline void tcg_out_st8_r(TCGContext *s, int cond,
834 int rd, int rn, int rm)
835 {
836 tcg_out32(s, (cond << 28) | 0x07c00000 |
837 (rn << 16) | (rd << 12) | rm);
838 }
839
840 static inline void tcg_out_ld8s_8(TCGContext *s, int cond,
841 int rd, int rn, tcg_target_long im)
842 {
843 if (im >= 0)
844 tcg_out32(s, (cond << 28) | 0x01d000d0 |
845 (rn << 16) | (rd << 12) |
846 ((im & 0xf0) << 4) | (im & 0xf));
847 else
848 tcg_out32(s, (cond << 28) | 0x015000d0 |
849 (rn << 16) | (rd << 12) |
850 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
851 }
852
853 static inline void tcg_out_ld8s_r(TCGContext *s, int cond,
854 int rd, int rn, int rm)
855 {
856 tcg_out32(s, (cond << 28) | 0x019000d0 |
857 (rn << 16) | (rd << 12) | rm);
858 }
859
860 static inline void tcg_out_ld32u(TCGContext *s, int cond,
861 int rd, int rn, int32_t offset)
862 {
863 if (offset > 0xfff || offset < -0xfff) {
864 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
865 tcg_out_ld32_r(s, cond, rd, rn, TCG_REG_R8);
866 } else
867 tcg_out_ld32_12(s, cond, rd, rn, offset);
868 }
869
870 static inline void tcg_out_st32(TCGContext *s, int cond,
871 int rd, int rn, int32_t offset)
872 {
873 if (offset > 0xfff || offset < -0xfff) {
874 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
875 tcg_out_st32_r(s, cond, rd, rn, TCG_REG_R8);
876 } else
877 tcg_out_st32_12(s, cond, rd, rn, offset);
878 }
879
880 static inline void tcg_out_ld16u(TCGContext *s, int cond,
881 int rd, int rn, int32_t offset)
882 {
883 if (offset > 0xff || offset < -0xff) {
884 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
885 tcg_out_ld16u_r(s, cond, rd, rn, TCG_REG_R8);
886 } else
887 tcg_out_ld16u_8(s, cond, rd, rn, offset);
888 }
889
890 static inline void tcg_out_ld16s(TCGContext *s, int cond,
891 int rd, int rn, int32_t offset)
892 {
893 if (offset > 0xff || offset < -0xff) {
894 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
895 tcg_out_ld16s_r(s, cond, rd, rn, TCG_REG_R8);
896 } else
897 tcg_out_ld16s_8(s, cond, rd, rn, offset);
898 }
899
900 static inline void tcg_out_st16(TCGContext *s, int cond,
901 int rd, int rn, int32_t offset)
902 {
903 if (offset > 0xff || offset < -0xff) {
904 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
905 tcg_out_st16_r(s, cond, rd, rn, TCG_REG_R8);
906 } else
907 tcg_out_st16_8(s, cond, rd, rn, offset);
908 }
909
910 static inline void tcg_out_ld8u(TCGContext *s, int cond,
911 int rd, int rn, int32_t offset)
912 {
913 if (offset > 0xfff || offset < -0xfff) {
914 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
915 tcg_out_ld8_r(s, cond, rd, rn, TCG_REG_R8);
916 } else
917 tcg_out_ld8_12(s, cond, rd, rn, offset);
918 }
919
920 static inline void tcg_out_ld8s(TCGContext *s, int cond,
921 int rd, int rn, int32_t offset)
922 {
923 if (offset > 0xff || offset < -0xff) {
924 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
925 tcg_out_ld8s_r(s, cond, rd, rn, TCG_REG_R8);
926 } else
927 tcg_out_ld8s_8(s, cond, rd, rn, offset);
928 }
929
930 static inline void tcg_out_st8(TCGContext *s, int cond,
931 int rd, int rn, int32_t offset)
932 {
933 if (offset > 0xfff || offset < -0xfff) {
934 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
935 tcg_out_st8_r(s, cond, rd, rn, TCG_REG_R8);
936 } else
937 tcg_out_st8_12(s, cond, rd, rn, offset);
938 }
939
940 /* The _goto case is normally between TBs within the same code buffer,
941 * and with the code buffer limited to 16MB we shouldn't need the long
942 * case.
943 *
944 * .... except to the prologue that is in its own buffer.
945 */
946 static inline void tcg_out_goto(TCGContext *s, int cond, uint32_t addr)
947 {
948 int32_t val;
949
950 if (addr & 1) {
951 /* goto to a Thumb destination isn't supported */
952 tcg_abort();
953 }
954
955 val = addr - (tcg_target_long) s->code_ptr;
956 if (val - 8 < 0x01fffffd && val - 8 > -0x01fffffd)
957 tcg_out_b(s, cond, val);
958 else {
959 if (cond == COND_AL) {
960 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4);
961 tcg_out32(s, addr);
962 } else {
963 tcg_out_movi32(s, cond, TCG_REG_R8, val - 8);
964 tcg_out_dat_reg(s, cond, ARITH_ADD,
965 TCG_REG_PC, TCG_REG_PC,
966 TCG_REG_R8, SHIFT_IMM_LSL(0));
967 }
968 }
969 }
970
971 /* The call case is mostly used for helpers - so it's not unreasonable
972 * for them to be beyond branch range */
973 static inline void tcg_out_call(TCGContext *s, uint32_t addr)
974 {
975 int32_t val;
976
977 val = addr - (tcg_target_long) s->code_ptr;
978 if (val - 8 < 0x02000000 && val - 8 >= -0x02000000) {
979 if (addr & 1) {
980 /* Use BLX if the target is in Thumb mode */
981 if (!use_armv5_instructions) {
982 tcg_abort();
983 }
984 tcg_out_blx_imm(s, val);
985 } else {
986 tcg_out_bl(s, COND_AL, val);
987 }
988 } else {
989 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R14, TCG_REG_PC, 4);
990 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4);
991 tcg_out32(s, addr);
992 }
993 }
994
995 static inline void tcg_out_callr(TCGContext *s, int cond, int arg)
996 {
997 if (use_armv5_instructions) {
998 tcg_out_blx(s, cond, arg);
999 } else {
1000 tcg_out_dat_reg(s, cond, ARITH_MOV, TCG_REG_R14, 0,
1001 TCG_REG_PC, SHIFT_IMM_LSL(0));
1002 tcg_out_bx(s, cond, arg);
1003 }
1004 }
1005
1006 static inline void tcg_out_goto_label(TCGContext *s, int cond, int label_index)
1007 {
1008 TCGLabel *l = &s->labels[label_index];
1009
1010 if (l->has_value)
1011 tcg_out_goto(s, cond, l->u.value);
1012 else if (cond == COND_AL) {
1013 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4);
1014 tcg_out_reloc(s, s->code_ptr, R_ARM_ABS32, label_index, 31337);
1015 s->code_ptr += 4;
1016 } else {
1017 /* Probably this should be preferred even for COND_AL... */
1018 tcg_out_reloc(s, s->code_ptr, R_ARM_PC24, label_index, 31337);
1019 tcg_out_b_noaddr(s, cond);
1020 }
1021 }
1022
1023 #ifdef CONFIG_SOFTMMU
1024
1025 #include "exec/softmmu_defs.h"
1026
1027 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
1028 int mmu_idx) */
1029 static const void * const qemu_ld_helpers[4] = {
1030 helper_ldb_mmu,
1031 helper_ldw_mmu,
1032 helper_ldl_mmu,
1033 helper_ldq_mmu,
1034 };
1035
1036 /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
1037 uintxx_t val, int mmu_idx) */
1038 static const void * const qemu_st_helpers[4] = {
1039 helper_stb_mmu,
1040 helper_stw_mmu,
1041 helper_stl_mmu,
1042 helper_stq_mmu,
1043 };
1044
1045 /* Helper routines for marshalling helper function arguments into
1046 * the correct registers and stack.
1047 * argreg is where we want to put this argument, arg is the argument itself.
1048 * Return value is the updated argreg ready for the next call.
1049 * Note that argreg 0..3 is real registers, 4+ on stack.
1050 *
1051 * We provide routines for arguments which are: immediate, 32 bit
1052 * value in register, 16 and 8 bit values in register (which must be zero
1053 * extended before use) and 64 bit value in a lo:hi register pair.
1054 */
1055 #define DEFINE_TCG_OUT_ARG(NAME, ARGTYPE, MOV_ARG, EXT_ARG) \
1056 static TCGReg NAME(TCGContext *s, TCGReg argreg, ARGTYPE arg) \
1057 { \
1058 if (argreg < 4) { \
1059 MOV_ARG(s, COND_AL, argreg, arg); \
1060 } else { \
1061 int ofs = (argreg - 4) * 4; \
1062 EXT_ARG; \
1063 assert(ofs + 4 <= TCG_STATIC_CALL_ARGS_SIZE); \
1064 tcg_out_st32_12(s, COND_AL, arg, TCG_REG_CALL_STACK, ofs); \
1065 } \
1066 return argreg + 1; \
1067 }
1068
1069 DEFINE_TCG_OUT_ARG(tcg_out_arg_imm32, uint32_t, tcg_out_movi32,
1070 (tcg_out_movi32(s, COND_AL, TCG_REG_R8, arg), arg = TCG_REG_R8))
1071 DEFINE_TCG_OUT_ARG(tcg_out_arg_reg8, TCGReg, tcg_out_ext8u,
1072 (tcg_out_ext8u(s, COND_AL, TCG_REG_R8, arg), arg = TCG_REG_R8))
1073 DEFINE_TCG_OUT_ARG(tcg_out_arg_reg16, TCGReg, tcg_out_ext16u,
1074 (tcg_out_ext16u(s, COND_AL, TCG_REG_R8, arg), arg = TCG_REG_R8))
1075 DEFINE_TCG_OUT_ARG(tcg_out_arg_reg32, TCGReg, tcg_out_mov_reg, )
1076
1077 static TCGReg tcg_out_arg_reg64(TCGContext *s, TCGReg argreg,
1078 TCGReg arglo, TCGReg arghi)
1079 {
1080 /* 64 bit arguments must go in even/odd register pairs
1081 * and in 8-aligned stack slots.
1082 */
1083 if (argreg & 1) {
1084 argreg++;
1085 }
1086 argreg = tcg_out_arg_reg32(s, argreg, arglo);
1087 argreg = tcg_out_arg_reg32(s, argreg, arghi);
1088 return argreg;
1089 }
1090 #endif /* SOFTMMU */
1091
1092 #define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS)
1093
1094 static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
1095 {
1096 int addr_reg, data_reg, data_reg2, bswap;
1097 #ifdef CONFIG_SOFTMMU
1098 int mem_index, s_bits, tlb_offset;
1099 TCGReg argreg;
1100 # if TARGET_LONG_BITS == 64
1101 int addr_reg2;
1102 # endif
1103 uint32_t *label_ptr;
1104 #endif
1105
1106 #ifdef TARGET_WORDS_BIGENDIAN
1107 bswap = 1;
1108 #else
1109 bswap = 0;
1110 #endif
1111 data_reg = *args++;
1112 if (opc == 3)
1113 data_reg2 = *args++;
1114 else
1115 data_reg2 = 0; /* suppress warning */
1116 addr_reg = *args++;
1117 #ifdef CONFIG_SOFTMMU
1118 # if TARGET_LONG_BITS == 64
1119 addr_reg2 = *args++;
1120 # endif
1121 mem_index = *args;
1122 s_bits = opc & 3;
1123
1124 /* Should generate something like the following:
1125 * shr r8, addr_reg, #TARGET_PAGE_BITS
1126 * and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8
1127 * add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
1128 */
1129 # if CPU_TLB_BITS > 8
1130 # error
1131 # endif
1132 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_R8,
1133 0, addr_reg, SHIFT_IMM_LSR(TARGET_PAGE_BITS));
1134 tcg_out_dat_imm(s, COND_AL, ARITH_AND,
1135 TCG_REG_R0, TCG_REG_R8, CPU_TLB_SIZE - 1);
1136 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_AREG0,
1137 TCG_REG_R0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS));
1138 /* We assume that the offset is contained within 20 bits. */
1139 tlb_offset = offsetof(CPUArchState, tlb_table[mem_index][0].addr_read);
1140 assert((tlb_offset & ~0xfffff) == 0);
1141 if (tlb_offset > 0xfff) {
1142 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_REG_R0,
1143 0xa00 | (tlb_offset >> 12));
1144 tlb_offset &= 0xfff;
1145 }
1146 tcg_out_ld32_12wb(s, COND_AL, TCG_REG_R1, TCG_REG_R0, tlb_offset);
1147 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R1,
1148 TCG_REG_R8, SHIFT_IMM_LSL(TARGET_PAGE_BITS));
1149 /* Check alignment. */
1150 if (s_bits)
1151 tcg_out_dat_imm(s, COND_EQ, ARITH_TST,
1152 0, addr_reg, (1 << s_bits) - 1);
1153 # if TARGET_LONG_BITS == 64
1154 /* XXX: possibly we could use a block data load in the first access. */
1155 tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0, 4);
1156 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
1157 TCG_REG_R1, addr_reg2, SHIFT_IMM_LSL(0));
1158 # endif
1159 tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
1160 offsetof(CPUTLBEntry, addend)
1161 - offsetof(CPUTLBEntry, addr_read));
1162
1163 switch (opc) {
1164 case 0:
1165 tcg_out_ld8_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
1166 break;
1167 case 0 | 4:
1168 tcg_out_ld8s_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
1169 break;
1170 case 1:
1171 tcg_out_ld16u_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
1172 if (bswap) {
1173 tcg_out_bswap16(s, COND_EQ, data_reg, data_reg);
1174 }
1175 break;
1176 case 1 | 4:
1177 if (bswap) {
1178 tcg_out_ld16u_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
1179 tcg_out_bswap16s(s, COND_EQ, data_reg, data_reg);
1180 } else {
1181 tcg_out_ld16s_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
1182 }
1183 break;
1184 case 2:
1185 default:
1186 tcg_out_ld32_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
1187 if (bswap) {
1188 tcg_out_bswap32(s, COND_EQ, data_reg, data_reg);
1189 }
1190 break;
1191 case 3:
1192 if (bswap) {
1193 tcg_out_ld32_rwb(s, COND_EQ, data_reg2, TCG_REG_R1, addr_reg);
1194 tcg_out_ld32_12(s, COND_EQ, data_reg, TCG_REG_R1, 4);
1195 tcg_out_bswap32(s, COND_EQ, data_reg2, data_reg2);
1196 tcg_out_bswap32(s, COND_EQ, data_reg, data_reg);
1197 } else {
1198 tcg_out_ld32_rwb(s, COND_EQ, data_reg, TCG_REG_R1, addr_reg);
1199 tcg_out_ld32_12(s, COND_EQ, data_reg2, TCG_REG_R1, 4);
1200 }
1201 break;
1202 }
1203
1204 label_ptr = (void *) s->code_ptr;
1205 tcg_out_b_noaddr(s, COND_EQ);
1206
1207 /* TODO: move this code to where the constants pool will be */
1208 /* Note that this code relies on the constraints we set in arm_op_defs[]
1209 * to ensure that later arguments are not passed to us in registers we
1210 * trash by moving the earlier arguments into them.
1211 */
1212 argreg = TCG_REG_R0;
1213 argreg = tcg_out_arg_reg32(s, argreg, TCG_AREG0);
1214 #if TARGET_LONG_BITS == 64
1215 argreg = tcg_out_arg_reg64(s, argreg, addr_reg, addr_reg2);
1216 #else
1217 argreg = tcg_out_arg_reg32(s, argreg, addr_reg);
1218 #endif
1219 argreg = tcg_out_arg_imm32(s, argreg, mem_index);
1220 tcg_out_call(s, (tcg_target_long) qemu_ld_helpers[s_bits]);
1221
1222 switch (opc) {
1223 case 0 | 4:
1224 tcg_out_ext8s(s, COND_AL, data_reg, TCG_REG_R0);
1225 break;
1226 case 1 | 4:
1227 tcg_out_ext16s(s, COND_AL, data_reg, TCG_REG_R0);
1228 break;
1229 case 0:
1230 case 1:
1231 case 2:
1232 default:
1233 tcg_out_mov_reg(s, COND_AL, data_reg, TCG_REG_R0);
1234 break;
1235 case 3:
1236 tcg_out_mov_reg(s, COND_AL, data_reg, TCG_REG_R0);
1237 tcg_out_mov_reg(s, COND_AL, data_reg2, TCG_REG_R1);
1238 break;
1239 }
1240
1241 reloc_pc24(label_ptr, (tcg_target_long)s->code_ptr);
1242 #else /* !CONFIG_SOFTMMU */
1243 if (GUEST_BASE) {
1244 uint32_t offset = GUEST_BASE;
1245 int i;
1246 int rot;
1247
1248 while (offset) {
1249 i = ctz32(offset) & ~1;
1250 rot = ((32 - i) << 7) & 0xf00;
1251
1252 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R8, addr_reg,
1253 ((offset >> i) & 0xff) | rot);
1254 addr_reg = TCG_REG_R8;
1255 offset &= ~(0xff << i);
1256 }
1257 }
1258 switch (opc) {
1259 case 0:
1260 tcg_out_ld8_12(s, COND_AL, data_reg, addr_reg, 0);
1261 break;
1262 case 0 | 4:
1263 tcg_out_ld8s_8(s, COND_AL, data_reg, addr_reg, 0);
1264 break;
1265 case 1:
1266 tcg_out_ld16u_8(s, COND_AL, data_reg, addr_reg, 0);
1267 if (bswap) {
1268 tcg_out_bswap16(s, COND_AL, data_reg, data_reg);
1269 }
1270 break;
1271 case 1 | 4:
1272 if (bswap) {
1273 tcg_out_ld16u_8(s, COND_AL, data_reg, addr_reg, 0);
1274 tcg_out_bswap16s(s, COND_AL, data_reg, data_reg);
1275 } else {
1276 tcg_out_ld16s_8(s, COND_AL, data_reg, addr_reg, 0);
1277 }
1278 break;
1279 case 2:
1280 default:
1281 tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, 0);
1282 if (bswap) {
1283 tcg_out_bswap32(s, COND_AL, data_reg, data_reg);
1284 }
1285 break;
1286 case 3:
1287 /* TODO: use block load -
1288 * check that data_reg2 > data_reg or the other way */
1289 if (data_reg == addr_reg) {
1290 tcg_out_ld32_12(s, COND_AL, data_reg2, addr_reg, bswap ? 0 : 4);
1291 tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, bswap ? 4 : 0);
1292 } else {
1293 tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, bswap ? 4 : 0);
1294 tcg_out_ld32_12(s, COND_AL, data_reg2, addr_reg, bswap ? 0 : 4);
1295 }
1296 if (bswap) {
1297 tcg_out_bswap32(s, COND_AL, data_reg, data_reg);
1298 tcg_out_bswap32(s, COND_AL, data_reg2, data_reg2);
1299 }
1300 break;
1301 }
1302 #endif
1303 }
1304
1305 static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
1306 {
1307 int addr_reg, data_reg, data_reg2, bswap;
1308 #ifdef CONFIG_SOFTMMU
1309 int mem_index, s_bits, tlb_offset;
1310 TCGReg argreg;
1311 # if TARGET_LONG_BITS == 64
1312 int addr_reg2;
1313 # endif
1314 uint32_t *label_ptr;
1315 #endif
1316
1317 #ifdef TARGET_WORDS_BIGENDIAN
1318 bswap = 1;
1319 #else
1320 bswap = 0;
1321 #endif
1322 data_reg = *args++;
1323 if (opc == 3)
1324 data_reg2 = *args++;
1325 else
1326 data_reg2 = 0; /* suppress warning */
1327 addr_reg = *args++;
1328 #ifdef CONFIG_SOFTMMU
1329 # if TARGET_LONG_BITS == 64
1330 addr_reg2 = *args++;
1331 # endif
1332 mem_index = *args;
1333 s_bits = opc & 3;
1334
1335 /* Should generate something like the following:
1336 * shr r8, addr_reg, #TARGET_PAGE_BITS
1337 * and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8
1338 * add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
1339 */
1340 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1341 TCG_REG_R8, 0, addr_reg, SHIFT_IMM_LSR(TARGET_PAGE_BITS));
1342 tcg_out_dat_imm(s, COND_AL, ARITH_AND,
1343 TCG_REG_R0, TCG_REG_R8, CPU_TLB_SIZE - 1);
1344 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_R0,
1345 TCG_AREG0, TCG_REG_R0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS));
1346 /* We assume that the offset is contained within 20 bits. */
1347 tlb_offset = offsetof(CPUArchState, tlb_table[mem_index][0].addr_write);
1348 assert((tlb_offset & ~0xfffff) == 0);
1349 if (tlb_offset > 0xfff) {
1350 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_REG_R0,
1351 0xa00 | (tlb_offset >> 12));
1352 tlb_offset &= 0xfff;
1353 }
1354 tcg_out_ld32_12wb(s, COND_AL, TCG_REG_R1, TCG_REG_R0, tlb_offset);
1355 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R1,
1356 TCG_REG_R8, SHIFT_IMM_LSL(TARGET_PAGE_BITS));
1357 /* Check alignment. */
1358 if (s_bits)
1359 tcg_out_dat_imm(s, COND_EQ, ARITH_TST,
1360 0, addr_reg, (1 << s_bits) - 1);
1361 # if TARGET_LONG_BITS == 64
1362 /* XXX: possibly we could use a block data load in the first access. */
1363 tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0, 4);
1364 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
1365 TCG_REG_R1, addr_reg2, SHIFT_IMM_LSL(0));
1366 # endif
1367 tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
1368 offsetof(CPUTLBEntry, addend)
1369 - offsetof(CPUTLBEntry, addr_write));
1370
1371 switch (opc) {
1372 case 0:
1373 tcg_out_st8_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
1374 break;
1375 case 1:
1376 if (bswap) {
1377 tcg_out_bswap16st(s, COND_EQ, TCG_REG_R0, data_reg);
1378 tcg_out_st16_r(s, COND_EQ, TCG_REG_R0, addr_reg, TCG_REG_R1);
1379 } else {
1380 tcg_out_st16_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
1381 }
1382 break;
1383 case 2:
1384 default:
1385 if (bswap) {
1386 tcg_out_bswap32(s, COND_EQ, TCG_REG_R0, data_reg);
1387 tcg_out_st32_r(s, COND_EQ, TCG_REG_R0, addr_reg, TCG_REG_R1);
1388 } else {
1389 tcg_out_st32_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
1390 }
1391 break;
1392 case 3:
1393 if (bswap) {
1394 tcg_out_bswap32(s, COND_EQ, TCG_REG_R0, data_reg2);
1395 tcg_out_st32_rwb(s, COND_EQ, TCG_REG_R0, TCG_REG_R1, addr_reg);
1396 tcg_out_bswap32(s, COND_EQ, TCG_REG_R0, data_reg);
1397 tcg_out_st32_12(s, COND_EQ, TCG_REG_R0, TCG_REG_R1, 4);
1398 } else {
1399 tcg_out_st32_rwb(s, COND_EQ, data_reg, TCG_REG_R1, addr_reg);
1400 tcg_out_st32_12(s, COND_EQ, data_reg2, TCG_REG_R1, 4);
1401 }
1402 break;
1403 }
1404
1405 label_ptr = (void *) s->code_ptr;
1406 tcg_out_b_noaddr(s, COND_EQ);
1407
1408 /* TODO: move this code to where the constants pool will be */
1409 /* Note that this code relies on the constraints we set in arm_op_defs[]
1410 * to ensure that later arguments are not passed to us in registers we
1411 * trash by moving the earlier arguments into them.
1412 */
1413 argreg = TCG_REG_R0;
1414 argreg = tcg_out_arg_reg32(s, argreg, TCG_AREG0);
1415 #if TARGET_LONG_BITS == 64
1416 argreg = tcg_out_arg_reg64(s, argreg, addr_reg, addr_reg2);
1417 #else
1418 argreg = tcg_out_arg_reg32(s, argreg, addr_reg);
1419 #endif
1420
1421 switch (opc) {
1422 case 0:
1423 argreg = tcg_out_arg_reg8(s, argreg, data_reg);
1424 break;
1425 case 1:
1426 argreg = tcg_out_arg_reg16(s, argreg, data_reg);
1427 break;
1428 case 2:
1429 argreg = tcg_out_arg_reg32(s, argreg, data_reg);
1430 break;
1431 case 3:
1432 argreg = tcg_out_arg_reg64(s, argreg, data_reg, data_reg2);
1433 break;
1434 }
1435
1436 argreg = tcg_out_arg_imm32(s, argreg, mem_index);
1437 tcg_out_call(s, (tcg_target_long) qemu_st_helpers[s_bits]);
1438
1439 reloc_pc24(label_ptr, (tcg_target_long)s->code_ptr);
1440 #else /* !CONFIG_SOFTMMU */
1441 if (GUEST_BASE) {
1442 uint32_t offset = GUEST_BASE;
1443 int i;
1444 int rot;
1445
1446 while (offset) {
1447 i = ctz32(offset) & ~1;
1448 rot = ((32 - i) << 7) & 0xf00;
1449
1450 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R1, addr_reg,
1451 ((offset >> i) & 0xff) | rot);
1452 addr_reg = TCG_REG_R1;
1453 offset &= ~(0xff << i);
1454 }
1455 }
1456 switch (opc) {
1457 case 0:
1458 tcg_out_st8_12(s, COND_AL, data_reg, addr_reg, 0);
1459 break;
1460 case 1:
1461 if (bswap) {
1462 tcg_out_bswap16st(s, COND_AL, TCG_REG_R0, data_reg);
1463 tcg_out_st16_8(s, COND_AL, TCG_REG_R0, addr_reg, 0);
1464 } else {
1465 tcg_out_st16_8(s, COND_AL, data_reg, addr_reg, 0);
1466 }
1467 break;
1468 case 2:
1469 default:
1470 if (bswap) {
1471 tcg_out_bswap32(s, COND_AL, TCG_REG_R0, data_reg);
1472 tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addr_reg, 0);
1473 } else {
1474 tcg_out_st32_12(s, COND_AL, data_reg, addr_reg, 0);
1475 }
1476 break;
1477 case 3:
1478 /* TODO: use block store -
1479 * check that data_reg2 > data_reg or the other way */
1480 if (bswap) {
1481 tcg_out_bswap32(s, COND_AL, TCG_REG_R0, data_reg2);
1482 tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addr_reg, 0);
1483 tcg_out_bswap32(s, COND_AL, TCG_REG_R0, data_reg);
1484 tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addr_reg, 4);
1485 } else {
1486 tcg_out_st32_12(s, COND_AL, data_reg, addr_reg, 0);
1487 tcg_out_st32_12(s, COND_AL, data_reg2, addr_reg, 4);
1488 }
1489 break;
1490 }
1491 #endif
1492 }
1493
1494 static uint8_t *tb_ret_addr;
1495
1496 static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
1497 const TCGArg *args, const int *const_args)
1498 {
1499 int c;
1500
1501 switch (opc) {
1502 case INDEX_op_exit_tb:
1503 {
1504 uint8_t *ld_ptr = s->code_ptr;
1505 if (args[0] >> 8)
1506 tcg_out_ld32_12(s, COND_AL, TCG_REG_R0, TCG_REG_PC, 0);
1507 else
1508 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R0, 0, args[0]);
1509 tcg_out_goto(s, COND_AL, (tcg_target_ulong) tb_ret_addr);
1510 if (args[0] >> 8) {
1511 *ld_ptr = (uint8_t) (s->code_ptr - ld_ptr) - 8;
1512 tcg_out32(s, args[0]);
1513 }
1514 }
1515 break;
1516 case INDEX_op_goto_tb:
1517 if (s->tb_jmp_offset) {
1518 /* Direct jump method */
1519 #if defined(USE_DIRECT_JUMP)
1520 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1521 tcg_out_b_noaddr(s, COND_AL);
1522 #else
1523 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4);
1524 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1525 tcg_out32(s, 0);
1526 #endif
1527 } else {
1528 /* Indirect jump method */
1529 #if 1
1530 c = (int) (s->tb_next + args[0]) - ((int) s->code_ptr + 8);
1531 if (c > 0xfff || c < -0xfff) {
1532 tcg_out_movi32(s, COND_AL, TCG_REG_R0,
1533 (tcg_target_long) (s->tb_next + args[0]));
1534 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_R0, 0);
1535 } else
1536 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, c);
1537 #else
1538 tcg_out_ld32_12(s, COND_AL, TCG_REG_R0, TCG_REG_PC, 0);
1539 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_R0, 0);
1540 tcg_out32(s, (tcg_target_long) (s->tb_next + args[0]));
1541 #endif
1542 }
1543 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1544 break;
1545 case INDEX_op_call:
1546 if (const_args[0])
1547 tcg_out_call(s, args[0]);
1548 else
1549 tcg_out_callr(s, COND_AL, args[0]);
1550 break;
1551 case INDEX_op_br:
1552 tcg_out_goto_label(s, COND_AL, args[0]);
1553 break;
1554
1555 case INDEX_op_ld8u_i32:
1556 tcg_out_ld8u(s, COND_AL, args[0], args[1], args[2]);
1557 break;
1558 case INDEX_op_ld8s_i32:
1559 tcg_out_ld8s(s, COND_AL, args[0], args[1], args[2]);
1560 break;
1561 case INDEX_op_ld16u_i32:
1562 tcg_out_ld16u(s, COND_AL, args[0], args[1], args[2]);
1563 break;
1564 case INDEX_op_ld16s_i32:
1565 tcg_out_ld16s(s, COND_AL, args[0], args[1], args[2]);
1566 break;
1567 case INDEX_op_ld_i32:
1568 tcg_out_ld32u(s, COND_AL, args[0], args[1], args[2]);
1569 break;
1570 case INDEX_op_st8_i32:
1571 tcg_out_st8(s, COND_AL, args[0], args[1], args[2]);
1572 break;
1573 case INDEX_op_st16_i32:
1574 tcg_out_st16(s, COND_AL, args[0], args[1], args[2]);
1575 break;
1576 case INDEX_op_st_i32:
1577 tcg_out_st32(s, COND_AL, args[0], args[1], args[2]);
1578 break;
1579
1580 case INDEX_op_mov_i32:
1581 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1582 args[0], 0, args[1], SHIFT_IMM_LSL(0));
1583 break;
1584 case INDEX_op_movi_i32:
1585 tcg_out_movi32(s, COND_AL, args[0], args[1]);
1586 break;
1587 case INDEX_op_movcond_i32:
1588 /* Constraints mean that v2 is always in the same register as dest,
1589 * so we only need to do "if condition passed, move v1 to dest".
1590 */
1591 tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0,
1592 args[1], args[2], const_args[2]);
1593 tcg_out_dat_rI(s, tcg_cond_to_arm_cond[args[5]],
1594 ARITH_MOV, args[0], 0, args[3], const_args[3]);
1595 break;
1596 case INDEX_op_add_i32:
1597 c = ARITH_ADD;
1598 goto gen_arith;
1599 case INDEX_op_sub_i32:
1600 c = ARITH_SUB;
1601 goto gen_arith;
1602 case INDEX_op_and_i32:
1603 tcg_out_dat_rIK(s, COND_AL, ARITH_AND, ARITH_BIC,
1604 args[0], args[1], args[2], const_args[2]);
1605 break;
1606 case INDEX_op_andc_i32:
1607 tcg_out_dat_rIK(s, COND_AL, ARITH_BIC, ARITH_AND,
1608 args[0], args[1], args[2], const_args[2]);
1609 break;
1610 case INDEX_op_or_i32:
1611 c = ARITH_ORR;
1612 goto gen_arith;
1613 case INDEX_op_xor_i32:
1614 c = ARITH_EOR;
1615 /* Fall through. */
1616 gen_arith:
1617 tcg_out_dat_rI(s, COND_AL, c, args[0], args[1], args[2], const_args[2]);
1618 break;
1619 case INDEX_op_add2_i32:
1620 tcg_out_dat_reg2(s, COND_AL, ARITH_ADD, ARITH_ADC,
1621 args[0], args[1], args[2], args[3],
1622 args[4], args[5], SHIFT_IMM_LSL(0));
1623 break;
1624 case INDEX_op_sub2_i32:
1625 tcg_out_dat_reg2(s, COND_AL, ARITH_SUB, ARITH_SBC,
1626 args[0], args[1], args[2], args[3],
1627 args[4], args[5], SHIFT_IMM_LSL(0));
1628 break;
1629 case INDEX_op_neg_i32:
1630 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, args[0], args[1], 0);
1631 break;
1632 case INDEX_op_not_i32:
1633 tcg_out_dat_reg(s, COND_AL,
1634 ARITH_MVN, args[0], 0, args[1], SHIFT_IMM_LSL(0));
1635 break;
1636 case INDEX_op_mul_i32:
1637 tcg_out_mul32(s, COND_AL, args[0], args[1], args[2]);
1638 break;
1639 case INDEX_op_mulu2_i32:
1640 tcg_out_umull32(s, COND_AL, args[0], args[1], args[2], args[3]);
1641 break;
1642 case INDEX_op_muls2_i32:
1643 tcg_out_smull32(s, COND_AL, args[0], args[1], args[2], args[3]);
1644 break;
1645 /* XXX: Perhaps args[2] & 0x1f is wrong */
1646 case INDEX_op_shl_i32:
1647 c = const_args[2] ?
1648 SHIFT_IMM_LSL(args[2] & 0x1f) : SHIFT_REG_LSL(args[2]);
1649 goto gen_shift32;
1650 case INDEX_op_shr_i32:
1651 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_LSR(args[2] & 0x1f) :
1652 SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args[2]);
1653 goto gen_shift32;
1654 case INDEX_op_sar_i32:
1655 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ASR(args[2] & 0x1f) :
1656 SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args[2]);
1657 goto gen_shift32;
1658 case INDEX_op_rotr_i32:
1659 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ROR(args[2] & 0x1f) :
1660 SHIFT_IMM_LSL(0) : SHIFT_REG_ROR(args[2]);
1661 /* Fall through. */
1662 gen_shift32:
1663 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], c);
1664 break;
1665
1666 case INDEX_op_rotl_i32:
1667 if (const_args[2]) {
1668 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1],
1669 ((0x20 - args[2]) & 0x1f) ?
1670 SHIFT_IMM_ROR((0x20 - args[2]) & 0x1f) :
1671 SHIFT_IMM_LSL(0));
1672 } else {
1673 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, TCG_REG_R8, args[1], 0x20);
1674 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1],
1675 SHIFT_REG_ROR(TCG_REG_R8));
1676 }
1677 break;
1678
1679 case INDEX_op_brcond_i32:
1680 tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0,
1681 args[0], args[1], const_args[1]);
1682 tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[2]], args[3]);
1683 break;
1684 case INDEX_op_brcond2_i32:
1685 /* The resulting conditions are:
1686 * TCG_COND_EQ --> a0 == a2 && a1 == a3,
1687 * TCG_COND_NE --> (a0 != a2 && a1 == a3) || a1 != a3,
1688 * TCG_COND_LT(U) --> (a0 < a2 && a1 == a3) || a1 < a3,
1689 * TCG_COND_GE(U) --> (a0 >= a2 && a1 == a3) || (a1 >= a3 && a1 != a3),
1690 * TCG_COND_LE(U) --> (a0 <= a2 && a1 == a3) || (a1 <= a3 && a1 != a3),
1691 * TCG_COND_GT(U) --> (a0 > a2 && a1 == a3) || a1 > a3,
1692 */
1693 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1694 args[1], args[3], SHIFT_IMM_LSL(0));
1695 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
1696 args[0], args[2], SHIFT_IMM_LSL(0));
1697 tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[4]], args[5]);
1698 break;
1699 case INDEX_op_setcond_i32:
1700 tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0,
1701 args[1], args[2], const_args[2]);
1702 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[3]],
1703 ARITH_MOV, args[0], 0, 1);
1704 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[3])],
1705 ARITH_MOV, args[0], 0, 0);
1706 break;
1707 case INDEX_op_setcond2_i32:
1708 /* See brcond2_i32 comment */
1709 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1710 args[2], args[4], SHIFT_IMM_LSL(0));
1711 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
1712 args[1], args[3], SHIFT_IMM_LSL(0));
1713 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[5]],
1714 ARITH_MOV, args[0], 0, 1);
1715 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[5])],
1716 ARITH_MOV, args[0], 0, 0);
1717 break;
1718
1719 case INDEX_op_qemu_ld8u:
1720 tcg_out_qemu_ld(s, args, 0);
1721 break;
1722 case INDEX_op_qemu_ld8s:
1723 tcg_out_qemu_ld(s, args, 0 | 4);
1724 break;
1725 case INDEX_op_qemu_ld16u:
1726 tcg_out_qemu_ld(s, args, 1);
1727 break;
1728 case INDEX_op_qemu_ld16s:
1729 tcg_out_qemu_ld(s, args, 1 | 4);
1730 break;
1731 case INDEX_op_qemu_ld32:
1732 tcg_out_qemu_ld(s, args, 2);
1733 break;
1734 case INDEX_op_qemu_ld64:
1735 tcg_out_qemu_ld(s, args, 3);
1736 break;
1737
1738 case INDEX_op_qemu_st8:
1739 tcg_out_qemu_st(s, args, 0);
1740 break;
1741 case INDEX_op_qemu_st16:
1742 tcg_out_qemu_st(s, args, 1);
1743 break;
1744 case INDEX_op_qemu_st32:
1745 tcg_out_qemu_st(s, args, 2);
1746 break;
1747 case INDEX_op_qemu_st64:
1748 tcg_out_qemu_st(s, args, 3);
1749 break;
1750
1751 case INDEX_op_bswap16_i32:
1752 tcg_out_bswap16(s, COND_AL, args[0], args[1]);
1753 break;
1754 case INDEX_op_bswap32_i32:
1755 tcg_out_bswap32(s, COND_AL, args[0], args[1]);
1756 break;
1757
1758 case INDEX_op_ext8s_i32:
1759 tcg_out_ext8s(s, COND_AL, args[0], args[1]);
1760 break;
1761 case INDEX_op_ext16s_i32:
1762 tcg_out_ext16s(s, COND_AL, args[0], args[1]);
1763 break;
1764 case INDEX_op_ext16u_i32:
1765 tcg_out_ext16u(s, COND_AL, args[0], args[1]);
1766 break;
1767
1768 default:
1769 tcg_abort();
1770 }
1771 }
1772
1773 static const TCGTargetOpDef arm_op_defs[] = {
1774 { INDEX_op_exit_tb, { } },
1775 { INDEX_op_goto_tb, { } },
1776 { INDEX_op_call, { "ri" } },
1777 { INDEX_op_br, { } },
1778
1779 { INDEX_op_mov_i32, { "r", "r" } },
1780 { INDEX_op_movi_i32, { "r" } },
1781
1782 { INDEX_op_ld8u_i32, { "r", "r" } },
1783 { INDEX_op_ld8s_i32, { "r", "r" } },
1784 { INDEX_op_ld16u_i32, { "r", "r" } },
1785 { INDEX_op_ld16s_i32, { "r", "r" } },
1786 { INDEX_op_ld_i32, { "r", "r" } },
1787 { INDEX_op_st8_i32, { "r", "r" } },
1788 { INDEX_op_st16_i32, { "r", "r" } },
1789 { INDEX_op_st_i32, { "r", "r" } },
1790
1791 /* TODO: "r", "r", "ri" */
1792 { INDEX_op_add_i32, { "r", "r", "rI" } },
1793 { INDEX_op_sub_i32, { "r", "r", "rI" } },
1794 { INDEX_op_mul_i32, { "r", "r", "r" } },
1795 { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
1796 { INDEX_op_muls2_i32, { "r", "r", "r", "r" } },
1797 { INDEX_op_and_i32, { "r", "r", "rIK" } },
1798 { INDEX_op_andc_i32, { "r", "r", "rIK" } },
1799 { INDEX_op_or_i32, { "r", "r", "rI" } },
1800 { INDEX_op_xor_i32, { "r", "r", "rI" } },
1801 { INDEX_op_neg_i32, { "r", "r" } },
1802 { INDEX_op_not_i32, { "r", "r" } },
1803
1804 { INDEX_op_shl_i32, { "r", "r", "ri" } },
1805 { INDEX_op_shr_i32, { "r", "r", "ri" } },
1806 { INDEX_op_sar_i32, { "r", "r", "ri" } },
1807 { INDEX_op_rotl_i32, { "r", "r", "ri" } },
1808 { INDEX_op_rotr_i32, { "r", "r", "ri" } },
1809
1810 { INDEX_op_brcond_i32, { "r", "rI" } },
1811 { INDEX_op_setcond_i32, { "r", "r", "rI" } },
1812 { INDEX_op_movcond_i32, { "r", "r", "rI", "rI", "0" } },
1813
1814 /* TODO: "r", "r", "r", "r", "ri", "ri" */
1815 { INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } },
1816 { INDEX_op_sub2_i32, { "r", "r", "r", "r", "r", "r" } },
1817 { INDEX_op_brcond2_i32, { "r", "r", "r", "r" } },
1818 { INDEX_op_setcond2_i32, { "r", "r", "r", "r", "r" } },
1819
1820 #if TARGET_LONG_BITS == 32
1821 { INDEX_op_qemu_ld8u, { "r", "l" } },
1822 { INDEX_op_qemu_ld8s, { "r", "l" } },
1823 { INDEX_op_qemu_ld16u, { "r", "l" } },
1824 { INDEX_op_qemu_ld16s, { "r", "l" } },
1825 { INDEX_op_qemu_ld32, { "r", "l" } },
1826 { INDEX_op_qemu_ld64, { "L", "L", "l" } },
1827
1828 { INDEX_op_qemu_st8, { "s", "s" } },
1829 { INDEX_op_qemu_st16, { "s", "s" } },
1830 { INDEX_op_qemu_st32, { "s", "s" } },
1831 { INDEX_op_qemu_st64, { "S", "S", "s" } },
1832 #else
1833 { INDEX_op_qemu_ld8u, { "r", "l", "l" } },
1834 { INDEX_op_qemu_ld8s, { "r", "l", "l" } },
1835 { INDEX_op_qemu_ld16u, { "r", "l", "l" } },
1836 { INDEX_op_qemu_ld16s, { "r", "l", "l" } },
1837 { INDEX_op_qemu_ld32, { "r", "l", "l" } },
1838 { INDEX_op_qemu_ld64, { "L", "L", "l", "l" } },
1839
1840 { INDEX_op_qemu_st8, { "s", "s", "s" } },
1841 { INDEX_op_qemu_st16, { "s", "s", "s" } },
1842 { INDEX_op_qemu_st32, { "s", "s", "s" } },
1843 { INDEX_op_qemu_st64, { "S", "S", "s", "s" } },
1844 #endif
1845
1846 { INDEX_op_bswap16_i32, { "r", "r" } },
1847 { INDEX_op_bswap32_i32, { "r", "r" } },
1848
1849 { INDEX_op_ext8s_i32, { "r", "r" } },
1850 { INDEX_op_ext16s_i32, { "r", "r" } },
1851 { INDEX_op_ext16u_i32, { "r", "r" } },
1852
1853 { -1 },
1854 };
1855
1856 static void tcg_target_init(TCGContext *s)
1857 {
1858 #if !defined(CONFIG_USER_ONLY)
1859 /* fail safe */
1860 if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
1861 tcg_abort();
1862 #endif
1863
1864 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
1865 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1866 (1 << TCG_REG_R0) |
1867 (1 << TCG_REG_R1) |
1868 (1 << TCG_REG_R2) |
1869 (1 << TCG_REG_R3) |
1870 (1 << TCG_REG_R12) |
1871 (1 << TCG_REG_R14));
1872
1873 tcg_regset_clear(s->reserved_regs);
1874 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
1875 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R8);
1876 tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC);
1877
1878 tcg_add_target_add_op_defs(arm_op_defs);
1879 }
1880
1881 static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
1882 TCGReg arg1, tcg_target_long arg2)
1883 {
1884 tcg_out_ld32u(s, COND_AL, arg, arg1, arg2);
1885 }
1886
1887 static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
1888 TCGReg arg1, tcg_target_long arg2)
1889 {
1890 tcg_out_st32(s, COND_AL, arg, arg1, arg2);
1891 }
1892
1893 static inline void tcg_out_mov(TCGContext *s, TCGType type,
1894 TCGReg ret, TCGReg arg)
1895 {
1896 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, ret, 0, arg, SHIFT_IMM_LSL(0));
1897 }
1898
1899 static inline void tcg_out_movi(TCGContext *s, TCGType type,
1900 TCGReg ret, tcg_target_long arg)
1901 {
1902 tcg_out_movi32(s, COND_AL, ret, arg);
1903 }
1904
1905 static void tcg_target_qemu_prologue(TCGContext *s)
1906 {
1907 int frame_size;
1908
1909 /* Calling convention requires us to save r4-r11 and lr. */
1910 /* stmdb sp!, { r4 - r11, lr } */
1911 tcg_out32(s, (COND_AL << 28) | 0x092d4ff0);
1912
1913 /* Allocate the local stack frame. */
1914 frame_size = TCG_STATIC_CALL_ARGS_SIZE;
1915 frame_size += CPU_TEMP_BUF_NLONGS * sizeof(long);
1916 /* We saved an odd number of registers above; keep an 8 aligned stack. */
1917 frame_size = ((frame_size + TCG_TARGET_STACK_ALIGN - 1)
1918 & -TCG_TARGET_STACK_ALIGN) + 4;
1919
1920 tcg_out_dat_rI(s, COND_AL, ARITH_SUB, TCG_REG_CALL_STACK,
1921 TCG_REG_CALL_STACK, frame_size, 1);
1922 tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE,
1923 CPU_TEMP_BUF_NLONGS * sizeof(long));
1924
1925 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
1926
1927 tcg_out_bx(s, COND_AL, tcg_target_call_iarg_regs[1]);
1928 tb_ret_addr = s->code_ptr;
1929
1930 /* Epilogue. We branch here via tb_ret_addr. */
1931 tcg_out_dat_rI(s, COND_AL, ARITH_ADD, TCG_REG_CALL_STACK,
1932 TCG_REG_CALL_STACK, frame_size, 1);
1933
1934 /* ldmia sp!, { r4 - r11, pc } */
1935 tcg_out32(s, (COND_AL << 28) | 0x08bd8ff0);
1936 }
Qemu copy for testing