2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Andrzej Zaborowski
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 /* The __ARM_ARCH define is provided by gcc 4.8. Construct it otherwise. */
27 # if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) \
28 || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) \
29 || defined(__ARM_ARCH_7EM__)
31 # elif defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) \
32 || defined(__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6ZK__) \
33 || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6T2__)
35 # elif defined(__ARM_ARCH_5__) || defined(__ARM_ARCH_5E__) \
36 || defined(__ARM_ARCH_5T__) || defined(__ARM_ARCH_5TE__) \
37 || defined(__ARM_ARCH_5TEJ__)
44 static int arm_arch
= __ARM_ARCH
;
46 #if defined(__ARM_ARCH_5T__) \
47 || defined(__ARM_ARCH_5TE__) || defined(__ARM_ARCH_5TEJ__)
48 # define use_armv5t_instructions 1
50 # define use_armv5t_instructions use_armv6_instructions
53 #define use_armv6_instructions (__ARM_ARCH >= 6 || arm_arch >= 6)
54 #define use_armv7_instructions (__ARM_ARCH >= 7 || arm_arch >= 7)
56 #ifndef use_idiv_instructions
57 bool use_idiv_instructions
;
59 #ifdef CONFIG_GETAUXVAL
60 # include <sys/auxv.h>
64 static const char * const tcg_target_reg_names
[TCG_TARGET_NB_REGS
] = {
84 static const int tcg_target_reg_alloc_order
[] = {
102 static const int tcg_target_call_iarg_regs
[4] = {
103 TCG_REG_R0
, TCG_REG_R1
, TCG_REG_R2
, TCG_REG_R3
105 static const int tcg_target_call_oarg_regs
[2] = {
106 TCG_REG_R0
, TCG_REG_R1
109 #define TCG_REG_TMP TCG_REG_R12
111 static inline void reloc_abs32(void *code_ptr
, intptr_t target
)
113 *(uint32_t *) code_ptr
= target
;
116 static inline void reloc_pc24(void *code_ptr
, intptr_t target
)
118 uint32_t offset
= ((target
- ((intptr_t)code_ptr
+ 8)) >> 2);
120 *(uint32_t *) code_ptr
= ((*(uint32_t *) code_ptr
) & ~0xffffff)
121 | (offset
& 0xffffff);
124 static void patch_reloc(uint8_t *code_ptr
, int type
,
125 intptr_t value
, intptr_t addend
)
129 reloc_abs32(code_ptr
, value
);
138 reloc_pc24(code_ptr
, value
);
143 #define TCG_CT_CONST_ARM 0x100
144 #define TCG_CT_CONST_INV 0x200
145 #define TCG_CT_CONST_NEG 0x400
146 #define TCG_CT_CONST_ZERO 0x800
148 /* parse target specific constraints */
149 static int target_parse_constraint(TCGArgConstraint
*ct
, const char **pct_str
)
156 ct
->ct
|= TCG_CT_CONST_ARM
;
159 ct
->ct
|= TCG_CT_CONST_INV
;
161 case 'N': /* The gcc constraint letter is L, already used here. */
162 ct
->ct
|= TCG_CT_CONST_NEG
;
165 ct
->ct
|= TCG_CT_CONST_ZERO
;
169 ct
->ct
|= TCG_CT_REG
;
170 tcg_regset_set32(ct
->u
.regs
, 0, (1 << TCG_TARGET_NB_REGS
) - 1);
173 /* qemu_ld address */
175 ct
->ct
|= TCG_CT_REG
;
176 tcg_regset_set32(ct
->u
.regs
, 0, (1 << TCG_TARGET_NB_REGS
) - 1);
177 #ifdef CONFIG_SOFTMMU
178 /* r0-r2 will be overwritten when reading the tlb entry,
179 so don't use these. */
180 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R0
);
181 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R1
);
182 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R2
);
186 ct
->ct
|= TCG_CT_REG
;
187 tcg_regset_set32(ct
->u
.regs
, 0, (1 << TCG_TARGET_NB_REGS
) - 1);
188 #ifdef CONFIG_SOFTMMU
189 /* r1 is still needed to load data_reg or data_reg2,
191 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R1
);
195 /* qemu_st address & data_reg */
197 ct
->ct
|= TCG_CT_REG
;
198 tcg_regset_set32(ct
->u
.regs
, 0, (1 << TCG_TARGET_NB_REGS
) - 1);
199 /* r0-r2 will be overwritten when reading the tlb entry (softmmu only)
200 and r0-r1 doing the byte swapping, so don't use these. */
201 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R0
);
202 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R1
);
203 #if defined(CONFIG_SOFTMMU)
204 /* Avoid clashes with registers being used for helper args */
205 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R2
);
206 #if TARGET_LONG_BITS == 64
207 /* Avoid clashes with registers being used for helper args */
208 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R3
);
222 static inline uint32_t rotl(uint32_t val
, int n
)
224 return (val
<< n
) | (val
>> (32 - n
));
227 /* ARM immediates for ALU instructions are made of an unsigned 8-bit
228 right-rotated by an even amount between 0 and 30. */
229 static inline int encode_imm(uint32_t imm
)
233 /* simple case, only lower bits */
234 if ((imm
& ~0xff) == 0)
236 /* then try a simple even shift */
237 shift
= ctz32(imm
) & ~1;
238 if (((imm
>> shift
) & ~0xff) == 0)
240 /* now try harder with rotations */
241 if ((rotl(imm
, 2) & ~0xff) == 0)
243 if ((rotl(imm
, 4) & ~0xff) == 0)
245 if ((rotl(imm
, 6) & ~0xff) == 0)
247 /* imm can't be encoded */
251 static inline int check_fit_imm(uint32_t imm
)
253 return encode_imm(imm
) >= 0;
256 /* Test if a constant matches the constraint.
257 * TODO: define constraints for:
259 * ldr/str offset: between -0xfff and 0xfff
260 * ldrh/strh offset: between -0xff and 0xff
261 * mov operand2: values represented with x << (2 * y), x < 0x100
262 * add, sub, eor...: ditto
264 static inline int tcg_target_const_match(tcg_target_long val
,
265 const TCGArgConstraint
*arg_ct
)
269 if (ct
& TCG_CT_CONST
) {
271 } else if ((ct
& TCG_CT_CONST_ARM
) && check_fit_imm(val
)) {
273 } else if ((ct
& TCG_CT_CONST_INV
) && check_fit_imm(~val
)) {
275 } else if ((ct
& TCG_CT_CONST_NEG
) && check_fit_imm(-val
)) {
277 } else if ((ct
& TCG_CT_CONST_ZERO
) && val
== 0) {
284 #define TO_CPSR (1 << 20)
287 ARITH_AND
= 0x0 << 21,
288 ARITH_EOR
= 0x1 << 21,
289 ARITH_SUB
= 0x2 << 21,
290 ARITH_RSB
= 0x3 << 21,
291 ARITH_ADD
= 0x4 << 21,
292 ARITH_ADC
= 0x5 << 21,
293 ARITH_SBC
= 0x6 << 21,
294 ARITH_RSC
= 0x7 << 21,
295 ARITH_TST
= 0x8 << 21 | TO_CPSR
,
296 ARITH_CMP
= 0xa << 21 | TO_CPSR
,
297 ARITH_CMN
= 0xb << 21 | TO_CPSR
,
298 ARITH_ORR
= 0xc << 21,
299 ARITH_MOV
= 0xd << 21,
300 ARITH_BIC
= 0xe << 21,
301 ARITH_MVN
= 0xf << 21,
303 INSN_LDR_IMM
= 0x04100000,
304 INSN_LDR_REG
= 0x06100000,
305 INSN_STR_IMM
= 0x04000000,
306 INSN_STR_REG
= 0x06000000,
308 INSN_LDRH_IMM
= 0x005000b0,
309 INSN_LDRH_REG
= 0x001000b0,
310 INSN_LDRSH_IMM
= 0x005000f0,
311 INSN_LDRSH_REG
= 0x001000f0,
312 INSN_STRH_IMM
= 0x004000b0,
313 INSN_STRH_REG
= 0x000000b0,
315 INSN_LDRB_IMM
= 0x04500000,
316 INSN_LDRB_REG
= 0x06500000,
317 INSN_LDRSB_IMM
= 0x005000d0,
318 INSN_LDRSB_REG
= 0x001000d0,
319 INSN_STRB_IMM
= 0x04400000,
320 INSN_STRB_REG
= 0x06400000,
322 INSN_LDRD_IMM
= 0x004000d0,
325 #define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00)
326 #define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20)
327 #define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40)
328 #define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60)
329 #define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10)
330 #define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30)
331 #define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50)
332 #define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70)
334 enum arm_cond_code_e
{
337 COND_CS
= 0x2, /* Unsigned greater or equal */
338 COND_CC
= 0x3, /* Unsigned less than */
339 COND_MI
= 0x4, /* Negative */
340 COND_PL
= 0x5, /* Zero or greater */
341 COND_VS
= 0x6, /* Overflow */
342 COND_VC
= 0x7, /* No overflow */
343 COND_HI
= 0x8, /* Unsigned greater than */
344 COND_LS
= 0x9, /* Unsigned less or equal */
352 static const uint8_t tcg_cond_to_arm_cond
[] = {
353 [TCG_COND_EQ
] = COND_EQ
,
354 [TCG_COND_NE
] = COND_NE
,
355 [TCG_COND_LT
] = COND_LT
,
356 [TCG_COND_GE
] = COND_GE
,
357 [TCG_COND_LE
] = COND_LE
,
358 [TCG_COND_GT
] = COND_GT
,
360 [TCG_COND_LTU
] = COND_CC
,
361 [TCG_COND_GEU
] = COND_CS
,
362 [TCG_COND_LEU
] = COND_LS
,
363 [TCG_COND_GTU
] = COND_HI
,
366 static inline void tcg_out_bx(TCGContext
*s
, int cond
, int rn
)
368 tcg_out32(s
, (cond
<< 28) | 0x012fff10 | rn
);
371 static inline void tcg_out_b(TCGContext
*s
, int cond
, int32_t offset
)
373 tcg_out32(s
, (cond
<< 28) | 0x0a000000 |
374 (((offset
- 8) >> 2) & 0x00ffffff));
377 static inline void tcg_out_b_noaddr(TCGContext
*s
, int cond
)
379 /* We pay attention here to not modify the branch target by skipping
380 the corresponding bytes. This ensure that caches and memory are
381 kept coherent during retranslation. */
382 #ifdef HOST_WORDS_BIGENDIAN
383 tcg_out8(s
, (cond
<< 4) | 0x0a);
387 tcg_out8(s
, (cond
<< 4) | 0x0a);
391 static inline void tcg_out_bl(TCGContext
*s
, int cond
, int32_t offset
)
393 tcg_out32(s
, (cond
<< 28) | 0x0b000000 |
394 (((offset
- 8) >> 2) & 0x00ffffff));
397 static inline void tcg_out_blx(TCGContext
*s
, int cond
, int rn
)
399 tcg_out32(s
, (cond
<< 28) | 0x012fff30 | rn
);
402 static inline void tcg_out_blx_imm(TCGContext
*s
, int32_t offset
)
404 tcg_out32(s
, 0xfa000000 | ((offset
& 2) << 23) |
405 (((offset
- 8) >> 2) & 0x00ffffff));
408 static inline void tcg_out_dat_reg(TCGContext
*s
,
409 int cond
, int opc
, int rd
, int rn
, int rm
, int shift
)
411 tcg_out32(s
, (cond
<< 28) | (0 << 25) | opc
|
412 (rn
<< 16) | (rd
<< 12) | shift
| rm
);
415 static inline void tcg_out_nop(TCGContext
*s
)
417 if (use_armv7_instructions
) {
418 /* Architected nop introduced in v6k. */
419 /* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this
420 also Just So Happened to do nothing on pre-v6k so that we
421 don't need to conditionalize it? */
422 tcg_out32(s
, 0xe320f000);
424 /* Prior to that the assembler uses mov r0, r0. */
425 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
, 0, 0, 0, SHIFT_IMM_LSL(0));
429 static inline void tcg_out_mov_reg(TCGContext
*s
, int cond
, int rd
, int rm
)
431 /* Simple reg-reg move, optimising out the 'do nothing' case */
433 tcg_out_dat_reg(s
, cond
, ARITH_MOV
, rd
, 0, rm
, SHIFT_IMM_LSL(0));
437 static inline void tcg_out_dat_imm(TCGContext
*s
,
438 int cond
, int opc
, int rd
, int rn
, int im
)
440 tcg_out32(s
, (cond
<< 28) | (1 << 25) | opc
|
441 (rn
<< 16) | (rd
<< 12) | im
);
444 static void tcg_out_movi32(TCGContext
*s
, int cond
, int rd
, uint32_t arg
)
448 /* For armv7, make sure not to use movw+movt when mov/mvn would do.
449 Speed things up by only checking when movt would be required.
450 Prior to armv7, have one go at fully rotated immediates before
451 doing the decomposition thing below. */
452 if (!use_armv7_instructions
|| (arg
& 0xffff0000)) {
453 rot
= encode_imm(arg
);
455 tcg_out_dat_imm(s
, cond
, ARITH_MOV
, rd
, 0,
456 rotl(arg
, rot
) | (rot
<< 7));
459 rot
= encode_imm(~arg
);
461 tcg_out_dat_imm(s
, cond
, ARITH_MVN
, rd
, 0,
462 rotl(~arg
, rot
) | (rot
<< 7));
467 /* Use movw + movt. */
468 if (use_armv7_instructions
) {
470 tcg_out32(s
, (cond
<< 28) | 0x03000000 | (rd
<< 12)
471 | ((arg
<< 4) & 0x000f0000) | (arg
& 0xfff));
472 if (arg
& 0xffff0000) {
474 tcg_out32(s
, (cond
<< 28) | 0x03400000 | (rd
<< 12)
475 | ((arg
>> 12) & 0x000f0000) | ((arg
>> 16) & 0xfff));
480 /* TODO: This is very suboptimal, we can easily have a constant
481 pool somewhere after all the instructions. */
484 /* If we have lots of leading 1's, we can shorten the sequence by
485 beginning with mvn and then clearing higher bits with eor. */
486 if (clz32(~arg
) > clz32(arg
)) {
487 opc
= ARITH_MVN
, arg
= ~arg
;
490 int i
= ctz32(arg
) & ~1;
491 rot
= ((32 - i
) << 7) & 0xf00;
492 tcg_out_dat_imm(s
, cond
, opc
, rd
, rn
, ((arg
>> i
) & 0xff) | rot
);
500 static inline void tcg_out_dat_rI(TCGContext
*s
, int cond
, int opc
, TCGArg dst
,
501 TCGArg lhs
, TCGArg rhs
, int rhs_is_const
)
503 /* Emit either the reg,imm or reg,reg form of a data-processing insn.
504 * rhs must satisfy the "rI" constraint.
507 int rot
= encode_imm(rhs
);
509 tcg_out_dat_imm(s
, cond
, opc
, dst
, lhs
, rotl(rhs
, rot
) | (rot
<< 7));
511 tcg_out_dat_reg(s
, cond
, opc
, dst
, lhs
, rhs
, SHIFT_IMM_LSL(0));
515 static void tcg_out_dat_rIK(TCGContext
*s
, int cond
, int opc
, int opinv
,
516 TCGReg dst
, TCGReg lhs
, TCGArg rhs
,
519 /* Emit either the reg,imm or reg,reg form of a data-processing insn.
520 * rhs must satisfy the "rIK" constraint.
523 int rot
= encode_imm(rhs
);
526 rot
= encode_imm(rhs
);
530 tcg_out_dat_imm(s
, cond
, opc
, dst
, lhs
, rotl(rhs
, rot
) | (rot
<< 7));
532 tcg_out_dat_reg(s
, cond
, opc
, dst
, lhs
, rhs
, SHIFT_IMM_LSL(0));
536 static void tcg_out_dat_rIN(TCGContext
*s
, int cond
, int opc
, int opneg
,
537 TCGArg dst
, TCGArg lhs
, TCGArg rhs
,
540 /* Emit either the reg,imm or reg,reg form of a data-processing insn.
541 * rhs must satisfy the "rIN" constraint.
544 int rot
= encode_imm(rhs
);
547 rot
= encode_imm(rhs
);
551 tcg_out_dat_imm(s
, cond
, opc
, dst
, lhs
, rotl(rhs
, rot
) | (rot
<< 7));
553 tcg_out_dat_reg(s
, cond
, opc
, dst
, lhs
, rhs
, SHIFT_IMM_LSL(0));
557 static inline void tcg_out_mul32(TCGContext
*s
, int cond
, TCGReg rd
,
558 TCGReg rn
, TCGReg rm
)
560 /* if ArchVersion() < 6 && d == n then UNPREDICTABLE; */
561 if (!use_armv6_instructions
&& rd
== rn
) {
563 /* rd == rn == rm; copy an input to tmp first. */
564 tcg_out_mov_reg(s
, cond
, TCG_REG_TMP
, rn
);
565 rm
= rn
= TCG_REG_TMP
;
572 tcg_out32(s
, (cond
<< 28) | 0x90 | (rd
<< 16) | (rm
<< 8) | rn
);
575 static inline void tcg_out_umull32(TCGContext
*s
, int cond
, TCGReg rd0
,
576 TCGReg rd1
, TCGReg rn
, TCGReg rm
)
578 /* if ArchVersion() < 6 && (dHi == n || dLo == n) then UNPREDICTABLE; */
579 if (!use_armv6_instructions
&& (rd0
== rn
|| rd1
== rn
)) {
580 if (rd0
== rm
|| rd1
== rm
) {
581 tcg_out_mov_reg(s
, cond
, TCG_REG_TMP
, rn
);
590 tcg_out32(s
, (cond
<< 28) | 0x00800090 |
591 (rd1
<< 16) | (rd0
<< 12) | (rm
<< 8) | rn
);
594 static inline void tcg_out_smull32(TCGContext
*s
, int cond
, TCGReg rd0
,
595 TCGReg rd1
, TCGReg rn
, TCGReg rm
)
597 /* if ArchVersion() < 6 && (dHi == n || dLo == n) then UNPREDICTABLE; */
598 if (!use_armv6_instructions
&& (rd0
== rn
|| rd1
== rn
)) {
599 if (rd0
== rm
|| rd1
== rm
) {
600 tcg_out_mov_reg(s
, cond
, TCG_REG_TMP
, rn
);
609 tcg_out32(s
, (cond
<< 28) | 0x00c00090 |
610 (rd1
<< 16) | (rd0
<< 12) | (rm
<< 8) | rn
);
613 static inline void tcg_out_sdiv(TCGContext
*s
, int cond
, int rd
, int rn
, int rm
)
615 tcg_out32(s
, 0x0710f010 | (cond
<< 28) | (rd
<< 16) | rn
| (rm
<< 8));
618 static inline void tcg_out_udiv(TCGContext
*s
, int cond
, int rd
, int rn
, int rm
)
620 tcg_out32(s
, 0x0730f010 | (cond
<< 28) | (rd
<< 16) | rn
| (rm
<< 8));
623 static inline void tcg_out_ext8s(TCGContext
*s
, int cond
,
626 if (use_armv6_instructions
) {
628 tcg_out32(s
, 0x06af0070 | (cond
<< 28) | (rd
<< 12) | rn
);
630 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
631 rd
, 0, rn
, SHIFT_IMM_LSL(24));
632 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
633 rd
, 0, rd
, SHIFT_IMM_ASR(24));
637 static inline void tcg_out_ext8u(TCGContext
*s
, int cond
,
640 tcg_out_dat_imm(s
, cond
, ARITH_AND
, rd
, rn
, 0xff);
643 static inline void tcg_out_ext16s(TCGContext
*s
, int cond
,
646 if (use_armv6_instructions
) {
648 tcg_out32(s
, 0x06bf0070 | (cond
<< 28) | (rd
<< 12) | rn
);
650 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
651 rd
, 0, rn
, SHIFT_IMM_LSL(16));
652 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
653 rd
, 0, rd
, SHIFT_IMM_ASR(16));
657 static inline void tcg_out_ext16u(TCGContext
*s
, int cond
,
660 if (use_armv6_instructions
) {
662 tcg_out32(s
, 0x06ff0070 | (cond
<< 28) | (rd
<< 12) | rn
);
664 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
665 rd
, 0, rn
, SHIFT_IMM_LSL(16));
666 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
667 rd
, 0, rd
, SHIFT_IMM_LSR(16));
671 static inline void tcg_out_bswap16s(TCGContext
*s
, int cond
, int rd
, int rn
)
673 if (use_armv6_instructions
) {
675 tcg_out32(s
, 0x06ff0fb0 | (cond
<< 28) | (rd
<< 12) | rn
);
677 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
678 TCG_REG_TMP
, 0, rn
, SHIFT_IMM_LSL(24));
679 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
680 TCG_REG_TMP
, 0, TCG_REG_TMP
, SHIFT_IMM_ASR(16));
681 tcg_out_dat_reg(s
, cond
, ARITH_ORR
,
682 rd
, TCG_REG_TMP
, rn
, SHIFT_IMM_LSR(8));
686 static inline void tcg_out_bswap16(TCGContext
*s
, int cond
, int rd
, int rn
)
688 if (use_armv6_instructions
) {
690 tcg_out32(s
, 0x06bf0fb0 | (cond
<< 28) | (rd
<< 12) | rn
);
692 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
693 TCG_REG_TMP
, 0, rn
, SHIFT_IMM_LSL(24));
694 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
695 TCG_REG_TMP
, 0, TCG_REG_TMP
, SHIFT_IMM_LSR(16));
696 tcg_out_dat_reg(s
, cond
, ARITH_ORR
,
697 rd
, TCG_REG_TMP
, rn
, SHIFT_IMM_LSR(8));
701 /* swap the two low bytes assuming that the two high input bytes and the
702 two high output bit can hold any value. */
703 static inline void tcg_out_bswap16st(TCGContext
*s
, int cond
, int rd
, int rn
)
705 if (use_armv6_instructions
) {
707 tcg_out32(s
, 0x06bf0fb0 | (cond
<< 28) | (rd
<< 12) | rn
);
709 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
710 TCG_REG_TMP
, 0, rn
, SHIFT_IMM_LSR(8));
711 tcg_out_dat_imm(s
, cond
, ARITH_AND
, TCG_REG_TMP
, TCG_REG_TMP
, 0xff);
712 tcg_out_dat_reg(s
, cond
, ARITH_ORR
,
713 rd
, TCG_REG_TMP
, rn
, SHIFT_IMM_LSL(8));
717 static inline void tcg_out_bswap32(TCGContext
*s
, int cond
, int rd
, int rn
)
719 if (use_armv6_instructions
) {
721 tcg_out32(s
, 0x06bf0f30 | (cond
<< 28) | (rd
<< 12) | rn
);
723 tcg_out_dat_reg(s
, cond
, ARITH_EOR
,
724 TCG_REG_TMP
, rn
, rn
, SHIFT_IMM_ROR(16));
725 tcg_out_dat_imm(s
, cond
, ARITH_BIC
,
726 TCG_REG_TMP
, TCG_REG_TMP
, 0xff | 0x800);
727 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
728 rd
, 0, rn
, SHIFT_IMM_ROR(8));
729 tcg_out_dat_reg(s
, cond
, ARITH_EOR
,
730 rd
, rd
, TCG_REG_TMP
, SHIFT_IMM_LSR(8));
734 bool tcg_target_deposit_valid(int ofs
, int len
)
736 /* ??? Without bfi, we could improve over generic code by combining
737 the right-shift from a non-zero ofs with the orr. We do run into
738 problems when rd == rs, and the mask generated from ofs+len doesn't
739 fit into an immediate. We would have to be careful not to pessimize
740 wrt the optimizations performed on the expanded code. */
741 return use_armv7_instructions
;
744 static inline void tcg_out_deposit(TCGContext
*s
, int cond
, TCGReg rd
,
745 TCGArg a1
, int ofs
, int len
, bool const_a1
)
748 /* bfi becomes bfc with rn == 15. */
752 tcg_out32(s
, 0x07c00010 | (cond
<< 28) | (rd
<< 12) | a1
753 | (ofs
<< 7) | ((ofs
+ len
- 1) << 16));
756 /* Note that this routine is used for both LDR and LDRH formats, so we do
757 not wish to include an immediate shift at this point. */
758 static void tcg_out_memop_r(TCGContext
*s
, int cond
, ARMInsn opc
, TCGReg rt
,
759 TCGReg rn
, TCGReg rm
, bool u
, bool p
, bool w
)
761 tcg_out32(s
, (cond
<< 28) | opc
| (u
<< 23) | (p
<< 24)
762 | (w
<< 21) | (rn
<< 16) | (rt
<< 12) | rm
);
765 static void tcg_out_memop_8(TCGContext
*s
, int cond
, ARMInsn opc
, TCGReg rt
,
766 TCGReg rn
, int imm8
, bool p
, bool w
)
773 tcg_out32(s
, (cond
<< 28) | opc
| (u
<< 23) | (p
<< 24) | (w
<< 21) |
774 (rn
<< 16) | (rt
<< 12) | ((imm8
& 0xf0) << 4) | (imm8
& 0xf));
777 static void tcg_out_memop_12(TCGContext
*s
, int cond
, ARMInsn opc
, TCGReg rt
,
778 TCGReg rn
, int imm12
, bool p
, bool w
)
785 tcg_out32(s
, (cond
<< 28) | opc
| (u
<< 23) | (p
<< 24) | (w
<< 21) |
786 (rn
<< 16) | (rt
<< 12) | imm12
);
789 static inline void tcg_out_ld32_12(TCGContext
*s
, int cond
, TCGReg rt
,
790 TCGReg rn
, int imm12
)
792 tcg_out_memop_12(s
, cond
, INSN_LDR_IMM
, rt
, rn
, imm12
, 1, 0);
795 static inline void tcg_out_st32_12(TCGContext
*s
, int cond
, TCGReg rt
,
796 TCGReg rn
, int imm12
)
798 tcg_out_memop_12(s
, cond
, INSN_STR_IMM
, rt
, rn
, imm12
, 1, 0);
801 static inline void tcg_out_ld32_r(TCGContext
*s
, int cond
, TCGReg rt
,
802 TCGReg rn
, TCGReg rm
)
804 tcg_out_memop_r(s
, cond
, INSN_LDR_REG
, rt
, rn
, rm
, 1, 1, 0);
807 static inline void tcg_out_st32_r(TCGContext
*s
, int cond
, TCGReg rt
,
808 TCGReg rn
, TCGReg rm
)
810 tcg_out_memop_r(s
, cond
, INSN_STR_REG
, rt
, rn
, rm
, 1, 1, 0);
813 /* Register pre-increment with base writeback. */
814 static inline void tcg_out_ld32_rwb(TCGContext
*s
, int cond
, TCGReg rt
,
815 TCGReg rn
, TCGReg rm
)
817 tcg_out_memop_r(s
, cond
, INSN_LDR_REG
, rt
, rn
, rm
, 1, 1, 1);
820 static inline void tcg_out_st32_rwb(TCGContext
*s
, int cond
, TCGReg rt
,
821 TCGReg rn
, TCGReg rm
)
823 tcg_out_memop_r(s
, cond
, INSN_STR_REG
, rt
, rn
, rm
, 1, 1, 1);
826 static inline void tcg_out_ld16u_8(TCGContext
*s
, int cond
, TCGReg rt
,
829 tcg_out_memop_8(s
, cond
, INSN_LDRH_IMM
, rt
, rn
, imm8
, 1, 0);
832 static inline void tcg_out_st16_8(TCGContext
*s
, int cond
, TCGReg rt
,
835 tcg_out_memop_8(s
, cond
, INSN_STRH_IMM
, rt
, rn
, imm8
, 1, 0);
838 static inline void tcg_out_ld16u_r(TCGContext
*s
, int cond
, TCGReg rt
,
839 TCGReg rn
, TCGReg rm
)
841 tcg_out_memop_r(s
, cond
, INSN_LDRH_REG
, rt
, rn
, rm
, 1, 1, 0);
844 static inline void tcg_out_st16_r(TCGContext
*s
, int cond
, TCGReg rt
,
845 TCGReg rn
, TCGReg rm
)
847 tcg_out_memop_r(s
, cond
, INSN_STRH_REG
, rt
, rn
, rm
, 1, 1, 0);
850 static inline void tcg_out_ld16s_8(TCGContext
*s
, int cond
, TCGReg rt
,
853 tcg_out_memop_8(s
, cond
, INSN_LDRSH_IMM
, rt
, rn
, imm8
, 1, 0);
856 static inline void tcg_out_ld16s_r(TCGContext
*s
, int cond
, TCGReg rt
,
857 TCGReg rn
, TCGReg rm
)
859 tcg_out_memop_r(s
, cond
, INSN_LDRSH_REG
, rt
, rn
, rm
, 1, 1, 0);
862 static inline void tcg_out_ld8_12(TCGContext
*s
, int cond
, TCGReg rt
,
863 TCGReg rn
, int imm12
)
865 tcg_out_memop_12(s
, cond
, INSN_LDRB_IMM
, rt
, rn
, imm12
, 1, 0);
868 static inline void tcg_out_st8_12(TCGContext
*s
, int cond
, TCGReg rt
,
869 TCGReg rn
, int imm12
)
871 tcg_out_memop_12(s
, cond
, INSN_STRB_IMM
, rt
, rn
, imm12
, 1, 0);
874 static inline void tcg_out_ld8_r(TCGContext
*s
, int cond
, TCGReg rt
,
875 TCGReg rn
, TCGReg rm
)
877 tcg_out_memop_r(s
, cond
, INSN_LDRB_REG
, rt
, rn
, rm
, 1, 1, 0);
880 static inline void tcg_out_st8_r(TCGContext
*s
, int cond
, TCGReg rt
,
881 TCGReg rn
, TCGReg rm
)
883 tcg_out_memop_r(s
, cond
, INSN_STRB_REG
, rt
, rn
, rm
, 1, 1, 0);
886 static inline void tcg_out_ld8s_8(TCGContext
*s
, int cond
, TCGReg rt
,
889 tcg_out_memop_8(s
, cond
, INSN_LDRSB_IMM
, rt
, rn
, imm8
, 1, 0);
892 static inline void tcg_out_ld8s_r(TCGContext
*s
, int cond
, TCGReg rt
,
893 TCGReg rn
, TCGReg rm
)
895 tcg_out_memop_r(s
, cond
, INSN_LDRSB_REG
, rt
, rn
, rm
, 1, 1, 0);
898 static inline void tcg_out_ld32u(TCGContext
*s
, int cond
,
899 int rd
, int rn
, int32_t offset
)
901 if (offset
> 0xfff || offset
< -0xfff) {
902 tcg_out_movi32(s
, cond
, TCG_REG_TMP
, offset
);
903 tcg_out_ld32_r(s
, cond
, rd
, rn
, TCG_REG_TMP
);
905 tcg_out_ld32_12(s
, cond
, rd
, rn
, offset
);
908 static inline void tcg_out_st32(TCGContext
*s
, int cond
,
909 int rd
, int rn
, int32_t offset
)
911 if (offset
> 0xfff || offset
< -0xfff) {
912 tcg_out_movi32(s
, cond
, TCG_REG_TMP
, offset
);
913 tcg_out_st32_r(s
, cond
, rd
, rn
, TCG_REG_TMP
);
915 tcg_out_st32_12(s
, cond
, rd
, rn
, offset
);
918 static inline void tcg_out_ld16u(TCGContext
*s
, int cond
,
919 int rd
, int rn
, int32_t offset
)
921 if (offset
> 0xff || offset
< -0xff) {
922 tcg_out_movi32(s
, cond
, TCG_REG_TMP
, offset
);
923 tcg_out_ld16u_r(s
, cond
, rd
, rn
, TCG_REG_TMP
);
925 tcg_out_ld16u_8(s
, cond
, rd
, rn
, offset
);
928 static inline void tcg_out_ld16s(TCGContext
*s
, int cond
,
929 int rd
, int rn
, int32_t offset
)
931 if (offset
> 0xff || offset
< -0xff) {
932 tcg_out_movi32(s
, cond
, TCG_REG_TMP
, offset
);
933 tcg_out_ld16s_r(s
, cond
, rd
, rn
, TCG_REG_TMP
);
935 tcg_out_ld16s_8(s
, cond
, rd
, rn
, offset
);
938 static inline void tcg_out_st16(TCGContext
*s
, int cond
,
939 int rd
, int rn
, int32_t offset
)
941 if (offset
> 0xff || offset
< -0xff) {
942 tcg_out_movi32(s
, cond
, TCG_REG_TMP
, offset
);
943 tcg_out_st16_r(s
, cond
, rd
, rn
, TCG_REG_TMP
);
945 tcg_out_st16_8(s
, cond
, rd
, rn
, offset
);
948 static inline void tcg_out_ld8u(TCGContext
*s
, int cond
,
949 int rd
, int rn
, int32_t offset
)
951 if (offset
> 0xfff || offset
< -0xfff) {
952 tcg_out_movi32(s
, cond
, TCG_REG_TMP
, offset
);
953 tcg_out_ld8_r(s
, cond
, rd
, rn
, TCG_REG_TMP
);
955 tcg_out_ld8_12(s
, cond
, rd
, rn
, offset
);
958 static inline void tcg_out_ld8s(TCGContext
*s
, int cond
,
959 int rd
, int rn
, int32_t offset
)
961 if (offset
> 0xff || offset
< -0xff) {
962 tcg_out_movi32(s
, cond
, TCG_REG_TMP
, offset
);
963 tcg_out_ld8s_r(s
, cond
, rd
, rn
, TCG_REG_TMP
);
965 tcg_out_ld8s_8(s
, cond
, rd
, rn
, offset
);
968 static inline void tcg_out_st8(TCGContext
*s
, int cond
,
969 int rd
, int rn
, int32_t offset
)
971 if (offset
> 0xfff || offset
< -0xfff) {
972 tcg_out_movi32(s
, cond
, TCG_REG_TMP
, offset
);
973 tcg_out_st8_r(s
, cond
, rd
, rn
, TCG_REG_TMP
);
975 tcg_out_st8_12(s
, cond
, rd
, rn
, offset
);
978 /* The _goto case is normally between TBs within the same code buffer,
979 * and with the code buffer limited to 16MB we shouldn't need the long
982 * .... except to the prologue that is in its own buffer.
984 static inline void tcg_out_goto(TCGContext
*s
, int cond
, uint32_t addr
)
989 /* goto to a Thumb destination isn't supported */
993 val
= addr
- (tcg_target_long
) s
->code_ptr
;
994 if (val
- 8 < 0x01fffffd && val
- 8 > -0x01fffffd)
995 tcg_out_b(s
, cond
, val
);
997 if (cond
== COND_AL
) {
998 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_PC
, TCG_REG_PC
, -4);
1001 tcg_out_movi32(s
, cond
, TCG_REG_TMP
, val
- 8);
1002 tcg_out_dat_reg(s
, cond
, ARITH_ADD
,
1003 TCG_REG_PC
, TCG_REG_PC
,
1004 TCG_REG_TMP
, SHIFT_IMM_LSL(0));
1009 /* The call case is mostly used for helpers - so it's not unreasonable
1010 * for them to be beyond branch range */
1011 static inline void tcg_out_call(TCGContext
*s
, uint32_t addr
)
1015 val
= addr
- (tcg_target_long
) s
->code_ptr
;
1016 if (val
- 8 < 0x02000000 && val
- 8 >= -0x02000000) {
1018 /* Use BLX if the target is in Thumb mode */
1019 if (!use_armv5t_instructions
) {
1022 tcg_out_blx_imm(s
, val
);
1024 tcg_out_bl(s
, COND_AL
, val
);
1026 } else if (use_armv7_instructions
) {
1027 tcg_out_movi32(s
, COND_AL
, TCG_REG_TMP
, addr
);
1028 tcg_out_blx(s
, COND_AL
, TCG_REG_TMP
);
1030 tcg_out_dat_imm(s
, COND_AL
, ARITH_ADD
, TCG_REG_R14
, TCG_REG_PC
, 4);
1031 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_PC
, TCG_REG_PC
, -4);
1036 static inline void tcg_out_callr(TCGContext
*s
, int cond
, int arg
)
1038 if (use_armv5t_instructions
) {
1039 tcg_out_blx(s
, cond
, arg
);
1041 tcg_out_dat_reg(s
, cond
, ARITH_MOV
, TCG_REG_R14
, 0,
1042 TCG_REG_PC
, SHIFT_IMM_LSL(0));
1043 tcg_out_bx(s
, cond
, arg
);
1047 static inline void tcg_out_goto_label(TCGContext
*s
, int cond
, int label_index
)
1049 TCGLabel
*l
= &s
->labels
[label_index
];
1052 tcg_out_goto(s
, cond
, l
->u
.value
);
1054 tcg_out_reloc(s
, s
->code_ptr
, R_ARM_PC24
, label_index
, 31337);
1055 tcg_out_b_noaddr(s
, cond
);
1059 #ifdef CONFIG_SOFTMMU
1061 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
1063 static const void * const qemu_ld_helpers
[4] = {
1070 /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
1071 uintxx_t val, int mmu_idx) */
1072 static const void * const qemu_st_helpers
[4] = {
1079 /* Helper routines for marshalling helper function arguments into
1080 * the correct registers and stack.
1081 * argreg is where we want to put this argument, arg is the argument itself.
1082 * Return value is the updated argreg ready for the next call.
1083 * Note that argreg 0..3 is real registers, 4+ on stack.
1085 * We provide routines for arguments which are: immediate, 32 bit
1086 * value in register, 16 and 8 bit values in register (which must be zero
1087 * extended before use) and 64 bit value in a lo:hi register pair.
1089 #define DEFINE_TCG_OUT_ARG(NAME, ARGTYPE, MOV_ARG, EXT_ARG) \
1090 static TCGReg NAME(TCGContext *s, TCGReg argreg, ARGTYPE arg) \
1093 MOV_ARG(s, COND_AL, argreg, arg); \
1095 int ofs = (argreg - 4) * 4; \
1097 assert(ofs + 4 <= TCG_STATIC_CALL_ARGS_SIZE); \
1098 tcg_out_st32_12(s, COND_AL, arg, TCG_REG_CALL_STACK, ofs); \
1100 return argreg + 1; \
1103 DEFINE_TCG_OUT_ARG(tcg_out_arg_imm32
, uint32_t, tcg_out_movi32
,
1104 (tcg_out_movi32(s
, COND_AL
, TCG_REG_TMP
, arg
), arg
= TCG_REG_TMP
))
1105 DEFINE_TCG_OUT_ARG(tcg_out_arg_reg8
, TCGReg
, tcg_out_ext8u
,
1106 (tcg_out_ext8u(s
, COND_AL
, TCG_REG_TMP
, arg
), arg
= TCG_REG_TMP
))
1107 DEFINE_TCG_OUT_ARG(tcg_out_arg_reg16
, TCGReg
, tcg_out_ext16u
,
1108 (tcg_out_ext16u(s
, COND_AL
, TCG_REG_TMP
, arg
), arg
= TCG_REG_TMP
))
1109 DEFINE_TCG_OUT_ARG(tcg_out_arg_reg32
, TCGReg
, tcg_out_mov_reg
, )
1111 static TCGReg
tcg_out_arg_reg64(TCGContext
*s
, TCGReg argreg
,
1112 TCGReg arglo
, TCGReg arghi
)
1114 /* 64 bit arguments must go in even/odd register pairs
1115 * and in 8-aligned stack slots.
1120 argreg
= tcg_out_arg_reg32(s
, argreg
, arglo
);
1121 argreg
= tcg_out_arg_reg32(s
, argreg
, arghi
);
1125 #define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS)
1127 /* Load and compare a TLB entry, leaving the flags set. Leaves R2 pointing
1128 to the tlb entry. Clobbers R1 and TMP. */
1130 static void tcg_out_tlb_read(TCGContext
*s
, TCGReg addrlo
, TCGReg addrhi
,
1131 int s_bits
, int tlb_offset
)
1133 TCGReg base
= TCG_AREG0
;
1135 /* Should generate something like the following:
1137 * shr tmp, addr_reg, #TARGET_PAGE_BITS (1)
1138 * add r2, env, #off & 0xff00
1139 * and r0, tmp, #(CPU_TLB_SIZE - 1) (2)
1140 * add r2, r2, r0, lsl #CPU_TLB_ENTRY_BITS (3)
1141 * ldr r0, [r2, #off & 0xff]! (4)
1142 * tst addr_reg, #s_mask
1143 * cmpeq r0, tmp, lsl #TARGET_PAGE_BITS (5)
1145 * v7 (not implemented yet):
1146 * ubfx r2, addr_reg, #TARGET_PAGE_BITS, #CPU_TLB_BITS (1)
1147 * movw tmp, #~TARGET_PAGE_MASK & ~s_mask
1149 * add r2, env, r2, lsl #CPU_TLB_ENTRY_BITS (2)
1150 * bic tmp, addr_reg, tmp
1151 * ldr r0, [r2, r0]! (3)
1154 # if CPU_TLB_BITS > 8
1157 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
, TCG_REG_TMP
,
1158 0, addrlo
, SHIFT_IMM_LSR(TARGET_PAGE_BITS
));
1160 /* We assume that the offset is contained within 16 bits. */
1161 assert((tlb_offset
& ~0xffff) == 0);
1162 if (tlb_offset
> 0xff) {
1163 tcg_out_dat_imm(s
, COND_AL
, ARITH_ADD
, TCG_REG_R2
, base
,
1164 (24 << 7) | (tlb_offset
>> 8));
1169 tcg_out_dat_imm(s
, COND_AL
, ARITH_AND
,
1170 TCG_REG_R0
, TCG_REG_TMP
, CPU_TLB_SIZE
- 1);
1171 tcg_out_dat_reg(s
, COND_AL
, ARITH_ADD
, TCG_REG_R2
, base
,
1172 TCG_REG_R0
, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS
));
1174 /* Load the tlb comparator. Use ldrd if needed and available,
1175 but due to how the pointer needs setting up, ldm isn't useful.
1176 Base arm5 doesn't have ldrd, but armv5te does. */
1177 if (use_armv6_instructions
&& TARGET_LONG_BITS
== 64) {
1178 tcg_out_memop_8(s
, COND_AL
, INSN_LDRD_IMM
, TCG_REG_R0
,
1179 TCG_REG_R2
, tlb_offset
, 1, 1);
1181 tcg_out_memop_12(s
, COND_AL
, INSN_LDR_IMM
, TCG_REG_R0
,
1182 TCG_REG_R2
, tlb_offset
, 1, 1);
1183 if (TARGET_LONG_BITS
== 64) {
1184 tcg_out_memop_12(s
, COND_AL
, INSN_LDR_IMM
, TCG_REG_R1
,
1185 TCG_REG_R2
, 4, 1, 0);
1189 /* Check alignment. */
1191 tcg_out_dat_imm(s
, COND_AL
, ARITH_TST
,
1192 0, addrlo
, (1 << s_bits
) - 1);
1195 tcg_out_dat_reg(s
, (s_bits
? COND_EQ
: COND_AL
), ARITH_CMP
, 0,
1196 TCG_REG_R0
, TCG_REG_TMP
, SHIFT_IMM_LSL(TARGET_PAGE_BITS
));
1198 if (TARGET_LONG_BITS
== 64) {
1199 tcg_out_dat_reg(s
, COND_EQ
, ARITH_CMP
, 0,
1200 TCG_REG_R1
, addrhi
, SHIFT_IMM_LSL(0));
1204 /* Record the context of a call to the out of line helper code for the slow
1205 path for a load or store, so that we can later generate the correct
1207 static void add_qemu_ldst_label(TCGContext
*s
, int is_ld
, int opc
,
1208 int data_reg
, int data_reg2
, int addrlo_reg
,
1209 int addrhi_reg
, int mem_index
,
1210 uint8_t *raddr
, uint8_t *label_ptr
)
1213 TCGLabelQemuLdst
*label
;
1215 if (s
->nb_qemu_ldst_labels
>= TCG_MAX_QEMU_LDST
) {
1219 idx
= s
->nb_qemu_ldst_labels
++;
1220 label
= (TCGLabelQemuLdst
*)&s
->qemu_ldst_labels
[idx
];
1221 label
->is_ld
= is_ld
;
1223 label
->datalo_reg
= data_reg
;
1224 label
->datahi_reg
= data_reg2
;
1225 label
->addrlo_reg
= addrlo_reg
;
1226 label
->addrhi_reg
= addrhi_reg
;
1227 label
->mem_index
= mem_index
;
1228 label
->raddr
= raddr
;
1229 label
->label_ptr
[0] = label_ptr
;
1232 static void tcg_out_qemu_ld_slow_path(TCGContext
*s
, TCGLabelQemuLdst
*lb
)
1234 TCGReg argreg
, data_reg
, data_reg2
;
1237 reloc_pc24(lb
->label_ptr
[0], (tcg_target_long
)s
->code_ptr
);
1239 argreg
= tcg_out_arg_reg32(s
, TCG_REG_R0
, TCG_AREG0
);
1240 if (TARGET_LONG_BITS
== 64) {
1241 argreg
= tcg_out_arg_reg64(s
, argreg
, lb
->addrlo_reg
, lb
->addrhi_reg
);
1243 argreg
= tcg_out_arg_reg32(s
, argreg
, lb
->addrlo_reg
);
1245 argreg
= tcg_out_arg_imm32(s
, argreg
, lb
->mem_index
);
1246 tcg_out_call(s
, (tcg_target_long
) qemu_ld_helpers
[lb
->opc
& 3]);
1248 data_reg
= lb
->datalo_reg
;
1249 data_reg2
= lb
->datahi_reg
;
1251 start
= s
->code_ptr
;
1254 tcg_out_ext8s(s
, COND_AL
, data_reg
, TCG_REG_R0
);
1257 tcg_out_ext16s(s
, COND_AL
, data_reg
, TCG_REG_R0
);
1263 tcg_out_mov_reg(s
, COND_AL
, data_reg
, TCG_REG_R0
);
1266 tcg_out_mov_reg(s
, COND_AL
, data_reg
, TCG_REG_R0
);
1267 tcg_out_mov_reg(s
, COND_AL
, data_reg2
, TCG_REG_R1
);
1271 /* For GETPC_LDST in exec-all.h, we architect exactly 2 insns between
1272 the call and the branch back to straight-line code. Note that the
1273 moves above could be elided by register allocation, nor do we know
1274 which code alternative we chose for extension. */
1275 switch (s
->code_ptr
- start
) {
1288 tcg_out_goto(s
, COND_AL
, (tcg_target_long
)lb
->raddr
);
1291 static void tcg_out_qemu_st_slow_path(TCGContext
*s
, TCGLabelQemuLdst
*lb
)
1293 TCGReg argreg
, data_reg
, data_reg2
;
1295 reloc_pc24(lb
->label_ptr
[0], (tcg_target_long
)s
->code_ptr
);
1297 argreg
= TCG_REG_R0
;
1298 argreg
= tcg_out_arg_reg32(s
, argreg
, TCG_AREG0
);
1299 if (TARGET_LONG_BITS
== 64) {
1300 argreg
= tcg_out_arg_reg64(s
, argreg
, lb
->addrlo_reg
, lb
->addrhi_reg
);
1302 argreg
= tcg_out_arg_reg32(s
, argreg
, lb
->addrlo_reg
);
1305 data_reg
= lb
->datalo_reg
;
1306 data_reg2
= lb
->datahi_reg
;
1309 argreg
= tcg_out_arg_reg8(s
, argreg
, data_reg
);
1312 argreg
= tcg_out_arg_reg16(s
, argreg
, data_reg
);
1315 argreg
= tcg_out_arg_reg32(s
, argreg
, data_reg
);
1318 argreg
= tcg_out_arg_reg64(s
, argreg
, data_reg
, data_reg2
);
1322 argreg
= tcg_out_arg_imm32(s
, argreg
, lb
->mem_index
);
1323 tcg_out_call(s
, (tcg_target_long
) qemu_st_helpers
[lb
->opc
& 3]);
1325 /* For GETPC_LDST in exec-all.h, we architect exactly 2 insns between
1326 the call and the branch back to straight-line code. */
1329 tcg_out_goto(s
, COND_AL
, (tcg_target_long
)lb
->raddr
);
1331 #endif /* SOFTMMU */
1333 static void tcg_out_qemu_ld(TCGContext
*s
, const TCGArg
*args
, int opc
)
1335 TCGReg addr_reg
, data_reg
, data_reg2
;
1337 #ifdef CONFIG_SOFTMMU
1338 int mem_index
, s_bits
;
1342 #ifdef TARGET_WORDS_BIGENDIAN
1349 data_reg2
= (opc
== 3 ? *args
++ : 0);
1351 #ifdef CONFIG_SOFTMMU
1352 addr_reg2
= (TARGET_LONG_BITS
== 64 ? *args
++ : 0);
1356 tcg_out_tlb_read(s
, addr_reg
, addr_reg2
, s_bits
,
1357 offsetof(CPUArchState
, tlb_table
[mem_index
][0].addr_read
));
1359 label_ptr
= s
->code_ptr
;
1360 tcg_out_b_noaddr(s
, COND_NE
);
1362 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_R1
, TCG_REG_R2
,
1363 offsetof(CPUTLBEntry
, addend
)
1364 - offsetof(CPUTLBEntry
, addr_read
));
1368 tcg_out_ld8_r(s
, COND_AL
, data_reg
, addr_reg
, TCG_REG_R1
);
1371 tcg_out_ld8s_r(s
, COND_AL
, data_reg
, addr_reg
, TCG_REG_R1
);
1374 tcg_out_ld16u_r(s
, COND_AL
, data_reg
, addr_reg
, TCG_REG_R1
);
1376 tcg_out_bswap16(s
, COND_AL
, data_reg
, data_reg
);
1381 tcg_out_ld16u_r(s
, COND_AL
, data_reg
, addr_reg
, TCG_REG_R1
);
1382 tcg_out_bswap16s(s
, COND_AL
, data_reg
, data_reg
);
1384 tcg_out_ld16s_r(s
, COND_AL
, data_reg
, addr_reg
, TCG_REG_R1
);
1389 tcg_out_ld32_r(s
, COND_AL
, data_reg
, addr_reg
, TCG_REG_R1
);
1391 tcg_out_bswap32(s
, COND_AL
, data_reg
, data_reg
);
1396 tcg_out_ld32_rwb(s
, COND_AL
, data_reg2
, TCG_REG_R1
, addr_reg
);
1397 tcg_out_ld32_12(s
, COND_AL
, data_reg
, TCG_REG_R1
, 4);
1398 tcg_out_bswap32(s
, COND_AL
, data_reg2
, data_reg2
);
1399 tcg_out_bswap32(s
, COND_AL
, data_reg
, data_reg
);
1401 tcg_out_ld32_rwb(s
, COND_AL
, data_reg
, TCG_REG_R1
, addr_reg
);
1402 tcg_out_ld32_12(s
, COND_AL
, data_reg2
, TCG_REG_R1
, 4);
1407 add_qemu_ldst_label(s
, 1, opc
, data_reg
, data_reg2
, addr_reg
, addr_reg2
,
1408 mem_index
, s
->code_ptr
, label_ptr
);
1409 #else /* !CONFIG_SOFTMMU */
1411 uint32_t offset
= GUEST_BASE
;
1415 i
= ctz32(offset
) & ~1;
1416 rot
= ((32 - i
) << 7) & 0xf00;
1418 tcg_out_dat_imm(s
, COND_AL
, ARITH_ADD
, TCG_REG_TMP
, addr_reg
,
1419 ((offset
>> i
) & 0xff) | rot
);
1420 addr_reg
= TCG_REG_TMP
;
1421 offset
&= ~(0xff << i
);
1426 tcg_out_ld8_12(s
, COND_AL
, data_reg
, addr_reg
, 0);
1429 tcg_out_ld8s_8(s
, COND_AL
, data_reg
, addr_reg
, 0);
1432 tcg_out_ld16u_8(s
, COND_AL
, data_reg
, addr_reg
, 0);
1434 tcg_out_bswap16(s
, COND_AL
, data_reg
, data_reg
);
1439 tcg_out_ld16u_8(s
, COND_AL
, data_reg
, addr_reg
, 0);
1440 tcg_out_bswap16s(s
, COND_AL
, data_reg
, data_reg
);
1442 tcg_out_ld16s_8(s
, COND_AL
, data_reg
, addr_reg
, 0);
1447 tcg_out_ld32_12(s
, COND_AL
, data_reg
, addr_reg
, 0);
1449 tcg_out_bswap32(s
, COND_AL
, data_reg
, data_reg
);
1453 /* TODO: use block load -
1454 * check that data_reg2 > data_reg or the other way */
1455 if (data_reg
== addr_reg
) {
1456 tcg_out_ld32_12(s
, COND_AL
, data_reg2
, addr_reg
, bswap
? 0 : 4);
1457 tcg_out_ld32_12(s
, COND_AL
, data_reg
, addr_reg
, bswap
? 4 : 0);
1459 tcg_out_ld32_12(s
, COND_AL
, data_reg
, addr_reg
, bswap
? 4 : 0);
1460 tcg_out_ld32_12(s
, COND_AL
, data_reg2
, addr_reg
, bswap
? 0 : 4);
1463 tcg_out_bswap32(s
, COND_AL
, data_reg
, data_reg
);
1464 tcg_out_bswap32(s
, COND_AL
, data_reg2
, data_reg2
);
1471 static void tcg_out_qemu_st(TCGContext
*s
, const TCGArg
*args
, int opc
)
1473 TCGReg addr_reg
, data_reg
, data_reg2
;
1475 #ifdef CONFIG_SOFTMMU
1476 int mem_index
, s_bits
;
1480 #ifdef TARGET_WORDS_BIGENDIAN
1487 data_reg2
= (opc
== 3 ? *args
++ : 0);
1489 #ifdef CONFIG_SOFTMMU
1490 addr_reg2
= (TARGET_LONG_BITS
== 64 ? *args
++ : 0);
1494 tcg_out_tlb_read(s
, addr_reg
, addr_reg2
, s_bits
,
1495 offsetof(CPUArchState
,
1496 tlb_table
[mem_index
][0].addr_write
));
1498 label_ptr
= s
->code_ptr
;
1499 tcg_out_b_noaddr(s
, COND_NE
);
1501 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_R1
, TCG_REG_R2
,
1502 offsetof(CPUTLBEntry
, addend
)
1503 - offsetof(CPUTLBEntry
, addr_write
));
1507 tcg_out_st8_r(s
, COND_AL
, data_reg
, addr_reg
, TCG_REG_R1
);
1511 tcg_out_bswap16st(s
, COND_AL
, TCG_REG_R0
, data_reg
);
1512 tcg_out_st16_r(s
, COND_AL
, TCG_REG_R0
, addr_reg
, TCG_REG_R1
);
1514 tcg_out_st16_r(s
, COND_AL
, data_reg
, addr_reg
, TCG_REG_R1
);
1520 tcg_out_bswap32(s
, COND_AL
, TCG_REG_R0
, data_reg
);
1521 tcg_out_st32_r(s
, COND_AL
, TCG_REG_R0
, addr_reg
, TCG_REG_R1
);
1523 tcg_out_st32_r(s
, COND_AL
, data_reg
, addr_reg
, TCG_REG_R1
);
1528 tcg_out_bswap32(s
, COND_AL
, TCG_REG_R0
, data_reg2
);
1529 tcg_out_st32_rwb(s
, COND_AL
, TCG_REG_R0
, TCG_REG_R1
, addr_reg
);
1530 tcg_out_bswap32(s
, COND_AL
, TCG_REG_R0
, data_reg
);
1531 tcg_out_st32_12(s
, COND_AL
, TCG_REG_R0
, TCG_REG_R1
, 4);
1533 tcg_out_st32_rwb(s
, COND_AL
, data_reg
, TCG_REG_R1
, addr_reg
);
1534 tcg_out_st32_12(s
, COND_AL
, data_reg2
, TCG_REG_R1
, 4);
1539 add_qemu_ldst_label(s
, 0, opc
, data_reg
, data_reg2
, addr_reg
, addr_reg2
,
1540 mem_index
, s
->code_ptr
, label_ptr
);
1541 #else /* !CONFIG_SOFTMMU */
1543 uint32_t offset
= GUEST_BASE
;
1548 i
= ctz32(offset
) & ~1;
1549 rot
= ((32 - i
) << 7) & 0xf00;
1551 tcg_out_dat_imm(s
, COND_AL
, ARITH_ADD
, TCG_REG_R1
, addr_reg
,
1552 ((offset
>> i
) & 0xff) | rot
);
1553 addr_reg
= TCG_REG_R1
;
1554 offset
&= ~(0xff << i
);
1559 tcg_out_st8_12(s
, COND_AL
, data_reg
, addr_reg
, 0);
1563 tcg_out_bswap16st(s
, COND_AL
, TCG_REG_R0
, data_reg
);
1564 tcg_out_st16_8(s
, COND_AL
, TCG_REG_R0
, addr_reg
, 0);
1566 tcg_out_st16_8(s
, COND_AL
, data_reg
, addr_reg
, 0);
1572 tcg_out_bswap32(s
, COND_AL
, TCG_REG_R0
, data_reg
);
1573 tcg_out_st32_12(s
, COND_AL
, TCG_REG_R0
, addr_reg
, 0);
1575 tcg_out_st32_12(s
, COND_AL
, data_reg
, addr_reg
, 0);
1579 /* TODO: use block store -
1580 * check that data_reg2 > data_reg or the other way */
1582 tcg_out_bswap32(s
, COND_AL
, TCG_REG_R0
, data_reg2
);
1583 tcg_out_st32_12(s
, COND_AL
, TCG_REG_R0
, addr_reg
, 0);
1584 tcg_out_bswap32(s
, COND_AL
, TCG_REG_R0
, data_reg
);
1585 tcg_out_st32_12(s
, COND_AL
, TCG_REG_R0
, addr_reg
, 4);
1587 tcg_out_st32_12(s
, COND_AL
, data_reg
, addr_reg
, 0);
1588 tcg_out_st32_12(s
, COND_AL
, data_reg2
, addr_reg
, 4);
1595 static uint8_t *tb_ret_addr
;
1597 static inline void tcg_out_op(TCGContext
*s
, TCGOpcode opc
,
1598 const TCGArg
*args
, const int *const_args
)
1600 TCGArg a0
, a1
, a2
, a3
, a4
, a5
;
1604 case INDEX_op_exit_tb
:
1605 if (use_armv7_instructions
|| check_fit_imm(args
[0])) {
1606 tcg_out_movi32(s
, COND_AL
, TCG_REG_R0
, args
[0]);
1607 tcg_out_goto(s
, COND_AL
, (tcg_target_ulong
) tb_ret_addr
);
1609 uint8_t *ld_ptr
= s
->code_ptr
;
1610 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_R0
, TCG_REG_PC
, 0);
1611 tcg_out_goto(s
, COND_AL
, (tcg_target_ulong
) tb_ret_addr
);
1612 *ld_ptr
= (uint8_t) (s
->code_ptr
- ld_ptr
) - 8;
1613 tcg_out32(s
, args
[0]);
1616 case INDEX_op_goto_tb
:
1617 if (s
->tb_jmp_offset
) {
1618 /* Direct jump method */
1619 #if defined(USE_DIRECT_JUMP)
1620 s
->tb_jmp_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
1621 tcg_out_b_noaddr(s
, COND_AL
);
1623 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_PC
, TCG_REG_PC
, -4);
1624 s
->tb_jmp_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
1628 /* Indirect jump method */
1630 c
= (int) (s
->tb_next
+ args
[0]) - ((int) s
->code_ptr
+ 8);
1631 if (c
> 0xfff || c
< -0xfff) {
1632 tcg_out_movi32(s
, COND_AL
, TCG_REG_R0
,
1633 (tcg_target_long
) (s
->tb_next
+ args
[0]));
1634 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_PC
, TCG_REG_R0
, 0);
1636 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_PC
, TCG_REG_PC
, c
);
1638 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_R0
, TCG_REG_PC
, 0);
1639 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_PC
, TCG_REG_R0
, 0);
1640 tcg_out32(s
, (tcg_target_long
) (s
->tb_next
+ args
[0]));
1643 s
->tb_next_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
1647 tcg_out_call(s
, args
[0]);
1649 tcg_out_callr(s
, COND_AL
, args
[0]);
1652 tcg_out_goto_label(s
, COND_AL
, args
[0]);
1655 case INDEX_op_ld8u_i32
:
1656 tcg_out_ld8u(s
, COND_AL
, args
[0], args
[1], args
[2]);
1658 case INDEX_op_ld8s_i32
:
1659 tcg_out_ld8s(s
, COND_AL
, args
[0], args
[1], args
[2]);
1661 case INDEX_op_ld16u_i32
:
1662 tcg_out_ld16u(s
, COND_AL
, args
[0], args
[1], args
[2]);
1664 case INDEX_op_ld16s_i32
:
1665 tcg_out_ld16s(s
, COND_AL
, args
[0], args
[1], args
[2]);
1667 case INDEX_op_ld_i32
:
1668 tcg_out_ld32u(s
, COND_AL
, args
[0], args
[1], args
[2]);
1670 case INDEX_op_st8_i32
:
1671 tcg_out_st8(s
, COND_AL
, args
[0], args
[1], args
[2]);
1673 case INDEX_op_st16_i32
:
1674 tcg_out_st16(s
, COND_AL
, args
[0], args
[1], args
[2]);
1676 case INDEX_op_st_i32
:
1677 tcg_out_st32(s
, COND_AL
, args
[0], args
[1], args
[2]);
1680 case INDEX_op_mov_i32
:
1681 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1682 args
[0], 0, args
[1], SHIFT_IMM_LSL(0));
1684 case INDEX_op_movi_i32
:
1685 tcg_out_movi32(s
, COND_AL
, args
[0], args
[1]);
1687 case INDEX_op_movcond_i32
:
1688 /* Constraints mean that v2 is always in the same register as dest,
1689 * so we only need to do "if condition passed, move v1 to dest".
1691 tcg_out_dat_rIN(s
, COND_AL
, ARITH_CMP
, ARITH_CMN
, 0,
1692 args
[1], args
[2], const_args
[2]);
1693 tcg_out_dat_rIK(s
, tcg_cond_to_arm_cond
[args
[5]], ARITH_MOV
,
1694 ARITH_MVN
, args
[0], 0, args
[3], const_args
[3]);
1696 case INDEX_op_add_i32
:
1697 tcg_out_dat_rIN(s
, COND_AL
, ARITH_ADD
, ARITH_SUB
,
1698 args
[0], args
[1], args
[2], const_args
[2]);
1700 case INDEX_op_sub_i32
:
1701 if (const_args
[1]) {
1702 if (const_args
[2]) {
1703 tcg_out_movi32(s
, COND_AL
, args
[0], args
[1] - args
[2]);
1705 tcg_out_dat_rI(s
, COND_AL
, ARITH_RSB
,
1706 args
[0], args
[2], args
[1], 1);
1709 tcg_out_dat_rIN(s
, COND_AL
, ARITH_SUB
, ARITH_ADD
,
1710 args
[0], args
[1], args
[2], const_args
[2]);
1713 case INDEX_op_and_i32
:
1714 tcg_out_dat_rIK(s
, COND_AL
, ARITH_AND
, ARITH_BIC
,
1715 args
[0], args
[1], args
[2], const_args
[2]);
1717 case INDEX_op_andc_i32
:
1718 tcg_out_dat_rIK(s
, COND_AL
, ARITH_BIC
, ARITH_AND
,
1719 args
[0], args
[1], args
[2], const_args
[2]);
1721 case INDEX_op_or_i32
:
1724 case INDEX_op_xor_i32
:
1728 tcg_out_dat_rI(s
, COND_AL
, c
, args
[0], args
[1], args
[2], const_args
[2]);
1730 case INDEX_op_add2_i32
:
1731 a0
= args
[0], a1
= args
[1], a2
= args
[2];
1732 a3
= args
[3], a4
= args
[4], a5
= args
[5];
1733 if (a0
== a3
|| (a0
== a5
&& !const_args
[5])) {
1736 tcg_out_dat_rIN(s
, COND_AL
, ARITH_ADD
| TO_CPSR
, ARITH_SUB
| TO_CPSR
,
1737 a0
, a2
, a4
, const_args
[4]);
1738 tcg_out_dat_rIK(s
, COND_AL
, ARITH_ADC
, ARITH_SBC
,
1739 a1
, a3
, a5
, const_args
[5]);
1740 tcg_out_mov_reg(s
, COND_AL
, args
[0], a0
);
1742 case INDEX_op_sub2_i32
:
1743 a0
= args
[0], a1
= args
[1], a2
= args
[2];
1744 a3
= args
[3], a4
= args
[4], a5
= args
[5];
1745 if ((a0
== a3
&& !const_args
[3]) || (a0
== a5
&& !const_args
[5])) {
1748 if (const_args
[2]) {
1749 if (const_args
[4]) {
1750 tcg_out_movi32(s
, COND_AL
, a0
, a4
);
1753 tcg_out_dat_rI(s
, COND_AL
, ARITH_RSB
| TO_CPSR
, a0
, a4
, a2
, 1);
1755 tcg_out_dat_rIN(s
, COND_AL
, ARITH_SUB
| TO_CPSR
,
1756 ARITH_ADD
| TO_CPSR
, a0
, a2
, a4
, const_args
[4]);
1758 if (const_args
[3]) {
1759 if (const_args
[5]) {
1760 tcg_out_movi32(s
, COND_AL
, a1
, a5
);
1763 tcg_out_dat_rI(s
, COND_AL
, ARITH_RSC
, a1
, a5
, a3
, 1);
1765 tcg_out_dat_rIK(s
, COND_AL
, ARITH_SBC
, ARITH_ADC
,
1766 a1
, a3
, a5
, const_args
[5]);
1768 tcg_out_mov_reg(s
, COND_AL
, args
[0], a0
);
1770 case INDEX_op_neg_i32
:
1771 tcg_out_dat_imm(s
, COND_AL
, ARITH_RSB
, args
[0], args
[1], 0);
1773 case INDEX_op_not_i32
:
1774 tcg_out_dat_reg(s
, COND_AL
,
1775 ARITH_MVN
, args
[0], 0, args
[1], SHIFT_IMM_LSL(0));
1777 case INDEX_op_mul_i32
:
1778 tcg_out_mul32(s
, COND_AL
, args
[0], args
[1], args
[2]);
1780 case INDEX_op_mulu2_i32
:
1781 tcg_out_umull32(s
, COND_AL
, args
[0], args
[1], args
[2], args
[3]);
1783 case INDEX_op_muls2_i32
:
1784 tcg_out_smull32(s
, COND_AL
, args
[0], args
[1], args
[2], args
[3]);
1786 /* XXX: Perhaps args[2] & 0x1f is wrong */
1787 case INDEX_op_shl_i32
:
1789 SHIFT_IMM_LSL(args
[2] & 0x1f) : SHIFT_REG_LSL(args
[2]);
1791 case INDEX_op_shr_i32
:
1792 c
= const_args
[2] ? (args
[2] & 0x1f) ? SHIFT_IMM_LSR(args
[2] & 0x1f) :
1793 SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args
[2]);
1795 case INDEX_op_sar_i32
:
1796 c
= const_args
[2] ? (args
[2] & 0x1f) ? SHIFT_IMM_ASR(args
[2] & 0x1f) :
1797 SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args
[2]);
1799 case INDEX_op_rotr_i32
:
1800 c
= const_args
[2] ? (args
[2] & 0x1f) ? SHIFT_IMM_ROR(args
[2] & 0x1f) :
1801 SHIFT_IMM_LSL(0) : SHIFT_REG_ROR(args
[2]);
1804 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
, args
[0], 0, args
[1], c
);
1807 case INDEX_op_rotl_i32
:
1808 if (const_args
[2]) {
1809 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
, args
[0], 0, args
[1],
1810 ((0x20 - args
[2]) & 0x1f) ?
1811 SHIFT_IMM_ROR((0x20 - args
[2]) & 0x1f) :
1814 tcg_out_dat_imm(s
, COND_AL
, ARITH_RSB
, TCG_REG_TMP
, args
[1], 0x20);
1815 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
, args
[0], 0, args
[1],
1816 SHIFT_REG_ROR(TCG_REG_TMP
));
1820 case INDEX_op_brcond_i32
:
1821 tcg_out_dat_rIN(s
, COND_AL
, ARITH_CMP
, ARITH_CMN
, 0,
1822 args
[0], args
[1], const_args
[1]);
1823 tcg_out_goto_label(s
, tcg_cond_to_arm_cond
[args
[2]], args
[3]);
1825 case INDEX_op_brcond2_i32
:
1826 /* The resulting conditions are:
1827 * TCG_COND_EQ --> a0 == a2 && a1 == a3,
1828 * TCG_COND_NE --> (a0 != a2 && a1 == a3) || a1 != a3,
1829 * TCG_COND_LT(U) --> (a0 < a2 && a1 == a3) || a1 < a3,
1830 * TCG_COND_GE(U) --> (a0 >= a2 && a1 == a3) || (a1 >= a3 && a1 != a3),
1831 * TCG_COND_LE(U) --> (a0 <= a2 && a1 == a3) || (a1 <= a3 && a1 != a3),
1832 * TCG_COND_GT(U) --> (a0 > a2 && a1 == a3) || a1 > a3,
1834 tcg_out_dat_rIN(s
, COND_AL
, ARITH_CMP
, ARITH_CMN
, 0,
1835 args
[1], args
[3], const_args
[3]);
1836 tcg_out_dat_rIN(s
, COND_EQ
, ARITH_CMP
, ARITH_CMN
, 0,
1837 args
[0], args
[2], const_args
[2]);
1838 tcg_out_goto_label(s
, tcg_cond_to_arm_cond
[args
[4]], args
[5]);
1840 case INDEX_op_setcond_i32
:
1841 tcg_out_dat_rIN(s
, COND_AL
, ARITH_CMP
, ARITH_CMN
, 0,
1842 args
[1], args
[2], const_args
[2]);
1843 tcg_out_dat_imm(s
, tcg_cond_to_arm_cond
[args
[3]],
1844 ARITH_MOV
, args
[0], 0, 1);
1845 tcg_out_dat_imm(s
, tcg_cond_to_arm_cond
[tcg_invert_cond(args
[3])],
1846 ARITH_MOV
, args
[0], 0, 0);
1848 case INDEX_op_setcond2_i32
:
1849 /* See brcond2_i32 comment */
1850 tcg_out_dat_rIN(s
, COND_AL
, ARITH_CMP
, ARITH_CMN
, 0,
1851 args
[2], args
[4], const_args
[4]);
1852 tcg_out_dat_rIN(s
, COND_EQ
, ARITH_CMP
, ARITH_CMN
, 0,
1853 args
[1], args
[3], const_args
[3]);
1854 tcg_out_dat_imm(s
, tcg_cond_to_arm_cond
[args
[5]],
1855 ARITH_MOV
, args
[0], 0, 1);
1856 tcg_out_dat_imm(s
, tcg_cond_to_arm_cond
[tcg_invert_cond(args
[5])],
1857 ARITH_MOV
, args
[0], 0, 0);
1860 case INDEX_op_qemu_ld8u
:
1861 tcg_out_qemu_ld(s
, args
, 0);
1863 case INDEX_op_qemu_ld8s
:
1864 tcg_out_qemu_ld(s
, args
, 0 | 4);
1866 case INDEX_op_qemu_ld16u
:
1867 tcg_out_qemu_ld(s
, args
, 1);
1869 case INDEX_op_qemu_ld16s
:
1870 tcg_out_qemu_ld(s
, args
, 1 | 4);
1872 case INDEX_op_qemu_ld32
:
1873 tcg_out_qemu_ld(s
, args
, 2);
1875 case INDEX_op_qemu_ld64
:
1876 tcg_out_qemu_ld(s
, args
, 3);
1879 case INDEX_op_qemu_st8
:
1880 tcg_out_qemu_st(s
, args
, 0);
1882 case INDEX_op_qemu_st16
:
1883 tcg_out_qemu_st(s
, args
, 1);
1885 case INDEX_op_qemu_st32
:
1886 tcg_out_qemu_st(s
, args
, 2);
1888 case INDEX_op_qemu_st64
:
1889 tcg_out_qemu_st(s
, args
, 3);
1892 case INDEX_op_bswap16_i32
:
1893 tcg_out_bswap16(s
, COND_AL
, args
[0], args
[1]);
1895 case INDEX_op_bswap32_i32
:
1896 tcg_out_bswap32(s
, COND_AL
, args
[0], args
[1]);
1899 case INDEX_op_ext8s_i32
:
1900 tcg_out_ext8s(s
, COND_AL
, args
[0], args
[1]);
1902 case INDEX_op_ext16s_i32
:
1903 tcg_out_ext16s(s
, COND_AL
, args
[0], args
[1]);
1905 case INDEX_op_ext16u_i32
:
1906 tcg_out_ext16u(s
, COND_AL
, args
[0], args
[1]);
1909 case INDEX_op_deposit_i32
:
1910 tcg_out_deposit(s
, COND_AL
, args
[0], args
[2],
1911 args
[3], args
[4], const_args
[2]);
1914 case INDEX_op_div_i32
:
1915 tcg_out_sdiv(s
, COND_AL
, args
[0], args
[1], args
[2]);
1917 case INDEX_op_divu_i32
:
1918 tcg_out_udiv(s
, COND_AL
, args
[0], args
[1], args
[2]);
1926 #ifdef CONFIG_SOFTMMU
1927 /* Generate TB finalization at the end of block. */
1928 void tcg_out_tb_finalize(TCGContext
*s
)
1931 for (i
= 0; i
< s
->nb_qemu_ldst_labels
; i
++) {
1932 TCGLabelQemuLdst
*label
= &s
->qemu_ldst_labels
[i
];
1934 tcg_out_qemu_ld_slow_path(s
, label
);
1936 tcg_out_qemu_st_slow_path(s
, label
);
1940 #endif /* SOFTMMU */
1942 static const TCGTargetOpDef arm_op_defs
[] = {
1943 { INDEX_op_exit_tb
, { } },
1944 { INDEX_op_goto_tb
, { } },
1945 { INDEX_op_call
, { "ri" } },
1946 { INDEX_op_br
, { } },
1948 { INDEX_op_mov_i32
, { "r", "r" } },
1949 { INDEX_op_movi_i32
, { "r" } },
1951 { INDEX_op_ld8u_i32
, { "r", "r" } },
1952 { INDEX_op_ld8s_i32
, { "r", "r" } },
1953 { INDEX_op_ld16u_i32
, { "r", "r" } },
1954 { INDEX_op_ld16s_i32
, { "r", "r" } },
1955 { INDEX_op_ld_i32
, { "r", "r" } },
1956 { INDEX_op_st8_i32
, { "r", "r" } },
1957 { INDEX_op_st16_i32
, { "r", "r" } },
1958 { INDEX_op_st_i32
, { "r", "r" } },
1960 /* TODO: "r", "r", "ri" */
1961 { INDEX_op_add_i32
, { "r", "r", "rIN" } },
1962 { INDEX_op_sub_i32
, { "r", "rI", "rIN" } },
1963 { INDEX_op_mul_i32
, { "r", "r", "r" } },
1964 { INDEX_op_mulu2_i32
, { "r", "r", "r", "r" } },
1965 { INDEX_op_muls2_i32
, { "r", "r", "r", "r" } },
1966 { INDEX_op_and_i32
, { "r", "r", "rIK" } },
1967 { INDEX_op_andc_i32
, { "r", "r", "rIK" } },
1968 { INDEX_op_or_i32
, { "r", "r", "rI" } },
1969 { INDEX_op_xor_i32
, { "r", "r", "rI" } },
1970 { INDEX_op_neg_i32
, { "r", "r" } },
1971 { INDEX_op_not_i32
, { "r", "r" } },
1973 { INDEX_op_shl_i32
, { "r", "r", "ri" } },
1974 { INDEX_op_shr_i32
, { "r", "r", "ri" } },
1975 { INDEX_op_sar_i32
, { "r", "r", "ri" } },
1976 { INDEX_op_rotl_i32
, { "r", "r", "ri" } },
1977 { INDEX_op_rotr_i32
, { "r", "r", "ri" } },
1979 { INDEX_op_brcond_i32
, { "r", "rIN" } },
1980 { INDEX_op_setcond_i32
, { "r", "r", "rIN" } },
1981 { INDEX_op_movcond_i32
, { "r", "r", "rIN", "rIK", "0" } },
1983 { INDEX_op_add2_i32
, { "r", "r", "r", "r", "rIN", "rIK" } },
1984 { INDEX_op_sub2_i32
, { "r", "r", "rI", "rI", "rIN", "rIK" } },
1985 { INDEX_op_brcond2_i32
, { "r", "r", "rIN", "rIN" } },
1986 { INDEX_op_setcond2_i32
, { "r", "r", "r", "rIN", "rIN" } },
1988 #if TARGET_LONG_BITS == 32
1989 { INDEX_op_qemu_ld8u
, { "r", "l" } },
1990 { INDEX_op_qemu_ld8s
, { "r", "l" } },
1991 { INDEX_op_qemu_ld16u
, { "r", "l" } },
1992 { INDEX_op_qemu_ld16s
, { "r", "l" } },
1993 { INDEX_op_qemu_ld32
, { "r", "l" } },
1994 { INDEX_op_qemu_ld64
, { "L", "L", "l" } },
1996 { INDEX_op_qemu_st8
, { "s", "s" } },
1997 { INDEX_op_qemu_st16
, { "s", "s" } },
1998 { INDEX_op_qemu_st32
, { "s", "s" } },
1999 { INDEX_op_qemu_st64
, { "s", "s", "s" } },
2001 { INDEX_op_qemu_ld8u
, { "r", "l", "l" } },
2002 { INDEX_op_qemu_ld8s
, { "r", "l", "l" } },
2003 { INDEX_op_qemu_ld16u
, { "r", "l", "l" } },
2004 { INDEX_op_qemu_ld16s
, { "r", "l", "l" } },
2005 { INDEX_op_qemu_ld32
, { "r", "l", "l" } },
2006 { INDEX_op_qemu_ld64
, { "L", "L", "l", "l" } },
2008 { INDEX_op_qemu_st8
, { "s", "s", "s" } },
2009 { INDEX_op_qemu_st16
, { "s", "s", "s" } },
2010 { INDEX_op_qemu_st32
, { "s", "s", "s" } },
2011 { INDEX_op_qemu_st64
, { "s", "s", "s", "s" } },
2014 { INDEX_op_bswap16_i32
, { "r", "r" } },
2015 { INDEX_op_bswap32_i32
, { "r", "r" } },
2017 { INDEX_op_ext8s_i32
, { "r", "r" } },
2018 { INDEX_op_ext16s_i32
, { "r", "r" } },
2019 { INDEX_op_ext16u_i32
, { "r", "r" } },
2021 { INDEX_op_deposit_i32
, { "r", "0", "rZ" } },
2023 { INDEX_op_div_i32
, { "r", "r", "r" } },
2024 { INDEX_op_divu_i32
, { "r", "r", "r" } },
2029 static void tcg_target_init(TCGContext
*s
)
2031 #if defined(CONFIG_GETAUXVAL)
2032 /* Only probe for the platform and capabilities if we havn't already
2033 determined maximum values at compile time. */
2034 # if !defined(use_idiv_instructions)
2036 unsigned long hwcap
= getauxval(AT_HWCAP
);
2037 use_idiv_instructions
= (hwcap
& HWCAP_ARM_IDIVA
) != 0;
2040 if (__ARM_ARCH
< 7) {
2041 const char *pl
= (const char *)getauxval(AT_PLATFORM
);
2042 if (pl
!= NULL
&& pl
[0] == 'v' && pl
[1] >= '4' && pl
[1] <= '9') {
2043 arm_arch
= pl
[1] - '0';
2046 #endif /* GETAUXVAL */
2048 tcg_regset_set32(tcg_target_available_regs
[TCG_TYPE_I32
], 0, 0xffff);
2049 tcg_regset_set32(tcg_target_call_clobber_regs
, 0,
2054 (1 << TCG_REG_R12
) |
2055 (1 << TCG_REG_R14
));
2057 tcg_regset_clear(s
->reserved_regs
);
2058 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_CALL_STACK
);
2059 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_TMP
);
2060 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_PC
);
2062 tcg_add_target_add_op_defs(arm_op_defs
);
2065 static inline void tcg_out_ld(TCGContext
*s
, TCGType type
, TCGReg arg
,
2066 TCGReg arg1
, intptr_t arg2
)
2068 tcg_out_ld32u(s
, COND_AL
, arg
, arg1
, arg2
);
2071 static inline void tcg_out_st(TCGContext
*s
, TCGType type
, TCGReg arg
,
2072 TCGReg arg1
, intptr_t arg2
)
2074 tcg_out_st32(s
, COND_AL
, arg
, arg1
, arg2
);
2077 static inline void tcg_out_mov(TCGContext
*s
, TCGType type
,
2078 TCGReg ret
, TCGReg arg
)
2080 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
, ret
, 0, arg
, SHIFT_IMM_LSL(0));
2083 static inline void tcg_out_movi(TCGContext
*s
, TCGType type
,
2084 TCGReg ret
, tcg_target_long arg
)
2086 tcg_out_movi32(s
, COND_AL
, ret
, arg
);
2089 /* Compute frame size via macros, to share between tcg_target_qemu_prologue
2090 and tcg_register_jit. */
2092 #define PUSH_SIZE ((11 - 4 + 1 + 1) * sizeof(tcg_target_long))
2094 #define FRAME_SIZE \
2096 + TCG_STATIC_CALL_ARGS_SIZE \
2097 + CPU_TEMP_BUF_NLONGS * sizeof(long) \
2098 + TCG_TARGET_STACK_ALIGN - 1) \
2099 & -TCG_TARGET_STACK_ALIGN)
2101 static void tcg_target_qemu_prologue(TCGContext
*s
)
2105 /* Calling convention requires us to save r4-r11 and lr. */
2106 /* stmdb sp!, { r4 - r11, lr } */
2107 tcg_out32(s
, (COND_AL
<< 28) | 0x092d4ff0);
2109 /* Reserve callee argument and tcg temp space. */
2110 stack_addend
= FRAME_SIZE
- PUSH_SIZE
;
2112 tcg_out_dat_rI(s
, COND_AL
, ARITH_SUB
, TCG_REG_CALL_STACK
,
2113 TCG_REG_CALL_STACK
, stack_addend
, 1);
2114 tcg_set_frame(s
, TCG_REG_CALL_STACK
, TCG_STATIC_CALL_ARGS_SIZE
,
2115 CPU_TEMP_BUF_NLONGS
* sizeof(long));
2117 tcg_out_mov(s
, TCG_TYPE_PTR
, TCG_AREG0
, tcg_target_call_iarg_regs
[0]);
2119 tcg_out_bx(s
, COND_AL
, tcg_target_call_iarg_regs
[1]);
2120 tb_ret_addr
= s
->code_ptr
;
2122 /* Epilogue. We branch here via tb_ret_addr. */
2123 tcg_out_dat_rI(s
, COND_AL
, ARITH_ADD
, TCG_REG_CALL_STACK
,
2124 TCG_REG_CALL_STACK
, stack_addend
, 1);
2126 /* ldmia sp!, { r4 - r11, pc } */
2127 tcg_out32(s
, (COND_AL
<< 28) | 0x08bd8ff0);
2132 DebugFrameFDEHeader fde
;
2133 uint8_t fde_def_cfa
[4];
2134 uint8_t fde_reg_ofs
[18];
2137 #define ELF_HOST_MACHINE EM_ARM
2139 /* We're expecting a 2 byte uleb128 encoded value. */
2140 QEMU_BUILD_BUG_ON(FRAME_SIZE
>= (1 << 14));
2142 static DebugFrame debug_frame
= {
2143 .cie
.len
= sizeof(DebugFrameCIE
)-4, /* length after .len member */
2146 .cie
.code_align
= 1,
2147 .cie
.data_align
= 0x7c, /* sleb128 -4 */
2148 .cie
.return_column
= 14,
2150 /* Total FDE size does not include the "len" member. */
2151 .fde
.len
= sizeof(DebugFrame
) - offsetof(DebugFrame
, fde
.cie_offset
),
2154 12, 13, /* DW_CFA_def_cfa sp, ... */
2155 (FRAME_SIZE
& 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2159 /* The following must match the stmdb in the prologue. */
2160 0x8e, 1, /* DW_CFA_offset, lr, -4 */
2161 0x8b, 2, /* DW_CFA_offset, r11, -8 */
2162 0x8a, 3, /* DW_CFA_offset, r10, -12 */
2163 0x89, 4, /* DW_CFA_offset, r9, -16 */
2164 0x88, 5, /* DW_CFA_offset, r8, -20 */
2165 0x87, 6, /* DW_CFA_offset, r7, -24 */
2166 0x86, 7, /* DW_CFA_offset, r6, -28 */
2167 0x85, 8, /* DW_CFA_offset, r5, -32 */
2168 0x84, 9, /* DW_CFA_offset, r4, -36 */
2172 void tcg_register_jit(void *buf
, size_t buf_size
)
2174 debug_frame
.fde
.func_start
= (tcg_target_long
) buf
;
2175 debug_frame
.fde
.func_len
= buf_size
;
2177 tcg_register_jit_int(buf
, buf_size
, &debug_frame
, sizeof(debug_frame
));