tcg/hppa/tcg-target.h

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2008 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #ifndef TCG_TARGET_HPPA
  26 #define TCG_TARGET_HPPA 1
  27
  28 #define TCG_TARGET_WORDS_BIGENDIAN
  29
  30 #define TCG_TARGET_NB_REGS 32
  31
  32 typedef enum {
  33     TCG_REG_R0 = 0,
  34     TCG_REG_R1,
  35     TCG_REG_RP,
  36     TCG_REG_R3,
  37     TCG_REG_R4,
  38     TCG_REG_R5,
  39     TCG_REG_R6,
  40     TCG_REG_R7,
  41     TCG_REG_R8,
  42     TCG_REG_R9,
  43     TCG_REG_R10,
  44     TCG_REG_R11,
  45     TCG_REG_R12,
  46     TCG_REG_R13,
  47     TCG_REG_R14,
  48     TCG_REG_R15,
  49     TCG_REG_R16,
  50     TCG_REG_R17,
  51     TCG_REG_R18,
  52     TCG_REG_R19,
  53     TCG_REG_R20,
  54     TCG_REG_R21,
  55     TCG_REG_R22,
  56     TCG_REG_R23,
  57     TCG_REG_R24,
  58     TCG_REG_R25,
  59     TCG_REG_R26,
  60     TCG_REG_DP,
  61     TCG_REG_RET0,
  62     TCG_REG_RET1,
  63     TCG_REG_SP,
  64     TCG_REG_R31,
  65 } TCGReg;
  66
  67 #define TCG_CT_CONST_0    0x0100
  68 #define TCG_CT_CONST_S5   0x0200
  69 #define TCG_CT_CONST_S11  0x0400
  70 #define TCG_CT_CONST_MS11 0x0800
  71 #define TCG_CT_CONST_AND  0x1000
  72 #define TCG_CT_CONST_OR   0x2000
  73
  74 /* used for function call generation */
  75 #define TCG_REG_CALL_STACK TCG_REG_SP
  76 #define TCG_TARGET_STACK_ALIGN 64
  77 #define TCG_TARGET_CALL_STACK_OFFSET -48
  78 #define TCG_TARGET_STATIC_CALL_ARGS_SIZE 8*4
  79 #define TCG_TARGET_CALL_ALIGN_ARGS 1
  80 #define TCG_TARGET_STACK_GROWSUP
  81
  82 /* optional instructions */
  83 #define TCG_TARGET_HAS_div_i32          0
  84 #define TCG_TARGET_HAS_rem_i32          0
  85 #define TCG_TARGET_HAS_rot_i32          1
  86 #define TCG_TARGET_HAS_ext8s_i32        1
  87 #define TCG_TARGET_HAS_ext16s_i32       1
  88 #define TCG_TARGET_HAS_bswap16_i32      1
  89 #define TCG_TARGET_HAS_bswap32_i32      1
  90 #define TCG_TARGET_HAS_not_i32          1
  91 #define TCG_TARGET_HAS_andc_i32         1
  92 #define TCG_TARGET_HAS_orc_i32          0
  93 #define TCG_TARGET_HAS_eqv_i32          0
  94 #define TCG_TARGET_HAS_nand_i32         0
  95 #define TCG_TARGET_HAS_nor_i32          0
  96 #define TCG_TARGET_HAS_deposit_i32      1
  97 #define TCG_TARGET_HAS_movcond_i32      1
  98 #define TCG_TARGET_HAS_muls2_i32        0
  99 #define TCG_TARGET_HAS_muluh_i32        0
 100 #define TCG_TARGET_HAS_mulsh_i32        0
 101
 102 /* optional instructions automatically implemented */
 103 #define TCG_TARGET_HAS_neg_i32          0 /* sub rd, 0, rs */
 104 #define TCG_TARGET_HAS_ext8u_i32        0 /* and rd, rs, 0xff */
 105 #define TCG_TARGET_HAS_ext16u_i32       0 /* and rd, rs, 0xffff */
 106
 107 #define TCG_AREG0 TCG_REG_R17
 108
 109
 110 static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
 111 {
 112     start &= ~31;
 113     while (start <= stop) {
 114         asm volatile ("fdc 0(%0)\n\t"
 115                       "sync\n\t"
 116                       "fic 0(%%sr4, %0)\n\t"
 117                       "sync"
 118                       : : "r"(start) : "memory");
 119         start += 32;
 120     }
 121 }
 122
 123 #endif