tcg/hppa/tcg-target.h

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2008 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #define TCG_TARGET_HPPA 1
  26
  27 #if defined(_PA_RISC1_1)
  28 #define TCG_TARGET_REG_BITS 32
  29 #else
  30 #error unsupported
  31 #endif
  32
  33 #define TCG_TARGET_WORDS_BIGENDIAN
  34
  35 #define TCG_TARGET_NB_REGS 32
  36
  37 enum {
  38     TCG_REG_R0 = 0,
  39     TCG_REG_R1,
  40     TCG_REG_RP,
  41     TCG_REG_R3,
  42     TCG_REG_R4,
  43     TCG_REG_R5,
  44     TCG_REG_R6,
  45     TCG_REG_R7,
  46     TCG_REG_R8,
  47     TCG_REG_R9,
  48     TCG_REG_R10,
  49     TCG_REG_R11,
  50     TCG_REG_R12,
  51     TCG_REG_R13,
  52     TCG_REG_R14,
  53     TCG_REG_R15,
  54     TCG_REG_R16,
  55     TCG_REG_R17,
  56     TCG_REG_R18,
  57     TCG_REG_R19,
  58     TCG_REG_R20,
  59     TCG_REG_R21,
  60     TCG_REG_R22,
  61     TCG_REG_R23,
  62     TCG_REG_R24,
  63     TCG_REG_R25,
  64     TCG_REG_R26,
  65     TCG_REG_DP,
  66     TCG_REG_RET0,
  67     TCG_REG_RET1,
  68     TCG_REG_SP,
  69     TCG_REG_R31,
  70 };
  71
  72 /* used for function call generation */
  73 #define TCG_REG_CALL_STACK TCG_REG_SP
  74 #define TCG_TARGET_STACK_ALIGN 16
  75 #define TCG_TARGET_STACK_GROWSUP
  76
  77 /* optional instructions */
  78 #define TCG_TARGET_HAS_div2_i32
  79 //#define TCG_TARGET_HAS_ext8s_i32
  80 //#define TCG_TARGET_HAS_ext16s_i32
  81 //#define TCG_TARGET_HAS_bswap16_i32
  82 //#define TCG_TARGET_HAS_bswap32_i32
  83
  84 /* Note: must be synced with dyngen-exec.h */
  85 #define TCG_AREG0 TCG_REG_R17
  86
  87 static inline void flush_icache_range(unsigned long start, unsigned long stop)
  88 {
  89     start &= ~31;
  90     while (start <= stop)
  91     {
  92         asm volatile ("fdc 0(%0)\n"
  93                       "sync\n"
  94                       "fic 0(%%sr4, %0)\n"
  95                       "sync\n"
  96                       : : "r"(start) : "memory");
  97         start += 32;
  98     }
  99 }
 100
 101 /* supplied by libgcc */
 102 extern void *__canonicalize_funcptr_for_compare(void *);
 103
 104 /* Field selection types defined by hppa */
 105 #define rnd(x)                  (((x)+0x1000)&~0x1fff)
 106 /* lsel: select left 21 bits */
 107 #define lsel(v,a)               (((v)+(a))>>11)
 108 /* rsel: select right 11 bits */
 109 #define rsel(v,a)               (((v)+(a))&0x7ff)
 110 /* lrsel with rounding of addend to nearest 8k */
 111 #define lrsel(v,a)              (((v)+rnd(a))>>11)
 112 /* rrsel with rounding of addend to nearest 8k */
 113 #define rrsel(v,a)              ((((v)+rnd(a))&0x7ff)+((a)-rnd(a)))
 114
 115 #define mask(x,sz)              ((x) & ~((1<<(sz))-1))
 116
 117 static inline int reassemble_12(int as12)
 118 {
 119     return (((as12 & 0x800) >> 11) |
 120             ((as12 & 0x400) >> 8) |
 121             ((as12 & 0x3ff) << 3));
 122 }
 123
 124 static inline int reassemble_14(int as14)
 125 {
 126     return (((as14 & 0x1fff) << 1) |
 127             ((as14 & 0x2000) >> 13));
 128 }
 129
 130 static inline int reassemble_17(int as17)
 131 {
 132     return (((as17 & 0x10000) >> 16) |
 133             ((as17 & 0x0f800) << 5) |
 134             ((as17 & 0x00400) >> 8) |
 135             ((as17 & 0x003ff) << 3));
 136 }
 137
 138 static inline int reassemble_21(int as21)
 139 {
 140     return (((as21 & 0x100000) >> 20) |
 141             ((as21 & 0x0ffe00) >> 8) |
 142             ((as21 & 0x000180) << 7) |
 143             ((as21 & 0x00007c) << 14) |
 144             ((as21 & 0x000003) << 12));
 145 }
 146
 147 static inline void hppa_patch21l(uint32_t *insn, int val, int addend)
 148 {
 149     val = lrsel(val, addend);
 150     *insn = mask(*insn, 21) | reassemble_21(val);
 151 }
 152
 153 static inline void hppa_patch14r(uint32_t *insn, int val, int addend)
 154 {
 155     val = rrsel(val, addend);
 156     *insn = mask(*insn, 14) | reassemble_14(val);
 157 }
 158
 159 static inline void hppa_patch17r(uint32_t *insn, int val, int addend)
 160 {
 161     val = rrsel(val, addend);
 162     *insn = (*insn & ~0x1f1ffd) | reassemble_17(val);
 163 }
 164
 165
 166 static inline void hppa_patch21l_dprel(uint32_t *insn, int val, int addend)
 167 {
 168     register unsigned int dp asm("r27");
 169     hppa_patch21l(insn, val - dp, addend);
 170 }
 171
 172 static inline void hppa_patch14r_dprel(uint32_t *insn, int val, int addend)
 173 {
 174     register unsigned int dp asm("r27");
 175     hppa_patch14r(insn, val - dp, addend);
 176 }
 177
 178 static inline void hppa_patch17f(uint32_t *insn, int val, int addend)
 179 {
 180     int dot = (int)insn & ~0x3;
 181     int v = ((val + addend) - dot - 8) / 4;
 182     if (v > (1 << 16) || v < -(1 << 16)) {
 183         printf("cannot fit branch to offset %d [%08x->%08x]\n", v, dot, val);
 184         abort();
 185     }
 186     *insn = (*insn & ~0x1f1ffd) | reassemble_17(v);
 187 }
 188
 189 static inline void hppa_load_imm21l(uint32_t *insn, int val, int addend)
 190 {
 191     /* Transform addil L'sym(%dp) to ldil L'val, %r1 */
 192     *insn = 0x20200000 | reassemble_21(lrsel(val, 0));
 193 }
 194
 195 static inline void hppa_load_imm14r(uint32_t *insn, int val, int addend)
 196 {
 197     /* Transform ldw R'sym(%r1), %rN to ldo R'sym(%r1), %rN */
 198     hppa_patch14r(insn, val, addend);
 199     /* HACK */
 200     if (addend == 0)
 201         *insn = (*insn & ~0xfc000000) | (0x0d << 26);
 202 }