2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 static const char * const tcg_target_reg_names
[TCG_TARGET_NB_REGS
] = {
27 #if TCG_TARGET_REG_BITS == 64
28 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
29 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
31 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
36 static const int tcg_target_reg_alloc_order
[] = {
37 #if TCG_TARGET_REG_BITS == 64
64 static const int tcg_target_call_iarg_regs
[] = {
65 #if TCG_TARGET_REG_BITS == 64
84 static const int tcg_target_call_oarg_regs
[] = {
86 #if TCG_TARGET_REG_BITS == 32
91 static uint8_t *tb_ret_addr
;
93 static void patch_reloc(uint8_t *code_ptr
, int type
,
94 tcg_target_long value
, tcg_target_long addend
)
99 value
-= (uintptr_t)code_ptr
;
100 if (value
!= (int32_t)value
) {
103 *(uint32_t *)code_ptr
= value
;
106 value
-= (uintptr_t)code_ptr
;
107 if (value
!= (int8_t)value
) {
110 *(uint8_t *)code_ptr
= value
;
117 /* maximum number of register used for input function arguments */
118 static inline int tcg_target_get_call_iarg_regs_count(int flags
)
120 if (TCG_TARGET_REG_BITS
== 64) {
127 /* parse target specific constraints */
128 static int target_parse_constraint(TCGArgConstraint
*ct
, const char **pct_str
)
135 ct
->ct
|= TCG_CT_REG
;
136 tcg_regset_set_reg(ct
->u
.regs
, TCG_REG_EAX
);
139 ct
->ct
|= TCG_CT_REG
;
140 tcg_regset_set_reg(ct
->u
.regs
, TCG_REG_EBX
);
143 ct
->ct
|= TCG_CT_REG
;
144 tcg_regset_set_reg(ct
->u
.regs
, TCG_REG_ECX
);
147 ct
->ct
|= TCG_CT_REG
;
148 tcg_regset_set_reg(ct
->u
.regs
, TCG_REG_EDX
);
151 ct
->ct
|= TCG_CT_REG
;
152 tcg_regset_set_reg(ct
->u
.regs
, TCG_REG_ESI
);
155 ct
->ct
|= TCG_CT_REG
;
156 tcg_regset_set_reg(ct
->u
.regs
, TCG_REG_EDI
);
159 ct
->ct
|= TCG_CT_REG
;
160 if (TCG_TARGET_REG_BITS
== 64) {
161 tcg_regset_set32(ct
->u
.regs
, 0, 0xffff);
163 tcg_regset_set32(ct
->u
.regs
, 0, 0xf);
167 ct
->ct
|= TCG_CT_REG
;
168 tcg_regset_set32(ct
->u
.regs
, 0, 0xf);
171 ct
->ct
|= TCG_CT_REG
;
172 if (TCG_TARGET_REG_BITS
== 64) {
173 tcg_regset_set32(ct
->u
.regs
, 0, 0xffff);
175 tcg_regset_set32(ct
->u
.regs
, 0, 0xff);
179 /* qemu_ld/st address constraint */
181 ct
->ct
|= TCG_CT_REG
;
182 if (TCG_TARGET_REG_BITS
== 64) {
183 tcg_regset_set32(ct
->u
.regs
, 0, 0xffff);
184 tcg_regset_reset_reg(ct
->u
.regs
, tcg_target_call_iarg_regs
[0]);
185 tcg_regset_reset_reg(ct
->u
.regs
, tcg_target_call_iarg_regs
[1]);
186 tcg_regset_reset_reg(ct
->u
.regs
, tcg_target_call_iarg_regs
[2]);
188 tcg_regset_set32(ct
->u
.regs
, 0, 0xff);
189 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_EAX
);
190 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_EDX
);
195 ct
->ct
|= TCG_CT_CONST_S32
;
198 ct
->ct
|= TCG_CT_CONST_U32
;
209 /* test if a constant matches the constraint */
210 static inline int tcg_target_const_match(tcg_target_long val
,
211 const TCGArgConstraint
*arg_ct
)
214 if (ct
& TCG_CT_CONST
) {
217 if ((ct
& TCG_CT_CONST_S32
) && val
== (int32_t)val
) {
220 if ((ct
& TCG_CT_CONST_U32
) && val
== (uint32_t)val
) {
226 #if TCG_TARGET_REG_BITS == 64
227 # define LOWREGMASK(x) ((x) & 7)
229 # define LOWREGMASK(x) (x)
232 #define P_EXT 0x100 /* 0x0f opcode prefix */
233 #define P_DATA16 0x200 /* 0x66 opcode prefix */
234 #if TCG_TARGET_REG_BITS == 64
235 # define P_ADDR32 0x400 /* 0x67 opcode prefix */
236 # define P_REXW 0x800 /* Set REX.W = 1 */
237 # define P_REXB_R 0x1000 /* REG field as byte register */
238 # define P_REXB_RM 0x2000 /* R/M field as byte register */
246 #define OPC_ARITH_EvIz (0x81)
247 #define OPC_ARITH_EvIb (0x83)
248 #define OPC_ARITH_GvEv (0x03) /* ... plus (ARITH_FOO << 3) */
249 #define OPC_ADD_GvEv (OPC_ARITH_GvEv | (ARITH_ADD << 3))
250 #define OPC_BSWAP (0xc8 | P_EXT)
251 #define OPC_CALL_Jz (0xe8)
252 #define OPC_CMP_GvEv (OPC_ARITH_GvEv | (ARITH_CMP << 3))
253 #define OPC_DEC_r32 (0x48)
254 #define OPC_IMUL_GvEv (0xaf | P_EXT)
255 #define OPC_IMUL_GvEvIb (0x6b)
256 #define OPC_IMUL_GvEvIz (0x69)
257 #define OPC_INC_r32 (0x40)
258 #define OPC_JCC_long (0x80 | P_EXT) /* ... plus condition code */
259 #define OPC_JCC_short (0x70) /* ... plus condition code */
260 #define OPC_JMP_long (0xe9)
261 #define OPC_JMP_short (0xeb)
262 #define OPC_LEA (0x8d)
263 #define OPC_MOVB_EvGv (0x88) /* stores, more or less */
264 #define OPC_MOVL_EvGv (0x89) /* stores, more or less */
265 #define OPC_MOVL_GvEv (0x8b) /* loads, more or less */
266 #define OPC_MOVL_EvIz (0xc7)
267 #define OPC_MOVL_Iv (0xb8)
268 #define OPC_MOVSBL (0xbe | P_EXT)
269 #define OPC_MOVSWL (0xbf | P_EXT)
270 #define OPC_MOVSLQ (0x63 | P_REXW)
271 #define OPC_MOVZBL (0xb6 | P_EXT)
272 #define OPC_MOVZWL (0xb7 | P_EXT)
273 #define OPC_POP_r32 (0x58)
274 #define OPC_PUSH_r32 (0x50)
275 #define OPC_PUSH_Iv (0x68)
276 #define OPC_PUSH_Ib (0x6a)
277 #define OPC_RET (0xc3)
278 #define OPC_SETCC (0x90 | P_EXT | P_REXB_RM) /* ... plus cc */
279 #define OPC_SHIFT_1 (0xd1)
280 #define OPC_SHIFT_Ib (0xc1)
281 #define OPC_SHIFT_cl (0xd3)
282 #define OPC_TESTL (0x85)
283 #define OPC_XCHG_ax_r32 (0x90)
285 #define OPC_GRP3_Ev (0xf7)
286 #define OPC_GRP5 (0xff)
288 /* Group 1 opcode extensions for 0x80-0x83.
289 These are also used as modifiers for OPC_ARITH. */
299 /* Group 2 opcode extensions for 0xc0, 0xc1, 0xd0-0xd3. */
306 /* Group 3 opcode extensions for 0xf6, 0xf7. To be used with OPC_GRP3. */
314 /* Group 5 opcode extensions for 0xff. To be used with OPC_GRP5. */
315 #define EXT5_INC_Ev 0
316 #define EXT5_DEC_Ev 1
317 #define EXT5_CALLN_Ev 2
318 #define EXT5_JMPN_Ev 4
320 /* Condition codes to be added to OPC_JCC_{long,short}. */
339 static const uint8_t tcg_cond_to_jcc
[10] = {
340 [TCG_COND_EQ
] = JCC_JE
,
341 [TCG_COND_NE
] = JCC_JNE
,
342 [TCG_COND_LT
] = JCC_JL
,
343 [TCG_COND_GE
] = JCC_JGE
,
344 [TCG_COND_LE
] = JCC_JLE
,
345 [TCG_COND_GT
] = JCC_JG
,
346 [TCG_COND_LTU
] = JCC_JB
,
347 [TCG_COND_GEU
] = JCC_JAE
,
348 [TCG_COND_LEU
] = JCC_JBE
,
349 [TCG_COND_GTU
] = JCC_JA
,
352 #if TCG_TARGET_REG_BITS == 64
353 static void tcg_out_opc(TCGContext
*s
, int opc
, int r
, int rm
, int x
)
357 if (opc
& P_DATA16
) {
358 /* We should never be asking for both 16 and 64-bit operation. */
359 assert((opc
& P_REXW
) == 0);
362 if (opc
& P_ADDR32
) {
367 rex
|= (opc
& P_REXW
) >> 8; /* REX.W */
368 rex
|= (r
& 8) >> 1; /* REX.R */
369 rex
|= (x
& 8) >> 2; /* REX.X */
370 rex
|= (rm
& 8) >> 3; /* REX.B */
372 /* P_REXB_{R,RM} indicates that the given register is the low byte.
373 For %[abcd]l we need no REX prefix, but for %{si,di,bp,sp}l we do,
374 as otherwise the encoding indicates %[abcd]h. Note that the values
375 that are ORed in merely indicate that the REX byte must be present;
376 those bits get discarded in output. */
377 rex
|= opc
& (r
>= 4 ? P_REXB_R
: 0);
378 rex
|= opc
& (rm
>= 4 ? P_REXB_RM
: 0);
381 tcg_out8(s
, (uint8_t)(rex
| 0x40));
390 static void tcg_out_opc(TCGContext
*s
, int opc
)
392 if (opc
& P_DATA16
) {
400 /* Discard the register arguments to tcg_out_opc early, so as not to penalize
401 the 32-bit compilation paths. This method works with all versions of gcc,
402 whereas relying on optimization may not be able to exclude them. */
403 #define tcg_out_opc(s, opc, r, rm, x) (tcg_out_opc)(s, opc)
406 static void tcg_out_modrm(TCGContext
*s
, int opc
, int r
, int rm
)
408 tcg_out_opc(s
, opc
, r
, rm
, 0);
409 tcg_out8(s
, 0xc0 | (LOWREGMASK(r
) << 3) | LOWREGMASK(rm
));
412 /* Output an opcode with a full "rm + (index<<shift) + offset" address mode.
413 We handle either RM and INDEX missing with a negative value. In 64-bit
414 mode for absolute addresses, ~RM is the size of the immediate operand
415 that will follow the instruction. */
417 static void tcg_out_modrm_sib_offset(TCGContext
*s
, int opc
, int r
, int rm
,
418 int index
, int shift
,
419 tcg_target_long offset
)
423 if (index
< 0 && rm
< 0) {
424 if (TCG_TARGET_REG_BITS
== 64) {
425 /* Try for a rip-relative addressing mode. This has replaced
426 the 32-bit-mode absolute addressing encoding. */
427 tcg_target_long pc
= (tcg_target_long
)s
->code_ptr
+ 5 + ~rm
;
428 tcg_target_long disp
= offset
- pc
;
429 if (disp
== (int32_t)disp
) {
430 tcg_out_opc(s
, opc
, r
, 0, 0);
431 tcg_out8(s
, (LOWREGMASK(r
) << 3) | 5);
436 /* Try for an absolute address encoding. This requires the
437 use of the MODRM+SIB encoding and is therefore larger than
438 rip-relative addressing. */
439 if (offset
== (int32_t)offset
) {
440 tcg_out_opc(s
, opc
, r
, 0, 0);
441 tcg_out8(s
, (LOWREGMASK(r
) << 3) | 4);
442 tcg_out8(s
, (4 << 3) | 5);
443 tcg_out32(s
, offset
);
447 /* ??? The memory isn't directly addressable. */
450 /* Absolute address. */
451 tcg_out_opc(s
, opc
, r
, 0, 0);
452 tcg_out8(s
, (r
<< 3) | 5);
453 tcg_out32(s
, offset
);
458 /* Find the length of the immediate addend. Note that the encoding
459 that would be used for (%ebp) indicates absolute addressing. */
461 mod
= 0, len
= 4, rm
= 5;
462 } else if (offset
== 0 && LOWREGMASK(rm
) != TCG_REG_EBP
) {
464 } else if (offset
== (int8_t)offset
) {
470 /* Use a single byte MODRM format if possible. Note that the encoding
471 that would be used for %esp is the escape to the two byte form. */
472 if (index
< 0 && LOWREGMASK(rm
) != TCG_REG_ESP
) {
473 /* Single byte MODRM format. */
474 tcg_out_opc(s
, opc
, r
, rm
, 0);
475 tcg_out8(s
, mod
| (LOWREGMASK(r
) << 3) | LOWREGMASK(rm
));
477 /* Two byte MODRM+SIB format. */
479 /* Note that the encoding that would place %esp into the index
480 field indicates no index register. In 64-bit mode, the REX.X
481 bit counts, so %r12 can be used as the index. */
485 assert(index
!= TCG_REG_ESP
);
488 tcg_out_opc(s
, opc
, r
, rm
, index
);
489 tcg_out8(s
, mod
| (LOWREGMASK(r
) << 3) | 4);
490 tcg_out8(s
, (shift
<< 6) | (LOWREGMASK(index
) << 3) | LOWREGMASK(rm
));
495 } else if (len
== 4) {
496 tcg_out32(s
, offset
);
500 /* A simplification of the above with no index or shift. */
501 static inline void tcg_out_modrm_offset(TCGContext
*s
, int opc
, int r
,
502 int rm
, tcg_target_long offset
)
504 tcg_out_modrm_sib_offset(s
, opc
, r
, rm
, -1, 0, offset
);
507 /* Generate dest op= src. Uses the same ARITH_* codes as tgen_arithi. */
508 static inline void tgen_arithr(TCGContext
*s
, int subop
, int dest
, int src
)
510 /* Propagate an opcode prefix, such as P_REXW. */
511 int ext
= subop
& ~0x7;
514 tcg_out_modrm(s
, OPC_ARITH_GvEv
+ (subop
<< 3) + ext
, dest
, src
);
517 static inline void tcg_out_mov(TCGContext
*s
, TCGType type
,
518 TCGReg ret
, TCGReg arg
)
521 int opc
= OPC_MOVL_GvEv
+ (type
== TCG_TYPE_I64
? P_REXW
: 0);
522 tcg_out_modrm(s
, opc
, ret
, arg
);
526 static void tcg_out_movi(TCGContext
*s
, TCGType type
,
527 TCGReg ret
, tcg_target_long arg
)
530 tgen_arithr(s
, ARITH_XOR
, ret
, ret
);
532 } else if (arg
== (uint32_t)arg
|| type
== TCG_TYPE_I32
) {
533 tcg_out_opc(s
, OPC_MOVL_Iv
+ LOWREGMASK(ret
), 0, ret
, 0);
535 } else if (arg
== (int32_t)arg
) {
536 tcg_out_modrm(s
, OPC_MOVL_EvIz
+ P_REXW
, 0, ret
);
539 tcg_out_opc(s
, OPC_MOVL_Iv
+ P_REXW
+ LOWREGMASK(ret
), 0, ret
, 0);
541 tcg_out32(s
, arg
>> 31 >> 1);
545 static inline void tcg_out_pushi(TCGContext
*s
, tcg_target_long val
)
547 if (val
== (int8_t)val
) {
548 tcg_out_opc(s
, OPC_PUSH_Ib
, 0, 0, 0);
550 } else if (val
== (int32_t)val
) {
551 tcg_out_opc(s
, OPC_PUSH_Iv
, 0, 0, 0);
558 static inline void tcg_out_push(TCGContext
*s
, int reg
)
560 tcg_out_opc(s
, OPC_PUSH_r32
+ LOWREGMASK(reg
), 0, reg
, 0);
563 static inline void tcg_out_pop(TCGContext
*s
, int reg
)
565 tcg_out_opc(s
, OPC_POP_r32
+ LOWREGMASK(reg
), 0, reg
, 0);
568 static inline void tcg_out_ld(TCGContext
*s
, TCGType type
, TCGReg ret
,
569 TCGReg arg1
, tcg_target_long arg2
)
571 int opc
= OPC_MOVL_GvEv
+ (type
== TCG_TYPE_I64
? P_REXW
: 0);
572 tcg_out_modrm_offset(s
, opc
, ret
, arg1
, arg2
);
575 static inline void tcg_out_st(TCGContext
*s
, TCGType type
, TCGReg arg
,
576 TCGReg arg1
, tcg_target_long arg2
)
578 int opc
= OPC_MOVL_EvGv
+ (type
== TCG_TYPE_I64
? P_REXW
: 0);
579 tcg_out_modrm_offset(s
, opc
, arg
, arg1
, arg2
);
582 static void tcg_out_shifti(TCGContext
*s
, int subopc
, int reg
, int count
)
584 /* Propagate an opcode prefix, such as P_DATA16. */
585 int ext
= subopc
& ~0x7;
589 tcg_out_modrm(s
, OPC_SHIFT_1
+ ext
, subopc
, reg
);
591 tcg_out_modrm(s
, OPC_SHIFT_Ib
+ ext
, subopc
, reg
);
596 static inline void tcg_out_bswap32(TCGContext
*s
, int reg
)
598 tcg_out_opc(s
, OPC_BSWAP
+ LOWREGMASK(reg
), 0, reg
, 0);
601 static inline void tcg_out_rolw_8(TCGContext
*s
, int reg
)
603 tcg_out_shifti(s
, SHIFT_ROL
+ P_DATA16
, reg
, 8);
606 static inline void tcg_out_ext8u(TCGContext
*s
, int dest
, int src
)
609 assert(src
< 4 || TCG_TARGET_REG_BITS
== 64);
610 tcg_out_modrm(s
, OPC_MOVZBL
+ P_REXB_RM
, dest
, src
);
613 static void tcg_out_ext8s(TCGContext
*s
, int dest
, int src
, int rexw
)
616 assert(src
< 4 || TCG_TARGET_REG_BITS
== 64);
617 tcg_out_modrm(s
, OPC_MOVSBL
+ P_REXB_RM
+ rexw
, dest
, src
);
620 static inline void tcg_out_ext16u(TCGContext
*s
, int dest
, int src
)
623 tcg_out_modrm(s
, OPC_MOVZWL
, dest
, src
);
626 static inline void tcg_out_ext16s(TCGContext
*s
, int dest
, int src
, int rexw
)
629 tcg_out_modrm(s
, OPC_MOVSWL
+ rexw
, dest
, src
);
632 static inline void tcg_out_ext32u(TCGContext
*s
, int dest
, int src
)
634 /* 32-bit mov zero extends. */
635 tcg_out_modrm(s
, OPC_MOVL_GvEv
, dest
, src
);
638 static inline void tcg_out_ext32s(TCGContext
*s
, int dest
, int src
)
640 tcg_out_modrm(s
, OPC_MOVSLQ
, dest
, src
);
643 static inline void tcg_out_bswap64(TCGContext
*s
, int reg
)
645 tcg_out_opc(s
, OPC_BSWAP
+ P_REXW
+ LOWREGMASK(reg
), 0, reg
, 0);
648 static void tgen_arithi(TCGContext
*s
, int c
, int r0
,
649 tcg_target_long val
, int cf
)
653 if (TCG_TARGET_REG_BITS
== 64) {
658 /* ??? While INC is 2 bytes shorter than ADDL $1, they also induce
659 partial flags update stalls on Pentium4 and are not recommended
660 by current Intel optimization manuals. */
661 if (!cf
&& (c
== ARITH_ADD
|| c
== ARITH_SUB
) && (val
== 1 || val
== -1)) {
662 int is_inc
= (c
== ARITH_ADD
) ^ (val
< 0);
663 if (TCG_TARGET_REG_BITS
== 64) {
664 /* The single-byte increment encodings are re-tasked as the
665 REX prefixes. Use the MODRM encoding. */
666 tcg_out_modrm(s
, OPC_GRP5
+ rexw
,
667 (is_inc
? EXT5_INC_Ev
: EXT5_DEC_Ev
), r0
);
669 tcg_out8(s
, (is_inc
? OPC_INC_r32
: OPC_DEC_r32
) + r0
);
674 if (c
== ARITH_AND
) {
675 if (TCG_TARGET_REG_BITS
== 64) {
676 if (val
== 0xffffffffu
) {
677 tcg_out_ext32u(s
, r0
, r0
);
680 if (val
== (uint32_t)val
) {
681 /* AND with no high bits set can use a 32-bit operation. */
685 if (val
== 0xffu
&& (r0
< 4 || TCG_TARGET_REG_BITS
== 64)) {
686 tcg_out_ext8u(s
, r0
, r0
);
689 if (val
== 0xffffu
) {
690 tcg_out_ext16u(s
, r0
, r0
);
695 if (val
== (int8_t)val
) {
696 tcg_out_modrm(s
, OPC_ARITH_EvIb
+ rexw
, c
, r0
);
700 if (rexw
== 0 || val
== (int32_t)val
) {
701 tcg_out_modrm(s
, OPC_ARITH_EvIz
+ rexw
, c
, r0
);
709 static void tcg_out_addi(TCGContext
*s
, int reg
, tcg_target_long val
)
712 tgen_arithi(s
, ARITH_ADD
+ P_REXW
, reg
, val
, 0);
716 /* Use SMALL != 0 to force a short forward branch. */
717 static void tcg_out_jxx(TCGContext
*s
, int opc
, int label_index
, int small
)
720 TCGLabel
*l
= &s
->labels
[label_index
];
723 val
= l
->u
.value
- (tcg_target_long
)s
->code_ptr
;
725 if ((int8_t)val1
== val1
) {
727 tcg_out8(s
, OPC_JMP_short
);
729 tcg_out8(s
, OPC_JCC_short
+ opc
);
737 tcg_out8(s
, OPC_JMP_long
);
738 tcg_out32(s
, val
- 5);
740 tcg_out_opc(s
, OPC_JCC_long
+ opc
, 0, 0, 0);
741 tcg_out32(s
, val
- 6);
746 tcg_out8(s
, OPC_JMP_short
);
748 tcg_out8(s
, OPC_JCC_short
+ opc
);
750 tcg_out_reloc(s
, s
->code_ptr
, R_386_PC8
, label_index
, -1);
754 tcg_out8(s
, OPC_JMP_long
);
756 tcg_out_opc(s
, OPC_JCC_long
+ opc
, 0, 0, 0);
758 tcg_out_reloc(s
, s
->code_ptr
, R_386_PC32
, label_index
, -4);
763 static void tcg_out_cmp(TCGContext
*s
, TCGArg arg1
, TCGArg arg2
,
764 int const_arg2
, int rexw
)
769 tcg_out_modrm(s
, OPC_TESTL
+ rexw
, arg1
, arg1
);
771 tgen_arithi(s
, ARITH_CMP
+ rexw
, arg1
, arg2
, 0);
774 tgen_arithr(s
, ARITH_CMP
+ rexw
, arg1
, arg2
);
778 static void tcg_out_brcond32(TCGContext
*s
, TCGCond cond
,
779 TCGArg arg1
, TCGArg arg2
, int const_arg2
,
780 int label_index
, int small
)
782 tcg_out_cmp(s
, arg1
, arg2
, const_arg2
, 0);
783 tcg_out_jxx(s
, tcg_cond_to_jcc
[cond
], label_index
, small
);
786 #if TCG_TARGET_REG_BITS == 64
787 static void tcg_out_brcond64(TCGContext
*s
, TCGCond cond
,
788 TCGArg arg1
, TCGArg arg2
, int const_arg2
,
789 int label_index
, int small
)
791 tcg_out_cmp(s
, arg1
, arg2
, const_arg2
, P_REXW
);
792 tcg_out_jxx(s
, tcg_cond_to_jcc
[cond
], label_index
, small
);
795 /* XXX: we implement it at the target level to avoid having to
796 handle cross basic blocks temporaries */
797 static void tcg_out_brcond2(TCGContext
*s
, const TCGArg
*args
,
798 const int *const_args
, int small
)
801 label_next
= gen_new_label();
804 tcg_out_brcond32(s
, TCG_COND_NE
, args
[0], args
[2], const_args
[2],
806 tcg_out_brcond32(s
, TCG_COND_EQ
, args
[1], args
[3], const_args
[3],
810 tcg_out_brcond32(s
, TCG_COND_NE
, args
[0], args
[2], const_args
[2],
812 tcg_out_brcond32(s
, TCG_COND_NE
, args
[1], args
[3], const_args
[3],
816 tcg_out_brcond32(s
, TCG_COND_LT
, args
[1], args
[3], const_args
[3],
818 tcg_out_jxx(s
, JCC_JNE
, label_next
, 1);
819 tcg_out_brcond32(s
, TCG_COND_LTU
, args
[0], args
[2], const_args
[2],
823 tcg_out_brcond32(s
, TCG_COND_LT
, args
[1], args
[3], const_args
[3],
825 tcg_out_jxx(s
, JCC_JNE
, label_next
, 1);
826 tcg_out_brcond32(s
, TCG_COND_LEU
, args
[0], args
[2], const_args
[2],
830 tcg_out_brcond32(s
, TCG_COND_GT
, args
[1], args
[3], const_args
[3],
832 tcg_out_jxx(s
, JCC_JNE
, label_next
, 1);
833 tcg_out_brcond32(s
, TCG_COND_GTU
, args
[0], args
[2], const_args
[2],
837 tcg_out_brcond32(s
, TCG_COND_GT
, args
[1], args
[3], const_args
[3],
839 tcg_out_jxx(s
, JCC_JNE
, label_next
, 1);
840 tcg_out_brcond32(s
, TCG_COND_GEU
, args
[0], args
[2], const_args
[2],
844 tcg_out_brcond32(s
, TCG_COND_LTU
, args
[1], args
[3], const_args
[3],
846 tcg_out_jxx(s
, JCC_JNE
, label_next
, 1);
847 tcg_out_brcond32(s
, TCG_COND_LTU
, args
[0], args
[2], const_args
[2],
851 tcg_out_brcond32(s
, TCG_COND_LTU
, args
[1], args
[3], const_args
[3],
853 tcg_out_jxx(s
, JCC_JNE
, label_next
, 1);
854 tcg_out_brcond32(s
, TCG_COND_LEU
, args
[0], args
[2], const_args
[2],
858 tcg_out_brcond32(s
, TCG_COND_GTU
, args
[1], args
[3], const_args
[3],
860 tcg_out_jxx(s
, JCC_JNE
, label_next
, 1);
861 tcg_out_brcond32(s
, TCG_COND_GTU
, args
[0], args
[2], const_args
[2],
865 tcg_out_brcond32(s
, TCG_COND_GTU
, args
[1], args
[3], const_args
[3],
867 tcg_out_jxx(s
, JCC_JNE
, label_next
, 1);
868 tcg_out_brcond32(s
, TCG_COND_GEU
, args
[0], args
[2], const_args
[2],
874 tcg_out_label(s
, label_next
, s
->code_ptr
);
878 static void tcg_out_setcond32(TCGContext
*s
, TCGCond cond
, TCGArg dest
,
879 TCGArg arg1
, TCGArg arg2
, int const_arg2
)
881 tcg_out_cmp(s
, arg1
, arg2
, const_arg2
, 0);
882 tcg_out_modrm(s
, OPC_SETCC
| tcg_cond_to_jcc
[cond
], 0, dest
);
883 tcg_out_ext8u(s
, dest
, dest
);
886 #if TCG_TARGET_REG_BITS == 64
887 static void tcg_out_setcond64(TCGContext
*s
, TCGCond cond
, TCGArg dest
,
888 TCGArg arg1
, TCGArg arg2
, int const_arg2
)
890 tcg_out_cmp(s
, arg1
, arg2
, const_arg2
, P_REXW
);
891 tcg_out_modrm(s
, OPC_SETCC
| tcg_cond_to_jcc
[cond
], 0, dest
);
892 tcg_out_ext8u(s
, dest
, dest
);
895 static void tcg_out_setcond2(TCGContext
*s
, const TCGArg
*args
,
896 const int *const_args
)
899 int label_true
, label_over
;
901 memcpy(new_args
, args
+1, 5*sizeof(TCGArg
));
903 if (args
[0] == args
[1] || args
[0] == args
[2]
904 || (!const_args
[3] && args
[0] == args
[3])
905 || (!const_args
[4] && args
[0] == args
[4])) {
906 /* When the destination overlaps with one of the argument
907 registers, don't do anything tricky. */
908 label_true
= gen_new_label();
909 label_over
= gen_new_label();
911 new_args
[5] = label_true
;
912 tcg_out_brcond2(s
, new_args
, const_args
+1, 1);
914 tcg_out_movi(s
, TCG_TYPE_I32
, args
[0], 0);
915 tcg_out_jxx(s
, JCC_JMP
, label_over
, 1);
916 tcg_out_label(s
, label_true
, s
->code_ptr
);
918 tcg_out_movi(s
, TCG_TYPE_I32
, args
[0], 1);
919 tcg_out_label(s
, label_over
, s
->code_ptr
);
921 /* When the destination does not overlap one of the arguments,
922 clear the destination first, jump if cond false, and emit an
923 increment in the true case. This results in smaller code. */
925 tcg_out_movi(s
, TCG_TYPE_I32
, args
[0], 0);
927 label_over
= gen_new_label();
928 new_args
[4] = tcg_invert_cond(new_args
[4]);
929 new_args
[5] = label_over
;
930 tcg_out_brcond2(s
, new_args
, const_args
+1, 1);
932 tgen_arithi(s
, ARITH_ADD
, args
[0], 1, 0);
933 tcg_out_label(s
, label_over
, s
->code_ptr
);
938 static void tcg_out_branch(TCGContext
*s
, int call
, tcg_target_long dest
)
940 tcg_target_long disp
= dest
- (tcg_target_long
)s
->code_ptr
- 5;
942 if (disp
== (int32_t)disp
) {
943 tcg_out_opc(s
, call
? OPC_CALL_Jz
: OPC_JMP_long
, 0, 0, 0);
946 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_R10
, dest
);
947 tcg_out_modrm(s
, OPC_GRP5
,
948 call
? EXT5_CALLN_Ev
: EXT5_JMPN_Ev
, TCG_REG_R10
);
952 static inline void tcg_out_calli(TCGContext
*s
, tcg_target_long dest
)
954 tcg_out_branch(s
, 1, dest
);
957 static void tcg_out_jmp(TCGContext
*s
, tcg_target_long dest
)
959 tcg_out_branch(s
, 0, dest
);
962 #if defined(CONFIG_SOFTMMU)
964 #include "../../softmmu_defs.h"
966 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
968 static const void *qemu_ld_helpers
[4] = {
975 /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
976 uintxx_t val, int mmu_idx) */
977 static const void *qemu_st_helpers
[4] = {
984 /* Perform the TLB load and compare.
987 ADDRLO_IDX contains the index into ARGS of the low part of the
988 address; the high part of the address is at ADDR_LOW_IDX+1.
990 MEM_INDEX and S_BITS are the memory context and log2 size of the load.
992 WHICH is the offset into the CPUTLBEntry structure of the slot to read.
993 This should be offsetof addr_read or addr_write.
996 LABEL_PTRS is filled with 1 (32-bit addresses) or 2 (64-bit addresses)
997 positions of the displacements of forward jumps to the TLB miss case.
999 First argument register is loaded with the low part of the address.
1000 In the TLB hit case, it has been adjusted as indicated by the TLB
1001 and so is a host address. In the TLB miss case, it continues to
1002 hold a guest address.
1004 Second argument register is clobbered. */
1006 static inline void tcg_out_tlb_load(TCGContext
*s
, int addrlo_idx
,
1007 int mem_index
, int s_bits
,
1009 uint8_t **label_ptr
, int which
)
1011 const int addrlo
= args
[addrlo_idx
];
1012 const int r0
= tcg_target_call_iarg_regs
[0];
1013 const int r1
= tcg_target_call_iarg_regs
[1];
1014 TCGType type
= TCG_TYPE_I32
;
1017 if (TCG_TARGET_REG_BITS
== 64 && TARGET_LONG_BITS
== 64) {
1018 type
= TCG_TYPE_I64
;
1022 tcg_out_mov(s
, type
, r1
, addrlo
);
1023 tcg_out_mov(s
, type
, r0
, addrlo
);
1025 tcg_out_shifti(s
, SHIFT_SHR
+ rexw
, r1
,
1026 TARGET_PAGE_BITS
- CPU_TLB_ENTRY_BITS
);
1028 tgen_arithi(s
, ARITH_AND
+ rexw
, r0
,
1029 TARGET_PAGE_MASK
| ((1 << s_bits
) - 1), 0);
1030 tgen_arithi(s
, ARITH_AND
+ rexw
, r1
,
1031 (CPU_TLB_SIZE
- 1) << CPU_TLB_ENTRY_BITS
, 0);
1033 tcg_out_modrm_sib_offset(s
, OPC_LEA
+ P_REXW
, r1
, TCG_AREG0
, r1
, 0,
1034 offsetof(CPUArchState
, tlb_table
[mem_index
][0])
1038 tcg_out_modrm_offset(s
, OPC_CMP_GvEv
+ rexw
, r0
, r1
, 0);
1040 tcg_out_mov(s
, type
, r0
, addrlo
);
1043 tcg_out8(s
, OPC_JCC_short
+ JCC_JNE
);
1044 label_ptr
[0] = s
->code_ptr
;
1047 if (TARGET_LONG_BITS
> TCG_TARGET_REG_BITS
) {
1048 /* cmp 4(r1), addrhi */
1049 tcg_out_modrm_offset(s
, OPC_CMP_GvEv
, args
[addrlo_idx
+1], r1
, 4);
1052 tcg_out8(s
, OPC_JCC_short
+ JCC_JNE
);
1053 label_ptr
[1] = s
->code_ptr
;
1059 /* add addend(r1), r0 */
1060 tcg_out_modrm_offset(s
, OPC_ADD_GvEv
+ P_REXW
, r0
, r1
,
1061 offsetof(CPUTLBEntry
, addend
) - which
);
1065 static void tcg_out_qemu_ld_direct(TCGContext
*s
, int datalo
, int datahi
,
1066 int base
, tcg_target_long ofs
, int sizeop
)
1068 #ifdef TARGET_WORDS_BIGENDIAN
1069 const int bswap
= 1;
1071 const int bswap
= 0;
1075 tcg_out_modrm_offset(s
, OPC_MOVZBL
, datalo
, base
, ofs
);
1078 tcg_out_modrm_offset(s
, OPC_MOVSBL
+ P_REXW
, datalo
, base
, ofs
);
1081 tcg_out_modrm_offset(s
, OPC_MOVZWL
, datalo
, base
, ofs
);
1083 tcg_out_rolw_8(s
, datalo
);
1088 tcg_out_modrm_offset(s
, OPC_MOVZWL
, datalo
, base
, ofs
);
1089 tcg_out_rolw_8(s
, datalo
);
1090 tcg_out_modrm(s
, OPC_MOVSWL
+ P_REXW
, datalo
, datalo
);
1092 tcg_out_modrm_offset(s
, OPC_MOVSWL
+ P_REXW
, datalo
, base
, ofs
);
1096 tcg_out_ld(s
, TCG_TYPE_I32
, datalo
, base
, ofs
);
1098 tcg_out_bswap32(s
, datalo
);
1101 #if TCG_TARGET_REG_BITS == 64
1104 tcg_out_ld(s
, TCG_TYPE_I32
, datalo
, base
, ofs
);
1105 tcg_out_bswap32(s
, datalo
);
1106 tcg_out_ext32s(s
, datalo
, datalo
);
1108 tcg_out_modrm_offset(s
, OPC_MOVSLQ
, datalo
, base
, ofs
);
1113 if (TCG_TARGET_REG_BITS
== 64) {
1114 tcg_out_ld(s
, TCG_TYPE_I64
, datalo
, base
, ofs
);
1116 tcg_out_bswap64(s
, datalo
);
1124 if (base
!= datalo
) {
1125 tcg_out_ld(s
, TCG_TYPE_I32
, datalo
, base
, ofs
);
1126 tcg_out_ld(s
, TCG_TYPE_I32
, datahi
, base
, ofs
+ 4);
1128 tcg_out_ld(s
, TCG_TYPE_I32
, datahi
, base
, ofs
+ 4);
1129 tcg_out_ld(s
, TCG_TYPE_I32
, datalo
, base
, ofs
);
1132 tcg_out_bswap32(s
, datalo
);
1133 tcg_out_bswap32(s
, datahi
);
1142 /* XXX: qemu_ld and qemu_st could be modified to clobber only EDX and
1143 EAX. It will be useful once fixed registers globals are less
1145 static void tcg_out_qemu_ld(TCGContext
*s
, const TCGArg
*args
,
1148 int data_reg
, data_reg2
= 0;
1150 #if defined(CONFIG_SOFTMMU)
1151 int mem_index
, s_bits
;
1152 #if TCG_TARGET_REG_BITS == 64
1157 uint8_t *label_ptr
[3];
1162 if (TCG_TARGET_REG_BITS
== 32 && opc
== 3) {
1163 data_reg2
= args
[1];
1167 #if defined(CONFIG_SOFTMMU)
1168 mem_index
= args
[addrlo_idx
+ 1 + (TARGET_LONG_BITS
> TCG_TARGET_REG_BITS
)];
1171 tcg_out_tlb_load(s
, addrlo_idx
, mem_index
, s_bits
, args
,
1172 label_ptr
, offsetof(CPUTLBEntry
, addr_read
));
1175 tcg_out_qemu_ld_direct(s
, data_reg
, data_reg2
,
1176 tcg_target_call_iarg_regs
[0], 0, opc
);
1179 tcg_out8(s
, OPC_JMP_short
);
1180 label_ptr
[2] = s
->code_ptr
;
1186 *label_ptr
[0] = s
->code_ptr
- label_ptr
[0] - 1;
1187 if (TARGET_LONG_BITS
> TCG_TARGET_REG_BITS
) {
1188 *label_ptr
[1] = s
->code_ptr
- label_ptr
[1] - 1;
1191 /* XXX: move that code at the end of the TB */
1192 #if TCG_TARGET_REG_BITS == 32
1193 tcg_out_pushi(s
, mem_index
);
1195 if (TARGET_LONG_BITS
== 64) {
1196 tcg_out_push(s
, args
[addrlo_idx
+ 1]);
1199 tcg_out_push(s
, args
[addrlo_idx
]);
1201 tcg_out_push(s
, TCG_AREG0
);
1204 /* The first argument is already loaded with addrlo. */
1206 tcg_out_movi(s
, TCG_TYPE_I32
, tcg_target_call_iarg_regs
[arg_idx
],
1208 /* XXX/FIXME: suboptimal */
1209 tcg_out_mov(s
, TCG_TYPE_I64
, tcg_target_call_iarg_regs
[3],
1210 tcg_target_call_iarg_regs
[2]);
1211 tcg_out_mov(s
, TCG_TYPE_I64
, tcg_target_call_iarg_regs
[2],
1212 tcg_target_call_iarg_regs
[1]);
1213 tcg_out_mov(s
, TCG_TYPE_I64
, tcg_target_call_iarg_regs
[1],
1214 tcg_target_call_iarg_regs
[0]);
1215 tcg_out_mov(s
, TCG_TYPE_I64
, tcg_target_call_iarg_regs
[0],
1219 tcg_out_calli(s
, (tcg_target_long
)qemu_ld_helpers
[s_bits
]);
1221 #if TCG_TARGET_REG_BITS == 32
1222 if (stack_adjust
== (TCG_TARGET_REG_BITS
/ 8)) {
1223 /* Pop and discard. This is 2 bytes smaller than the add. */
1224 tcg_out_pop(s
, TCG_REG_ECX
);
1225 } else if (stack_adjust
!= 0) {
1226 tcg_out_addi(s
, TCG_REG_CALL_STACK
, stack_adjust
);
1232 tcg_out_ext8s(s
, data_reg
, TCG_REG_EAX
, P_REXW
);
1235 tcg_out_ext16s(s
, data_reg
, TCG_REG_EAX
, P_REXW
);
1238 tcg_out_ext8u(s
, data_reg
, TCG_REG_EAX
);
1241 tcg_out_ext16u(s
, data_reg
, TCG_REG_EAX
);
1244 tcg_out_mov(s
, TCG_TYPE_I32
, data_reg
, TCG_REG_EAX
);
1246 #if TCG_TARGET_REG_BITS == 64
1248 tcg_out_ext32s(s
, data_reg
, TCG_REG_EAX
);
1252 if (TCG_TARGET_REG_BITS
== 64) {
1253 tcg_out_mov(s
, TCG_TYPE_I64
, data_reg
, TCG_REG_RAX
);
1254 } else if (data_reg
== TCG_REG_EDX
) {
1255 /* xchg %edx, %eax */
1256 tcg_out_opc(s
, OPC_XCHG_ax_r32
+ TCG_REG_EDX
, 0, 0, 0);
1257 tcg_out_mov(s
, TCG_TYPE_I32
, data_reg2
, TCG_REG_EAX
);
1259 tcg_out_mov(s
, TCG_TYPE_I32
, data_reg
, TCG_REG_EAX
);
1260 tcg_out_mov(s
, TCG_TYPE_I32
, data_reg2
, TCG_REG_EDX
);
1268 *label_ptr
[2] = s
->code_ptr
- label_ptr
[2] - 1;
1271 int32_t offset
= GUEST_BASE
;
1272 int base
= args
[addrlo_idx
];
1274 if (TCG_TARGET_REG_BITS
== 64) {
1275 /* ??? We assume all operations have left us with register
1276 contents that are zero extended. So far this appears to
1277 be true. If we want to enforce this, we can either do
1278 an explicit zero-extension here, or (if GUEST_BASE == 0)
1279 use the ADDR32 prefix. For now, do nothing. */
1281 if (offset
!= GUEST_BASE
) {
1282 tcg_out_movi(s
, TCG_TYPE_I64
,
1283 tcg_target_call_iarg_regs
[0], GUEST_BASE
);
1284 tgen_arithr(s
, ARITH_ADD
+ P_REXW
,
1285 tcg_target_call_iarg_regs
[0], base
);
1286 base
= tcg_target_call_iarg_regs
[0];
1291 tcg_out_qemu_ld_direct(s
, data_reg
, data_reg2
, base
, offset
, opc
);
1296 static void tcg_out_qemu_st_direct(TCGContext
*s
, int datalo
, int datahi
,
1297 int base
, tcg_target_long ofs
, int sizeop
)
1299 #ifdef TARGET_WORDS_BIGENDIAN
1300 const int bswap
= 1;
1302 const int bswap
= 0;
1304 /* ??? Ideally we wouldn't need a scratch register. For user-only,
1305 we could perform the bswap twice to restore the original value
1306 instead of moving to the scratch. But as it is, the L constraint
1307 means that the second argument reg is definitely free here. */
1308 int scratch
= tcg_target_call_iarg_regs
[1];
1312 tcg_out_modrm_offset(s
, OPC_MOVB_EvGv
+ P_REXB_R
, datalo
, base
, ofs
);
1316 tcg_out_mov(s
, TCG_TYPE_I32
, scratch
, datalo
);
1317 tcg_out_rolw_8(s
, scratch
);
1320 tcg_out_modrm_offset(s
, OPC_MOVL_EvGv
+ P_DATA16
, datalo
, base
, ofs
);
1324 tcg_out_mov(s
, TCG_TYPE_I32
, scratch
, datalo
);
1325 tcg_out_bswap32(s
, scratch
);
1328 tcg_out_st(s
, TCG_TYPE_I32
, datalo
, base
, ofs
);
1331 if (TCG_TARGET_REG_BITS
== 64) {
1333 tcg_out_mov(s
, TCG_TYPE_I64
, scratch
, datalo
);
1334 tcg_out_bswap64(s
, scratch
);
1337 tcg_out_st(s
, TCG_TYPE_I64
, datalo
, base
, ofs
);
1339 tcg_out_mov(s
, TCG_TYPE_I32
, scratch
, datahi
);
1340 tcg_out_bswap32(s
, scratch
);
1341 tcg_out_st(s
, TCG_TYPE_I32
, scratch
, base
, ofs
);
1342 tcg_out_mov(s
, TCG_TYPE_I32
, scratch
, datalo
);
1343 tcg_out_bswap32(s
, scratch
);
1344 tcg_out_st(s
, TCG_TYPE_I32
, scratch
, base
, ofs
+ 4);
1346 tcg_out_st(s
, TCG_TYPE_I32
, datalo
, base
, ofs
);
1347 tcg_out_st(s
, TCG_TYPE_I32
, datahi
, base
, ofs
+ 4);
1355 static void tcg_out_qemu_st(TCGContext
*s
, const TCGArg
*args
,
1358 int data_reg
, data_reg2
= 0;
1360 #if defined(CONFIG_SOFTMMU)
1361 int mem_index
, s_bits
;
1363 uint8_t *label_ptr
[3];
1368 if (TCG_TARGET_REG_BITS
== 32 && opc
== 3) {
1369 data_reg2
= args
[1];
1373 #if defined(CONFIG_SOFTMMU)
1374 mem_index
= args
[addrlo_idx
+ 1 + (TARGET_LONG_BITS
> TCG_TARGET_REG_BITS
)];
1377 tcg_out_tlb_load(s
, addrlo_idx
, mem_index
, s_bits
, args
,
1378 label_ptr
, offsetof(CPUTLBEntry
, addr_write
));
1381 tcg_out_qemu_st_direct(s
, data_reg
, data_reg2
,
1382 tcg_target_call_iarg_regs
[0], 0, opc
);
1385 tcg_out8(s
, OPC_JMP_short
);
1386 label_ptr
[2] = s
->code_ptr
;
1392 *label_ptr
[0] = s
->code_ptr
- label_ptr
[0] - 1;
1393 if (TARGET_LONG_BITS
> TCG_TARGET_REG_BITS
) {
1394 *label_ptr
[1] = s
->code_ptr
- label_ptr
[1] - 1;
1397 /* XXX: move that code at the end of the TB */
1398 #if TCG_TARGET_REG_BITS == 32
1399 tcg_out_pushi(s
, mem_index
);
1402 tcg_out_push(s
, data_reg2
);
1405 tcg_out_push(s
, data_reg
);
1407 if (TARGET_LONG_BITS
== 64) {
1408 tcg_out_push(s
, args
[addrlo_idx
+ 1]);
1411 tcg_out_push(s
, args
[addrlo_idx
]);
1413 tcg_out_push(s
, TCG_AREG0
);
1416 tcg_out_mov(s
, (opc
== 3 ? TCG_TYPE_I64
: TCG_TYPE_I32
),
1417 tcg_target_call_iarg_regs
[1], data_reg
);
1418 tcg_out_movi(s
, TCG_TYPE_I32
, tcg_target_call_iarg_regs
[2], mem_index
);
1420 /* XXX/FIXME: suboptimal */
1421 tcg_out_mov(s
, TCG_TYPE_I64
, tcg_target_call_iarg_regs
[3],
1422 tcg_target_call_iarg_regs
[2]);
1423 tcg_out_mov(s
, TCG_TYPE_I64
, tcg_target_call_iarg_regs
[2],
1424 tcg_target_call_iarg_regs
[1]);
1425 tcg_out_mov(s
, TCG_TYPE_I64
, tcg_target_call_iarg_regs
[1],
1426 tcg_target_call_iarg_regs
[0]);
1427 tcg_out_mov(s
, TCG_TYPE_I64
, tcg_target_call_iarg_regs
[0],
1431 tcg_out_calli(s
, (tcg_target_long
)qemu_st_helpers
[s_bits
]);
1433 if (stack_adjust
== (TCG_TARGET_REG_BITS
/ 8)) {
1434 /* Pop and discard. This is 2 bytes smaller than the add. */
1435 tcg_out_pop(s
, TCG_REG_ECX
);
1436 } else if (stack_adjust
!= 0) {
1437 tcg_out_addi(s
, TCG_REG_CALL_STACK
, stack_adjust
);
1441 *label_ptr
[2] = s
->code_ptr
- label_ptr
[2] - 1;
1444 int32_t offset
= GUEST_BASE
;
1445 int base
= args
[addrlo_idx
];
1447 if (TCG_TARGET_REG_BITS
== 64) {
1448 /* ??? We assume all operations have left us with register
1449 contents that are zero extended. So far this appears to
1450 be true. If we want to enforce this, we can either do
1451 an explicit zero-extension here, or (if GUEST_BASE == 0)
1452 use the ADDR32 prefix. For now, do nothing. */
1454 if (offset
!= GUEST_BASE
) {
1455 tcg_out_movi(s
, TCG_TYPE_I64
,
1456 tcg_target_call_iarg_regs
[0], GUEST_BASE
);
1457 tgen_arithr(s
, ARITH_ADD
+ P_REXW
,
1458 tcg_target_call_iarg_regs
[0], base
);
1459 base
= tcg_target_call_iarg_regs
[0];
1464 tcg_out_qemu_st_direct(s
, data_reg
, data_reg2
, base
, offset
, opc
);
1469 static inline void tcg_out_op(TCGContext
*s
, TCGOpcode opc
,
1470 const TCGArg
*args
, const int *const_args
)
1474 #if TCG_TARGET_REG_BITS == 64
1475 # define OP_32_64(x) \
1476 case glue(glue(INDEX_op_, x), _i64): \
1477 rexw = P_REXW; /* FALLTHRU */ \
1478 case glue(glue(INDEX_op_, x), _i32)
1480 # define OP_32_64(x) \
1481 case glue(glue(INDEX_op_, x), _i32)
1485 case INDEX_op_exit_tb
:
1486 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_EAX
, args
[0]);
1487 tcg_out_jmp(s
, (tcg_target_long
) tb_ret_addr
);
1489 case INDEX_op_goto_tb
:
1490 if (s
->tb_jmp_offset
) {
1491 /* direct jump method */
1492 tcg_out8(s
, OPC_JMP_long
); /* jmp im */
1493 s
->tb_jmp_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
1496 /* indirect jump method */
1497 tcg_out_modrm_offset(s
, OPC_GRP5
, EXT5_JMPN_Ev
, -1,
1498 (tcg_target_long
)(s
->tb_next
+ args
[0]));
1500 s
->tb_next_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
1503 if (const_args
[0]) {
1504 tcg_out_calli(s
, args
[0]);
1507 tcg_out_modrm(s
, OPC_GRP5
, EXT5_CALLN_Ev
, args
[0]);
1511 if (const_args
[0]) {
1512 tcg_out_jmp(s
, args
[0]);
1515 tcg_out_modrm(s
, OPC_GRP5
, EXT5_JMPN_Ev
, args
[0]);
1519 tcg_out_jxx(s
, JCC_JMP
, args
[0], 0);
1521 case INDEX_op_movi_i32
:
1522 tcg_out_movi(s
, TCG_TYPE_I32
, args
[0], args
[1]);
1525 /* Note that we can ignore REXW for the zero-extend to 64-bit. */
1526 tcg_out_modrm_offset(s
, OPC_MOVZBL
, args
[0], args
[1], args
[2]);
1529 tcg_out_modrm_offset(s
, OPC_MOVSBL
+ rexw
, args
[0], args
[1], args
[2]);
1532 /* Note that we can ignore REXW for the zero-extend to 64-bit. */
1533 tcg_out_modrm_offset(s
, OPC_MOVZWL
, args
[0], args
[1], args
[2]);
1536 tcg_out_modrm_offset(s
, OPC_MOVSWL
+ rexw
, args
[0], args
[1], args
[2]);
1538 #if TCG_TARGET_REG_BITS == 64
1539 case INDEX_op_ld32u_i64
:
1541 case INDEX_op_ld_i32
:
1542 tcg_out_ld(s
, TCG_TYPE_I32
, args
[0], args
[1], args
[2]);
1546 tcg_out_modrm_offset(s
, OPC_MOVB_EvGv
| P_REXB_R
,
1547 args
[0], args
[1], args
[2]);
1550 tcg_out_modrm_offset(s
, OPC_MOVL_EvGv
| P_DATA16
,
1551 args
[0], args
[1], args
[2]);
1553 #if TCG_TARGET_REG_BITS == 64
1554 case INDEX_op_st32_i64
:
1556 case INDEX_op_st_i32
:
1557 tcg_out_st(s
, TCG_TYPE_I32
, args
[0], args
[1], args
[2]);
1561 /* For 3-operand addition, use LEA. */
1562 if (args
[0] != args
[1]) {
1563 TCGArg a0
= args
[0], a1
= args
[1], a2
= args
[2], c3
= 0;
1565 if (const_args
[2]) {
1567 } else if (a0
== a2
) {
1568 /* Watch out for dest = src + dest, since we've removed
1569 the matching constraint on the add. */
1570 tgen_arithr(s
, ARITH_ADD
+ rexw
, a0
, a1
);
1574 tcg_out_modrm_sib_offset(s
, OPC_LEA
+ rexw
, a0
, a1
, a2
, 0, c3
);
1592 if (const_args
[2]) {
1593 tgen_arithi(s
, c
+ rexw
, args
[0], args
[2], 0);
1595 tgen_arithr(s
, c
+ rexw
, args
[0], args
[2]);
1600 if (const_args
[2]) {
1603 if (val
== (int8_t)val
) {
1604 tcg_out_modrm(s
, OPC_IMUL_GvEvIb
+ rexw
, args
[0], args
[0]);
1607 tcg_out_modrm(s
, OPC_IMUL_GvEvIz
+ rexw
, args
[0], args
[0]);
1611 tcg_out_modrm(s
, OPC_IMUL_GvEv
+ rexw
, args
[0], args
[2]);
1616 tcg_out_modrm(s
, OPC_GRP3_Ev
+ rexw
, EXT3_IDIV
, args
[4]);
1619 tcg_out_modrm(s
, OPC_GRP3_Ev
+ rexw
, EXT3_DIV
, args
[4]);
1638 if (const_args
[2]) {
1639 tcg_out_shifti(s
, c
+ rexw
, args
[0], args
[2]);
1641 tcg_out_modrm(s
, OPC_SHIFT_cl
+ rexw
, c
, args
[0]);
1645 case INDEX_op_brcond_i32
:
1646 tcg_out_brcond32(s
, args
[2], args
[0], args
[1], const_args
[1],
1649 case INDEX_op_setcond_i32
:
1650 tcg_out_setcond32(s
, args
[3], args
[0], args
[1],
1651 args
[2], const_args
[2]);
1655 tcg_out_rolw_8(s
, args
[0]);
1658 tcg_out_bswap32(s
, args
[0]);
1662 tcg_out_modrm(s
, OPC_GRP3_Ev
+ rexw
, EXT3_NEG
, args
[0]);
1665 tcg_out_modrm(s
, OPC_GRP3_Ev
+ rexw
, EXT3_NOT
, args
[0]);
1669 tcg_out_ext8s(s
, args
[0], args
[1], rexw
);
1672 tcg_out_ext16s(s
, args
[0], args
[1], rexw
);
1675 tcg_out_ext8u(s
, args
[0], args
[1]);
1678 tcg_out_ext16u(s
, args
[0], args
[1]);
1681 case INDEX_op_qemu_ld8u
:
1682 tcg_out_qemu_ld(s
, args
, 0);
1684 case INDEX_op_qemu_ld8s
:
1685 tcg_out_qemu_ld(s
, args
, 0 | 4);
1687 case INDEX_op_qemu_ld16u
:
1688 tcg_out_qemu_ld(s
, args
, 1);
1690 case INDEX_op_qemu_ld16s
:
1691 tcg_out_qemu_ld(s
, args
, 1 | 4);
1693 #if TCG_TARGET_REG_BITS == 64
1694 case INDEX_op_qemu_ld32u
:
1696 case INDEX_op_qemu_ld32
:
1697 tcg_out_qemu_ld(s
, args
, 2);
1699 case INDEX_op_qemu_ld64
:
1700 tcg_out_qemu_ld(s
, args
, 3);
1703 case INDEX_op_qemu_st8
:
1704 tcg_out_qemu_st(s
, args
, 0);
1706 case INDEX_op_qemu_st16
:
1707 tcg_out_qemu_st(s
, args
, 1);
1709 case INDEX_op_qemu_st32
:
1710 tcg_out_qemu_st(s
, args
, 2);
1712 case INDEX_op_qemu_st64
:
1713 tcg_out_qemu_st(s
, args
, 3);
1716 #if TCG_TARGET_REG_BITS == 32
1717 case INDEX_op_brcond2_i32
:
1718 tcg_out_brcond2(s
, args
, const_args
, 0);
1720 case INDEX_op_setcond2_i32
:
1721 tcg_out_setcond2(s
, args
, const_args
);
1723 case INDEX_op_mulu2_i32
:
1724 tcg_out_modrm(s
, OPC_GRP3_Ev
, EXT3_MUL
, args
[3]);
1726 case INDEX_op_add2_i32
:
1727 if (const_args
[4]) {
1728 tgen_arithi(s
, ARITH_ADD
, args
[0], args
[4], 1);
1730 tgen_arithr(s
, ARITH_ADD
, args
[0], args
[4]);
1732 if (const_args
[5]) {
1733 tgen_arithi(s
, ARITH_ADC
, args
[1], args
[5], 1);
1735 tgen_arithr(s
, ARITH_ADC
, args
[1], args
[5]);
1738 case INDEX_op_sub2_i32
:
1739 if (const_args
[4]) {
1740 tgen_arithi(s
, ARITH_SUB
, args
[0], args
[4], 1);
1742 tgen_arithr(s
, ARITH_SUB
, args
[0], args
[4]);
1744 if (const_args
[5]) {
1745 tgen_arithi(s
, ARITH_SBB
, args
[1], args
[5], 1);
1747 tgen_arithr(s
, ARITH_SBB
, args
[1], args
[5]);
1750 #else /* TCG_TARGET_REG_BITS == 64 */
1751 case INDEX_op_movi_i64
:
1752 tcg_out_movi(s
, TCG_TYPE_I64
, args
[0], args
[1]);
1754 case INDEX_op_ld32s_i64
:
1755 tcg_out_modrm_offset(s
, OPC_MOVSLQ
, args
[0], args
[1], args
[2]);
1757 case INDEX_op_ld_i64
:
1758 tcg_out_ld(s
, TCG_TYPE_I64
, args
[0], args
[1], args
[2]);
1760 case INDEX_op_st_i64
:
1761 tcg_out_st(s
, TCG_TYPE_I64
, args
[0], args
[1], args
[2]);
1763 case INDEX_op_qemu_ld32s
:
1764 tcg_out_qemu_ld(s
, args
, 2 | 4);
1767 case INDEX_op_brcond_i64
:
1768 tcg_out_brcond64(s
, args
[2], args
[0], args
[1], const_args
[1],
1771 case INDEX_op_setcond_i64
:
1772 tcg_out_setcond64(s
, args
[3], args
[0], args
[1],
1773 args
[2], const_args
[2]);
1776 case INDEX_op_bswap64_i64
:
1777 tcg_out_bswap64(s
, args
[0]);
1779 case INDEX_op_ext32u_i64
:
1780 tcg_out_ext32u(s
, args
[0], args
[1]);
1782 case INDEX_op_ext32s_i64
:
1783 tcg_out_ext32s(s
, args
[0], args
[1]);
1788 if (args
[3] == 0 && args
[4] == 8) {
1789 /* load bits 0..7 */
1790 tcg_out_modrm(s
, OPC_MOVB_EvGv
| P_REXB_R
| P_REXB_RM
,
1792 } else if (args
[3] == 8 && args
[4] == 8) {
1793 /* load bits 8..15 */
1794 tcg_out_modrm(s
, OPC_MOVB_EvGv
, args
[2], args
[0] + 4);
1795 } else if (args
[3] == 0 && args
[4] == 16) {
1796 /* load bits 0..15 */
1797 tcg_out_modrm(s
, OPC_MOVL_EvGv
| P_DATA16
, args
[2], args
[0]);
1810 static const TCGTargetOpDef x86_op_defs
[] = {
1811 { INDEX_op_exit_tb
, { } },
1812 { INDEX_op_goto_tb
, { } },
1813 { INDEX_op_call
, { "ri" } },
1814 { INDEX_op_jmp
, { "ri" } },
1815 { INDEX_op_br
, { } },
1816 { INDEX_op_mov_i32
, { "r", "r" } },
1817 { INDEX_op_movi_i32
, { "r" } },
1818 { INDEX_op_ld8u_i32
, { "r", "r" } },
1819 { INDEX_op_ld8s_i32
, { "r", "r" } },
1820 { INDEX_op_ld16u_i32
, { "r", "r" } },
1821 { INDEX_op_ld16s_i32
, { "r", "r" } },
1822 { INDEX_op_ld_i32
, { "r", "r" } },
1823 { INDEX_op_st8_i32
, { "q", "r" } },
1824 { INDEX_op_st16_i32
, { "r", "r" } },
1825 { INDEX_op_st_i32
, { "r", "r" } },
1827 { INDEX_op_add_i32
, { "r", "r", "ri" } },
1828 { INDEX_op_sub_i32
, { "r", "0", "ri" } },
1829 { INDEX_op_mul_i32
, { "r", "0", "ri" } },
1830 { INDEX_op_div2_i32
, { "a", "d", "0", "1", "r" } },
1831 { INDEX_op_divu2_i32
, { "a", "d", "0", "1", "r" } },
1832 { INDEX_op_and_i32
, { "r", "0", "ri" } },
1833 { INDEX_op_or_i32
, { "r", "0", "ri" } },
1834 { INDEX_op_xor_i32
, { "r", "0", "ri" } },
1836 { INDEX_op_shl_i32
, { "r", "0", "ci" } },
1837 { INDEX_op_shr_i32
, { "r", "0", "ci" } },
1838 { INDEX_op_sar_i32
, { "r", "0", "ci" } },
1839 { INDEX_op_rotl_i32
, { "r", "0", "ci" } },
1840 { INDEX_op_rotr_i32
, { "r", "0", "ci" } },
1842 { INDEX_op_brcond_i32
, { "r", "ri" } },
1844 { INDEX_op_bswap16_i32
, { "r", "0" } },
1845 { INDEX_op_bswap32_i32
, { "r", "0" } },
1847 { INDEX_op_neg_i32
, { "r", "0" } },
1849 { INDEX_op_not_i32
, { "r", "0" } },
1851 { INDEX_op_ext8s_i32
, { "r", "q" } },
1852 { INDEX_op_ext16s_i32
, { "r", "r" } },
1853 { INDEX_op_ext8u_i32
, { "r", "q" } },
1854 { INDEX_op_ext16u_i32
, { "r", "r" } },
1856 { INDEX_op_setcond_i32
, { "q", "r", "ri" } },
1858 { INDEX_op_deposit_i32
, { "Q", "0", "Q" } },
1860 #if TCG_TARGET_REG_BITS == 32
1861 { INDEX_op_mulu2_i32
, { "a", "d", "a", "r" } },
1862 { INDEX_op_add2_i32
, { "r", "r", "0", "1", "ri", "ri" } },
1863 { INDEX_op_sub2_i32
, { "r", "r", "0", "1", "ri", "ri" } },
1864 { INDEX_op_brcond2_i32
, { "r", "r", "ri", "ri" } },
1865 { INDEX_op_setcond2_i32
, { "r", "r", "r", "ri", "ri" } },
1867 { INDEX_op_mov_i64
, { "r", "r" } },
1868 { INDEX_op_movi_i64
, { "r" } },
1869 { INDEX_op_ld8u_i64
, { "r", "r" } },
1870 { INDEX_op_ld8s_i64
, { "r", "r" } },
1871 { INDEX_op_ld16u_i64
, { "r", "r" } },
1872 { INDEX_op_ld16s_i64
, { "r", "r" } },
1873 { INDEX_op_ld32u_i64
, { "r", "r" } },
1874 { INDEX_op_ld32s_i64
, { "r", "r" } },
1875 { INDEX_op_ld_i64
, { "r", "r" } },
1876 { INDEX_op_st8_i64
, { "r", "r" } },
1877 { INDEX_op_st16_i64
, { "r", "r" } },
1878 { INDEX_op_st32_i64
, { "r", "r" } },
1879 { INDEX_op_st_i64
, { "r", "r" } },
1881 { INDEX_op_add_i64
, { "r", "0", "re" } },
1882 { INDEX_op_mul_i64
, { "r", "0", "re" } },
1883 { INDEX_op_div2_i64
, { "a", "d", "0", "1", "r" } },
1884 { INDEX_op_divu2_i64
, { "a", "d", "0", "1", "r" } },
1885 { INDEX_op_sub_i64
, { "r", "0", "re" } },
1886 { INDEX_op_and_i64
, { "r", "0", "reZ" } },
1887 { INDEX_op_or_i64
, { "r", "0", "re" } },
1888 { INDEX_op_xor_i64
, { "r", "0", "re" } },
1890 { INDEX_op_shl_i64
, { "r", "0", "ci" } },
1891 { INDEX_op_shr_i64
, { "r", "0", "ci" } },
1892 { INDEX_op_sar_i64
, { "r", "0", "ci" } },
1893 { INDEX_op_rotl_i64
, { "r", "0", "ci" } },
1894 { INDEX_op_rotr_i64
, { "r", "0", "ci" } },
1896 { INDEX_op_brcond_i64
, { "r", "re" } },
1897 { INDEX_op_setcond_i64
, { "r", "r", "re" } },
1899 { INDEX_op_bswap16_i64
, { "r", "0" } },
1900 { INDEX_op_bswap32_i64
, { "r", "0" } },
1901 { INDEX_op_bswap64_i64
, { "r", "0" } },
1902 { INDEX_op_neg_i64
, { "r", "0" } },
1903 { INDEX_op_not_i64
, { "r", "0" } },
1905 { INDEX_op_ext8s_i64
, { "r", "r" } },
1906 { INDEX_op_ext16s_i64
, { "r", "r" } },
1907 { INDEX_op_ext32s_i64
, { "r", "r" } },
1908 { INDEX_op_ext8u_i64
, { "r", "r" } },
1909 { INDEX_op_ext16u_i64
, { "r", "r" } },
1910 { INDEX_op_ext32u_i64
, { "r", "r" } },
1912 { INDEX_op_deposit_i64
, { "Q", "0", "Q" } },
1915 #if TCG_TARGET_REG_BITS == 64
1916 { INDEX_op_qemu_ld8u
, { "r", "L" } },
1917 { INDEX_op_qemu_ld8s
, { "r", "L" } },
1918 { INDEX_op_qemu_ld16u
, { "r", "L" } },
1919 { INDEX_op_qemu_ld16s
, { "r", "L" } },
1920 { INDEX_op_qemu_ld32
, { "r", "L" } },
1921 { INDEX_op_qemu_ld32u
, { "r", "L" } },
1922 { INDEX_op_qemu_ld32s
, { "r", "L" } },
1923 { INDEX_op_qemu_ld64
, { "r", "L" } },
1925 { INDEX_op_qemu_st8
, { "L", "L" } },
1926 { INDEX_op_qemu_st16
, { "L", "L" } },
1927 { INDEX_op_qemu_st32
, { "L", "L" } },
1928 { INDEX_op_qemu_st64
, { "L", "L" } },
1929 #elif TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
1930 { INDEX_op_qemu_ld8u
, { "r", "L" } },
1931 { INDEX_op_qemu_ld8s
, { "r", "L" } },
1932 { INDEX_op_qemu_ld16u
, { "r", "L" } },
1933 { INDEX_op_qemu_ld16s
, { "r", "L" } },
1934 { INDEX_op_qemu_ld32
, { "r", "L" } },
1935 { INDEX_op_qemu_ld64
, { "r", "r", "L" } },
1937 { INDEX_op_qemu_st8
, { "cb", "L" } },
1938 { INDEX_op_qemu_st16
, { "L", "L" } },
1939 { INDEX_op_qemu_st32
, { "L", "L" } },
1940 { INDEX_op_qemu_st64
, { "L", "L", "L" } },
1942 { INDEX_op_qemu_ld8u
, { "r", "L", "L" } },
1943 { INDEX_op_qemu_ld8s
, { "r", "L", "L" } },
1944 { INDEX_op_qemu_ld16u
, { "r", "L", "L" } },
1945 { INDEX_op_qemu_ld16s
, { "r", "L", "L" } },
1946 { INDEX_op_qemu_ld32
, { "r", "L", "L" } },
1947 { INDEX_op_qemu_ld64
, { "r", "r", "L", "L" } },
1949 { INDEX_op_qemu_st8
, { "cb", "L", "L" } },
1950 { INDEX_op_qemu_st16
, { "L", "L", "L" } },
1951 { INDEX_op_qemu_st32
, { "L", "L", "L" } },
1952 { INDEX_op_qemu_st64
, { "L", "L", "L", "L" } },
1957 static int tcg_target_callee_save_regs
[] = {
1958 #if TCG_TARGET_REG_BITS == 64
1967 TCG_REG_R14
, /* Currently used for the global env. */
1970 TCG_REG_EBP
, /* Currently used for the global env. */
1977 /* Compute frame size via macros, to share between tcg_target_qemu_prologue
1978 and tcg_register_jit. */
1981 ((1 + ARRAY_SIZE(tcg_target_callee_save_regs)) \
1982 * (TCG_TARGET_REG_BITS / 8))
1984 #define FRAME_SIZE \
1986 + TCG_STATIC_CALL_ARGS_SIZE \
1987 + CPU_TEMP_BUF_NLONGS * sizeof(long) \
1988 + TCG_TARGET_STACK_ALIGN - 1) \
1989 & ~(TCG_TARGET_STACK_ALIGN - 1))
1991 /* Generate global QEMU prologue and epilogue code */
1992 static void tcg_target_qemu_prologue(TCGContext
*s
)
1994 int i
, stack_addend
;
1998 /* Reserve some stack space, also for TCG temps. */
1999 stack_addend
= FRAME_SIZE
- PUSH_SIZE
;
2000 tcg_set_frame(s
, TCG_REG_CALL_STACK
, TCG_STATIC_CALL_ARGS_SIZE
,
2001 CPU_TEMP_BUF_NLONGS
* sizeof(long));
2003 /* Save all callee saved registers. */
2004 for (i
= 0; i
< ARRAY_SIZE(tcg_target_callee_save_regs
); i
++) {
2005 tcg_out_push(s
, tcg_target_callee_save_regs
[i
]);
2008 #if TCG_TARGET_REG_BITS == 32
2009 tcg_out_ld(s
, TCG_TYPE_PTR
, TCG_AREG0
, TCG_REG_ESP
,
2010 (ARRAY_SIZE(tcg_target_callee_save_regs
) + 1) * 4);
2011 tcg_out_ld(s
, TCG_TYPE_PTR
, tcg_target_call_iarg_regs
[1], TCG_REG_ESP
,
2012 (ARRAY_SIZE(tcg_target_callee_save_regs
) + 2) * 4);
2014 tcg_out_mov(s
, TCG_TYPE_PTR
, TCG_AREG0
, tcg_target_call_iarg_regs
[0]);
2016 tcg_out_addi(s
, TCG_REG_ESP
, -stack_addend
);
2019 tcg_out_modrm(s
, OPC_GRP5
, EXT5_JMPN_Ev
, tcg_target_call_iarg_regs
[1]);
2022 tb_ret_addr
= s
->code_ptr
;
2024 tcg_out_addi(s
, TCG_REG_CALL_STACK
, stack_addend
);
2026 for (i
= ARRAY_SIZE(tcg_target_callee_save_regs
) - 1; i
>= 0; i
--) {
2027 tcg_out_pop(s
, tcg_target_callee_save_regs
[i
]);
2029 tcg_out_opc(s
, OPC_RET
, 0, 0, 0);
2032 static void tcg_target_init(TCGContext
*s
)
2034 #if !defined(CONFIG_USER_ONLY)
2036 if ((1 << CPU_TLB_ENTRY_BITS
) != sizeof(CPUTLBEntry
))
2040 if (TCG_TARGET_REG_BITS
== 64) {
2041 tcg_regset_set32(tcg_target_available_regs
[TCG_TYPE_I32
], 0, 0xffff);
2042 tcg_regset_set32(tcg_target_available_regs
[TCG_TYPE_I64
], 0, 0xffff);
2044 tcg_regset_set32(tcg_target_available_regs
[TCG_TYPE_I32
], 0, 0xff);
2047 tcg_regset_clear(tcg_target_call_clobber_regs
);
2048 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_EAX
);
2049 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_EDX
);
2050 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_ECX
);
2051 if (TCG_TARGET_REG_BITS
== 64) {
2052 #if !defined(_WIN64)
2053 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_RDI
);
2054 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_RSI
);
2056 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R8
);
2057 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R9
);
2058 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R10
);
2059 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R11
);
2062 tcg_regset_clear(s
->reserved_regs
);
2063 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_CALL_STACK
);
2065 tcg_add_target_add_op_defs(x86_op_defs
);
2069 uint32_t len
__attribute__((aligned((sizeof(void *)))));
2072 char augmentation
[1];
2075 uint8_t return_column
;
2079 uint32_t len
__attribute__((aligned((sizeof(void *)))));
2080 uint32_t cie_offset
;
2081 tcg_target_long func_start
__attribute__((packed
));
2082 tcg_target_long func_len
__attribute__((packed
));
2084 uint8_t reg_ofs
[14];
2092 #if !defined(__ELF__)
2093 /* Host machine without ELF. */
2094 #elif TCG_TARGET_REG_BITS == 64
2095 #define ELF_HOST_MACHINE EM_X86_64
2096 static DebugFrame debug_frame
= {
2097 .cie
.len
= sizeof(DebugFrameCIE
)-4, /* length after .len member */
2100 .cie
.code_align
= 1,
2101 .cie
.data_align
= 0x78, /* sleb128 -8 */
2102 .cie
.return_column
= 16,
2104 .fde
.len
= sizeof(DebugFrameFDE
)-4, /* length after .len member */
2106 12, 7, /* DW_CFA_def_cfa %rsp, ... */
2107 (FRAME_SIZE
& 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2111 0x90, 1, /* DW_CFA_offset, %rip, -8 */
2112 /* The following ordering must match tcg_target_callee_save_regs. */
2113 0x86, 2, /* DW_CFA_offset, %rbp, -16 */
2114 0x83, 3, /* DW_CFA_offset, %rbx, -24 */
2115 0x8c, 4, /* DW_CFA_offset, %r12, -32 */
2116 0x8d, 5, /* DW_CFA_offset, %r13, -40 */
2117 0x8e, 6, /* DW_CFA_offset, %r14, -48 */
2118 0x8f, 7, /* DW_CFA_offset, %r15, -56 */
2122 #define ELF_HOST_MACHINE EM_386
2123 static DebugFrame debug_frame
= {
2124 .cie
.len
= sizeof(DebugFrameCIE
)-4, /* length after .len member */
2127 .cie
.code_align
= 1,
2128 .cie
.data_align
= 0x7c, /* sleb128 -4 */
2129 .cie
.return_column
= 8,
2131 .fde
.len
= sizeof(DebugFrameFDE
)-4, /* length after .len member */
2133 12, 4, /* DW_CFA_def_cfa %esp, ... */
2134 (FRAME_SIZE
& 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2138 0x88, 1, /* DW_CFA_offset, %eip, -4 */
2139 /* The following ordering must match tcg_target_callee_save_regs. */
2140 0x85, 2, /* DW_CFA_offset, %ebp, -8 */
2141 0x83, 3, /* DW_CFA_offset, %ebx, -12 */
2142 0x86, 4, /* DW_CFA_offset, %esi, -16 */
2143 0x87, 5, /* DW_CFA_offset, %edi, -20 */
2148 #if defined(ELF_HOST_MACHINE)
2149 void tcg_register_jit(void *buf
, size_t buf_size
)
2151 /* We're expecting a 2 byte uleb128 encoded value. */
2152 assert(FRAME_SIZE
>> 14 == 0);
2154 debug_frame
.fde
.func_start
= (tcg_target_long
) buf
;
2155 debug_frame
.fde
.func_len
= buf_size
;
2157 tcg_register_jit_int(buf
, buf_size
, &debug_frame
, sizeof(debug_frame
));