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tcg-ia64: Simplify brcond
[qemu.git] / tcg / ia64 / tcg-target.c
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2009-2010 Aurelien Jarno <aurelien@aurel32.net>
5 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
26 #include "tcg-be-null.h"
27
28 /*
29 * Register definitions
30 */
31
32 #ifndef NDEBUG
33 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
34 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
35 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
36 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
37 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
38 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
39 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
40 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
41 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
42 };
43 #endif
44
45 #ifdef CONFIG_USE_GUEST_BASE
46 #define TCG_GUEST_BASE_REG TCG_REG_R55
47 #else
48 #define TCG_GUEST_BASE_REG TCG_REG_R0
49 #endif
50 #ifndef GUEST_BASE
51 #define GUEST_BASE 0
52 #endif
53
54 /* Branch registers */
55 enum {
56 TCG_REG_B0 = 0,
57 TCG_REG_B1,
58 TCG_REG_B2,
59 TCG_REG_B3,
60 TCG_REG_B4,
61 TCG_REG_B5,
62 TCG_REG_B6,
63 TCG_REG_B7,
64 };
65
66 /* Floating point registers */
67 enum {
68 TCG_REG_F0 = 0,
69 TCG_REG_F1,
70 TCG_REG_F2,
71 TCG_REG_F3,
72 TCG_REG_F4,
73 TCG_REG_F5,
74 TCG_REG_F6,
75 TCG_REG_F7,
76 TCG_REG_F8,
77 TCG_REG_F9,
78 TCG_REG_F10,
79 TCG_REG_F11,
80 TCG_REG_F12,
81 TCG_REG_F13,
82 TCG_REG_F14,
83 TCG_REG_F15,
84 };
85
86 /* Predicate registers */
87 enum {
88 TCG_REG_P0 = 0,
89 TCG_REG_P1,
90 TCG_REG_P2,
91 TCG_REG_P3,
92 TCG_REG_P4,
93 TCG_REG_P5,
94 TCG_REG_P6,
95 TCG_REG_P7,
96 TCG_REG_P8,
97 TCG_REG_P9,
98 TCG_REG_P10,
99 TCG_REG_P11,
100 TCG_REG_P12,
101 TCG_REG_P13,
102 TCG_REG_P14,
103 TCG_REG_P15,
104 };
105
106 /* Application registers */
107 enum {
108 TCG_REG_PFS = 64,
109 };
110
111 static const int tcg_target_reg_alloc_order[] = {
112 TCG_REG_R33,
113 TCG_REG_R35,
114 TCG_REG_R36,
115 TCG_REG_R37,
116 TCG_REG_R38,
117 TCG_REG_R39,
118 TCG_REG_R40,
119 TCG_REG_R41,
120 TCG_REG_R42,
121 TCG_REG_R43,
122 TCG_REG_R44,
123 TCG_REG_R45,
124 TCG_REG_R46,
125 TCG_REG_R47,
126 TCG_REG_R48,
127 TCG_REG_R49,
128 TCG_REG_R50,
129 TCG_REG_R51,
130 TCG_REG_R52,
131 TCG_REG_R53,
132 TCG_REG_R54,
133 TCG_REG_R55,
134 TCG_REG_R14,
135 TCG_REG_R15,
136 TCG_REG_R16,
137 TCG_REG_R17,
138 TCG_REG_R18,
139 TCG_REG_R19,
140 TCG_REG_R20,
141 TCG_REG_R21,
142 TCG_REG_R22,
143 TCG_REG_R23,
144 TCG_REG_R24,
145 TCG_REG_R25,
146 TCG_REG_R26,
147 TCG_REG_R27,
148 TCG_REG_R28,
149 TCG_REG_R29,
150 TCG_REG_R30,
151 TCG_REG_R31,
152 TCG_REG_R56,
153 TCG_REG_R57,
154 TCG_REG_R58,
155 TCG_REG_R59,
156 TCG_REG_R60,
157 TCG_REG_R61,
158 TCG_REG_R62,
159 TCG_REG_R63,
160 TCG_REG_R8,
161 TCG_REG_R9,
162 TCG_REG_R10,
163 TCG_REG_R11
164 };
165
166 static const int tcg_target_call_iarg_regs[8] = {
167 TCG_REG_R56,
168 TCG_REG_R57,
169 TCG_REG_R58,
170 TCG_REG_R59,
171 TCG_REG_R60,
172 TCG_REG_R61,
173 TCG_REG_R62,
174 TCG_REG_R63,
175 };
176
177 static const int tcg_target_call_oarg_regs[] = {
178 TCG_REG_R8
179 };
180
181 /*
182 * opcode formation
183 */
184
185 /* bundle templates: stops (double bar in the IA64 manual) are marked with
186 an uppercase letter. */
187 enum {
188 mii = 0x00,
189 miI = 0x01,
190 mIi = 0x02,
191 mII = 0x03,
192 mlx = 0x04,
193 mLX = 0x05,
194 mmi = 0x08,
195 mmI = 0x09,
196 Mmi = 0x0a,
197 MmI = 0x0b,
198 mfi = 0x0c,
199 mfI = 0x0d,
200 mmf = 0x0e,
201 mmF = 0x0f,
202 mib = 0x10,
203 miB = 0x11,
204 mbb = 0x12,
205 mbB = 0x13,
206 bbb = 0x16,
207 bbB = 0x17,
208 mmb = 0x18,
209 mmB = 0x19,
210 mfb = 0x1c,
211 mfB = 0x1d,
212 };
213
214 enum {
215 OPC_ADD_A1 = 0x10000000000ull,
216 OPC_AND_A1 = 0x10060000000ull,
217 OPC_AND_A3 = 0x10160000000ull,
218 OPC_ANDCM_A1 = 0x10068000000ull,
219 OPC_ANDCM_A3 = 0x10168000000ull,
220 OPC_ADDS_A4 = 0x10800000000ull,
221 OPC_ADDL_A5 = 0x12000000000ull,
222 OPC_ALLOC_M34 = 0x02c00000000ull,
223 OPC_BR_DPTK_FEW_B1 = 0x08400000000ull,
224 OPC_BR_SPTK_MANY_B1 = 0x08000001000ull,
225 OPC_BR_SPTK_MANY_B4 = 0x00100001000ull,
226 OPC_BR_CALL_SPTK_MANY_B5 = 0x02100001000ull,
227 OPC_BR_RET_SPTK_MANY_B4 = 0x00108001100ull,
228 OPC_BRL_SPTK_MANY_X3 = 0x18000001000ull,
229 OPC_BRL_CALL_SPTK_MANY_X4 = 0x1a000001000ull,
230 OPC_CMP_LT_A6 = 0x18000000000ull,
231 OPC_CMP_LTU_A6 = 0x1a000000000ull,
232 OPC_CMP_EQ_A6 = 0x1c000000000ull,
233 OPC_CMP4_LT_A6 = 0x18400000000ull,
234 OPC_CMP4_LTU_A6 = 0x1a400000000ull,
235 OPC_CMP4_EQ_A6 = 0x1c400000000ull,
236 OPC_DEP_I14 = 0x0ae00000000ull,
237 OPC_DEP_I15 = 0x08000000000ull,
238 OPC_DEP_Z_I12 = 0x0a600000000ull,
239 OPC_EXTR_I11 = 0x0a400002000ull,
240 OPC_EXTR_U_I11 = 0x0a400000000ull,
241 OPC_FCVT_FX_TRUNC_S1_F10 = 0x004d0000000ull,
242 OPC_FCVT_FXU_TRUNC_S1_F10 = 0x004d8000000ull,
243 OPC_FCVT_XF_F11 = 0x000e0000000ull,
244 OPC_FMA_S1_F1 = 0x10400000000ull,
245 OPC_FNMA_S1_F1 = 0x18400000000ull,
246 OPC_FRCPA_S1_F6 = 0x00600000000ull,
247 OPC_GETF_SIG_M19 = 0x08708000000ull,
248 OPC_LD1_M1 = 0x08000000000ull,
249 OPC_LD1_M3 = 0x0a000000000ull,
250 OPC_LD2_M1 = 0x08040000000ull,
251 OPC_LD2_M3 = 0x0a040000000ull,
252 OPC_LD4_M1 = 0x08080000000ull,
253 OPC_LD4_M3 = 0x0a080000000ull,
254 OPC_LD8_M1 = 0x080c0000000ull,
255 OPC_LD8_M3 = 0x0a0c0000000ull,
256 OPC_MUX1_I3 = 0x0eca0000000ull,
257 OPC_NOP_B9 = 0x04008000000ull,
258 OPC_NOP_F16 = 0x00008000000ull,
259 OPC_NOP_I18 = 0x00008000000ull,
260 OPC_NOP_M48 = 0x00008000000ull,
261 OPC_MOV_I21 = 0x00e00100000ull,
262 OPC_MOV_RET_I21 = 0x00e00500000ull,
263 OPC_MOV_I22 = 0x00188000000ull,
264 OPC_MOV_I_I26 = 0x00150000000ull,
265 OPC_MOVL_X2 = 0x0c000000000ull,
266 OPC_OR_A1 = 0x10070000000ull,
267 OPC_SETF_EXP_M18 = 0x0c748000000ull,
268 OPC_SETF_SIG_M18 = 0x0c708000000ull,
269 OPC_SHL_I7 = 0x0f240000000ull,
270 OPC_SHR_I5 = 0x0f220000000ull,
271 OPC_SHR_U_I5 = 0x0f200000000ull,
272 OPC_SHRP_I10 = 0x0ac00000000ull,
273 OPC_SXT1_I29 = 0x000a0000000ull,
274 OPC_SXT2_I29 = 0x000a8000000ull,
275 OPC_SXT4_I29 = 0x000b0000000ull,
276 OPC_ST1_M4 = 0x08c00000000ull,
277 OPC_ST2_M4 = 0x08c40000000ull,
278 OPC_ST4_M4 = 0x08c80000000ull,
279 OPC_ST8_M4 = 0x08cc0000000ull,
280 OPC_SUB_A1 = 0x10028000000ull,
281 OPC_SUB_A3 = 0x10128000000ull,
282 OPC_UNPACK4_L_I2 = 0x0f860000000ull,
283 OPC_XMA_L_F2 = 0x1d000000000ull,
284 OPC_XOR_A1 = 0x10078000000ull,
285 OPC_ZXT1_I29 = 0x00080000000ull,
286 OPC_ZXT2_I29 = 0x00088000000ull,
287 OPC_ZXT4_I29 = 0x00090000000ull,
288
289 INSN_NOP_M = OPC_NOP_M48, /* nop.m 0 */
290 INSN_NOP_I = OPC_NOP_I18, /* nop.i 0 */
291 };
292
293 static inline uint64_t tcg_opc_a1(int qp, uint64_t opc, int r1,
294 int r2, int r3)
295 {
296 return opc
297 | ((r3 & 0x7f) << 20)
298 | ((r2 & 0x7f) << 13)
299 | ((r1 & 0x7f) << 6)
300 | (qp & 0x3f);
301 }
302
303 static inline uint64_t tcg_opc_a3(int qp, uint64_t opc, int r1,
304 uint64_t imm, int r3)
305 {
306 return opc
307 | ((imm & 0x80) << 29) /* s */
308 | ((imm & 0x7f) << 13) /* imm7b */
309 | ((r3 & 0x7f) << 20)
310 | ((r1 & 0x7f) << 6)
311 | (qp & 0x3f);
312 }
313
314 static inline uint64_t tcg_opc_a4(int qp, uint64_t opc, int r1,
315 uint64_t imm, int r3)
316 {
317 return opc
318 | ((imm & 0x2000) << 23) /* s */
319 | ((imm & 0x1f80) << 20) /* imm6d */
320 | ((imm & 0x007f) << 13) /* imm7b */
321 | ((r3 & 0x7f) << 20)
322 | ((r1 & 0x7f) << 6)
323 | (qp & 0x3f);
324 }
325
326 static inline uint64_t tcg_opc_a5(int qp, uint64_t opc, int r1,
327 uint64_t imm, int r3)
328 {
329 return opc
330 | ((imm & 0x200000) << 15) /* s */
331 | ((imm & 0x1f0000) << 6) /* imm5c */
332 | ((imm & 0x00ff80) << 20) /* imm9d */
333 | ((imm & 0x00007f) << 13) /* imm7b */
334 | ((r3 & 0x03) << 20)
335 | ((r1 & 0x7f) << 6)
336 | (qp & 0x3f);
337 }
338
339 static inline uint64_t tcg_opc_a6(int qp, uint64_t opc, int p1,
340 int p2, int r2, int r3)
341 {
342 return opc
343 | ((p2 & 0x3f) << 27)
344 | ((r3 & 0x7f) << 20)
345 | ((r2 & 0x7f) << 13)
346 | ((p1 & 0x3f) << 6)
347 | (qp & 0x3f);
348 }
349
350 static inline uint64_t tcg_opc_b1(int qp, uint64_t opc, uint64_t imm)
351 {
352 return opc
353 | ((imm & 0x100000) << 16) /* s */
354 | ((imm & 0x0fffff) << 13) /* imm20b */
355 | (qp & 0x3f);
356 }
357
358 static inline uint64_t tcg_opc_b4(int qp, uint64_t opc, int b2)
359 {
360 return opc
361 | ((b2 & 0x7) << 13)
362 | (qp & 0x3f);
363 }
364
365 static inline uint64_t tcg_opc_b5(int qp, uint64_t opc, int b1, int b2)
366 {
367 return opc
368 | ((b2 & 0x7) << 13)
369 | ((b1 & 0x7) << 6)
370 | (qp & 0x3f);
371 }
372
373
374 static inline uint64_t tcg_opc_b9(int qp, uint64_t opc, uint64_t imm)
375 {
376 return opc
377 | ((imm & 0x100000) << 16) /* i */
378 | ((imm & 0x0fffff) << 6) /* imm20a */
379 | (qp & 0x3f);
380 }
381
382 static inline uint64_t tcg_opc_f1(int qp, uint64_t opc, int f1,
383 int f3, int f4, int f2)
384 {
385 return opc
386 | ((f4 & 0x7f) << 27)
387 | ((f3 & 0x7f) << 20)
388 | ((f2 & 0x7f) << 13)
389 | ((f1 & 0x7f) << 6)
390 | (qp & 0x3f);
391 }
392
393 static inline uint64_t tcg_opc_f2(int qp, uint64_t opc, int f1,
394 int f3, int f4, int f2)
395 {
396 return opc
397 | ((f4 & 0x7f) << 27)
398 | ((f3 & 0x7f) << 20)
399 | ((f2 & 0x7f) << 13)
400 | ((f1 & 0x7f) << 6)
401 | (qp & 0x3f);
402 }
403
404 static inline uint64_t tcg_opc_f6(int qp, uint64_t opc, int f1,
405 int p2, int f2, int f3)
406 {
407 return opc
408 | ((p2 & 0x3f) << 27)
409 | ((f3 & 0x7f) << 20)
410 | ((f2 & 0x7f) << 13)
411 | ((f1 & 0x7f) << 6)
412 | (qp & 0x3f);
413 }
414
415 static inline uint64_t tcg_opc_f10(int qp, uint64_t opc, int f1, int f2)
416 {
417 return opc
418 | ((f2 & 0x7f) << 13)
419 | ((f1 & 0x7f) << 6)
420 | (qp & 0x3f);
421 }
422
423 static inline uint64_t tcg_opc_f11(int qp, uint64_t opc, int f1, int f2)
424 {
425 return opc
426 | ((f2 & 0x7f) << 13)
427 | ((f1 & 0x7f) << 6)
428 | (qp & 0x3f);
429 }
430
431 static inline uint64_t tcg_opc_f16(int qp, uint64_t opc, uint64_t imm)
432 {
433 return opc
434 | ((imm & 0x100000) << 16) /* i */
435 | ((imm & 0x0fffff) << 6) /* imm20a */
436 | (qp & 0x3f);
437 }
438
439 static inline uint64_t tcg_opc_i2(int qp, uint64_t opc, int r1,
440 int r2, int r3)
441 {
442 return opc
443 | ((r3 & 0x7f) << 20)
444 | ((r2 & 0x7f) << 13)
445 | ((r1 & 0x7f) << 6)
446 | (qp & 0x3f);
447 }
448
449 static inline uint64_t tcg_opc_i3(int qp, uint64_t opc, int r1,
450 int r2, int mbtype)
451 {
452 return opc
453 | ((mbtype & 0x0f) << 20)
454 | ((r2 & 0x7f) << 13)
455 | ((r1 & 0x7f) << 6)
456 | (qp & 0x3f);
457 }
458
459 static inline uint64_t tcg_opc_i5(int qp, uint64_t opc, int r1,
460 int r3, int r2)
461 {
462 return opc
463 | ((r3 & 0x7f) << 20)
464 | ((r2 & 0x7f) << 13)
465 | ((r1 & 0x7f) << 6)
466 | (qp & 0x3f);
467 }
468
469 static inline uint64_t tcg_opc_i7(int qp, uint64_t opc, int r1,
470 int r2, int r3)
471 {
472 return opc
473 | ((r3 & 0x7f) << 20)
474 | ((r2 & 0x7f) << 13)
475 | ((r1 & 0x7f) << 6)
476 | (qp & 0x3f);
477 }
478
479 static inline uint64_t tcg_opc_i10(int qp, uint64_t opc, int r1,
480 int r2, int r3, uint64_t count)
481 {
482 return opc
483 | ((count & 0x3f) << 27)
484 | ((r3 & 0x7f) << 20)
485 | ((r2 & 0x7f) << 13)
486 | ((r1 & 0x7f) << 6)
487 | (qp & 0x3f);
488 }
489
490 static inline uint64_t tcg_opc_i11(int qp, uint64_t opc, int r1,
491 int r3, uint64_t pos, uint64_t len)
492 {
493 return opc
494 | ((len & 0x3f) << 27)
495 | ((r3 & 0x7f) << 20)
496 | ((pos & 0x3f) << 14)
497 | ((r1 & 0x7f) << 6)
498 | (qp & 0x3f);
499 }
500
501 static inline uint64_t tcg_opc_i12(int qp, uint64_t opc, int r1,
502 int r2, uint64_t pos, uint64_t len)
503 {
504 return opc
505 | ((len & 0x3f) << 27)
506 | ((pos & 0x3f) << 20)
507 | ((r2 & 0x7f) << 13)
508 | ((r1 & 0x7f) << 6)
509 | (qp & 0x3f);
510 }
511
512 static inline uint64_t tcg_opc_i14(int qp, uint64_t opc, int r1, uint64_t imm,
513 int r3, uint64_t pos, uint64_t len)
514 {
515 return opc
516 | ((imm & 0x01) << 36)
517 | ((len & 0x3f) << 27)
518 | ((r3 & 0x7f) << 20)
519 | ((pos & 0x3f) << 14)
520 | ((r1 & 0x7f) << 6)
521 | (qp & 0x3f);
522 }
523
524 static inline uint64_t tcg_opc_i15(int qp, uint64_t opc, int r1, int r2,
525 int r3, uint64_t pos, uint64_t len)
526 {
527 return opc
528 | ((pos & 0x3f) << 31)
529 | ((len & 0x0f) << 27)
530 | ((r3 & 0x7f) << 20)
531 | ((r2 & 0x7f) << 13)
532 | ((r1 & 0x7f) << 6)
533 | (qp & 0x3f);
534 }
535
536 static inline uint64_t tcg_opc_i18(int qp, uint64_t opc, uint64_t imm)
537 {
538 return opc
539 | ((imm & 0x100000) << 16) /* i */
540 | ((imm & 0x0fffff) << 6) /* imm20a */
541 | (qp & 0x3f);
542 }
543
544 static inline uint64_t tcg_opc_i21(int qp, uint64_t opc, int b1,
545 int r2, uint64_t imm)
546 {
547 return opc
548 | ((imm & 0x1ff) << 24)
549 | ((r2 & 0x7f) << 13)
550 | ((b1 & 0x7) << 6)
551 | (qp & 0x3f);
552 }
553
554 static inline uint64_t tcg_opc_i22(int qp, uint64_t opc, int r1, int b2)
555 {
556 return opc
557 | ((b2 & 0x7) << 13)
558 | ((r1 & 0x7f) << 6)
559 | (qp & 0x3f);
560 }
561
562 static inline uint64_t tcg_opc_i26(int qp, uint64_t opc, int ar3, int r2)
563 {
564 return opc
565 | ((ar3 & 0x7f) << 20)
566 | ((r2 & 0x7f) << 13)
567 | (qp & 0x3f);
568 }
569
570 static inline uint64_t tcg_opc_i29(int qp, uint64_t opc, int r1, int r3)
571 {
572 return opc
573 | ((r3 & 0x7f) << 20)
574 | ((r1 & 0x7f) << 6)
575 | (qp & 0x3f);
576 }
577
578 static inline uint64_t tcg_opc_l2(uint64_t imm)
579 {
580 return (imm & 0x7fffffffffc00000ull) >> 22;
581 }
582
583 static inline uint64_t tcg_opc_l3(uint64_t imm)
584 {
585 return (imm & 0x07fffffffff00000ull) >> 18;
586 }
587
588 #define tcg_opc_l4 tcg_opc_l3
589
590 static inline uint64_t tcg_opc_m1(int qp, uint64_t opc, int r1, int r3)
591 {
592 return opc
593 | ((r3 & 0x7f) << 20)
594 | ((r1 & 0x7f) << 6)
595 | (qp & 0x3f);
596 }
597
598 static inline uint64_t tcg_opc_m3(int qp, uint64_t opc, int r1,
599 int r3, uint64_t imm)
600 {
601 return opc
602 | ((imm & 0x100) << 28) /* s */
603 | ((imm & 0x080) << 20) /* i */
604 | ((imm & 0x07f) << 13) /* imm7b */
605 | ((r3 & 0x7f) << 20)
606 | ((r1 & 0x7f) << 6)
607 | (qp & 0x3f);
608 }
609
610 static inline uint64_t tcg_opc_m4(int qp, uint64_t opc, int r2, int r3)
611 {
612 return opc
613 | ((r3 & 0x7f) << 20)
614 | ((r2 & 0x7f) << 13)
615 | (qp & 0x3f);
616 }
617
618 static inline uint64_t tcg_opc_m18(int qp, uint64_t opc, int f1, int r2)
619 {
620 return opc
621 | ((r2 & 0x7f) << 13)
622 | ((f1 & 0x7f) << 6)
623 | (qp & 0x3f);
624 }
625
626 static inline uint64_t tcg_opc_m19(int qp, uint64_t opc, int r1, int f2)
627 {
628 return opc
629 | ((f2 & 0x7f) << 13)
630 | ((r1 & 0x7f) << 6)
631 | (qp & 0x3f);
632 }
633
634 static inline uint64_t tcg_opc_m34(int qp, uint64_t opc, int r1,
635 int sof, int sol, int sor)
636 {
637 return opc
638 | ((sor & 0x0f) << 27)
639 | ((sol & 0x7f) << 20)
640 | ((sof & 0x7f) << 13)
641 | ((r1 & 0x7f) << 6)
642 | (qp & 0x3f);
643 }
644
645 static inline uint64_t tcg_opc_m48(int qp, uint64_t opc, uint64_t imm)
646 {
647 return opc
648 | ((imm & 0x100000) << 16) /* i */
649 | ((imm & 0x0fffff) << 6) /* imm20a */
650 | (qp & 0x3f);
651 }
652
653 static inline uint64_t tcg_opc_x2(int qp, uint64_t opc,
654 int r1, uint64_t imm)
655 {
656 return opc
657 | ((imm & 0x8000000000000000ull) >> 27) /* i */
658 | (imm & 0x0000000000200000ull) /* ic */
659 | ((imm & 0x00000000001f0000ull) << 6) /* imm5c */
660 | ((imm & 0x000000000000ff80ull) << 20) /* imm9d */
661 | ((imm & 0x000000000000007full) << 13) /* imm7b */
662 | ((r1 & 0x7f) << 6)
663 | (qp & 0x3f);
664 }
665
666 static inline uint64_t tcg_opc_x3(int qp, uint64_t opc, uint64_t imm)
667 {
668 return opc
669 | ((imm & 0x0800000000000000ull) >> 23) /* i */
670 | ((imm & 0x00000000000fffffull) << 13) /* imm20b */
671 | (qp & 0x3f);
672 }
673
674 static inline uint64_t tcg_opc_x4(int qp, uint64_t opc, int b1, uint64_t imm)
675 {
676 return opc
677 | ((imm & 0x0800000000000000ull) >> 23) /* i */
678 | ((imm & 0x00000000000fffffull) << 13) /* imm20b */
679 | ((b1 & 0x7) << 6)
680 | (qp & 0x3f);
681 }
682
683
684 /*
685 * Relocations
686 */
687
688 static inline void reloc_pcrel21b(void *pc, intptr_t target)
689 {
690 uint64_t imm;
691 int64_t disp;
692 int slot;
693
694 slot = (intptr_t)pc & 3;
695 pc = (void *)((intptr_t)pc & ~3);
696
697 disp = target - (intptr_t)pc;
698 imm = (uint64_t) disp >> 4;
699
700 switch(slot) {
701 case 0:
702 *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 8) & 0xfffffdc00003ffffull)
703 | ((imm & 0x100000) << 21) /* s */
704 | ((imm & 0x0fffff) << 18); /* imm20b */
705 break;
706 case 1:
707 *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xfffffffffffb8000ull)
708 | ((imm & 0x100000) >> 2) /* s */
709 | ((imm & 0x0fffe0) >> 5); /* imm20b */
710 *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 0) & 0x07ffffffffffffffull)
711 | ((imm & 0x00001f) << 59); /* imm20b */
712 break;
713 case 2:
714 *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xf700000fffffffffull)
715 | ((imm & 0x100000) << 39) /* s */
716 | ((imm & 0x0fffff) << 36); /* imm20b */
717 break;
718 }
719 }
720
721 static inline uint64_t get_reloc_pcrel21b (void *pc)
722 {
723 int64_t low, high;
724 int slot;
725
726 slot = (tcg_target_long) pc & 3;
727 pc = (void *)((tcg_target_long) pc & ~3);
728
729 low = (*(uint64_t *)(pc + 0));
730 high = (*(uint64_t *)(pc + 8));
731
732 switch(slot) {
733 case 0:
734 return ((low >> 21) & 0x100000) + /* s */
735 ((low >> 18) & 0x0fffff); /* imm20b */
736 case 1:
737 return ((high << 2) & 0x100000) + /* s */
738 ((high << 5) & 0x0fffe0) + /* imm20b */
739 ((low >> 59) & 0x00001f); /* imm20b */
740 case 2:
741 return ((high >> 39) & 0x100000) + /* s */
742 ((high >> 36) & 0x0fffff); /* imm20b */
743 default:
744 tcg_abort();
745 }
746 }
747
748 static inline void reloc_pcrel60b(void *pc, intptr_t target)
749 {
750 int64_t disp;
751 uint64_t imm;
752
753 disp = target - (intptr_t)pc;
754 imm = (uint64_t) disp >> 4;
755
756 *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xf700000fff800000ull)
757 | (imm & 0x0800000000000000ull) /* s */
758 | ((imm & 0x07fffff000000000ull) >> 36) /* imm39 */
759 | ((imm & 0x00000000000fffffull) << 36); /* imm20b */
760 *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 0) & 0x00003fffffffffffull)
761 | ((imm & 0x0000000ffff00000ull) << 28); /* imm39 */
762 }
763
764 static inline uint64_t get_reloc_pcrel60b (void *pc)
765 {
766 int64_t low, high;
767
768 low = (*(uint64_t *)(pc + 0));
769 high = (*(uint64_t *)(pc + 8));
770
771 return ((high) & 0x0800000000000000ull) + /* s */
772 ((high >> 36) & 0x00000000000fffffull) + /* imm20b */
773 ((high << 36) & 0x07fffff000000000ull) + /* imm39 */
774 ((low >> 28) & 0x0000000ffff00000ull); /* imm39 */
775 }
776
777
778 static void patch_reloc(uint8_t *code_ptr, int type,
779 intptr_t value, intptr_t addend)
780 {
781 value += addend;
782 switch (type) {
783 case R_IA64_PCREL21B:
784 reloc_pcrel21b(code_ptr, value);
785 break;
786 case R_IA64_PCREL60B:
787 reloc_pcrel60b(code_ptr, value);
788 default:
789 tcg_abort();
790 }
791 }
792
793 /*
794 * Constraints
795 */
796
797 /* parse target specific constraints */
798 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
799 {
800 const char *ct_str;
801
802 ct_str = *pct_str;
803 switch(ct_str[0]) {
804 case 'r':
805 ct->ct |= TCG_CT_REG;
806 tcg_regset_set(ct->u.regs, 0xffffffffffffffffull);
807 break;
808 case 'I':
809 ct->ct |= TCG_CT_CONST_S22;
810 break;
811 case 'S':
812 ct->ct |= TCG_CT_REG;
813 tcg_regset_set(ct->u.regs, 0xffffffffffffffffull);
814 #if defined(CONFIG_SOFTMMU)
815 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R56);
816 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R57);
817 #endif
818 break;
819 case 'Z':
820 /* We are cheating a bit here, using the fact that the register
821 r0 is also the register number 0. Hence there is no need
822 to check for const_args in each instruction. */
823 ct->ct |= TCG_CT_CONST_ZERO;
824 break;
825 default:
826 return -1;
827 }
828 ct_str++;
829 *pct_str = ct_str;
830 return 0;
831 }
832
833 /* test if a constant matches the constraint */
834 static inline int tcg_target_const_match(tcg_target_long val,
835 const TCGArgConstraint *arg_ct)
836 {
837 int ct;
838 ct = arg_ct->ct;
839 if (ct & TCG_CT_CONST)
840 return 1;
841 else if ((ct & TCG_CT_CONST_ZERO) && val == 0)
842 return 1;
843 else if ((ct & TCG_CT_CONST_S22) && val == ((int32_t)val << 10) >> 10)
844 return 1;
845 else
846 return 0;
847 }
848
849 /*
850 * Code generation
851 */
852
853 static uint8_t *tb_ret_addr;
854
855 static inline void tcg_out_bundle(TCGContext *s, int template,
856 uint64_t slot0, uint64_t slot1,
857 uint64_t slot2)
858 {
859 template &= 0x1f; /* 5 bits */
860 slot0 &= 0x1ffffffffffull; /* 41 bits */
861 slot1 &= 0x1ffffffffffull; /* 41 bits */
862 slot2 &= 0x1ffffffffffull; /* 41 bits */
863
864 *(uint64_t *)(s->code_ptr + 0) = (slot1 << 46) | (slot0 << 5) | template;
865 *(uint64_t *)(s->code_ptr + 8) = (slot2 << 23) | (slot1 >> 18);
866 s->code_ptr += 16;
867 }
868
869 static inline void tcg_out_mov(TCGContext *s, TCGType type,
870 TCGReg ret, TCGReg arg)
871 {
872 tcg_out_bundle(s, mmI,
873 INSN_NOP_M,
874 INSN_NOP_M,
875 tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, ret, 0, arg));
876 }
877
878 static inline void tcg_out_movi(TCGContext *s, TCGType type,
879 TCGReg reg, tcg_target_long arg)
880 {
881 tcg_out_bundle(s, mLX,
882 INSN_NOP_M,
883 tcg_opc_l2 (arg),
884 tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2, reg, arg));
885 }
886
887 static void tcg_out_br(TCGContext *s, int label_index)
888 {
889 TCGLabel *l = &s->labels[label_index];
890
891 /* We pay attention here to not modify the branch target by reading
892 the existing value and using it again. This ensure that caches and
893 memory are kept coherent during retranslation. */
894 tcg_out_bundle(s, mmB,
895 INSN_NOP_M,
896 INSN_NOP_M,
897 tcg_opc_b1 (TCG_REG_P0, OPC_BR_SPTK_MANY_B1,
898 get_reloc_pcrel21b(s->code_ptr + 2)));
899
900 if (l->has_value) {
901 reloc_pcrel21b((s->code_ptr - 16) + 2, l->u.value);
902 } else {
903 tcg_out_reloc(s, (s->code_ptr - 16) + 2,
904 R_IA64_PCREL21B, label_index, 0);
905 }
906 }
907
908 static inline void tcg_out_calli(TCGContext *s, uintptr_t addr)
909 {
910 /* Look through the function descriptor. */
911 uintptr_t disp, *desc = (uintptr_t *)addr;
912 tcg_out_bundle(s, mlx,
913 INSN_NOP_M,
914 tcg_opc_l2 (desc[1]),
915 tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2, TCG_REG_R1, desc[1]));
916 disp = (desc[0] - (uintptr_t)s->code_ptr) >> 4;
917 tcg_out_bundle(s, mLX,
918 INSN_NOP_M,
919 tcg_opc_l4 (disp),
920 tcg_opc_x4 (TCG_REG_P0, OPC_BRL_CALL_SPTK_MANY_X4,
921 TCG_REG_B0, disp));
922 }
923
924 static inline void tcg_out_callr(TCGContext *s, TCGReg addr)
925 {
926 tcg_out_bundle(s, MmI,
927 tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, TCG_REG_R2, addr),
928 tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4, TCG_REG_R3, 8, addr),
929 tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21,
930 TCG_REG_B6, TCG_REG_R2, 0));
931 tcg_out_bundle(s, mmB,
932 tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R3),
933 INSN_NOP_M,
934 tcg_opc_b5 (TCG_REG_P0, OPC_BR_CALL_SPTK_MANY_B5,
935 TCG_REG_B0, TCG_REG_B6));
936 }
937
938 static void tcg_out_exit_tb(TCGContext *s, tcg_target_long arg)
939 {
940 int64_t disp;
941 uint64_t imm;
942
943 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R8, arg);
944
945 disp = tb_ret_addr - s->code_ptr;
946 imm = (uint64_t)disp >> 4;
947
948 tcg_out_bundle(s, mLX,
949 INSN_NOP_M,
950 tcg_opc_l3 (imm),
951 tcg_opc_x3 (TCG_REG_P0, OPC_BRL_SPTK_MANY_X3, imm));
952 }
953
954 static inline void tcg_out_goto_tb(TCGContext *s, TCGArg arg)
955 {
956 if (s->tb_jmp_offset) {
957 /* direct jump method */
958 tcg_abort();
959 } else {
960 /* indirect jump method */
961 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2,
962 (tcg_target_long)(s->tb_next + arg));
963 tcg_out_bundle(s, MmI,
964 tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1,
965 TCG_REG_R2, TCG_REG_R2),
966 INSN_NOP_M,
967 tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, TCG_REG_B6,
968 TCG_REG_R2, 0));
969 tcg_out_bundle(s, mmB,
970 INSN_NOP_M,
971 INSN_NOP_M,
972 tcg_opc_b4 (TCG_REG_P0, OPC_BR_SPTK_MANY_B4,
973 TCG_REG_B6));
974 }
975 s->tb_next_offset[arg] = s->code_ptr - s->code_buf;
976 }
977
978 static inline void tcg_out_jmp(TCGContext *s, TCGArg addr)
979 {
980 tcg_out_bundle(s, mmI,
981 INSN_NOP_M,
982 INSN_NOP_M,
983 tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, TCG_REG_B6, addr, 0));
984 tcg_out_bundle(s, mmB,
985 INSN_NOP_M,
986 INSN_NOP_M,
987 tcg_opc_b4(TCG_REG_P0, OPC_BR_SPTK_MANY_B4, TCG_REG_B6));
988 }
989
990 static inline void tcg_out_ld_rel(TCGContext *s, uint64_t opc_m4, TCGArg arg,
991 TCGArg arg1, tcg_target_long arg2)
992 {
993 if (arg2 == ((int16_t)arg2 >> 2) << 2) {
994 tcg_out_bundle(s, MmI,
995 tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4,
996 TCG_REG_R2, arg2, arg1),
997 tcg_opc_m1 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
998 INSN_NOP_I);
999 } else {
1000 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, arg2);
1001 tcg_out_bundle(s, MmI,
1002 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1,
1003 TCG_REG_R2, TCG_REG_R2, arg1),
1004 tcg_opc_m1 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
1005 INSN_NOP_I);
1006 }
1007 }
1008
1009 static inline void tcg_out_st_rel(TCGContext *s, uint64_t opc_m4, TCGArg arg,
1010 TCGArg arg1, tcg_target_long arg2)
1011 {
1012 if (arg2 == ((int16_t)arg2 >> 2) << 2) {
1013 tcg_out_bundle(s, MmI,
1014 tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4,
1015 TCG_REG_R2, arg2, arg1),
1016 tcg_opc_m4 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
1017 INSN_NOP_I);
1018 } else {
1019 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, arg2);
1020 tcg_out_bundle(s, MmI,
1021 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1,
1022 TCG_REG_R2, TCG_REG_R2, arg1),
1023 tcg_opc_m4 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
1024 INSN_NOP_I);
1025 }
1026 }
1027
1028 static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
1029 TCGReg arg1, intptr_t arg2)
1030 {
1031 if (type == TCG_TYPE_I32) {
1032 tcg_out_ld_rel(s, OPC_LD4_M1, arg, arg1, arg2);
1033 } else {
1034 tcg_out_ld_rel(s, OPC_LD8_M1, arg, arg1, arg2);
1035 }
1036 }
1037
1038 static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
1039 TCGReg arg1, intptr_t arg2)
1040 {
1041 if (type == TCG_TYPE_I32) {
1042 tcg_out_st_rel(s, OPC_ST4_M4, arg, arg1, arg2);
1043 } else {
1044 tcg_out_st_rel(s, OPC_ST8_M4, arg, arg1, arg2);
1045 }
1046 }
1047
1048 static inline void tcg_out_alu(TCGContext *s, uint64_t opc_a1, TCGArg ret,
1049 TCGArg arg1, int const_arg1,
1050 TCGArg arg2, int const_arg2)
1051 {
1052 uint64_t opc1, opc2;
1053
1054 if (const_arg1 && arg1 != 0) {
1055 opc1 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5,
1056 TCG_REG_R2, arg1, TCG_REG_R0);
1057 arg1 = TCG_REG_R2;
1058 } else {
1059 opc1 = INSN_NOP_M;
1060 }
1061
1062 if (const_arg2 && arg2 != 0) {
1063 opc2 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5,
1064 TCG_REG_R3, arg2, TCG_REG_R0);
1065 arg2 = TCG_REG_R3;
1066 } else {
1067 opc2 = INSN_NOP_I;
1068 }
1069
1070 tcg_out_bundle(s, mII,
1071 opc1,
1072 opc2,
1073 tcg_opc_a1(TCG_REG_P0, opc_a1, ret, arg1, arg2));
1074 }
1075
1076 static inline void tcg_out_eqv(TCGContext *s, TCGArg ret,
1077 TCGArg arg1, int const_arg1,
1078 TCGArg arg2, int const_arg2)
1079 {
1080 tcg_out_bundle(s, mII,
1081 INSN_NOP_M,
1082 tcg_opc_a1 (TCG_REG_P0, OPC_XOR_A1, ret, arg1, arg2),
1083 tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
1084 }
1085
1086 static inline void tcg_out_nand(TCGContext *s, TCGArg ret,
1087 TCGArg arg1, int const_arg1,
1088 TCGArg arg2, int const_arg2)
1089 {
1090 tcg_out_bundle(s, mII,
1091 INSN_NOP_M,
1092 tcg_opc_a1 (TCG_REG_P0, OPC_AND_A1, ret, arg1, arg2),
1093 tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
1094 }
1095
1096 static inline void tcg_out_nor(TCGContext *s, TCGArg ret,
1097 TCGArg arg1, int const_arg1,
1098 TCGArg arg2, int const_arg2)
1099 {
1100 tcg_out_bundle(s, mII,
1101 INSN_NOP_M,
1102 tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, arg1, arg2),
1103 tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
1104 }
1105
1106 static inline void tcg_out_orc(TCGContext *s, TCGArg ret,
1107 TCGArg arg1, int const_arg1,
1108 TCGArg arg2, int const_arg2)
1109 {
1110 tcg_out_bundle(s, mII,
1111 INSN_NOP_M,
1112 tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, TCG_REG_R2, -1, arg2),
1113 tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, arg1, TCG_REG_R2));
1114 }
1115
1116 static inline void tcg_out_mul(TCGContext *s, TCGArg ret,
1117 TCGArg arg1, TCGArg arg2)
1118 {
1119 tcg_out_bundle(s, mmI,
1120 tcg_opc_m18(TCG_REG_P0, OPC_SETF_SIG_M18, TCG_REG_F6, arg1),
1121 tcg_opc_m18(TCG_REG_P0, OPC_SETF_SIG_M18, TCG_REG_F7, arg2),
1122 INSN_NOP_I);
1123 tcg_out_bundle(s, mmF,
1124 INSN_NOP_M,
1125 INSN_NOP_M,
1126 tcg_opc_f2 (TCG_REG_P0, OPC_XMA_L_F2, TCG_REG_F6, TCG_REG_F6,
1127 TCG_REG_F7, TCG_REG_F0));
1128 tcg_out_bundle(s, miI,
1129 tcg_opc_m19(TCG_REG_P0, OPC_GETF_SIG_M19, ret, TCG_REG_F6),
1130 INSN_NOP_I,
1131 INSN_NOP_I);
1132 }
1133
1134 static inline void tcg_out_sar_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1135 TCGArg arg2, int const_arg2)
1136 {
1137 if (const_arg2) {
1138 tcg_out_bundle(s, miI,
1139 INSN_NOP_M,
1140 INSN_NOP_I,
1141 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_I11,
1142 ret, arg1, arg2, 31 - arg2));
1143 } else {
1144 tcg_out_bundle(s, mII,
1145 tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3,
1146 TCG_REG_R3, 0x1f, arg2),
1147 tcg_opc_i29(TCG_REG_P0, OPC_SXT4_I29, TCG_REG_R2, arg1),
1148 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_I5, ret,
1149 TCG_REG_R2, TCG_REG_R3));
1150 }
1151 }
1152
1153 static inline void tcg_out_sar_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1154 TCGArg arg2, int const_arg2)
1155 {
1156 if (const_arg2) {
1157 tcg_out_bundle(s, miI,
1158 INSN_NOP_M,
1159 INSN_NOP_I,
1160 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_I11,
1161 ret, arg1, arg2, 63 - arg2));
1162 } else {
1163 tcg_out_bundle(s, miI,
1164 INSN_NOP_M,
1165 INSN_NOP_I,
1166 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_I5, ret, arg1, arg2));
1167 }
1168 }
1169
1170 static inline void tcg_out_shl_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1171 TCGArg arg2, int const_arg2)
1172 {
1173 if (const_arg2) {
1174 tcg_out_bundle(s, miI,
1175 INSN_NOP_M,
1176 INSN_NOP_I,
1177 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret,
1178 arg1, 63 - arg2, 31 - arg2));
1179 } else {
1180 tcg_out_bundle(s, mII,
1181 INSN_NOP_M,
1182 tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R2,
1183 0x1f, arg2),
1184 tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, ret,
1185 arg1, TCG_REG_R2));
1186 }
1187 }
1188
1189 static inline void tcg_out_shl_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1190 TCGArg arg2, int const_arg2)
1191 {
1192 if (const_arg2) {
1193 tcg_out_bundle(s, miI,
1194 INSN_NOP_M,
1195 INSN_NOP_I,
1196 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret,
1197 arg1, 63 - arg2, 63 - arg2));
1198 } else {
1199 tcg_out_bundle(s, miI,
1200 INSN_NOP_M,
1201 INSN_NOP_I,
1202 tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, ret,
1203 arg1, arg2));
1204 }
1205 }
1206
1207 static inline void tcg_out_shr_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1208 TCGArg arg2, int const_arg2)
1209 {
1210 if (const_arg2) {
1211 tcg_out_bundle(s, miI,
1212 INSN_NOP_M,
1213 INSN_NOP_I,
1214 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1215 arg1, arg2, 31 - arg2));
1216 } else {
1217 tcg_out_bundle(s, mII,
1218 tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3,
1219 0x1f, arg2),
1220 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, TCG_REG_R2, arg1),
1221 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1222 TCG_REG_R2, TCG_REG_R3));
1223 }
1224 }
1225
1226 static inline void tcg_out_shr_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1227 TCGArg arg2, int const_arg2)
1228 {
1229 if (const_arg2) {
1230 tcg_out_bundle(s, miI,
1231 INSN_NOP_M,
1232 INSN_NOP_I,
1233 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1234 arg1, arg2, 63 - arg2));
1235 } else {
1236 tcg_out_bundle(s, miI,
1237 INSN_NOP_M,
1238 INSN_NOP_I,
1239 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1240 arg1, arg2));
1241 }
1242 }
1243
1244 static inline void tcg_out_rotl_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1245 TCGArg arg2, int const_arg2)
1246 {
1247 if (const_arg2) {
1248 tcg_out_bundle(s, mII,
1249 INSN_NOP_M,
1250 tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1251 TCG_REG_R2, arg1, arg1),
1252 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1253 TCG_REG_R2, 32 - arg2, 31));
1254 } else {
1255 tcg_out_bundle(s, miI,
1256 INSN_NOP_M,
1257 tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1258 TCG_REG_R2, arg1, arg1),
1259 tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3,
1260 0x1f, arg2));
1261 tcg_out_bundle(s, mII,
1262 INSN_NOP_M,
1263 tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R3,
1264 0x20, TCG_REG_R3),
1265 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1266 TCG_REG_R2, TCG_REG_R3));
1267 }
1268 }
1269
1270 static inline void tcg_out_rotl_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1271 TCGArg arg2, int const_arg2)
1272 {
1273 if (const_arg2) {
1274 tcg_out_bundle(s, miI,
1275 INSN_NOP_M,
1276 INSN_NOP_I,
1277 tcg_opc_i10(TCG_REG_P0, OPC_SHRP_I10, ret, arg1,
1278 arg1, 0x40 - arg2));
1279 } else {
1280 tcg_out_bundle(s, mII,
1281 tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R2,
1282 0x40, arg2),
1283 tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, TCG_REG_R3,
1284 arg1, arg2),
1285 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, TCG_REG_R2,
1286 arg1, TCG_REG_R2));
1287 tcg_out_bundle(s, miI,
1288 INSN_NOP_M,
1289 INSN_NOP_I,
1290 tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret,
1291 TCG_REG_R2, TCG_REG_R3));
1292 }
1293 }
1294
1295 static inline void tcg_out_rotr_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1296 TCGArg arg2, int const_arg2)
1297 {
1298 if (const_arg2) {
1299 tcg_out_bundle(s, mII,
1300 INSN_NOP_M,
1301 tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1302 TCG_REG_R2, arg1, arg1),
1303 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1304 TCG_REG_R2, arg2, 31));
1305 } else {
1306 tcg_out_bundle(s, mII,
1307 tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3,
1308 0x1f, arg2),
1309 tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1310 TCG_REG_R2, arg1, arg1),
1311 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1312 TCG_REG_R2, TCG_REG_R3));
1313 }
1314 }
1315
1316 static inline void tcg_out_rotr_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1317 TCGArg arg2, int const_arg2)
1318 {
1319 if (const_arg2) {
1320 tcg_out_bundle(s, miI,
1321 INSN_NOP_M,
1322 INSN_NOP_I,
1323 tcg_opc_i10(TCG_REG_P0, OPC_SHRP_I10, ret, arg1,
1324 arg1, arg2));
1325 } else {
1326 tcg_out_bundle(s, mII,
1327 tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R2,
1328 0x40, arg2),
1329 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, TCG_REG_R3,
1330 arg1, arg2),
1331 tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, TCG_REG_R2,
1332 arg1, TCG_REG_R2));
1333 tcg_out_bundle(s, miI,
1334 INSN_NOP_M,
1335 INSN_NOP_I,
1336 tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret,
1337 TCG_REG_R2, TCG_REG_R3));
1338 }
1339 }
1340
1341 static inline void tcg_out_ext(TCGContext *s, uint64_t opc_i29,
1342 TCGArg ret, TCGArg arg)
1343 {
1344 tcg_out_bundle(s, miI,
1345 INSN_NOP_M,
1346 INSN_NOP_I,
1347 tcg_opc_i29(TCG_REG_P0, opc_i29, ret, arg));
1348 }
1349
1350 static inline void tcg_out_bswap16(TCGContext *s, TCGArg ret, TCGArg arg)
1351 {
1352 tcg_out_bundle(s, mII,
1353 INSN_NOP_M,
1354 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, arg, 15, 15),
1355 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, ret, 0xb));
1356 }
1357
1358 static inline void tcg_out_bswap32(TCGContext *s, TCGArg ret, TCGArg arg)
1359 {
1360 tcg_out_bundle(s, mII,
1361 INSN_NOP_M,
1362 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, arg, 31, 31),
1363 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, ret, 0xb));
1364 }
1365
1366 static inline void tcg_out_bswap64(TCGContext *s, TCGArg ret, TCGArg arg)
1367 {
1368 tcg_out_bundle(s, miI,
1369 INSN_NOP_M,
1370 INSN_NOP_I,
1371 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, arg, 0xb));
1372 }
1373
1374 static inline void tcg_out_deposit(TCGContext *s, TCGArg ret, TCGArg a1,
1375 TCGArg a2, int const_a2, int pos, int len)
1376 {
1377 uint64_t i1 = 0, i2 = 0;
1378 int cpos = 63 - pos, lm1 = len - 1;
1379
1380 if (const_a2) {
1381 /* Truncate the value of a constant a2 to the width of the field. */
1382 int mask = (1u << len) - 1;
1383 a2 &= mask;
1384
1385 if (a2 == 0 || a2 == mask) {
1386 /* 1-bit signed constant inserted into register. */
1387 i2 = tcg_opc_i14(TCG_REG_P0, OPC_DEP_I14, ret, a2, a1, cpos, lm1);
1388 } else {
1389 /* Otherwise, load any constant into a temporary. Do this into
1390 the first I slot to help out with cross-unit delays. */
1391 i1 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5,
1392 TCG_REG_R2, a2, TCG_REG_R0);
1393 a2 = TCG_REG_R2;
1394 }
1395 }
1396 if (i2 == 0) {
1397 i2 = tcg_opc_i15(TCG_REG_P0, OPC_DEP_I15, ret, a2, a1, cpos, lm1);
1398 }
1399 tcg_out_bundle(s, (i1 ? mII : miI),
1400 INSN_NOP_M,
1401 i1 ? i1 : INSN_NOP_I,
1402 i2);
1403 }
1404
1405 static inline uint64_t tcg_opc_cmp_a(int qp, TCGCond cond, TCGArg arg1,
1406 TCGArg arg2, int cmp4)
1407 {
1408 uint64_t opc_eq_a6, opc_lt_a6, opc_ltu_a6;
1409
1410 if (cmp4) {
1411 opc_eq_a6 = OPC_CMP4_EQ_A6;
1412 opc_lt_a6 = OPC_CMP4_LT_A6;
1413 opc_ltu_a6 = OPC_CMP4_LTU_A6;
1414 } else {
1415 opc_eq_a6 = OPC_CMP_EQ_A6;
1416 opc_lt_a6 = OPC_CMP_LT_A6;
1417 opc_ltu_a6 = OPC_CMP_LTU_A6;
1418 }
1419
1420 switch (cond) {
1421 case TCG_COND_EQ:
1422 return tcg_opc_a6 (qp, opc_eq_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2);
1423 case TCG_COND_NE:
1424 return tcg_opc_a6 (qp, opc_eq_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2);
1425 case TCG_COND_LT:
1426 return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2);
1427 case TCG_COND_LTU:
1428 return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2);
1429 case TCG_COND_GE:
1430 return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2);
1431 case TCG_COND_GEU:
1432 return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2);
1433 case TCG_COND_LE:
1434 return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P7, TCG_REG_P6, arg2, arg1);
1435 case TCG_COND_LEU:
1436 return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P7, TCG_REG_P6, arg2, arg1);
1437 case TCG_COND_GT:
1438 return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P6, TCG_REG_P7, arg2, arg1);
1439 case TCG_COND_GTU:
1440 return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P6, TCG_REG_P7, arg2, arg1);
1441 default:
1442 tcg_abort();
1443 break;
1444 }
1445 }
1446
1447 static inline void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1,
1448 TCGReg arg2, int label_index, int cmp4)
1449 {
1450 TCGLabel *l = &s->labels[label_index];
1451
1452 tcg_out_bundle(s, miB,
1453 INSN_NOP_M,
1454 tcg_opc_cmp_a(TCG_REG_P0, cond, arg1, arg2, cmp4),
1455 tcg_opc_b1(TCG_REG_P6, OPC_BR_DPTK_FEW_B1,
1456 get_reloc_pcrel21b(s->code_ptr + 2)));
1457
1458 if (l->has_value) {
1459 reloc_pcrel21b((s->code_ptr - 16) + 2, l->u.value);
1460 } else {
1461 tcg_out_reloc(s, (s->code_ptr - 16) + 2,
1462 R_IA64_PCREL21B, label_index, 0);
1463 }
1464 }
1465
1466 static inline void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGArg ret,
1467 TCGArg arg1, TCGArg arg2, int cmp4)
1468 {
1469 tcg_out_bundle(s, MmI,
1470 tcg_opc_cmp_a(TCG_REG_P0, cond, arg1, arg2, cmp4),
1471 tcg_opc_a5(TCG_REG_P6, OPC_ADDL_A5, ret, 1, TCG_REG_R0),
1472 tcg_opc_a5(TCG_REG_P7, OPC_ADDL_A5, ret, 0, TCG_REG_R0));
1473 }
1474
1475 static inline void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGArg ret,
1476 TCGArg c1, TCGArg c2,
1477 TCGArg v1, int const_v1,
1478 TCGArg v2, int const_v2, int cmp4)
1479 {
1480 uint64_t opc1, opc2;
1481
1482 if (const_v1) {
1483 opc1 = tcg_opc_a5(TCG_REG_P6, OPC_ADDL_A5, ret, v1, TCG_REG_R0);
1484 } else if (ret == v1) {
1485 opc1 = INSN_NOP_M;
1486 } else {
1487 opc1 = tcg_opc_a4(TCG_REG_P6, OPC_ADDS_A4, ret, 0, v1);
1488 }
1489 if (const_v2) {
1490 opc2 = tcg_opc_a5(TCG_REG_P7, OPC_ADDL_A5, ret, v2, TCG_REG_R0);
1491 } else if (ret == v2) {
1492 opc2 = INSN_NOP_I;
1493 } else {
1494 opc2 = tcg_opc_a4(TCG_REG_P7, OPC_ADDS_A4, ret, 0, v2);
1495 }
1496
1497 tcg_out_bundle(s, MmI,
1498 tcg_opc_cmp_a(TCG_REG_P0, cond, c1, c2, cmp4),
1499 opc1,
1500 opc2);
1501 }
1502
1503 #if defined(CONFIG_SOFTMMU)
1504 /* Load and compare a TLB entry, and return the result in (p6, p7).
1505 R2 is loaded with the address of the addend TLB entry.
1506 R57 is loaded with the address, zero extented on 32-bit targets. */
1507 static inline void tcg_out_qemu_tlb(TCGContext *s, TCGArg addr_reg,
1508 TCGMemOp s_bits, uint64_t offset_rw,
1509 uint64_t offset_addend)
1510 {
1511 tcg_out_bundle(s, mII,
1512 INSN_NOP_M,
1513 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, TCG_REG_R2,
1514 addr_reg, TARGET_PAGE_BITS, CPU_TLB_BITS - 1),
1515 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, TCG_REG_R2,
1516 TCG_REG_R2, 63 - CPU_TLB_ENTRY_BITS,
1517 63 - CPU_TLB_ENTRY_BITS));
1518 tcg_out_bundle(s, mII,
1519 tcg_opc_a5 (TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R2,
1520 offset_rw, TCG_REG_R2),
1521 #if TARGET_LONG_BITS == 32
1522 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, TCG_REG_R57, addr_reg),
1523 #else
1524 tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, TCG_REG_R57,
1525 0, addr_reg),
1526 #endif
1527 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1528 TCG_REG_R2, TCG_AREG0));
1529 tcg_out_bundle(s, mII,
1530 tcg_opc_m3 (TCG_REG_P0,
1531 (TARGET_LONG_BITS == 32
1532 ? OPC_LD4_M3 : OPC_LD8_M3), TCG_REG_R56,
1533 TCG_REG_R2, offset_addend - offset_rw),
1534 tcg_opc_i14(TCG_REG_P0, OPC_DEP_I14, TCG_REG_R3, 0,
1535 TCG_REG_R57, 63 - s_bits,
1536 TARGET_PAGE_BITS - s_bits - 1),
1537 tcg_opc_a6 (TCG_REG_P0, OPC_CMP_EQ_A6, TCG_REG_P6,
1538 TCG_REG_P7, TCG_REG_R3, TCG_REG_R56));
1539 }
1540
1541 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
1542 int mmu_idx) */
1543 static const void * const qemu_ld_helpers[4] = {
1544 helper_ldb_mmu,
1545 helper_ldw_mmu,
1546 helper_ldl_mmu,
1547 helper_ldq_mmu,
1548 };
1549
1550 static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
1551 TCGMemOp opc)
1552 {
1553 static const uint64_t opc_ld_m1[4] = {
1554 OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1
1555 };
1556 static const uint64_t opc_ext_i29[8] = {
1557 OPC_ZXT1_I29, OPC_ZXT2_I29, OPC_ZXT4_I29, 0,
1558 OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0
1559 };
1560 int addr_reg, data_reg, mem_index;
1561 TCGMemOp s_bits, bswap;
1562
1563 data_reg = *args++;
1564 addr_reg = *args++;
1565 mem_index = *args;
1566 s_bits = opc & MO_SIZE;
1567 bswap = opc & MO_BSWAP;
1568
1569 /* Read the TLB entry */
1570 tcg_out_qemu_tlb(s, addr_reg, s_bits,
1571 offsetof(CPUArchState, tlb_table[mem_index][0].addr_read),
1572 offsetof(CPUArchState, tlb_table[mem_index][0].addend));
1573
1574 /* P6 is the fast path, and P7 the slow path */
1575 tcg_out_bundle(s, mLX,
1576 tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4,
1577 TCG_REG_R56, 0, TCG_AREG0),
1578 tcg_opc_l2 ((tcg_target_long) qemu_ld_helpers[s_bits]),
1579 tcg_opc_x2 (TCG_REG_P7, OPC_MOVL_X2, TCG_REG_R2,
1580 (tcg_target_long) qemu_ld_helpers[s_bits]));
1581 tcg_out_bundle(s, MmI,
1582 tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R3,
1583 TCG_REG_R2, 8),
1584 tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R3,
1585 TCG_REG_R3, TCG_REG_R57),
1586 tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6,
1587 TCG_REG_R3, 0));
1588 if (bswap && s_bits == MO_16) {
1589 tcg_out_bundle(s, MmI,
1590 tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits],
1591 TCG_REG_R8, TCG_REG_R3),
1592 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
1593 tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
1594 TCG_REG_R8, TCG_REG_R8, 15, 15));
1595 } else if (bswap && s_bits == MO_32) {
1596 tcg_out_bundle(s, MmI,
1597 tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits],
1598 TCG_REG_R8, TCG_REG_R3),
1599 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
1600 tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
1601 TCG_REG_R8, TCG_REG_R8, 31, 31));
1602 } else {
1603 tcg_out_bundle(s, mmI,
1604 tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits],
1605 TCG_REG_R8, TCG_REG_R3),
1606 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
1607 INSN_NOP_I);
1608 }
1609 if (!bswap) {
1610 tcg_out_bundle(s, miB,
1611 tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R58,
1612 mem_index, TCG_REG_R0),
1613 INSN_NOP_I,
1614 tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
1615 TCG_REG_B0, TCG_REG_B6));
1616 } else {
1617 tcg_out_bundle(s, miB,
1618 tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R58,
1619 mem_index, TCG_REG_R0),
1620 tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1621 TCG_REG_R8, TCG_REG_R8, 0xb),
1622 tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
1623 TCG_REG_B0, TCG_REG_B6));
1624 }
1625
1626 if (s_bits == MO_64) {
1627 tcg_out_bundle(s, miI,
1628 INSN_NOP_M,
1629 INSN_NOP_I,
1630 tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4,
1631 data_reg, 0, TCG_REG_R8));
1632 } else {
1633 tcg_out_bundle(s, miI,
1634 INSN_NOP_M,
1635 INSN_NOP_I,
1636 tcg_opc_i29(TCG_REG_P0, opc_ext_i29[opc & MO_SSIZE],
1637 data_reg, TCG_REG_R8));
1638 }
1639 }
1640
1641 /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
1642 uintxx_t val, int mmu_idx) */
1643 static const void * const qemu_st_helpers[4] = {
1644 helper_stb_mmu,
1645 helper_stw_mmu,
1646 helper_stl_mmu,
1647 helper_stq_mmu,
1648 };
1649
1650 static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
1651 TCGMemOp opc)
1652 {
1653 static const uint64_t opc_st_m4[4] = {
1654 OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4
1655 };
1656 int addr_reg, data_reg, mem_index;
1657 TCGMemOp s_bits;
1658
1659 data_reg = *args++;
1660 addr_reg = *args++;
1661 mem_index = *args;
1662 s_bits = opc & MO_SIZE;
1663
1664 tcg_out_qemu_tlb(s, addr_reg, s_bits,
1665 offsetof(CPUArchState, tlb_table[mem_index][0].addr_write),
1666 offsetof(CPUArchState, tlb_table[mem_index][0].addend));
1667
1668 /* P6 is the fast path, and P7 the slow path */
1669 tcg_out_bundle(s, mLX,
1670 tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4,
1671 TCG_REG_R56, 0, TCG_AREG0),
1672 tcg_opc_l2 ((tcg_target_long) qemu_st_helpers[s_bits]),
1673 tcg_opc_x2 (TCG_REG_P7, OPC_MOVL_X2, TCG_REG_R2,
1674 (tcg_target_long) qemu_st_helpers[s_bits]));
1675 tcg_out_bundle(s, MmI,
1676 tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R3,
1677 TCG_REG_R2, 8),
1678 tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R3,
1679 TCG_REG_R3, TCG_REG_R57),
1680 tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6,
1681 TCG_REG_R3, 0));
1682
1683 switch (opc) {
1684 case MO_8:
1685 case MO_16:
1686 case MO_32:
1687 case MO_64:
1688 tcg_out_bundle(s, mii,
1689 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1690 TCG_REG_R1, TCG_REG_R2),
1691 tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58,
1692 0, data_reg),
1693 INSN_NOP_I);
1694 break;
1695
1696 case MO_16 | MO_BSWAP:
1697 tcg_out_bundle(s, miI,
1698 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1699 TCG_REG_R1, TCG_REG_R2),
1700 INSN_NOP_I,
1701 tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
1702 TCG_REG_R2, data_reg, 15, 15));
1703 tcg_out_bundle(s, miI,
1704 tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58,
1705 0, data_reg),
1706 INSN_NOP_I,
1707 tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1708 TCG_REG_R2, TCG_REG_R2, 0xb));
1709 data_reg = TCG_REG_R2;
1710 break;
1711
1712 case MO_32 | MO_BSWAP:
1713 tcg_out_bundle(s, miI,
1714 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1715 TCG_REG_R1, TCG_REG_R2),
1716 INSN_NOP_I,
1717 tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
1718 TCG_REG_R2, data_reg, 31, 31));
1719 tcg_out_bundle(s, miI,
1720 tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58,
1721 0, data_reg),
1722 INSN_NOP_I,
1723 tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1724 TCG_REG_R2, TCG_REG_R2, 0xb));
1725 data_reg = TCG_REG_R2;
1726 break;
1727
1728 case MO_64 | MO_BSWAP:
1729 tcg_out_bundle(s, miI,
1730 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1731 TCG_REG_R1, TCG_REG_R2),
1732 tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58,
1733 0, data_reg),
1734 tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1735 TCG_REG_R2, data_reg, 0xb));
1736 data_reg = TCG_REG_R2;
1737 break;
1738
1739 default:
1740 tcg_abort();
1741 }
1742
1743 tcg_out_bundle(s, miB,
1744 tcg_opc_m4 (TCG_REG_P6, opc_st_m4[s_bits],
1745 data_reg, TCG_REG_R3),
1746 tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R59,
1747 mem_index, TCG_REG_R0),
1748 tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
1749 TCG_REG_B0, TCG_REG_B6));
1750 }
1751
1752 #else /* !CONFIG_SOFTMMU */
1753
1754 static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
1755 TCGMemOp opc)
1756 {
1757 static uint64_t const opc_ld_m1[4] = {
1758 OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1
1759 };
1760 static uint64_t const opc_sxt_i29[4] = {
1761 OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0
1762 };
1763 int addr_reg, data_reg;
1764 TCGMemOp s_bits, bswap;
1765
1766 data_reg = *args++;
1767 addr_reg = *args++;
1768 s_bits = opc & MO_SIZE;
1769 bswap = opc & MO_BSWAP;
1770
1771 #if TARGET_LONG_BITS == 32
1772 if (GUEST_BASE != 0) {
1773 tcg_out_bundle(s, mII,
1774 INSN_NOP_M,
1775 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
1776 TCG_REG_R3, addr_reg),
1777 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1778 TCG_GUEST_BASE_REG, TCG_REG_R3));
1779 } else {
1780 tcg_out_bundle(s, miI,
1781 INSN_NOP_M,
1782 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
1783 TCG_REG_R2, addr_reg),
1784 INSN_NOP_I);
1785 }
1786
1787 if (!bswap) {
1788 if (!(opc & MO_SIGN)) {
1789 tcg_out_bundle(s, miI,
1790 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1791 data_reg, TCG_REG_R2),
1792 INSN_NOP_I,
1793 INSN_NOP_I);
1794 } else {
1795 tcg_out_bundle(s, mII,
1796 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1797 data_reg, TCG_REG_R2),
1798 INSN_NOP_I,
1799 tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits],
1800 data_reg, data_reg));
1801 }
1802 } else if (s_bits == MO_64) {
1803 tcg_out_bundle(s, mII,
1804 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1805 data_reg, TCG_REG_R2),
1806 INSN_NOP_I,
1807 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1808 data_reg, data_reg, 0xb));
1809 } else {
1810 if (s_bits == MO_16) {
1811 tcg_out_bundle(s, mII,
1812 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1813 data_reg, TCG_REG_R2),
1814 INSN_NOP_I,
1815 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1816 data_reg, data_reg, 15, 15));
1817 } else {
1818 tcg_out_bundle(s, mII,
1819 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1820 data_reg, TCG_REG_R2),
1821 INSN_NOP_I,
1822 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1823 data_reg, data_reg, 31, 31));
1824 }
1825 if (!(opc & MO_SIGN)) {
1826 tcg_out_bundle(s, miI,
1827 INSN_NOP_M,
1828 INSN_NOP_I,
1829 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1830 data_reg, data_reg, 0xb));
1831 } else {
1832 tcg_out_bundle(s, mII,
1833 INSN_NOP_M,
1834 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1835 data_reg, data_reg, 0xb),
1836 tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits],
1837 data_reg, data_reg));
1838 }
1839 }
1840 #else
1841 if (GUEST_BASE != 0) {
1842 tcg_out_bundle(s, MmI,
1843 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1844 TCG_GUEST_BASE_REG, addr_reg),
1845 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1846 data_reg, TCG_REG_R2),
1847 INSN_NOP_I);
1848 } else {
1849 tcg_out_bundle(s, mmI,
1850 INSN_NOP_M,
1851 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1852 data_reg, addr_reg),
1853 INSN_NOP_I);
1854 }
1855
1856 if (bswap && s_bits == MO_16) {
1857 tcg_out_bundle(s, mII,
1858 INSN_NOP_M,
1859 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1860 data_reg, data_reg, 15, 15),
1861 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1862 data_reg, data_reg, 0xb));
1863 } else if (bswap && s_bits == MO_32) {
1864 tcg_out_bundle(s, mII,
1865 INSN_NOP_M,
1866 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1867 data_reg, data_reg, 31, 31),
1868 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1869 data_reg, data_reg, 0xb));
1870 } else if (bswap && s_bits == MO_64) {
1871 tcg_out_bundle(s, miI,
1872 INSN_NOP_M,
1873 INSN_NOP_I,
1874 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1875 data_reg, data_reg, 0xb));
1876 }
1877 if (opc & MO_SIGN) {
1878 tcg_out_bundle(s, miI,
1879 INSN_NOP_M,
1880 INSN_NOP_I,
1881 tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits],
1882 data_reg, data_reg));
1883 }
1884 #endif
1885 }
1886
1887 static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
1888 TCGMemOp opc)
1889 {
1890 static uint64_t const opc_st_m4[4] = {
1891 OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4
1892 };
1893 int addr_reg, data_reg;
1894 #if TARGET_LONG_BITS == 64
1895 uint64_t add_guest_base;
1896 #endif
1897 TCGMemOp s_bits, bswap;
1898
1899 data_reg = *args++;
1900 addr_reg = *args++;
1901 s_bits = opc & MO_SIZE;
1902 bswap = opc & MO_BSWAP;
1903
1904 #if TARGET_LONG_BITS == 32
1905 if (GUEST_BASE != 0) {
1906 tcg_out_bundle(s, mII,
1907 INSN_NOP_M,
1908 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
1909 TCG_REG_R3, addr_reg),
1910 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1911 TCG_GUEST_BASE_REG, TCG_REG_R3));
1912 } else {
1913 tcg_out_bundle(s, miI,
1914 INSN_NOP_M,
1915 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
1916 TCG_REG_R2, addr_reg),
1917 INSN_NOP_I);
1918 }
1919
1920 if (bswap) {
1921 if (s_bits == MO_16) {
1922 tcg_out_bundle(s, mII,
1923 INSN_NOP_M,
1924 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1925 TCG_REG_R3, data_reg, 15, 15),
1926 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1927 TCG_REG_R3, TCG_REG_R3, 0xb));
1928 data_reg = TCG_REG_R3;
1929 } else if (s_bits == MO_32) {
1930 tcg_out_bundle(s, mII,
1931 INSN_NOP_M,
1932 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1933 TCG_REG_R3, data_reg, 31, 31),
1934 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1935 TCG_REG_R3, TCG_REG_R3, 0xb));
1936 data_reg = TCG_REG_R3;
1937 } else if (s_bits == MO_64) {
1938 tcg_out_bundle(s, miI,
1939 INSN_NOP_M,
1940 INSN_NOP_I,
1941 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1942 TCG_REG_R3, data_reg, 0xb));
1943 data_reg = TCG_REG_R3;
1944 }
1945 }
1946 tcg_out_bundle(s, mmI,
1947 tcg_opc_m4 (TCG_REG_P0, opc_st_m4[s_bits],
1948 data_reg, TCG_REG_R2),
1949 INSN_NOP_M,
1950 INSN_NOP_I);
1951 #else
1952 if (GUEST_BASE != 0) {
1953 add_guest_base = tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1954 TCG_GUEST_BASE_REG, addr_reg);
1955 addr_reg = TCG_REG_R2;
1956 } else {
1957 add_guest_base = INSN_NOP_M;
1958 }
1959
1960 if (!bswap) {
1961 tcg_out_bundle(s, (GUEST_BASE ? MmI : mmI),
1962 add_guest_base,
1963 tcg_opc_m4 (TCG_REG_P0, opc_st_m4[s_bits],
1964 data_reg, addr_reg),
1965 INSN_NOP_I);
1966 } else {
1967 if (s_bits == MO_16) {
1968 tcg_out_bundle(s, mII,
1969 add_guest_base,
1970 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1971 TCG_REG_R3, data_reg, 15, 15),
1972 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1973 TCG_REG_R3, TCG_REG_R3, 0xb));
1974 data_reg = TCG_REG_R3;
1975 } else if (s_bits == MO_32) {
1976 tcg_out_bundle(s, mII,
1977 add_guest_base,
1978 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1979 TCG_REG_R3, data_reg, 31, 31),
1980 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1981 TCG_REG_R3, TCG_REG_R3, 0xb));
1982 data_reg = TCG_REG_R3;
1983 } else if (s_bits == MO_64) {
1984 tcg_out_bundle(s, miI,
1985 add_guest_base,
1986 INSN_NOP_I,
1987 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1988 TCG_REG_R3, data_reg, 0xb));
1989 data_reg = TCG_REG_R3;
1990 }
1991 tcg_out_bundle(s, miI,
1992 tcg_opc_m4 (TCG_REG_P0, opc_st_m4[s_bits],
1993 data_reg, addr_reg),
1994 INSN_NOP_I,
1995 INSN_NOP_I);
1996 }
1997 #endif
1998 }
1999
2000 #endif
2001
2002 static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
2003 const TCGArg *args, const int *const_args)
2004 {
2005 switch(opc) {
2006 case INDEX_op_exit_tb:
2007 tcg_out_exit_tb(s, args[0]);
2008 break;
2009 case INDEX_op_br:
2010 tcg_out_br(s, args[0]);
2011 break;
2012 case INDEX_op_call:
2013 if (likely(const_args[0])) {
2014 tcg_out_calli(s, args[0]);
2015 } else {
2016 tcg_out_callr(s, args[0]);
2017 }
2018 break;
2019 case INDEX_op_goto_tb:
2020 tcg_out_goto_tb(s, args[0]);
2021 break;
2022
2023 case INDEX_op_movi_i32:
2024 tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
2025 break;
2026 case INDEX_op_movi_i64:
2027 tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
2028 break;
2029
2030 case INDEX_op_ld8u_i32:
2031 case INDEX_op_ld8u_i64:
2032 tcg_out_ld_rel(s, OPC_LD1_M1, args[0], args[1], args[2]);
2033 break;
2034 case INDEX_op_ld8s_i32:
2035 case INDEX_op_ld8s_i64:
2036 tcg_out_ld_rel(s, OPC_LD1_M1, args[0], args[1], args[2]);
2037 tcg_out_ext(s, OPC_SXT1_I29, args[0], args[0]);
2038 break;
2039 case INDEX_op_ld16u_i32:
2040 case INDEX_op_ld16u_i64:
2041 tcg_out_ld_rel(s, OPC_LD2_M1, args[0], args[1], args[2]);
2042 break;
2043 case INDEX_op_ld16s_i32:
2044 case INDEX_op_ld16s_i64:
2045 tcg_out_ld_rel(s, OPC_LD2_M1, args[0], args[1], args[2]);
2046 tcg_out_ext(s, OPC_SXT2_I29, args[0], args[0]);
2047 break;
2048 case INDEX_op_ld_i32:
2049 case INDEX_op_ld32u_i64:
2050 tcg_out_ld_rel(s, OPC_LD4_M1, args[0], args[1], args[2]);
2051 break;
2052 case INDEX_op_ld32s_i64:
2053 tcg_out_ld_rel(s, OPC_LD4_M1, args[0], args[1], args[2]);
2054 tcg_out_ext(s, OPC_SXT4_I29, args[0], args[0]);
2055 break;
2056 case INDEX_op_ld_i64:
2057 tcg_out_ld_rel(s, OPC_LD8_M1, args[0], args[1], args[2]);
2058 break;
2059 case INDEX_op_st8_i32:
2060 case INDEX_op_st8_i64:
2061 tcg_out_st_rel(s, OPC_ST1_M4, args[0], args[1], args[2]);
2062 break;
2063 case INDEX_op_st16_i32:
2064 case INDEX_op_st16_i64:
2065 tcg_out_st_rel(s, OPC_ST2_M4, args[0], args[1], args[2]);
2066 break;
2067 case INDEX_op_st_i32:
2068 case INDEX_op_st32_i64:
2069 tcg_out_st_rel(s, OPC_ST4_M4, args[0], args[1], args[2]);
2070 break;
2071 case INDEX_op_st_i64:
2072 tcg_out_st_rel(s, OPC_ST8_M4, args[0], args[1], args[2]);
2073 break;
2074
2075 case INDEX_op_add_i32:
2076 case INDEX_op_add_i64:
2077 tcg_out_alu(s, OPC_ADD_A1, args[0], args[1], const_args[1],
2078 args[2], const_args[2]);
2079 break;
2080 case INDEX_op_sub_i32:
2081 case INDEX_op_sub_i64:
2082 tcg_out_alu(s, OPC_SUB_A1, args[0], args[1], const_args[1],
2083 args[2], const_args[2]);
2084 break;
2085
2086 case INDEX_op_and_i32:
2087 case INDEX_op_and_i64:
2088 tcg_out_alu(s, OPC_AND_A1, args[0], args[1], const_args[1],
2089 args[2], const_args[2]);
2090 break;
2091 case INDEX_op_andc_i32:
2092 case INDEX_op_andc_i64:
2093 tcg_out_alu(s, OPC_ANDCM_A1, args[0], args[1], const_args[1],
2094 args[2], const_args[2]);
2095 break;
2096 case INDEX_op_eqv_i32:
2097 case INDEX_op_eqv_i64:
2098 tcg_out_eqv(s, args[0], args[1], const_args[1],
2099 args[2], const_args[2]);
2100 break;
2101 case INDEX_op_nand_i32:
2102 case INDEX_op_nand_i64:
2103 tcg_out_nand(s, args[0], args[1], const_args[1],
2104 args[2], const_args[2]);
2105 break;
2106 case INDEX_op_nor_i32:
2107 case INDEX_op_nor_i64:
2108 tcg_out_nor(s, args[0], args[1], const_args[1],
2109 args[2], const_args[2]);
2110 break;
2111 case INDEX_op_or_i32:
2112 case INDEX_op_or_i64:
2113 tcg_out_alu(s, OPC_OR_A1, args[0], args[1], const_args[1],
2114 args[2], const_args[2]);
2115 break;
2116 case INDEX_op_orc_i32:
2117 case INDEX_op_orc_i64:
2118 tcg_out_orc(s, args[0], args[1], const_args[1],
2119 args[2], const_args[2]);
2120 break;
2121 case INDEX_op_xor_i32:
2122 case INDEX_op_xor_i64:
2123 tcg_out_alu(s, OPC_XOR_A1, args[0], args[1], const_args[1],
2124 args[2], const_args[2]);
2125 break;
2126
2127 case INDEX_op_mul_i32:
2128 case INDEX_op_mul_i64:
2129 tcg_out_mul(s, args[0], args[1], args[2]);
2130 break;
2131
2132 case INDEX_op_sar_i32:
2133 tcg_out_sar_i32(s, args[0], args[1], args[2], const_args[2]);
2134 break;
2135 case INDEX_op_sar_i64:
2136 tcg_out_sar_i64(s, args[0], args[1], args[2], const_args[2]);
2137 break;
2138 case INDEX_op_shl_i32:
2139 tcg_out_shl_i32(s, args[0], args[1], args[2], const_args[2]);
2140 break;
2141 case INDEX_op_shl_i64:
2142 tcg_out_shl_i64(s, args[0], args[1], args[2], const_args[2]);
2143 break;
2144 case INDEX_op_shr_i32:
2145 tcg_out_shr_i32(s, args[0], args[1], args[2], const_args[2]);
2146 break;
2147 case INDEX_op_shr_i64:
2148 tcg_out_shr_i64(s, args[0], args[1], args[2], const_args[2]);
2149 break;
2150 case INDEX_op_rotl_i32:
2151 tcg_out_rotl_i32(s, args[0], args[1], args[2], const_args[2]);
2152 break;
2153 case INDEX_op_rotl_i64:
2154 tcg_out_rotl_i64(s, args[0], args[1], args[2], const_args[2]);
2155 break;
2156 case INDEX_op_rotr_i32:
2157 tcg_out_rotr_i32(s, args[0], args[1], args[2], const_args[2]);
2158 break;
2159 case INDEX_op_rotr_i64:
2160 tcg_out_rotr_i64(s, args[0], args[1], args[2], const_args[2]);
2161 break;
2162
2163 case INDEX_op_ext8s_i32:
2164 case INDEX_op_ext8s_i64:
2165 tcg_out_ext(s, OPC_SXT1_I29, args[0], args[1]);
2166 break;
2167 case INDEX_op_ext8u_i32:
2168 case INDEX_op_ext8u_i64:
2169 tcg_out_ext(s, OPC_ZXT1_I29, args[0], args[1]);
2170 break;
2171 case INDEX_op_ext16s_i32:
2172 case INDEX_op_ext16s_i64:
2173 tcg_out_ext(s, OPC_SXT2_I29, args[0], args[1]);
2174 break;
2175 case INDEX_op_ext16u_i32:
2176 case INDEX_op_ext16u_i64:
2177 tcg_out_ext(s, OPC_ZXT2_I29, args[0], args[1]);
2178 break;
2179 case INDEX_op_ext32s_i64:
2180 tcg_out_ext(s, OPC_SXT4_I29, args[0], args[1]);
2181 break;
2182 case INDEX_op_ext32u_i64:
2183 tcg_out_ext(s, OPC_ZXT4_I29, args[0], args[1]);
2184 break;
2185
2186 case INDEX_op_bswap16_i32:
2187 case INDEX_op_bswap16_i64:
2188 tcg_out_bswap16(s, args[0], args[1]);
2189 break;
2190 case INDEX_op_bswap32_i32:
2191 case INDEX_op_bswap32_i64:
2192 tcg_out_bswap32(s, args[0], args[1]);
2193 break;
2194 case INDEX_op_bswap64_i64:
2195 tcg_out_bswap64(s, args[0], args[1]);
2196 break;
2197
2198 case INDEX_op_deposit_i32:
2199 case INDEX_op_deposit_i64:
2200 tcg_out_deposit(s, args[0], args[1], args[2], const_args[2],
2201 args[3], args[4]);
2202 break;
2203
2204 case INDEX_op_brcond_i32:
2205 tcg_out_brcond(s, args[2], args[0], args[1], args[3], 1);
2206 break;
2207 case INDEX_op_brcond_i64:
2208 tcg_out_brcond(s, args[2], args[0], args[1], args[3], 0);
2209 break;
2210 case INDEX_op_setcond_i32:
2211 tcg_out_setcond(s, args[3], args[0], args[1], args[2], 1);
2212 break;
2213 case INDEX_op_setcond_i64:
2214 tcg_out_setcond(s, args[3], args[0], args[1], args[2], 0);
2215 break;
2216 case INDEX_op_movcond_i32:
2217 tcg_out_movcond(s, args[5], args[0], args[1], args[2],
2218 args[3], const_args[3], args[4], const_args[4], 1);
2219 break;
2220 case INDEX_op_movcond_i64:
2221 tcg_out_movcond(s, args[5], args[0], args[1], args[2],
2222 args[3], const_args[3], args[4], const_args[4], 0);
2223 break;
2224
2225 case INDEX_op_qemu_ld8u:
2226 tcg_out_qemu_ld(s, args, MO_UB);
2227 break;
2228 case INDEX_op_qemu_ld8s:
2229 tcg_out_qemu_ld(s, args, MO_SB);
2230 break;
2231 case INDEX_op_qemu_ld16u:
2232 tcg_out_qemu_ld(s, args, MO_TEUW);
2233 break;
2234 case INDEX_op_qemu_ld16s:
2235 tcg_out_qemu_ld(s, args, MO_TESW);
2236 break;
2237 case INDEX_op_qemu_ld32:
2238 case INDEX_op_qemu_ld32u:
2239 tcg_out_qemu_ld(s, args, MO_TEUL);
2240 break;
2241 case INDEX_op_qemu_ld32s:
2242 tcg_out_qemu_ld(s, args, MO_TESL);
2243 break;
2244 case INDEX_op_qemu_ld64:
2245 tcg_out_qemu_ld(s, args, MO_TEQ);
2246 break;
2247
2248 case INDEX_op_qemu_st8:
2249 tcg_out_qemu_st(s, args, MO_UB);
2250 break;
2251 case INDEX_op_qemu_st16:
2252 tcg_out_qemu_st(s, args, MO_TEUW);
2253 break;
2254 case INDEX_op_qemu_st32:
2255 tcg_out_qemu_st(s, args, MO_TEUL);
2256 break;
2257 case INDEX_op_qemu_st64:
2258 tcg_out_qemu_st(s, args, MO_TEQ);
2259 break;
2260
2261 default:
2262 tcg_abort();
2263 }
2264 }
2265
2266 static const TCGTargetOpDef ia64_op_defs[] = {
2267 { INDEX_op_br, { } },
2268 { INDEX_op_call, { "ri" } },
2269 { INDEX_op_exit_tb, { } },
2270 { INDEX_op_goto_tb, { } },
2271
2272 { INDEX_op_mov_i32, { "r", "r" } },
2273 { INDEX_op_movi_i32, { "r" } },
2274
2275 { INDEX_op_ld8u_i32, { "r", "r" } },
2276 { INDEX_op_ld8s_i32, { "r", "r" } },
2277 { INDEX_op_ld16u_i32, { "r", "r" } },
2278 { INDEX_op_ld16s_i32, { "r", "r" } },
2279 { INDEX_op_ld_i32, { "r", "r" } },
2280 { INDEX_op_st8_i32, { "rZ", "r" } },
2281 { INDEX_op_st16_i32, { "rZ", "r" } },
2282 { INDEX_op_st_i32, { "rZ", "r" } },
2283
2284 { INDEX_op_add_i32, { "r", "rI", "rI" } },
2285 { INDEX_op_sub_i32, { "r", "rI", "rI" } },
2286
2287 { INDEX_op_and_i32, { "r", "rI", "rI" } },
2288 { INDEX_op_andc_i32, { "r", "rI", "rI" } },
2289 { INDEX_op_eqv_i32, { "r", "rZ", "rZ" } },
2290 { INDEX_op_nand_i32, { "r", "rZ", "rZ" } },
2291 { INDEX_op_nor_i32, { "r", "rZ", "rZ" } },
2292 { INDEX_op_or_i32, { "r", "rI", "rI" } },
2293 { INDEX_op_orc_i32, { "r", "rZ", "rZ" } },
2294 { INDEX_op_xor_i32, { "r", "rI", "rI" } },
2295
2296 { INDEX_op_mul_i32, { "r", "rZ", "rZ" } },
2297
2298 { INDEX_op_sar_i32, { "r", "rZ", "ri" } },
2299 { INDEX_op_shl_i32, { "r", "rZ", "ri" } },
2300 { INDEX_op_shr_i32, { "r", "rZ", "ri" } },
2301 { INDEX_op_rotl_i32, { "r", "rZ", "ri" } },
2302 { INDEX_op_rotr_i32, { "r", "rZ", "ri" } },
2303
2304 { INDEX_op_ext8s_i32, { "r", "rZ"} },
2305 { INDEX_op_ext8u_i32, { "r", "rZ"} },
2306 { INDEX_op_ext16s_i32, { "r", "rZ"} },
2307 { INDEX_op_ext16u_i32, { "r", "rZ"} },
2308
2309 { INDEX_op_bswap16_i32, { "r", "rZ" } },
2310 { INDEX_op_bswap32_i32, { "r", "rZ" } },
2311
2312 { INDEX_op_brcond_i32, { "rZ", "rZ" } },
2313 { INDEX_op_setcond_i32, { "r", "rZ", "rZ" } },
2314 { INDEX_op_movcond_i32, { "r", "rZ", "rZ", "rI", "rI" } },
2315
2316 { INDEX_op_mov_i64, { "r", "r" } },
2317 { INDEX_op_movi_i64, { "r" } },
2318
2319 { INDEX_op_ld8u_i64, { "r", "r" } },
2320 { INDEX_op_ld8s_i64, { "r", "r" } },
2321 { INDEX_op_ld16u_i64, { "r", "r" } },
2322 { INDEX_op_ld16s_i64, { "r", "r" } },
2323 { INDEX_op_ld32u_i64, { "r", "r" } },
2324 { INDEX_op_ld32s_i64, { "r", "r" } },
2325 { INDEX_op_ld_i64, { "r", "r" } },
2326 { INDEX_op_st8_i64, { "rZ", "r" } },
2327 { INDEX_op_st16_i64, { "rZ", "r" } },
2328 { INDEX_op_st32_i64, { "rZ", "r" } },
2329 { INDEX_op_st_i64, { "rZ", "r" } },
2330
2331 { INDEX_op_add_i64, { "r", "rI", "rI" } },
2332 { INDEX_op_sub_i64, { "r", "rI", "rI" } },
2333
2334 { INDEX_op_and_i64, { "r", "rI", "rI" } },
2335 { INDEX_op_andc_i64, { "r", "rI", "rI" } },
2336 { INDEX_op_eqv_i64, { "r", "rZ", "rZ" } },
2337 { INDEX_op_nand_i64, { "r", "rZ", "rZ" } },
2338 { INDEX_op_nor_i64, { "r", "rZ", "rZ" } },
2339 { INDEX_op_or_i64, { "r", "rI", "rI" } },
2340 { INDEX_op_orc_i64, { "r", "rZ", "rZ" } },
2341 { INDEX_op_xor_i64, { "r", "rI", "rI" } },
2342
2343 { INDEX_op_mul_i64, { "r", "rZ", "rZ" } },
2344
2345 { INDEX_op_sar_i64, { "r", "rZ", "ri" } },
2346 { INDEX_op_shl_i64, { "r", "rZ", "ri" } },
2347 { INDEX_op_shr_i64, { "r", "rZ", "ri" } },
2348 { INDEX_op_rotl_i64, { "r", "rZ", "ri" } },
2349 { INDEX_op_rotr_i64, { "r", "rZ", "ri" } },
2350
2351 { INDEX_op_ext8s_i64, { "r", "rZ"} },
2352 { INDEX_op_ext8u_i64, { "r", "rZ"} },
2353 { INDEX_op_ext16s_i64, { "r", "rZ"} },
2354 { INDEX_op_ext16u_i64, { "r", "rZ"} },
2355 { INDEX_op_ext32s_i64, { "r", "rZ"} },
2356 { INDEX_op_ext32u_i64, { "r", "rZ"} },
2357
2358 { INDEX_op_bswap16_i64, { "r", "rZ" } },
2359 { INDEX_op_bswap32_i64, { "r", "rZ" } },
2360 { INDEX_op_bswap64_i64, { "r", "rZ" } },
2361
2362 { INDEX_op_brcond_i64, { "rZ", "rZ" } },
2363 { INDEX_op_setcond_i64, { "r", "rZ", "rZ" } },
2364 { INDEX_op_movcond_i64, { "r", "rZ", "rZ", "rI", "rI" } },
2365
2366 { INDEX_op_deposit_i32, { "r", "rZ", "ri" } },
2367 { INDEX_op_deposit_i64, { "r", "rZ", "ri" } },
2368
2369 { INDEX_op_qemu_ld8u, { "r", "r" } },
2370 { INDEX_op_qemu_ld8s, { "r", "r" } },
2371 { INDEX_op_qemu_ld16u, { "r", "r" } },
2372 { INDEX_op_qemu_ld16s, { "r", "r" } },
2373 { INDEX_op_qemu_ld32, { "r", "r" } },
2374 { INDEX_op_qemu_ld32u, { "r", "r" } },
2375 { INDEX_op_qemu_ld32s, { "r", "r" } },
2376 { INDEX_op_qemu_ld64, { "r", "r" } },
2377
2378 { INDEX_op_qemu_st8, { "SZ", "r" } },
2379 { INDEX_op_qemu_st16, { "SZ", "r" } },
2380 { INDEX_op_qemu_st32, { "SZ", "r" } },
2381 { INDEX_op_qemu_st64, { "SZ", "r" } },
2382
2383 { -1 },
2384 };
2385
2386 /* Generate global QEMU prologue and epilogue code */
2387 static void tcg_target_qemu_prologue(TCGContext *s)
2388 {
2389 int frame_size;
2390
2391 /* reserve some stack space */
2392 frame_size = TCG_STATIC_CALL_ARGS_SIZE +
2393 CPU_TEMP_BUF_NLONGS * sizeof(long);
2394 frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
2395 ~(TCG_TARGET_STACK_ALIGN - 1);
2396 tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE,
2397 CPU_TEMP_BUF_NLONGS * sizeof(long));
2398
2399 /* First emit adhoc function descriptor */
2400 *(uint64_t *)(s->code_ptr) = (uint64_t)s->code_ptr + 16; /* entry point */
2401 s->code_ptr += 16; /* skip GP */
2402
2403 /* prologue */
2404 tcg_out_bundle(s, miI,
2405 tcg_opc_m34(TCG_REG_P0, OPC_ALLOC_M34,
2406 TCG_REG_R34, 32, 24, 0),
2407 tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4,
2408 TCG_AREG0, 0, TCG_REG_R32),
2409 tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21,
2410 TCG_REG_B6, TCG_REG_R33, 0));
2411
2412 /* ??? If GUEST_BASE < 0x200000, we could load the register via
2413 an ADDL in the M slot of the next bundle. */
2414 if (GUEST_BASE != 0) {
2415 tcg_out_bundle(s, mlx,
2416 INSN_NOP_M,
2417 tcg_opc_l2 (GUEST_BASE),
2418 tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2,
2419 TCG_GUEST_BASE_REG, GUEST_BASE));
2420 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
2421 }
2422
2423 tcg_out_bundle(s, miB,
2424 tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4,
2425 TCG_REG_R12, -frame_size, TCG_REG_R12),
2426 tcg_opc_i22(TCG_REG_P0, OPC_MOV_I22,
2427 TCG_REG_R32, TCG_REG_B0),
2428 tcg_opc_b4 (TCG_REG_P0, OPC_BR_SPTK_MANY_B4, TCG_REG_B6));
2429
2430 /* epilogue */
2431 tb_ret_addr = s->code_ptr;
2432 tcg_out_bundle(s, miI,
2433 INSN_NOP_M,
2434 tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21,
2435 TCG_REG_B0, TCG_REG_R32, 0),
2436 tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4,
2437 TCG_REG_R12, frame_size, TCG_REG_R12));
2438 tcg_out_bundle(s, miB,
2439 INSN_NOP_M,
2440 tcg_opc_i26(TCG_REG_P0, OPC_MOV_I_I26,
2441 TCG_REG_PFS, TCG_REG_R34),
2442 tcg_opc_b4 (TCG_REG_P0, OPC_BR_RET_SPTK_MANY_B4,
2443 TCG_REG_B0));
2444 }
2445
2446 static void tcg_target_init(TCGContext *s)
2447 {
2448 tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I32],
2449 0xffffffffffffffffull);
2450 tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I64],
2451 0xffffffffffffffffull);
2452
2453 tcg_regset_clear(tcg_target_call_clobber_regs);
2454 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8);
2455 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9);
2456 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10);
2457 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11);
2458 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14);
2459 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R15);
2460 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R16);
2461 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R17);
2462 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R18);
2463 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R19);
2464 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R20);
2465 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R21);
2466 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R22);
2467 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R23);
2468 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R24);
2469 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R25);
2470 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R26);
2471 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R27);
2472 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R28);
2473 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R29);
2474 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R30);
2475 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R31);
2476 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R56);
2477 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R57);
2478 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R58);
2479 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R59);
2480 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R60);
2481 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R61);
2482 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R62);
2483 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R63);
2484
2485 tcg_regset_clear(s->reserved_regs);
2486 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* zero register */
2487 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* global pointer */
2488 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* internal use */
2489 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R3); /* internal use */
2490 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R12); /* stack pointer */
2491 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */
2492 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R32); /* return address */
2493 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R34); /* PFS */
2494
2495 /* The following 3 are not in use, are call-saved, but *not* saved
2496 by the prologue. Therefore we cannot use them without modifying
2497 the prologue. There doesn't seem to be any good reason to use
2498 these as opposed to the windowed registers. */
2499 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R4);
2500 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R5);
2501 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R6);
2502
2503 tcg_add_target_add_op_defs(ia64_op_defs);
2504 }
Qemu copy for testing