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tcg-ia64: Introduce tcg_opc_movi_a
[qemu.git] / tcg / ia64 / tcg-target.c
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2009-2010 Aurelien Jarno <aurelien@aurel32.net>
5 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
26 #include "tcg-be-null.h"
27
28 /*
29 * Register definitions
30 */
31
32 #ifndef NDEBUG
33 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
34 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
35 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
36 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
37 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
38 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
39 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
40 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
41 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
42 };
43 #endif
44
45 #ifdef CONFIG_USE_GUEST_BASE
46 #define TCG_GUEST_BASE_REG TCG_REG_R55
47 #else
48 #define TCG_GUEST_BASE_REG TCG_REG_R0
49 #endif
50 #ifndef GUEST_BASE
51 #define GUEST_BASE 0
52 #endif
53
54 /* Branch registers */
55 enum {
56 TCG_REG_B0 = 0,
57 TCG_REG_B1,
58 TCG_REG_B2,
59 TCG_REG_B3,
60 TCG_REG_B4,
61 TCG_REG_B5,
62 TCG_REG_B6,
63 TCG_REG_B7,
64 };
65
66 /* Floating point registers */
67 enum {
68 TCG_REG_F0 = 0,
69 TCG_REG_F1,
70 TCG_REG_F2,
71 TCG_REG_F3,
72 TCG_REG_F4,
73 TCG_REG_F5,
74 TCG_REG_F6,
75 TCG_REG_F7,
76 TCG_REG_F8,
77 TCG_REG_F9,
78 TCG_REG_F10,
79 TCG_REG_F11,
80 TCG_REG_F12,
81 TCG_REG_F13,
82 TCG_REG_F14,
83 TCG_REG_F15,
84 };
85
86 /* Predicate registers */
87 enum {
88 TCG_REG_P0 = 0,
89 TCG_REG_P1,
90 TCG_REG_P2,
91 TCG_REG_P3,
92 TCG_REG_P4,
93 TCG_REG_P5,
94 TCG_REG_P6,
95 TCG_REG_P7,
96 TCG_REG_P8,
97 TCG_REG_P9,
98 TCG_REG_P10,
99 TCG_REG_P11,
100 TCG_REG_P12,
101 TCG_REG_P13,
102 TCG_REG_P14,
103 TCG_REG_P15,
104 };
105
106 /* Application registers */
107 enum {
108 TCG_REG_PFS = 64,
109 };
110
111 static const int tcg_target_reg_alloc_order[] = {
112 TCG_REG_R35,
113 TCG_REG_R36,
114 TCG_REG_R37,
115 TCG_REG_R38,
116 TCG_REG_R39,
117 TCG_REG_R40,
118 TCG_REG_R41,
119 TCG_REG_R42,
120 TCG_REG_R43,
121 TCG_REG_R44,
122 TCG_REG_R45,
123 TCG_REG_R46,
124 TCG_REG_R47,
125 TCG_REG_R48,
126 TCG_REG_R49,
127 TCG_REG_R50,
128 TCG_REG_R51,
129 TCG_REG_R52,
130 TCG_REG_R53,
131 TCG_REG_R54,
132 TCG_REG_R55,
133 TCG_REG_R14,
134 TCG_REG_R15,
135 TCG_REG_R16,
136 TCG_REG_R17,
137 TCG_REG_R18,
138 TCG_REG_R19,
139 TCG_REG_R20,
140 TCG_REG_R21,
141 TCG_REG_R22,
142 TCG_REG_R23,
143 TCG_REG_R24,
144 TCG_REG_R25,
145 TCG_REG_R26,
146 TCG_REG_R27,
147 TCG_REG_R28,
148 TCG_REG_R29,
149 TCG_REG_R30,
150 TCG_REG_R31,
151 TCG_REG_R56,
152 TCG_REG_R57,
153 TCG_REG_R58,
154 TCG_REG_R59,
155 TCG_REG_R60,
156 TCG_REG_R61,
157 TCG_REG_R62,
158 TCG_REG_R63,
159 TCG_REG_R8,
160 TCG_REG_R9,
161 TCG_REG_R10,
162 TCG_REG_R11
163 };
164
165 static const int tcg_target_call_iarg_regs[8] = {
166 TCG_REG_R56,
167 TCG_REG_R57,
168 TCG_REG_R58,
169 TCG_REG_R59,
170 TCG_REG_R60,
171 TCG_REG_R61,
172 TCG_REG_R62,
173 TCG_REG_R63,
174 };
175
176 static const int tcg_target_call_oarg_regs[] = {
177 TCG_REG_R8
178 };
179
180 /*
181 * opcode formation
182 */
183
184 /* bundle templates: stops (double bar in the IA64 manual) are marked with
185 an uppercase letter. */
186 enum {
187 mii = 0x00,
188 miI = 0x01,
189 mIi = 0x02,
190 mII = 0x03,
191 mlx = 0x04,
192 mLX = 0x05,
193 mmi = 0x08,
194 mmI = 0x09,
195 Mmi = 0x0a,
196 MmI = 0x0b,
197 mfi = 0x0c,
198 mfI = 0x0d,
199 mmf = 0x0e,
200 mmF = 0x0f,
201 mib = 0x10,
202 miB = 0x11,
203 mbb = 0x12,
204 mbB = 0x13,
205 bbb = 0x16,
206 bbB = 0x17,
207 mmb = 0x18,
208 mmB = 0x19,
209 mfb = 0x1c,
210 mfB = 0x1d,
211 };
212
213 enum {
214 OPC_ADD_A1 = 0x10000000000ull,
215 OPC_AND_A1 = 0x10060000000ull,
216 OPC_AND_A3 = 0x10160000000ull,
217 OPC_ANDCM_A1 = 0x10068000000ull,
218 OPC_ANDCM_A3 = 0x10168000000ull,
219 OPC_ADDS_A4 = 0x10800000000ull,
220 OPC_ADDL_A5 = 0x12000000000ull,
221 OPC_ALLOC_M34 = 0x02c00000000ull,
222 OPC_BR_DPTK_FEW_B1 = 0x08400000000ull,
223 OPC_BR_SPTK_MANY_B1 = 0x08000001000ull,
224 OPC_BR_SPTK_MANY_B4 = 0x00100001000ull,
225 OPC_BR_CALL_SPTK_MANY_B5 = 0x02100001000ull,
226 OPC_BR_RET_SPTK_MANY_B4 = 0x00108001100ull,
227 OPC_BRL_SPTK_MANY_X3 = 0x18000001000ull,
228 OPC_BRL_CALL_SPTK_MANY_X4 = 0x1a000001000ull,
229 OPC_CMP_LT_A6 = 0x18000000000ull,
230 OPC_CMP_LTU_A6 = 0x1a000000000ull,
231 OPC_CMP_EQ_A6 = 0x1c000000000ull,
232 OPC_CMP4_LT_A6 = 0x18400000000ull,
233 OPC_CMP4_LTU_A6 = 0x1a400000000ull,
234 OPC_CMP4_EQ_A6 = 0x1c400000000ull,
235 OPC_DEP_I14 = 0x0ae00000000ull,
236 OPC_DEP_I15 = 0x08000000000ull,
237 OPC_DEP_Z_I12 = 0x0a600000000ull,
238 OPC_EXTR_I11 = 0x0a400002000ull,
239 OPC_EXTR_U_I11 = 0x0a400000000ull,
240 OPC_FCVT_FX_TRUNC_S1_F10 = 0x004d0000000ull,
241 OPC_FCVT_FXU_TRUNC_S1_F10 = 0x004d8000000ull,
242 OPC_FCVT_XF_F11 = 0x000e0000000ull,
243 OPC_FMA_S1_F1 = 0x10400000000ull,
244 OPC_FNMA_S1_F1 = 0x18400000000ull,
245 OPC_FRCPA_S1_F6 = 0x00600000000ull,
246 OPC_GETF_SIG_M19 = 0x08708000000ull,
247 OPC_LD1_M1 = 0x08000000000ull,
248 OPC_LD1_M3 = 0x0a000000000ull,
249 OPC_LD2_M1 = 0x08040000000ull,
250 OPC_LD2_M3 = 0x0a040000000ull,
251 OPC_LD4_M1 = 0x08080000000ull,
252 OPC_LD4_M3 = 0x0a080000000ull,
253 OPC_LD8_M1 = 0x080c0000000ull,
254 OPC_LD8_M3 = 0x0a0c0000000ull,
255 OPC_MUX1_I3 = 0x0eca0000000ull,
256 OPC_NOP_B9 = 0x04008000000ull,
257 OPC_NOP_F16 = 0x00008000000ull,
258 OPC_NOP_I18 = 0x00008000000ull,
259 OPC_NOP_M48 = 0x00008000000ull,
260 OPC_MOV_I21 = 0x00e00100000ull,
261 OPC_MOV_RET_I21 = 0x00e00500000ull,
262 OPC_MOV_I22 = 0x00188000000ull,
263 OPC_MOV_I_I26 = 0x00150000000ull,
264 OPC_MOVL_X2 = 0x0c000000000ull,
265 OPC_OR_A1 = 0x10070000000ull,
266 OPC_OR_A3 = 0x10170000000ull,
267 OPC_SETF_EXP_M18 = 0x0c748000000ull,
268 OPC_SETF_SIG_M18 = 0x0c708000000ull,
269 OPC_SHL_I7 = 0x0f240000000ull,
270 OPC_SHR_I5 = 0x0f220000000ull,
271 OPC_SHR_U_I5 = 0x0f200000000ull,
272 OPC_SHRP_I10 = 0x0ac00000000ull,
273 OPC_SXT1_I29 = 0x000a0000000ull,
274 OPC_SXT2_I29 = 0x000a8000000ull,
275 OPC_SXT4_I29 = 0x000b0000000ull,
276 OPC_ST1_M4 = 0x08c00000000ull,
277 OPC_ST2_M4 = 0x08c40000000ull,
278 OPC_ST4_M4 = 0x08c80000000ull,
279 OPC_ST8_M4 = 0x08cc0000000ull,
280 OPC_SUB_A1 = 0x10028000000ull,
281 OPC_SUB_A3 = 0x10128000000ull,
282 OPC_UNPACK4_L_I2 = 0x0f860000000ull,
283 OPC_XMA_L_F2 = 0x1d000000000ull,
284 OPC_XOR_A1 = 0x10078000000ull,
285 OPC_XOR_A3 = 0x10178000000ull,
286 OPC_ZXT1_I29 = 0x00080000000ull,
287 OPC_ZXT2_I29 = 0x00088000000ull,
288 OPC_ZXT4_I29 = 0x00090000000ull,
289
290 INSN_NOP_M = OPC_NOP_M48, /* nop.m 0 */
291 INSN_NOP_I = OPC_NOP_I18, /* nop.i 0 */
292 };
293
294 static inline uint64_t tcg_opc_a1(int qp, uint64_t opc, int r1,
295 int r2, int r3)
296 {
297 return opc
298 | ((r3 & 0x7f) << 20)
299 | ((r2 & 0x7f) << 13)
300 | ((r1 & 0x7f) << 6)
301 | (qp & 0x3f);
302 }
303
304 static inline uint64_t tcg_opc_a3(int qp, uint64_t opc, int r1,
305 uint64_t imm, int r3)
306 {
307 return opc
308 | ((imm & 0x80) << 29) /* s */
309 | ((imm & 0x7f) << 13) /* imm7b */
310 | ((r3 & 0x7f) << 20)
311 | ((r1 & 0x7f) << 6)
312 | (qp & 0x3f);
313 }
314
315 static inline uint64_t tcg_opc_a4(int qp, uint64_t opc, int r1,
316 uint64_t imm, int r3)
317 {
318 return opc
319 | ((imm & 0x2000) << 23) /* s */
320 | ((imm & 0x1f80) << 20) /* imm6d */
321 | ((imm & 0x007f) << 13) /* imm7b */
322 | ((r3 & 0x7f) << 20)
323 | ((r1 & 0x7f) << 6)
324 | (qp & 0x3f);
325 }
326
327 static inline uint64_t tcg_opc_a5(int qp, uint64_t opc, int r1,
328 uint64_t imm, int r3)
329 {
330 return opc
331 | ((imm & 0x200000) << 15) /* s */
332 | ((imm & 0x1f0000) << 6) /* imm5c */
333 | ((imm & 0x00ff80) << 20) /* imm9d */
334 | ((imm & 0x00007f) << 13) /* imm7b */
335 | ((r3 & 0x03) << 20)
336 | ((r1 & 0x7f) << 6)
337 | (qp & 0x3f);
338 }
339
340 static inline uint64_t tcg_opc_a6(int qp, uint64_t opc, int p1,
341 int p2, int r2, int r3)
342 {
343 return opc
344 | ((p2 & 0x3f) << 27)
345 | ((r3 & 0x7f) << 20)
346 | ((r2 & 0x7f) << 13)
347 | ((p1 & 0x3f) << 6)
348 | (qp & 0x3f);
349 }
350
351 static inline uint64_t tcg_opc_b1(int qp, uint64_t opc, uint64_t imm)
352 {
353 return opc
354 | ((imm & 0x100000) << 16) /* s */
355 | ((imm & 0x0fffff) << 13) /* imm20b */
356 | (qp & 0x3f);
357 }
358
359 static inline uint64_t tcg_opc_b4(int qp, uint64_t opc, int b2)
360 {
361 return opc
362 | ((b2 & 0x7) << 13)
363 | (qp & 0x3f);
364 }
365
366 static inline uint64_t tcg_opc_b5(int qp, uint64_t opc, int b1, int b2)
367 {
368 return opc
369 | ((b2 & 0x7) << 13)
370 | ((b1 & 0x7) << 6)
371 | (qp & 0x3f);
372 }
373
374
375 static inline uint64_t tcg_opc_b9(int qp, uint64_t opc, uint64_t imm)
376 {
377 return opc
378 | ((imm & 0x100000) << 16) /* i */
379 | ((imm & 0x0fffff) << 6) /* imm20a */
380 | (qp & 0x3f);
381 }
382
383 static inline uint64_t tcg_opc_f1(int qp, uint64_t opc, int f1,
384 int f3, int f4, int f2)
385 {
386 return opc
387 | ((f4 & 0x7f) << 27)
388 | ((f3 & 0x7f) << 20)
389 | ((f2 & 0x7f) << 13)
390 | ((f1 & 0x7f) << 6)
391 | (qp & 0x3f);
392 }
393
394 static inline uint64_t tcg_opc_f2(int qp, uint64_t opc, int f1,
395 int f3, int f4, int f2)
396 {
397 return opc
398 | ((f4 & 0x7f) << 27)
399 | ((f3 & 0x7f) << 20)
400 | ((f2 & 0x7f) << 13)
401 | ((f1 & 0x7f) << 6)
402 | (qp & 0x3f);
403 }
404
405 static inline uint64_t tcg_opc_f6(int qp, uint64_t opc, int f1,
406 int p2, int f2, int f3)
407 {
408 return opc
409 | ((p2 & 0x3f) << 27)
410 | ((f3 & 0x7f) << 20)
411 | ((f2 & 0x7f) << 13)
412 | ((f1 & 0x7f) << 6)
413 | (qp & 0x3f);
414 }
415
416 static inline uint64_t tcg_opc_f10(int qp, uint64_t opc, int f1, int f2)
417 {
418 return opc
419 | ((f2 & 0x7f) << 13)
420 | ((f1 & 0x7f) << 6)
421 | (qp & 0x3f);
422 }
423
424 static inline uint64_t tcg_opc_f11(int qp, uint64_t opc, int f1, int f2)
425 {
426 return opc
427 | ((f2 & 0x7f) << 13)
428 | ((f1 & 0x7f) << 6)
429 | (qp & 0x3f);
430 }
431
432 static inline uint64_t tcg_opc_f16(int qp, uint64_t opc, uint64_t imm)
433 {
434 return opc
435 | ((imm & 0x100000) << 16) /* i */
436 | ((imm & 0x0fffff) << 6) /* imm20a */
437 | (qp & 0x3f);
438 }
439
440 static inline uint64_t tcg_opc_i2(int qp, uint64_t opc, int r1,
441 int r2, int r3)
442 {
443 return opc
444 | ((r3 & 0x7f) << 20)
445 | ((r2 & 0x7f) << 13)
446 | ((r1 & 0x7f) << 6)
447 | (qp & 0x3f);
448 }
449
450 static inline uint64_t tcg_opc_i3(int qp, uint64_t opc, int r1,
451 int r2, int mbtype)
452 {
453 return opc
454 | ((mbtype & 0x0f) << 20)
455 | ((r2 & 0x7f) << 13)
456 | ((r1 & 0x7f) << 6)
457 | (qp & 0x3f);
458 }
459
460 static inline uint64_t tcg_opc_i5(int qp, uint64_t opc, int r1,
461 int r3, int r2)
462 {
463 return opc
464 | ((r3 & 0x7f) << 20)
465 | ((r2 & 0x7f) << 13)
466 | ((r1 & 0x7f) << 6)
467 | (qp & 0x3f);
468 }
469
470 static inline uint64_t tcg_opc_i7(int qp, uint64_t opc, int r1,
471 int r2, int r3)
472 {
473 return opc
474 | ((r3 & 0x7f) << 20)
475 | ((r2 & 0x7f) << 13)
476 | ((r1 & 0x7f) << 6)
477 | (qp & 0x3f);
478 }
479
480 static inline uint64_t tcg_opc_i10(int qp, uint64_t opc, int r1,
481 int r2, int r3, uint64_t count)
482 {
483 return opc
484 | ((count & 0x3f) << 27)
485 | ((r3 & 0x7f) << 20)
486 | ((r2 & 0x7f) << 13)
487 | ((r1 & 0x7f) << 6)
488 | (qp & 0x3f);
489 }
490
491 static inline uint64_t tcg_opc_i11(int qp, uint64_t opc, int r1,
492 int r3, uint64_t pos, uint64_t len)
493 {
494 return opc
495 | ((len & 0x3f) << 27)
496 | ((r3 & 0x7f) << 20)
497 | ((pos & 0x3f) << 14)
498 | ((r1 & 0x7f) << 6)
499 | (qp & 0x3f);
500 }
501
502 static inline uint64_t tcg_opc_i12(int qp, uint64_t opc, int r1,
503 int r2, uint64_t pos, uint64_t len)
504 {
505 return opc
506 | ((len & 0x3f) << 27)
507 | ((pos & 0x3f) << 20)
508 | ((r2 & 0x7f) << 13)
509 | ((r1 & 0x7f) << 6)
510 | (qp & 0x3f);
511 }
512
513 static inline uint64_t tcg_opc_i14(int qp, uint64_t opc, int r1, uint64_t imm,
514 int r3, uint64_t pos, uint64_t len)
515 {
516 return opc
517 | ((imm & 0x01) << 36)
518 | ((len & 0x3f) << 27)
519 | ((r3 & 0x7f) << 20)
520 | ((pos & 0x3f) << 14)
521 | ((r1 & 0x7f) << 6)
522 | (qp & 0x3f);
523 }
524
525 static inline uint64_t tcg_opc_i15(int qp, uint64_t opc, int r1, int r2,
526 int r3, uint64_t pos, uint64_t len)
527 {
528 return opc
529 | ((pos & 0x3f) << 31)
530 | ((len & 0x0f) << 27)
531 | ((r3 & 0x7f) << 20)
532 | ((r2 & 0x7f) << 13)
533 | ((r1 & 0x7f) << 6)
534 | (qp & 0x3f);
535 }
536
537 static inline uint64_t tcg_opc_i18(int qp, uint64_t opc, uint64_t imm)
538 {
539 return opc
540 | ((imm & 0x100000) << 16) /* i */
541 | ((imm & 0x0fffff) << 6) /* imm20a */
542 | (qp & 0x3f);
543 }
544
545 static inline uint64_t tcg_opc_i21(int qp, uint64_t opc, int b1,
546 int r2, uint64_t imm)
547 {
548 return opc
549 | ((imm & 0x1ff) << 24)
550 | ((r2 & 0x7f) << 13)
551 | ((b1 & 0x7) << 6)
552 | (qp & 0x3f);
553 }
554
555 static inline uint64_t tcg_opc_i22(int qp, uint64_t opc, int r1, int b2)
556 {
557 return opc
558 | ((b2 & 0x7) << 13)
559 | ((r1 & 0x7f) << 6)
560 | (qp & 0x3f);
561 }
562
563 static inline uint64_t tcg_opc_i26(int qp, uint64_t opc, int ar3, int r2)
564 {
565 return opc
566 | ((ar3 & 0x7f) << 20)
567 | ((r2 & 0x7f) << 13)
568 | (qp & 0x3f);
569 }
570
571 static inline uint64_t tcg_opc_i29(int qp, uint64_t opc, int r1, int r3)
572 {
573 return opc
574 | ((r3 & 0x7f) << 20)
575 | ((r1 & 0x7f) << 6)
576 | (qp & 0x3f);
577 }
578
579 static inline uint64_t tcg_opc_l2(uint64_t imm)
580 {
581 return (imm & 0x7fffffffffc00000ull) >> 22;
582 }
583
584 static inline uint64_t tcg_opc_l3(uint64_t imm)
585 {
586 return (imm & 0x07fffffffff00000ull) >> 18;
587 }
588
589 #define tcg_opc_l4 tcg_opc_l3
590
591 static inline uint64_t tcg_opc_m1(int qp, uint64_t opc, int r1, int r3)
592 {
593 return opc
594 | ((r3 & 0x7f) << 20)
595 | ((r1 & 0x7f) << 6)
596 | (qp & 0x3f);
597 }
598
599 static inline uint64_t tcg_opc_m3(int qp, uint64_t opc, int r1,
600 int r3, uint64_t imm)
601 {
602 return opc
603 | ((imm & 0x100) << 28) /* s */
604 | ((imm & 0x080) << 20) /* i */
605 | ((imm & 0x07f) << 13) /* imm7b */
606 | ((r3 & 0x7f) << 20)
607 | ((r1 & 0x7f) << 6)
608 | (qp & 0x3f);
609 }
610
611 static inline uint64_t tcg_opc_m4(int qp, uint64_t opc, int r2, int r3)
612 {
613 return opc
614 | ((r3 & 0x7f) << 20)
615 | ((r2 & 0x7f) << 13)
616 | (qp & 0x3f);
617 }
618
619 static inline uint64_t tcg_opc_m18(int qp, uint64_t opc, int f1, int r2)
620 {
621 return opc
622 | ((r2 & 0x7f) << 13)
623 | ((f1 & 0x7f) << 6)
624 | (qp & 0x3f);
625 }
626
627 static inline uint64_t tcg_opc_m19(int qp, uint64_t opc, int r1, int f2)
628 {
629 return opc
630 | ((f2 & 0x7f) << 13)
631 | ((r1 & 0x7f) << 6)
632 | (qp & 0x3f);
633 }
634
635 static inline uint64_t tcg_opc_m34(int qp, uint64_t opc, int r1,
636 int sof, int sol, int sor)
637 {
638 return opc
639 | ((sor & 0x0f) << 27)
640 | ((sol & 0x7f) << 20)
641 | ((sof & 0x7f) << 13)
642 | ((r1 & 0x7f) << 6)
643 | (qp & 0x3f);
644 }
645
646 static inline uint64_t tcg_opc_m48(int qp, uint64_t opc, uint64_t imm)
647 {
648 return opc
649 | ((imm & 0x100000) << 16) /* i */
650 | ((imm & 0x0fffff) << 6) /* imm20a */
651 | (qp & 0x3f);
652 }
653
654 static inline uint64_t tcg_opc_x2(int qp, uint64_t opc,
655 int r1, uint64_t imm)
656 {
657 return opc
658 | ((imm & 0x8000000000000000ull) >> 27) /* i */
659 | (imm & 0x0000000000200000ull) /* ic */
660 | ((imm & 0x00000000001f0000ull) << 6) /* imm5c */
661 | ((imm & 0x000000000000ff80ull) << 20) /* imm9d */
662 | ((imm & 0x000000000000007full) << 13) /* imm7b */
663 | ((r1 & 0x7f) << 6)
664 | (qp & 0x3f);
665 }
666
667 static inline uint64_t tcg_opc_x3(int qp, uint64_t opc, uint64_t imm)
668 {
669 return opc
670 | ((imm & 0x0800000000000000ull) >> 23) /* i */
671 | ((imm & 0x00000000000fffffull) << 13) /* imm20b */
672 | (qp & 0x3f);
673 }
674
675 static inline uint64_t tcg_opc_x4(int qp, uint64_t opc, int b1, uint64_t imm)
676 {
677 return opc
678 | ((imm & 0x0800000000000000ull) >> 23) /* i */
679 | ((imm & 0x00000000000fffffull) << 13) /* imm20b */
680 | ((b1 & 0x7) << 6)
681 | (qp & 0x3f);
682 }
683
684
685 /*
686 * Relocations
687 */
688
689 static inline void reloc_pcrel21b(void *pc, intptr_t target)
690 {
691 uint64_t imm;
692 int64_t disp;
693 int slot;
694
695 slot = (intptr_t)pc & 3;
696 pc = (void *)((intptr_t)pc & ~3);
697
698 disp = target - (intptr_t)pc;
699 imm = (uint64_t) disp >> 4;
700
701 switch(slot) {
702 case 0:
703 *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 8) & 0xfffffdc00003ffffull)
704 | ((imm & 0x100000) << 21) /* s */
705 | ((imm & 0x0fffff) << 18); /* imm20b */
706 break;
707 case 1:
708 *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xfffffffffffb8000ull)
709 | ((imm & 0x100000) >> 2) /* s */
710 | ((imm & 0x0fffe0) >> 5); /* imm20b */
711 *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 0) & 0x07ffffffffffffffull)
712 | ((imm & 0x00001f) << 59); /* imm20b */
713 break;
714 case 2:
715 *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xf700000fffffffffull)
716 | ((imm & 0x100000) << 39) /* s */
717 | ((imm & 0x0fffff) << 36); /* imm20b */
718 break;
719 }
720 }
721
722 static inline uint64_t get_reloc_pcrel21b (void *pc)
723 {
724 int64_t low, high;
725 int slot;
726
727 slot = (tcg_target_long) pc & 3;
728 pc = (void *)((tcg_target_long) pc & ~3);
729
730 low = (*(uint64_t *)(pc + 0));
731 high = (*(uint64_t *)(pc + 8));
732
733 switch(slot) {
734 case 0:
735 return ((low >> 21) & 0x100000) + /* s */
736 ((low >> 18) & 0x0fffff); /* imm20b */
737 case 1:
738 return ((high << 2) & 0x100000) + /* s */
739 ((high << 5) & 0x0fffe0) + /* imm20b */
740 ((low >> 59) & 0x00001f); /* imm20b */
741 case 2:
742 return ((high >> 39) & 0x100000) + /* s */
743 ((high >> 36) & 0x0fffff); /* imm20b */
744 default:
745 tcg_abort();
746 }
747 }
748
749 static inline void reloc_pcrel60b(void *pc, intptr_t target)
750 {
751 int64_t disp;
752 uint64_t imm;
753
754 disp = target - (intptr_t)pc;
755 imm = (uint64_t) disp >> 4;
756
757 *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xf700000fff800000ull)
758 | (imm & 0x0800000000000000ull) /* s */
759 | ((imm & 0x07fffff000000000ull) >> 36) /* imm39 */
760 | ((imm & 0x00000000000fffffull) << 36); /* imm20b */
761 *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 0) & 0x00003fffffffffffull)
762 | ((imm & 0x0000000ffff00000ull) << 28); /* imm39 */
763 }
764
765 static inline uint64_t get_reloc_pcrel60b (void *pc)
766 {
767 int64_t low, high;
768
769 low = (*(uint64_t *)(pc + 0));
770 high = (*(uint64_t *)(pc + 8));
771
772 return ((high) & 0x0800000000000000ull) + /* s */
773 ((high >> 36) & 0x00000000000fffffull) + /* imm20b */
774 ((high << 36) & 0x07fffff000000000ull) + /* imm39 */
775 ((low >> 28) & 0x0000000ffff00000ull); /* imm39 */
776 }
777
778
779 static void patch_reloc(uint8_t *code_ptr, int type,
780 intptr_t value, intptr_t addend)
781 {
782 value += addend;
783 switch (type) {
784 case R_IA64_PCREL21B:
785 reloc_pcrel21b(code_ptr, value);
786 break;
787 case R_IA64_PCREL60B:
788 reloc_pcrel60b(code_ptr, value);
789 default:
790 tcg_abort();
791 }
792 }
793
794 /*
795 * Constraints
796 */
797
798 /* parse target specific constraints */
799 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
800 {
801 const char *ct_str;
802
803 ct_str = *pct_str;
804 switch(ct_str[0]) {
805 case 'r':
806 ct->ct |= TCG_CT_REG;
807 tcg_regset_set(ct->u.regs, 0xffffffffffffffffull);
808 break;
809 case 'I':
810 ct->ct |= TCG_CT_CONST_S22;
811 break;
812 case 'S':
813 ct->ct |= TCG_CT_REG;
814 tcg_regset_set(ct->u.regs, 0xffffffffffffffffull);
815 #if defined(CONFIG_SOFTMMU)
816 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R56);
817 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R57);
818 #endif
819 break;
820 case 'Z':
821 /* We are cheating a bit here, using the fact that the register
822 r0 is also the register number 0. Hence there is no need
823 to check for const_args in each instruction. */
824 ct->ct |= TCG_CT_CONST_ZERO;
825 break;
826 default:
827 return -1;
828 }
829 ct_str++;
830 *pct_str = ct_str;
831 return 0;
832 }
833
834 /* test if a constant matches the constraint */
835 static inline int tcg_target_const_match(tcg_target_long val,
836 const TCGArgConstraint *arg_ct)
837 {
838 int ct;
839 ct = arg_ct->ct;
840 if (ct & TCG_CT_CONST)
841 return 1;
842 else if ((ct & TCG_CT_CONST_ZERO) && val == 0)
843 return 1;
844 else if ((ct & TCG_CT_CONST_S22) && val == ((int32_t)val << 10) >> 10)
845 return 1;
846 else
847 return 0;
848 }
849
850 /*
851 * Code generation
852 */
853
854 static uint8_t *tb_ret_addr;
855
856 static inline void tcg_out_bundle(TCGContext *s, int template,
857 uint64_t slot0, uint64_t slot1,
858 uint64_t slot2)
859 {
860 template &= 0x1f; /* 5 bits */
861 slot0 &= 0x1ffffffffffull; /* 41 bits */
862 slot1 &= 0x1ffffffffffull; /* 41 bits */
863 slot2 &= 0x1ffffffffffull; /* 41 bits */
864
865 *(uint64_t *)(s->code_ptr + 0) = (slot1 << 46) | (slot0 << 5) | template;
866 *(uint64_t *)(s->code_ptr + 8) = (slot2 << 23) | (slot1 >> 18);
867 s->code_ptr += 16;
868 }
869
870 static inline uint64_t tcg_opc_mov_a(int qp, TCGReg dst, TCGReg src)
871 {
872 return tcg_opc_a4(qp, OPC_ADDS_A4, dst, 0, src);
873 }
874
875 static inline void tcg_out_mov(TCGContext *s, TCGType type,
876 TCGReg ret, TCGReg arg)
877 {
878 tcg_out_bundle(s, mmI,
879 INSN_NOP_M,
880 INSN_NOP_M,
881 tcg_opc_mov_a(TCG_REG_P0, ret, arg));
882 }
883
884 static inline uint64_t tcg_opc_movi_a(int qp, TCGReg dst, int64_t src)
885 {
886 assert(src == sextract64(src, 0, 22));
887 return tcg_opc_a5(qp, OPC_ADDL_A5, dst, src, TCG_REG_R0);
888 }
889
890 static inline void tcg_out_movi(TCGContext *s, TCGType type,
891 TCGReg reg, tcg_target_long arg)
892 {
893 tcg_out_bundle(s, mLX,
894 INSN_NOP_M,
895 tcg_opc_l2 (arg),
896 tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2, reg, arg));
897 }
898
899 static void tcg_out_br(TCGContext *s, int label_index)
900 {
901 TCGLabel *l = &s->labels[label_index];
902
903 /* We pay attention here to not modify the branch target by reading
904 the existing value and using it again. This ensure that caches and
905 memory are kept coherent during retranslation. */
906 tcg_out_bundle(s, mmB,
907 INSN_NOP_M,
908 INSN_NOP_M,
909 tcg_opc_b1 (TCG_REG_P0, OPC_BR_SPTK_MANY_B1,
910 get_reloc_pcrel21b(s->code_ptr + 2)));
911
912 if (l->has_value) {
913 reloc_pcrel21b((s->code_ptr - 16) + 2, l->u.value);
914 } else {
915 tcg_out_reloc(s, (s->code_ptr - 16) + 2,
916 R_IA64_PCREL21B, label_index, 0);
917 }
918 }
919
920 static inline void tcg_out_calli(TCGContext *s, uintptr_t addr)
921 {
922 /* Look through the function descriptor. */
923 uintptr_t disp, *desc = (uintptr_t *)addr;
924 tcg_out_bundle(s, mlx,
925 INSN_NOP_M,
926 tcg_opc_l2 (desc[1]),
927 tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2, TCG_REG_R1, desc[1]));
928 disp = (desc[0] - (uintptr_t)s->code_ptr) >> 4;
929 tcg_out_bundle(s, mLX,
930 INSN_NOP_M,
931 tcg_opc_l4 (disp),
932 tcg_opc_x4 (TCG_REG_P0, OPC_BRL_CALL_SPTK_MANY_X4,
933 TCG_REG_B0, disp));
934 }
935
936 static inline void tcg_out_callr(TCGContext *s, TCGReg addr)
937 {
938 tcg_out_bundle(s, MmI,
939 tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, TCG_REG_R2, addr),
940 tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4, TCG_REG_R3, 8, addr),
941 tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21,
942 TCG_REG_B6, TCG_REG_R2, 0));
943 tcg_out_bundle(s, mmB,
944 tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R3),
945 INSN_NOP_M,
946 tcg_opc_b5 (TCG_REG_P0, OPC_BR_CALL_SPTK_MANY_B5,
947 TCG_REG_B0, TCG_REG_B6));
948 }
949
950 static void tcg_out_exit_tb(TCGContext *s, tcg_target_long arg)
951 {
952 int64_t disp;
953 uint64_t imm;
954
955 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R8, arg);
956
957 disp = tb_ret_addr - s->code_ptr;
958 imm = (uint64_t)disp >> 4;
959
960 tcg_out_bundle(s, mLX,
961 INSN_NOP_M,
962 tcg_opc_l3 (imm),
963 tcg_opc_x3 (TCG_REG_P0, OPC_BRL_SPTK_MANY_X3, imm));
964 }
965
966 static inline void tcg_out_goto_tb(TCGContext *s, TCGArg arg)
967 {
968 if (s->tb_jmp_offset) {
969 /* direct jump method */
970 tcg_abort();
971 } else {
972 /* indirect jump method */
973 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2,
974 (tcg_target_long)(s->tb_next + arg));
975 tcg_out_bundle(s, MmI,
976 tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1,
977 TCG_REG_R2, TCG_REG_R2),
978 INSN_NOP_M,
979 tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, TCG_REG_B6,
980 TCG_REG_R2, 0));
981 tcg_out_bundle(s, mmB,
982 INSN_NOP_M,
983 INSN_NOP_M,
984 tcg_opc_b4 (TCG_REG_P0, OPC_BR_SPTK_MANY_B4,
985 TCG_REG_B6));
986 }
987 s->tb_next_offset[arg] = s->code_ptr - s->code_buf;
988 }
989
990 static inline void tcg_out_jmp(TCGContext *s, TCGArg addr)
991 {
992 tcg_out_bundle(s, mmI,
993 INSN_NOP_M,
994 INSN_NOP_M,
995 tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, TCG_REG_B6, addr, 0));
996 tcg_out_bundle(s, mmB,
997 INSN_NOP_M,
998 INSN_NOP_M,
999 tcg_opc_b4(TCG_REG_P0, OPC_BR_SPTK_MANY_B4, TCG_REG_B6));
1000 }
1001
1002 static inline void tcg_out_ld_rel(TCGContext *s, uint64_t opc_m4, TCGArg arg,
1003 TCGArg arg1, tcg_target_long arg2)
1004 {
1005 if (arg2 == ((int16_t)arg2 >> 2) << 2) {
1006 tcg_out_bundle(s, MmI,
1007 tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4,
1008 TCG_REG_R2, arg2, arg1),
1009 tcg_opc_m1 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
1010 INSN_NOP_I);
1011 } else {
1012 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, arg2);
1013 tcg_out_bundle(s, MmI,
1014 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1,
1015 TCG_REG_R2, TCG_REG_R2, arg1),
1016 tcg_opc_m1 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
1017 INSN_NOP_I);
1018 }
1019 }
1020
1021 static inline void tcg_out_st_rel(TCGContext *s, uint64_t opc_m4, TCGArg arg,
1022 TCGArg arg1, tcg_target_long arg2)
1023 {
1024 if (arg2 == ((int16_t)arg2 >> 2) << 2) {
1025 tcg_out_bundle(s, MmI,
1026 tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4,
1027 TCG_REG_R2, arg2, arg1),
1028 tcg_opc_m4 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
1029 INSN_NOP_I);
1030 } else {
1031 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, arg2);
1032 tcg_out_bundle(s, MmI,
1033 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1,
1034 TCG_REG_R2, TCG_REG_R2, arg1),
1035 tcg_opc_m4 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
1036 INSN_NOP_I);
1037 }
1038 }
1039
1040 static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
1041 TCGReg arg1, intptr_t arg2)
1042 {
1043 if (type == TCG_TYPE_I32) {
1044 tcg_out_ld_rel(s, OPC_LD4_M1, arg, arg1, arg2);
1045 } else {
1046 tcg_out_ld_rel(s, OPC_LD8_M1, arg, arg1, arg2);
1047 }
1048 }
1049
1050 static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
1051 TCGReg arg1, intptr_t arg2)
1052 {
1053 if (type == TCG_TYPE_I32) {
1054 tcg_out_st_rel(s, OPC_ST4_M4, arg, arg1, arg2);
1055 } else {
1056 tcg_out_st_rel(s, OPC_ST8_M4, arg, arg1, arg2);
1057 }
1058 }
1059
1060 static inline void tcg_out_alu(TCGContext *s, uint64_t opc_a1, uint64_t opc_a3,
1061 TCGReg ret, TCGArg arg1, int const_arg1,
1062 TCGArg arg2, int const_arg2)
1063 {
1064 uint64_t opc1 = 0, opc2 = 0, opc3 = 0;
1065
1066 if (const_arg2 && arg2 != 0) {
1067 opc2 = tcg_opc_movi_a(TCG_REG_P0, TCG_REG_R3, arg2);
1068 arg2 = TCG_REG_R3;
1069 }
1070 if (const_arg1 && arg1 != 0) {
1071 if (opc_a3 && arg1 == (int8_t)arg1) {
1072 opc3 = tcg_opc_a3(TCG_REG_P0, opc_a3, ret, arg1, arg2);
1073 } else {
1074 opc1 = tcg_opc_movi_a(TCG_REG_P0, TCG_REG_R2, arg1);
1075 arg1 = TCG_REG_R2;
1076 }
1077 }
1078 if (opc3 == 0) {
1079 opc3 = tcg_opc_a1(TCG_REG_P0, opc_a1, ret, arg1, arg2);
1080 }
1081
1082 tcg_out_bundle(s, (opc1 || opc2 ? mII : miI),
1083 opc1 ? opc1 : INSN_NOP_M,
1084 opc2 ? opc2 : INSN_NOP_I,
1085 opc3);
1086 }
1087
1088 static inline void tcg_out_add(TCGContext *s, TCGReg ret, TCGReg arg1,
1089 TCGArg arg2, int const_arg2)
1090 {
1091 if (const_arg2 && arg2 == sextract64(arg2, 0, 14)) {
1092 tcg_out_bundle(s, mmI,
1093 INSN_NOP_M,
1094 INSN_NOP_M,
1095 tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, ret, arg2, arg1));
1096 } else {
1097 tcg_out_alu(s, OPC_ADD_A1, 0, ret, arg1, 0, arg2, const_arg2);
1098 }
1099 }
1100
1101 static inline void tcg_out_sub(TCGContext *s, TCGReg ret, TCGArg arg1,
1102 int const_arg1, TCGArg arg2, int const_arg2)
1103 {
1104 if (!const_arg1 && const_arg2 && -arg2 == sextract64(-arg2, 0, 14)) {
1105 tcg_out_bundle(s, mmI,
1106 INSN_NOP_M,
1107 INSN_NOP_M,
1108 tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, ret, -arg2, arg1));
1109 } else {
1110 tcg_out_alu(s, OPC_SUB_A1, OPC_SUB_A3, ret,
1111 arg1, const_arg1, arg2, const_arg2);
1112 }
1113 }
1114
1115 static inline void tcg_out_eqv(TCGContext *s, TCGArg ret,
1116 TCGArg arg1, int const_arg1,
1117 TCGArg arg2, int const_arg2)
1118 {
1119 tcg_out_bundle(s, mII,
1120 INSN_NOP_M,
1121 tcg_opc_a1 (TCG_REG_P0, OPC_XOR_A1, ret, arg1, arg2),
1122 tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
1123 }
1124
1125 static inline void tcg_out_nand(TCGContext *s, TCGArg ret,
1126 TCGArg arg1, int const_arg1,
1127 TCGArg arg2, int const_arg2)
1128 {
1129 tcg_out_bundle(s, mII,
1130 INSN_NOP_M,
1131 tcg_opc_a1 (TCG_REG_P0, OPC_AND_A1, ret, arg1, arg2),
1132 tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
1133 }
1134
1135 static inline void tcg_out_nor(TCGContext *s, TCGArg ret,
1136 TCGArg arg1, int const_arg1,
1137 TCGArg arg2, int const_arg2)
1138 {
1139 tcg_out_bundle(s, mII,
1140 INSN_NOP_M,
1141 tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, arg1, arg2),
1142 tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
1143 }
1144
1145 static inline void tcg_out_orc(TCGContext *s, TCGArg ret,
1146 TCGArg arg1, int const_arg1,
1147 TCGArg arg2, int const_arg2)
1148 {
1149 tcg_out_bundle(s, mII,
1150 INSN_NOP_M,
1151 tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, TCG_REG_R2, -1, arg2),
1152 tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, arg1, TCG_REG_R2));
1153 }
1154
1155 static inline void tcg_out_mul(TCGContext *s, TCGArg ret,
1156 TCGArg arg1, TCGArg arg2)
1157 {
1158 tcg_out_bundle(s, mmI,
1159 tcg_opc_m18(TCG_REG_P0, OPC_SETF_SIG_M18, TCG_REG_F6, arg1),
1160 tcg_opc_m18(TCG_REG_P0, OPC_SETF_SIG_M18, TCG_REG_F7, arg2),
1161 INSN_NOP_I);
1162 tcg_out_bundle(s, mmF,
1163 INSN_NOP_M,
1164 INSN_NOP_M,
1165 tcg_opc_f2 (TCG_REG_P0, OPC_XMA_L_F2, TCG_REG_F6, TCG_REG_F6,
1166 TCG_REG_F7, TCG_REG_F0));
1167 tcg_out_bundle(s, miI,
1168 tcg_opc_m19(TCG_REG_P0, OPC_GETF_SIG_M19, ret, TCG_REG_F6),
1169 INSN_NOP_I,
1170 INSN_NOP_I);
1171 }
1172
1173 static inline void tcg_out_sar_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1174 TCGArg arg2, int const_arg2)
1175 {
1176 if (const_arg2) {
1177 tcg_out_bundle(s, miI,
1178 INSN_NOP_M,
1179 INSN_NOP_I,
1180 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_I11,
1181 ret, arg1, arg2, 31 - arg2));
1182 } else {
1183 tcg_out_bundle(s, mII,
1184 tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3,
1185 TCG_REG_R3, 0x1f, arg2),
1186 tcg_opc_i29(TCG_REG_P0, OPC_SXT4_I29, TCG_REG_R2, arg1),
1187 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_I5, ret,
1188 TCG_REG_R2, TCG_REG_R3));
1189 }
1190 }
1191
1192 static inline void tcg_out_sar_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1193 TCGArg arg2, int const_arg2)
1194 {
1195 if (const_arg2) {
1196 tcg_out_bundle(s, miI,
1197 INSN_NOP_M,
1198 INSN_NOP_I,
1199 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_I11,
1200 ret, arg1, arg2, 63 - arg2));
1201 } else {
1202 tcg_out_bundle(s, miI,
1203 INSN_NOP_M,
1204 INSN_NOP_I,
1205 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_I5, ret, arg1, arg2));
1206 }
1207 }
1208
1209 static inline void tcg_out_shl_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1210 TCGArg arg2, int const_arg2)
1211 {
1212 if (const_arg2) {
1213 tcg_out_bundle(s, miI,
1214 INSN_NOP_M,
1215 INSN_NOP_I,
1216 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret,
1217 arg1, 63 - arg2, 31 - arg2));
1218 } else {
1219 tcg_out_bundle(s, mII,
1220 INSN_NOP_M,
1221 tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R2,
1222 0x1f, arg2),
1223 tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, ret,
1224 arg1, TCG_REG_R2));
1225 }
1226 }
1227
1228 static inline void tcg_out_shl_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1229 TCGArg arg2, int const_arg2)
1230 {
1231 if (const_arg2) {
1232 tcg_out_bundle(s, miI,
1233 INSN_NOP_M,
1234 INSN_NOP_I,
1235 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret,
1236 arg1, 63 - arg2, 63 - arg2));
1237 } else {
1238 tcg_out_bundle(s, miI,
1239 INSN_NOP_M,
1240 INSN_NOP_I,
1241 tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, ret,
1242 arg1, arg2));
1243 }
1244 }
1245
1246 static inline void tcg_out_shr_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1247 TCGArg arg2, int const_arg2)
1248 {
1249 if (const_arg2) {
1250 tcg_out_bundle(s, miI,
1251 INSN_NOP_M,
1252 INSN_NOP_I,
1253 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1254 arg1, arg2, 31 - arg2));
1255 } else {
1256 tcg_out_bundle(s, mII,
1257 tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3,
1258 0x1f, arg2),
1259 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, TCG_REG_R2, arg1),
1260 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1261 TCG_REG_R2, TCG_REG_R3));
1262 }
1263 }
1264
1265 static inline void tcg_out_shr_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1266 TCGArg arg2, int const_arg2)
1267 {
1268 if (const_arg2) {
1269 tcg_out_bundle(s, miI,
1270 INSN_NOP_M,
1271 INSN_NOP_I,
1272 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1273 arg1, arg2, 63 - arg2));
1274 } else {
1275 tcg_out_bundle(s, miI,
1276 INSN_NOP_M,
1277 INSN_NOP_I,
1278 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1279 arg1, arg2));
1280 }
1281 }
1282
1283 static inline void tcg_out_rotl_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1284 TCGArg arg2, int const_arg2)
1285 {
1286 if (const_arg2) {
1287 tcg_out_bundle(s, mII,
1288 INSN_NOP_M,
1289 tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1290 TCG_REG_R2, arg1, arg1),
1291 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1292 TCG_REG_R2, 32 - arg2, 31));
1293 } else {
1294 tcg_out_bundle(s, miI,
1295 INSN_NOP_M,
1296 tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1297 TCG_REG_R2, arg1, arg1),
1298 tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3,
1299 0x1f, arg2));
1300 tcg_out_bundle(s, mII,
1301 INSN_NOP_M,
1302 tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R3,
1303 0x20, TCG_REG_R3),
1304 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1305 TCG_REG_R2, TCG_REG_R3));
1306 }
1307 }
1308
1309 static inline void tcg_out_rotl_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1310 TCGArg arg2, int const_arg2)
1311 {
1312 if (const_arg2) {
1313 tcg_out_bundle(s, miI,
1314 INSN_NOP_M,
1315 INSN_NOP_I,
1316 tcg_opc_i10(TCG_REG_P0, OPC_SHRP_I10, ret, arg1,
1317 arg1, 0x40 - arg2));
1318 } else {
1319 tcg_out_bundle(s, mII,
1320 tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R2,
1321 0x40, arg2),
1322 tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, TCG_REG_R3,
1323 arg1, arg2),
1324 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, TCG_REG_R2,
1325 arg1, TCG_REG_R2));
1326 tcg_out_bundle(s, miI,
1327 INSN_NOP_M,
1328 INSN_NOP_I,
1329 tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret,
1330 TCG_REG_R2, TCG_REG_R3));
1331 }
1332 }
1333
1334 static inline void tcg_out_rotr_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1335 TCGArg arg2, int const_arg2)
1336 {
1337 if (const_arg2) {
1338 tcg_out_bundle(s, mII,
1339 INSN_NOP_M,
1340 tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1341 TCG_REG_R2, arg1, arg1),
1342 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1343 TCG_REG_R2, arg2, 31));
1344 } else {
1345 tcg_out_bundle(s, mII,
1346 tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3,
1347 0x1f, arg2),
1348 tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1349 TCG_REG_R2, arg1, arg1),
1350 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1351 TCG_REG_R2, TCG_REG_R3));
1352 }
1353 }
1354
1355 static inline void tcg_out_rotr_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1356 TCGArg arg2, int const_arg2)
1357 {
1358 if (const_arg2) {
1359 tcg_out_bundle(s, miI,
1360 INSN_NOP_M,
1361 INSN_NOP_I,
1362 tcg_opc_i10(TCG_REG_P0, OPC_SHRP_I10, ret, arg1,
1363 arg1, arg2));
1364 } else {
1365 tcg_out_bundle(s, mII,
1366 tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R2,
1367 0x40, arg2),
1368 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, TCG_REG_R3,
1369 arg1, arg2),
1370 tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, TCG_REG_R2,
1371 arg1, TCG_REG_R2));
1372 tcg_out_bundle(s, miI,
1373 INSN_NOP_M,
1374 INSN_NOP_I,
1375 tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret,
1376 TCG_REG_R2, TCG_REG_R3));
1377 }
1378 }
1379
1380 static inline void tcg_out_ext(TCGContext *s, uint64_t opc_i29,
1381 TCGArg ret, TCGArg arg)
1382 {
1383 tcg_out_bundle(s, miI,
1384 INSN_NOP_M,
1385 INSN_NOP_I,
1386 tcg_opc_i29(TCG_REG_P0, opc_i29, ret, arg));
1387 }
1388
1389 static inline void tcg_out_bswap16(TCGContext *s, TCGArg ret, TCGArg arg)
1390 {
1391 tcg_out_bundle(s, mII,
1392 INSN_NOP_M,
1393 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, arg, 15, 15),
1394 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, ret, 0xb));
1395 }
1396
1397 static inline void tcg_out_bswap32(TCGContext *s, TCGArg ret, TCGArg arg)
1398 {
1399 tcg_out_bundle(s, mII,
1400 INSN_NOP_M,
1401 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, arg, 31, 31),
1402 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, ret, 0xb));
1403 }
1404
1405 static inline void tcg_out_bswap64(TCGContext *s, TCGArg ret, TCGArg arg)
1406 {
1407 tcg_out_bundle(s, miI,
1408 INSN_NOP_M,
1409 INSN_NOP_I,
1410 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, arg, 0xb));
1411 }
1412
1413 static inline void tcg_out_deposit(TCGContext *s, TCGArg ret, TCGArg a1,
1414 TCGArg a2, int const_a2, int pos, int len)
1415 {
1416 uint64_t i1 = 0, i2 = 0;
1417 int cpos = 63 - pos, lm1 = len - 1;
1418
1419 if (const_a2) {
1420 /* Truncate the value of a constant a2 to the width of the field. */
1421 int mask = (1u << len) - 1;
1422 a2 &= mask;
1423
1424 if (a2 == 0 || a2 == mask) {
1425 /* 1-bit signed constant inserted into register. */
1426 i2 = tcg_opc_i14(TCG_REG_P0, OPC_DEP_I14, ret, a2, a1, cpos, lm1);
1427 } else {
1428 /* Otherwise, load any constant into a temporary. Do this into
1429 the first I slot to help out with cross-unit delays. */
1430 i1 = tcg_opc_movi_a(TCG_REG_P0, TCG_REG_R2, a2);
1431 a2 = TCG_REG_R2;
1432 }
1433 }
1434 if (i2 == 0) {
1435 i2 = tcg_opc_i15(TCG_REG_P0, OPC_DEP_I15, ret, a2, a1, cpos, lm1);
1436 }
1437 tcg_out_bundle(s, (i1 ? mII : miI),
1438 INSN_NOP_M,
1439 i1 ? i1 : INSN_NOP_I,
1440 i2);
1441 }
1442
1443 static inline uint64_t tcg_opc_cmp_a(int qp, TCGCond cond, TCGArg arg1,
1444 TCGArg arg2, int cmp4)
1445 {
1446 uint64_t opc_eq_a6, opc_lt_a6, opc_ltu_a6;
1447
1448 if (cmp4) {
1449 opc_eq_a6 = OPC_CMP4_EQ_A6;
1450 opc_lt_a6 = OPC_CMP4_LT_A6;
1451 opc_ltu_a6 = OPC_CMP4_LTU_A6;
1452 } else {
1453 opc_eq_a6 = OPC_CMP_EQ_A6;
1454 opc_lt_a6 = OPC_CMP_LT_A6;
1455 opc_ltu_a6 = OPC_CMP_LTU_A6;
1456 }
1457
1458 switch (cond) {
1459 case TCG_COND_EQ:
1460 return tcg_opc_a6 (qp, opc_eq_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2);
1461 case TCG_COND_NE:
1462 return tcg_opc_a6 (qp, opc_eq_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2);
1463 case TCG_COND_LT:
1464 return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2);
1465 case TCG_COND_LTU:
1466 return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2);
1467 case TCG_COND_GE:
1468 return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2);
1469 case TCG_COND_GEU:
1470 return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2);
1471 case TCG_COND_LE:
1472 return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P7, TCG_REG_P6, arg2, arg1);
1473 case TCG_COND_LEU:
1474 return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P7, TCG_REG_P6, arg2, arg1);
1475 case TCG_COND_GT:
1476 return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P6, TCG_REG_P7, arg2, arg1);
1477 case TCG_COND_GTU:
1478 return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P6, TCG_REG_P7, arg2, arg1);
1479 default:
1480 tcg_abort();
1481 break;
1482 }
1483 }
1484
1485 static inline void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1,
1486 TCGReg arg2, int label_index, int cmp4)
1487 {
1488 TCGLabel *l = &s->labels[label_index];
1489
1490 tcg_out_bundle(s, miB,
1491 INSN_NOP_M,
1492 tcg_opc_cmp_a(TCG_REG_P0, cond, arg1, arg2, cmp4),
1493 tcg_opc_b1(TCG_REG_P6, OPC_BR_DPTK_FEW_B1,
1494 get_reloc_pcrel21b(s->code_ptr + 2)));
1495
1496 if (l->has_value) {
1497 reloc_pcrel21b((s->code_ptr - 16) + 2, l->u.value);
1498 } else {
1499 tcg_out_reloc(s, (s->code_ptr - 16) + 2,
1500 R_IA64_PCREL21B, label_index, 0);
1501 }
1502 }
1503
1504 static inline void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGArg ret,
1505 TCGArg arg1, TCGArg arg2, int cmp4)
1506 {
1507 tcg_out_bundle(s, MmI,
1508 tcg_opc_cmp_a(TCG_REG_P0, cond, arg1, arg2, cmp4),
1509 tcg_opc_movi_a(TCG_REG_P6, ret, 1),
1510 tcg_opc_movi_a(TCG_REG_P7, ret, 0));
1511 }
1512
1513 static inline void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGArg ret,
1514 TCGArg c1, TCGArg c2,
1515 TCGArg v1, int const_v1,
1516 TCGArg v2, int const_v2, int cmp4)
1517 {
1518 uint64_t opc1, opc2;
1519
1520 if (const_v1) {
1521 opc1 = tcg_opc_movi_a(TCG_REG_P6, ret, v1);
1522 } else if (ret == v1) {
1523 opc1 = INSN_NOP_M;
1524 } else {
1525 opc1 = tcg_opc_mov_a(TCG_REG_P6, ret, v1);
1526 }
1527 if (const_v2) {
1528 opc2 = tcg_opc_movi_a(TCG_REG_P7, ret, v2);
1529 } else if (ret == v2) {
1530 opc2 = INSN_NOP_I;
1531 } else {
1532 opc2 = tcg_opc_mov_a(TCG_REG_P7, ret, v2);
1533 }
1534
1535 tcg_out_bundle(s, MmI,
1536 tcg_opc_cmp_a(TCG_REG_P0, cond, c1, c2, cmp4),
1537 opc1,
1538 opc2);
1539 }
1540
1541 #if defined(CONFIG_SOFTMMU)
1542 /* Load and compare a TLB entry, and return the result in (p6, p7).
1543 R2 is loaded with the address of the addend TLB entry.
1544 R57 is loaded with the address, zero extented on 32-bit targets. */
1545 static inline void tcg_out_qemu_tlb(TCGContext *s, TCGArg addr_reg,
1546 TCGMemOp s_bits, uint64_t offset_rw,
1547 uint64_t offset_addend)
1548 {
1549 tcg_out_bundle(s, mII,
1550 INSN_NOP_M,
1551 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, TCG_REG_R2,
1552 addr_reg, TARGET_PAGE_BITS, CPU_TLB_BITS - 1),
1553 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, TCG_REG_R2,
1554 TCG_REG_R2, 63 - CPU_TLB_ENTRY_BITS,
1555 63 - CPU_TLB_ENTRY_BITS));
1556 tcg_out_bundle(s, mII,
1557 tcg_opc_a5 (TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R2,
1558 offset_rw, TCG_REG_R2),
1559 #if TARGET_LONG_BITS == 32
1560 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, TCG_REG_R57, addr_reg),
1561 #else
1562 tcg_opc_mov_a(TCG_REG_P0, TCG_REG_R57, addr_reg),
1563 #endif
1564 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1565 TCG_REG_R2, TCG_AREG0));
1566 tcg_out_bundle(s, mII,
1567 tcg_opc_m3 (TCG_REG_P0,
1568 (TARGET_LONG_BITS == 32
1569 ? OPC_LD4_M3 : OPC_LD8_M3), TCG_REG_R56,
1570 TCG_REG_R2, offset_addend - offset_rw),
1571 tcg_opc_i14(TCG_REG_P0, OPC_DEP_I14, TCG_REG_R3, 0,
1572 TCG_REG_R57, 63 - s_bits,
1573 TARGET_PAGE_BITS - s_bits - 1),
1574 tcg_opc_a6 (TCG_REG_P0, OPC_CMP_EQ_A6, TCG_REG_P6,
1575 TCG_REG_P7, TCG_REG_R3, TCG_REG_R56));
1576 }
1577
1578 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
1579 int mmu_idx) */
1580 static const void * const qemu_ld_helpers[4] = {
1581 helper_ldb_mmu,
1582 helper_ldw_mmu,
1583 helper_ldl_mmu,
1584 helper_ldq_mmu,
1585 };
1586
1587 static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
1588 TCGMemOp opc)
1589 {
1590 static const uint64_t opc_ld_m1[4] = {
1591 OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1
1592 };
1593 static const uint64_t opc_ext_i29[8] = {
1594 OPC_ZXT1_I29, OPC_ZXT2_I29, OPC_ZXT4_I29, 0,
1595 OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0
1596 };
1597 int addr_reg, data_reg, mem_index;
1598 TCGMemOp s_bits, bswap;
1599
1600 data_reg = *args++;
1601 addr_reg = *args++;
1602 mem_index = *args;
1603 s_bits = opc & MO_SIZE;
1604 bswap = opc & MO_BSWAP;
1605
1606 /* Read the TLB entry */
1607 tcg_out_qemu_tlb(s, addr_reg, s_bits,
1608 offsetof(CPUArchState, tlb_table[mem_index][0].addr_read),
1609 offsetof(CPUArchState, tlb_table[mem_index][0].addend));
1610
1611 /* P6 is the fast path, and P7 the slow path */
1612 tcg_out_bundle(s, mLX,
1613 tcg_opc_mov_a(TCG_REG_P7, TCG_REG_R56, TCG_AREG0),
1614 tcg_opc_l2 ((tcg_target_long) qemu_ld_helpers[s_bits]),
1615 tcg_opc_x2 (TCG_REG_P7, OPC_MOVL_X2, TCG_REG_R2,
1616 (tcg_target_long) qemu_ld_helpers[s_bits]));
1617 tcg_out_bundle(s, MmI,
1618 tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R3,
1619 TCG_REG_R2, 8),
1620 tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R3,
1621 TCG_REG_R3, TCG_REG_R57),
1622 tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6,
1623 TCG_REG_R3, 0));
1624 if (bswap && s_bits == MO_16) {
1625 tcg_out_bundle(s, MmI,
1626 tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits],
1627 TCG_REG_R8, TCG_REG_R3),
1628 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
1629 tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
1630 TCG_REG_R8, TCG_REG_R8, 15, 15));
1631 } else if (bswap && s_bits == MO_32) {
1632 tcg_out_bundle(s, MmI,
1633 tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits],
1634 TCG_REG_R8, TCG_REG_R3),
1635 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
1636 tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
1637 TCG_REG_R8, TCG_REG_R8, 31, 31));
1638 } else {
1639 tcg_out_bundle(s, mmI,
1640 tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits],
1641 TCG_REG_R8, TCG_REG_R3),
1642 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
1643 INSN_NOP_I);
1644 }
1645 if (!bswap) {
1646 tcg_out_bundle(s, miB,
1647 tcg_opc_movi_a(TCG_REG_P7, TCG_REG_R58, mem_index),
1648 INSN_NOP_I,
1649 tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
1650 TCG_REG_B0, TCG_REG_B6));
1651 } else {
1652 tcg_out_bundle(s, miB,
1653 tcg_opc_movi_a(TCG_REG_P7, TCG_REG_R58, mem_index),
1654 tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1655 TCG_REG_R8, TCG_REG_R8, 0xb),
1656 tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
1657 TCG_REG_B0, TCG_REG_B6));
1658 }
1659
1660 if (s_bits == MO_64) {
1661 tcg_out_bundle(s, miI,
1662 INSN_NOP_M,
1663 INSN_NOP_I,
1664 tcg_opc_mov_a(TCG_REG_P0, data_reg, TCG_REG_R8));
1665 } else {
1666 tcg_out_bundle(s, miI,
1667 INSN_NOP_M,
1668 INSN_NOP_I,
1669 tcg_opc_i29(TCG_REG_P0, opc_ext_i29[opc & MO_SSIZE],
1670 data_reg, TCG_REG_R8));
1671 }
1672 }
1673
1674 /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
1675 uintxx_t val, int mmu_idx) */
1676 static const void * const qemu_st_helpers[4] = {
1677 helper_stb_mmu,
1678 helper_stw_mmu,
1679 helper_stl_mmu,
1680 helper_stq_mmu,
1681 };
1682
1683 static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
1684 TCGMemOp opc)
1685 {
1686 static const uint64_t opc_st_m4[4] = {
1687 OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4
1688 };
1689 int addr_reg, data_reg, mem_index;
1690 TCGMemOp s_bits;
1691
1692 data_reg = *args++;
1693 addr_reg = *args++;
1694 mem_index = *args;
1695 s_bits = opc & MO_SIZE;
1696
1697 tcg_out_qemu_tlb(s, addr_reg, s_bits,
1698 offsetof(CPUArchState, tlb_table[mem_index][0].addr_write),
1699 offsetof(CPUArchState, tlb_table[mem_index][0].addend));
1700
1701 /* P6 is the fast path, and P7 the slow path */
1702 tcg_out_bundle(s, mLX,
1703 tcg_opc_mov_a(TCG_REG_P7, TCG_REG_R56, TCG_AREG0),
1704 tcg_opc_l2 ((tcg_target_long) qemu_st_helpers[s_bits]),
1705 tcg_opc_x2 (TCG_REG_P7, OPC_MOVL_X2, TCG_REG_R2,
1706 (tcg_target_long) qemu_st_helpers[s_bits]));
1707 tcg_out_bundle(s, MmI,
1708 tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R3,
1709 TCG_REG_R2, 8),
1710 tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R3,
1711 TCG_REG_R3, TCG_REG_R57),
1712 tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6,
1713 TCG_REG_R3, 0));
1714
1715 switch (opc) {
1716 case MO_8:
1717 case MO_16:
1718 case MO_32:
1719 case MO_64:
1720 tcg_out_bundle(s, mii,
1721 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1722 TCG_REG_R1, TCG_REG_R2),
1723 tcg_opc_mov_a(TCG_REG_P7, TCG_REG_R58, data_reg),
1724 INSN_NOP_I);
1725 break;
1726
1727 case MO_16 | MO_BSWAP:
1728 tcg_out_bundle(s, miI,
1729 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1730 TCG_REG_R1, TCG_REG_R2),
1731 INSN_NOP_I,
1732 tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
1733 TCG_REG_R2, data_reg, 15, 15));
1734 tcg_out_bundle(s, miI,
1735 tcg_opc_mov_a(TCG_REG_P7, TCG_REG_R58, data_reg),
1736 INSN_NOP_I,
1737 tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1738 TCG_REG_R2, TCG_REG_R2, 0xb));
1739 data_reg = TCG_REG_R2;
1740 break;
1741
1742 case MO_32 | MO_BSWAP:
1743 tcg_out_bundle(s, miI,
1744 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1745 TCG_REG_R1, TCG_REG_R2),
1746 INSN_NOP_I,
1747 tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
1748 TCG_REG_R2, data_reg, 31, 31));
1749 tcg_out_bundle(s, miI,
1750 tcg_opc_mov_a(TCG_REG_P7, TCG_REG_R58, data_reg),
1751 INSN_NOP_I,
1752 tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1753 TCG_REG_R2, TCG_REG_R2, 0xb));
1754 data_reg = TCG_REG_R2;
1755 break;
1756
1757 case MO_64 | MO_BSWAP:
1758 tcg_out_bundle(s, miI,
1759 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1760 TCG_REG_R1, TCG_REG_R2),
1761 tcg_opc_mov_a(TCG_REG_P7, TCG_REG_R58, data_reg),
1762 tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1763 TCG_REG_R2, data_reg, 0xb));
1764 data_reg = TCG_REG_R2;
1765 break;
1766
1767 default:
1768 tcg_abort();
1769 }
1770
1771 tcg_out_bundle(s, miB,
1772 tcg_opc_m4 (TCG_REG_P6, opc_st_m4[s_bits],
1773 data_reg, TCG_REG_R3),
1774 tcg_opc_movi_a(TCG_REG_P7, TCG_REG_R59, mem_index),
1775 tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
1776 TCG_REG_B0, TCG_REG_B6));
1777 }
1778
1779 #else /* !CONFIG_SOFTMMU */
1780
1781 static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
1782 TCGMemOp opc)
1783 {
1784 static uint64_t const opc_ld_m1[4] = {
1785 OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1
1786 };
1787 static uint64_t const opc_sxt_i29[4] = {
1788 OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0
1789 };
1790 int addr_reg, data_reg;
1791 TCGMemOp s_bits, bswap;
1792
1793 data_reg = *args++;
1794 addr_reg = *args++;
1795 s_bits = opc & MO_SIZE;
1796 bswap = opc & MO_BSWAP;
1797
1798 #if TARGET_LONG_BITS == 32
1799 if (GUEST_BASE != 0) {
1800 tcg_out_bundle(s, mII,
1801 INSN_NOP_M,
1802 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
1803 TCG_REG_R3, addr_reg),
1804 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1805 TCG_GUEST_BASE_REG, TCG_REG_R3));
1806 } else {
1807 tcg_out_bundle(s, miI,
1808 INSN_NOP_M,
1809 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
1810 TCG_REG_R2, addr_reg),
1811 INSN_NOP_I);
1812 }
1813
1814 if (!bswap) {
1815 if (!(opc & MO_SIGN)) {
1816 tcg_out_bundle(s, miI,
1817 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1818 data_reg, TCG_REG_R2),
1819 INSN_NOP_I,
1820 INSN_NOP_I);
1821 } else {
1822 tcg_out_bundle(s, mII,
1823 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1824 data_reg, TCG_REG_R2),
1825 INSN_NOP_I,
1826 tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits],
1827 data_reg, data_reg));
1828 }
1829 } else if (s_bits == MO_64) {
1830 tcg_out_bundle(s, mII,
1831 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1832 data_reg, TCG_REG_R2),
1833 INSN_NOP_I,
1834 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1835 data_reg, data_reg, 0xb));
1836 } else {
1837 if (s_bits == MO_16) {
1838 tcg_out_bundle(s, mII,
1839 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1840 data_reg, TCG_REG_R2),
1841 INSN_NOP_I,
1842 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1843 data_reg, data_reg, 15, 15));
1844 } else {
1845 tcg_out_bundle(s, mII,
1846 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1847 data_reg, TCG_REG_R2),
1848 INSN_NOP_I,
1849 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1850 data_reg, data_reg, 31, 31));
1851 }
1852 if (!(opc & MO_SIGN)) {
1853 tcg_out_bundle(s, miI,
1854 INSN_NOP_M,
1855 INSN_NOP_I,
1856 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1857 data_reg, data_reg, 0xb));
1858 } else {
1859 tcg_out_bundle(s, mII,
1860 INSN_NOP_M,
1861 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1862 data_reg, data_reg, 0xb),
1863 tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits],
1864 data_reg, data_reg));
1865 }
1866 }
1867 #else
1868 if (GUEST_BASE != 0) {
1869 tcg_out_bundle(s, MmI,
1870 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1871 TCG_GUEST_BASE_REG, addr_reg),
1872 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1873 data_reg, TCG_REG_R2),
1874 INSN_NOP_I);
1875 } else {
1876 tcg_out_bundle(s, mmI,
1877 INSN_NOP_M,
1878 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1879 data_reg, addr_reg),
1880 INSN_NOP_I);
1881 }
1882
1883 if (bswap && s_bits == MO_16) {
1884 tcg_out_bundle(s, mII,
1885 INSN_NOP_M,
1886 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1887 data_reg, data_reg, 15, 15),
1888 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1889 data_reg, data_reg, 0xb));
1890 } else if (bswap && s_bits == MO_32) {
1891 tcg_out_bundle(s, mII,
1892 INSN_NOP_M,
1893 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1894 data_reg, data_reg, 31, 31),
1895 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1896 data_reg, data_reg, 0xb));
1897 } else if (bswap && s_bits == MO_64) {
1898 tcg_out_bundle(s, miI,
1899 INSN_NOP_M,
1900 INSN_NOP_I,
1901 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1902 data_reg, data_reg, 0xb));
1903 }
1904 if (opc & MO_SIGN) {
1905 tcg_out_bundle(s, miI,
1906 INSN_NOP_M,
1907 INSN_NOP_I,
1908 tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits],
1909 data_reg, data_reg));
1910 }
1911 #endif
1912 }
1913
1914 static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
1915 TCGMemOp opc)
1916 {
1917 static uint64_t const opc_st_m4[4] = {
1918 OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4
1919 };
1920 int addr_reg, data_reg;
1921 #if TARGET_LONG_BITS == 64
1922 uint64_t add_guest_base;
1923 #endif
1924 TCGMemOp s_bits, bswap;
1925
1926 data_reg = *args++;
1927 addr_reg = *args++;
1928 s_bits = opc & MO_SIZE;
1929 bswap = opc & MO_BSWAP;
1930
1931 #if TARGET_LONG_BITS == 32
1932 if (GUEST_BASE != 0) {
1933 tcg_out_bundle(s, mII,
1934 INSN_NOP_M,
1935 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
1936 TCG_REG_R3, addr_reg),
1937 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1938 TCG_GUEST_BASE_REG, TCG_REG_R3));
1939 } else {
1940 tcg_out_bundle(s, miI,
1941 INSN_NOP_M,
1942 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
1943 TCG_REG_R2, addr_reg),
1944 INSN_NOP_I);
1945 }
1946
1947 if (bswap) {
1948 if (s_bits == MO_16) {
1949 tcg_out_bundle(s, mII,
1950 INSN_NOP_M,
1951 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1952 TCG_REG_R3, data_reg, 15, 15),
1953 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1954 TCG_REG_R3, TCG_REG_R3, 0xb));
1955 data_reg = TCG_REG_R3;
1956 } else if (s_bits == MO_32) {
1957 tcg_out_bundle(s, mII,
1958 INSN_NOP_M,
1959 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1960 TCG_REG_R3, data_reg, 31, 31),
1961 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1962 TCG_REG_R3, TCG_REG_R3, 0xb));
1963 data_reg = TCG_REG_R3;
1964 } else if (s_bits == MO_64) {
1965 tcg_out_bundle(s, miI,
1966 INSN_NOP_M,
1967 INSN_NOP_I,
1968 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1969 TCG_REG_R3, data_reg, 0xb));
1970 data_reg = TCG_REG_R3;
1971 }
1972 }
1973 tcg_out_bundle(s, mmI,
1974 tcg_opc_m4 (TCG_REG_P0, opc_st_m4[s_bits],
1975 data_reg, TCG_REG_R2),
1976 INSN_NOP_M,
1977 INSN_NOP_I);
1978 #else
1979 if (GUEST_BASE != 0) {
1980 add_guest_base = tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1981 TCG_GUEST_BASE_REG, addr_reg);
1982 addr_reg = TCG_REG_R2;
1983 } else {
1984 add_guest_base = INSN_NOP_M;
1985 }
1986
1987 if (!bswap) {
1988 tcg_out_bundle(s, (GUEST_BASE ? MmI : mmI),
1989 add_guest_base,
1990 tcg_opc_m4 (TCG_REG_P0, opc_st_m4[s_bits],
1991 data_reg, addr_reg),
1992 INSN_NOP_I);
1993 } else {
1994 if (s_bits == MO_16) {
1995 tcg_out_bundle(s, mII,
1996 add_guest_base,
1997 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1998 TCG_REG_R3, data_reg, 15, 15),
1999 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
2000 TCG_REG_R3, TCG_REG_R3, 0xb));
2001 data_reg = TCG_REG_R3;
2002 } else if (s_bits == MO_32) {
2003 tcg_out_bundle(s, mII,
2004 add_guest_base,
2005 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
2006 TCG_REG_R3, data_reg, 31, 31),
2007 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
2008 TCG_REG_R3, TCG_REG_R3, 0xb));
2009 data_reg = TCG_REG_R3;
2010 } else if (s_bits == MO_64) {
2011 tcg_out_bundle(s, miI,
2012 add_guest_base,
2013 INSN_NOP_I,
2014 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
2015 TCG_REG_R3, data_reg, 0xb));
2016 data_reg = TCG_REG_R3;
2017 }
2018 tcg_out_bundle(s, miI,
2019 tcg_opc_m4 (TCG_REG_P0, opc_st_m4[s_bits],
2020 data_reg, addr_reg),
2021 INSN_NOP_I,
2022 INSN_NOP_I);
2023 }
2024 #endif
2025 }
2026
2027 #endif
2028
2029 static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
2030 const TCGArg *args, const int *const_args)
2031 {
2032 switch(opc) {
2033 case INDEX_op_exit_tb:
2034 tcg_out_exit_tb(s, args[0]);
2035 break;
2036 case INDEX_op_br:
2037 tcg_out_br(s, args[0]);
2038 break;
2039 case INDEX_op_call:
2040 if (likely(const_args[0])) {
2041 tcg_out_calli(s, args[0]);
2042 } else {
2043 tcg_out_callr(s, args[0]);
2044 }
2045 break;
2046 case INDEX_op_goto_tb:
2047 tcg_out_goto_tb(s, args[0]);
2048 break;
2049
2050 case INDEX_op_movi_i32:
2051 tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
2052 break;
2053 case INDEX_op_movi_i64:
2054 tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
2055 break;
2056
2057 case INDEX_op_ld8u_i32:
2058 case INDEX_op_ld8u_i64:
2059 tcg_out_ld_rel(s, OPC_LD1_M1, args[0], args[1], args[2]);
2060 break;
2061 case INDEX_op_ld8s_i32:
2062 case INDEX_op_ld8s_i64:
2063 tcg_out_ld_rel(s, OPC_LD1_M1, args[0], args[1], args[2]);
2064 tcg_out_ext(s, OPC_SXT1_I29, args[0], args[0]);
2065 break;
2066 case INDEX_op_ld16u_i32:
2067 case INDEX_op_ld16u_i64:
2068 tcg_out_ld_rel(s, OPC_LD2_M1, args[0], args[1], args[2]);
2069 break;
2070 case INDEX_op_ld16s_i32:
2071 case INDEX_op_ld16s_i64:
2072 tcg_out_ld_rel(s, OPC_LD2_M1, args[0], args[1], args[2]);
2073 tcg_out_ext(s, OPC_SXT2_I29, args[0], args[0]);
2074 break;
2075 case INDEX_op_ld_i32:
2076 case INDEX_op_ld32u_i64:
2077 tcg_out_ld_rel(s, OPC_LD4_M1, args[0], args[1], args[2]);
2078 break;
2079 case INDEX_op_ld32s_i64:
2080 tcg_out_ld_rel(s, OPC_LD4_M1, args[0], args[1], args[2]);
2081 tcg_out_ext(s, OPC_SXT4_I29, args[0], args[0]);
2082 break;
2083 case INDEX_op_ld_i64:
2084 tcg_out_ld_rel(s, OPC_LD8_M1, args[0], args[1], args[2]);
2085 break;
2086 case INDEX_op_st8_i32:
2087 case INDEX_op_st8_i64:
2088 tcg_out_st_rel(s, OPC_ST1_M4, args[0], args[1], args[2]);
2089 break;
2090 case INDEX_op_st16_i32:
2091 case INDEX_op_st16_i64:
2092 tcg_out_st_rel(s, OPC_ST2_M4, args[0], args[1], args[2]);
2093 break;
2094 case INDEX_op_st_i32:
2095 case INDEX_op_st32_i64:
2096 tcg_out_st_rel(s, OPC_ST4_M4, args[0], args[1], args[2]);
2097 break;
2098 case INDEX_op_st_i64:
2099 tcg_out_st_rel(s, OPC_ST8_M4, args[0], args[1], args[2]);
2100 break;
2101
2102 case INDEX_op_add_i32:
2103 case INDEX_op_add_i64:
2104 tcg_out_add(s, args[0], args[1], args[2], const_args[2]);
2105 break;
2106 case INDEX_op_sub_i32:
2107 case INDEX_op_sub_i64:
2108 tcg_out_sub(s, args[0], args[1], const_args[1], args[2], const_args[2]);
2109 break;
2110
2111 case INDEX_op_and_i32:
2112 case INDEX_op_and_i64:
2113 /* TCG expects arg2 constant; A3 expects arg1 constant. Swap. */
2114 tcg_out_alu(s, OPC_AND_A1, OPC_AND_A3, args[0],
2115 args[2], const_args[2], args[1], const_args[1]);
2116 break;
2117 case INDEX_op_andc_i32:
2118 case INDEX_op_andc_i64:
2119 tcg_out_alu(s, OPC_ANDCM_A1, OPC_ANDCM_A3, args[0],
2120 args[1], const_args[1], args[2], const_args[2]);
2121 break;
2122 case INDEX_op_eqv_i32:
2123 case INDEX_op_eqv_i64:
2124 tcg_out_eqv(s, args[0], args[1], const_args[1],
2125 args[2], const_args[2]);
2126 break;
2127 case INDEX_op_nand_i32:
2128 case INDEX_op_nand_i64:
2129 tcg_out_nand(s, args[0], args[1], const_args[1],
2130 args[2], const_args[2]);
2131 break;
2132 case INDEX_op_nor_i32:
2133 case INDEX_op_nor_i64:
2134 tcg_out_nor(s, args[0], args[1], const_args[1],
2135 args[2], const_args[2]);
2136 break;
2137 case INDEX_op_or_i32:
2138 case INDEX_op_or_i64:
2139 /* TCG expects arg2 constant; A3 expects arg1 constant. Swap. */
2140 tcg_out_alu(s, OPC_OR_A1, OPC_OR_A3, args[0],
2141 args[2], const_args[2], args[1], const_args[1]);
2142 break;
2143 case INDEX_op_orc_i32:
2144 case INDEX_op_orc_i64:
2145 tcg_out_orc(s, args[0], args[1], const_args[1],
2146 args[2], const_args[2]);
2147 break;
2148 case INDEX_op_xor_i32:
2149 case INDEX_op_xor_i64:
2150 /* TCG expects arg2 constant; A3 expects arg1 constant. Swap. */
2151 tcg_out_alu(s, OPC_XOR_A1, OPC_XOR_A3, args[0],
2152 args[2], const_args[2], args[1], const_args[1]);
2153 break;
2154
2155 case INDEX_op_mul_i32:
2156 case INDEX_op_mul_i64:
2157 tcg_out_mul(s, args[0], args[1], args[2]);
2158 break;
2159
2160 case INDEX_op_sar_i32:
2161 tcg_out_sar_i32(s, args[0], args[1], args[2], const_args[2]);
2162 break;
2163 case INDEX_op_sar_i64:
2164 tcg_out_sar_i64(s, args[0], args[1], args[2], const_args[2]);
2165 break;
2166 case INDEX_op_shl_i32:
2167 tcg_out_shl_i32(s, args[0], args[1], args[2], const_args[2]);
2168 break;
2169 case INDEX_op_shl_i64:
2170 tcg_out_shl_i64(s, args[0], args[1], args[2], const_args[2]);
2171 break;
2172 case INDEX_op_shr_i32:
2173 tcg_out_shr_i32(s, args[0], args[1], args[2], const_args[2]);
2174 break;
2175 case INDEX_op_shr_i64:
2176 tcg_out_shr_i64(s, args[0], args[1], args[2], const_args[2]);
2177 break;
2178 case INDEX_op_rotl_i32:
2179 tcg_out_rotl_i32(s, args[0], args[1], args[2], const_args[2]);
2180 break;
2181 case INDEX_op_rotl_i64:
2182 tcg_out_rotl_i64(s, args[0], args[1], args[2], const_args[2]);
2183 break;
2184 case INDEX_op_rotr_i32:
2185 tcg_out_rotr_i32(s, args[0], args[1], args[2], const_args[2]);
2186 break;
2187 case INDEX_op_rotr_i64:
2188 tcg_out_rotr_i64(s, args[0], args[1], args[2], const_args[2]);
2189 break;
2190
2191 case INDEX_op_ext8s_i32:
2192 case INDEX_op_ext8s_i64:
2193 tcg_out_ext(s, OPC_SXT1_I29, args[0], args[1]);
2194 break;
2195 case INDEX_op_ext8u_i32:
2196 case INDEX_op_ext8u_i64:
2197 tcg_out_ext(s, OPC_ZXT1_I29, args[0], args[1]);
2198 break;
2199 case INDEX_op_ext16s_i32:
2200 case INDEX_op_ext16s_i64:
2201 tcg_out_ext(s, OPC_SXT2_I29, args[0], args[1]);
2202 break;
2203 case INDEX_op_ext16u_i32:
2204 case INDEX_op_ext16u_i64:
2205 tcg_out_ext(s, OPC_ZXT2_I29, args[0], args[1]);
2206 break;
2207 case INDEX_op_ext32s_i64:
2208 tcg_out_ext(s, OPC_SXT4_I29, args[0], args[1]);
2209 break;
2210 case INDEX_op_ext32u_i64:
2211 tcg_out_ext(s, OPC_ZXT4_I29, args[0], args[1]);
2212 break;
2213
2214 case INDEX_op_bswap16_i32:
2215 case INDEX_op_bswap16_i64:
2216 tcg_out_bswap16(s, args[0], args[1]);
2217 break;
2218 case INDEX_op_bswap32_i32:
2219 case INDEX_op_bswap32_i64:
2220 tcg_out_bswap32(s, args[0], args[1]);
2221 break;
2222 case INDEX_op_bswap64_i64:
2223 tcg_out_bswap64(s, args[0], args[1]);
2224 break;
2225
2226 case INDEX_op_deposit_i32:
2227 case INDEX_op_deposit_i64:
2228 tcg_out_deposit(s, args[0], args[1], args[2], const_args[2],
2229 args[3], args[4]);
2230 break;
2231
2232 case INDEX_op_brcond_i32:
2233 tcg_out_brcond(s, args[2], args[0], args[1], args[3], 1);
2234 break;
2235 case INDEX_op_brcond_i64:
2236 tcg_out_brcond(s, args[2], args[0], args[1], args[3], 0);
2237 break;
2238 case INDEX_op_setcond_i32:
2239 tcg_out_setcond(s, args[3], args[0], args[1], args[2], 1);
2240 break;
2241 case INDEX_op_setcond_i64:
2242 tcg_out_setcond(s, args[3], args[0], args[1], args[2], 0);
2243 break;
2244 case INDEX_op_movcond_i32:
2245 tcg_out_movcond(s, args[5], args[0], args[1], args[2],
2246 args[3], const_args[3], args[4], const_args[4], 1);
2247 break;
2248 case INDEX_op_movcond_i64:
2249 tcg_out_movcond(s, args[5], args[0], args[1], args[2],
2250 args[3], const_args[3], args[4], const_args[4], 0);
2251 break;
2252
2253 case INDEX_op_qemu_ld8u:
2254 tcg_out_qemu_ld(s, args, MO_UB);
2255 break;
2256 case INDEX_op_qemu_ld8s:
2257 tcg_out_qemu_ld(s, args, MO_SB);
2258 break;
2259 case INDEX_op_qemu_ld16u:
2260 tcg_out_qemu_ld(s, args, MO_TEUW);
2261 break;
2262 case INDEX_op_qemu_ld16s:
2263 tcg_out_qemu_ld(s, args, MO_TESW);
2264 break;
2265 case INDEX_op_qemu_ld32:
2266 case INDEX_op_qemu_ld32u:
2267 tcg_out_qemu_ld(s, args, MO_TEUL);
2268 break;
2269 case INDEX_op_qemu_ld32s:
2270 tcg_out_qemu_ld(s, args, MO_TESL);
2271 break;
2272 case INDEX_op_qemu_ld64:
2273 tcg_out_qemu_ld(s, args, MO_TEQ);
2274 break;
2275
2276 case INDEX_op_qemu_st8:
2277 tcg_out_qemu_st(s, args, MO_UB);
2278 break;
2279 case INDEX_op_qemu_st16:
2280 tcg_out_qemu_st(s, args, MO_TEUW);
2281 break;
2282 case INDEX_op_qemu_st32:
2283 tcg_out_qemu_st(s, args, MO_TEUL);
2284 break;
2285 case INDEX_op_qemu_st64:
2286 tcg_out_qemu_st(s, args, MO_TEQ);
2287 break;
2288
2289 default:
2290 tcg_abort();
2291 }
2292 }
2293
2294 static const TCGTargetOpDef ia64_op_defs[] = {
2295 { INDEX_op_br, { } },
2296 { INDEX_op_call, { "ri" } },
2297 { INDEX_op_exit_tb, { } },
2298 { INDEX_op_goto_tb, { } },
2299
2300 { INDEX_op_mov_i32, { "r", "r" } },
2301 { INDEX_op_movi_i32, { "r" } },
2302
2303 { INDEX_op_ld8u_i32, { "r", "r" } },
2304 { INDEX_op_ld8s_i32, { "r", "r" } },
2305 { INDEX_op_ld16u_i32, { "r", "r" } },
2306 { INDEX_op_ld16s_i32, { "r", "r" } },
2307 { INDEX_op_ld_i32, { "r", "r" } },
2308 { INDEX_op_st8_i32, { "rZ", "r" } },
2309 { INDEX_op_st16_i32, { "rZ", "r" } },
2310 { INDEX_op_st_i32, { "rZ", "r" } },
2311
2312 { INDEX_op_add_i32, { "r", "rZ", "rI" } },
2313 { INDEX_op_sub_i32, { "r", "rI", "rI" } },
2314
2315 { INDEX_op_and_i32, { "r", "rI", "rI" } },
2316 { INDEX_op_andc_i32, { "r", "rI", "rI" } },
2317 { INDEX_op_eqv_i32, { "r", "rZ", "rZ" } },
2318 { INDEX_op_nand_i32, { "r", "rZ", "rZ" } },
2319 { INDEX_op_nor_i32, { "r", "rZ", "rZ" } },
2320 { INDEX_op_or_i32, { "r", "rI", "rI" } },
2321 { INDEX_op_orc_i32, { "r", "rZ", "rZ" } },
2322 { INDEX_op_xor_i32, { "r", "rI", "rI" } },
2323
2324 { INDEX_op_mul_i32, { "r", "rZ", "rZ" } },
2325
2326 { INDEX_op_sar_i32, { "r", "rZ", "ri" } },
2327 { INDEX_op_shl_i32, { "r", "rZ", "ri" } },
2328 { INDEX_op_shr_i32, { "r", "rZ", "ri" } },
2329 { INDEX_op_rotl_i32, { "r", "rZ", "ri" } },
2330 { INDEX_op_rotr_i32, { "r", "rZ", "ri" } },
2331
2332 { INDEX_op_ext8s_i32, { "r", "rZ"} },
2333 { INDEX_op_ext8u_i32, { "r", "rZ"} },
2334 { INDEX_op_ext16s_i32, { "r", "rZ"} },
2335 { INDEX_op_ext16u_i32, { "r", "rZ"} },
2336
2337 { INDEX_op_bswap16_i32, { "r", "rZ" } },
2338 { INDEX_op_bswap32_i32, { "r", "rZ" } },
2339
2340 { INDEX_op_brcond_i32, { "rZ", "rZ" } },
2341 { INDEX_op_setcond_i32, { "r", "rZ", "rZ" } },
2342 { INDEX_op_movcond_i32, { "r", "rZ", "rZ", "rI", "rI" } },
2343
2344 { INDEX_op_mov_i64, { "r", "r" } },
2345 { INDEX_op_movi_i64, { "r" } },
2346
2347 { INDEX_op_ld8u_i64, { "r", "r" } },
2348 { INDEX_op_ld8s_i64, { "r", "r" } },
2349 { INDEX_op_ld16u_i64, { "r", "r" } },
2350 { INDEX_op_ld16s_i64, { "r", "r" } },
2351 { INDEX_op_ld32u_i64, { "r", "r" } },
2352 { INDEX_op_ld32s_i64, { "r", "r" } },
2353 { INDEX_op_ld_i64, { "r", "r" } },
2354 { INDEX_op_st8_i64, { "rZ", "r" } },
2355 { INDEX_op_st16_i64, { "rZ", "r" } },
2356 { INDEX_op_st32_i64, { "rZ", "r" } },
2357 { INDEX_op_st_i64, { "rZ", "r" } },
2358
2359 { INDEX_op_add_i64, { "r", "rZ", "rI" } },
2360 { INDEX_op_sub_i64, { "r", "rI", "rI" } },
2361
2362 { INDEX_op_and_i64, { "r", "rI", "rI" } },
2363 { INDEX_op_andc_i64, { "r", "rI", "rI" } },
2364 { INDEX_op_eqv_i64, { "r", "rZ", "rZ" } },
2365 { INDEX_op_nand_i64, { "r", "rZ", "rZ" } },
2366 { INDEX_op_nor_i64, { "r", "rZ", "rZ" } },
2367 { INDEX_op_or_i64, { "r", "rI", "rI" } },
2368 { INDEX_op_orc_i64, { "r", "rZ", "rZ" } },
2369 { INDEX_op_xor_i64, { "r", "rI", "rI" } },
2370
2371 { INDEX_op_mul_i64, { "r", "rZ", "rZ" } },
2372
2373 { INDEX_op_sar_i64, { "r", "rZ", "ri" } },
2374 { INDEX_op_shl_i64, { "r", "rZ", "ri" } },
2375 { INDEX_op_shr_i64, { "r", "rZ", "ri" } },
2376 { INDEX_op_rotl_i64, { "r", "rZ", "ri" } },
2377 { INDEX_op_rotr_i64, { "r", "rZ", "ri" } },
2378
2379 { INDEX_op_ext8s_i64, { "r", "rZ"} },
2380 { INDEX_op_ext8u_i64, { "r", "rZ"} },
2381 { INDEX_op_ext16s_i64, { "r", "rZ"} },
2382 { INDEX_op_ext16u_i64, { "r", "rZ"} },
2383 { INDEX_op_ext32s_i64, { "r", "rZ"} },
2384 { INDEX_op_ext32u_i64, { "r", "rZ"} },
2385
2386 { INDEX_op_bswap16_i64, { "r", "rZ" } },
2387 { INDEX_op_bswap32_i64, { "r", "rZ" } },
2388 { INDEX_op_bswap64_i64, { "r", "rZ" } },
2389
2390 { INDEX_op_brcond_i64, { "rZ", "rZ" } },
2391 { INDEX_op_setcond_i64, { "r", "rZ", "rZ" } },
2392 { INDEX_op_movcond_i64, { "r", "rZ", "rZ", "rI", "rI" } },
2393
2394 { INDEX_op_deposit_i32, { "r", "rZ", "ri" } },
2395 { INDEX_op_deposit_i64, { "r", "rZ", "ri" } },
2396
2397 { INDEX_op_qemu_ld8u, { "r", "r" } },
2398 { INDEX_op_qemu_ld8s, { "r", "r" } },
2399 { INDEX_op_qemu_ld16u, { "r", "r" } },
2400 { INDEX_op_qemu_ld16s, { "r", "r" } },
2401 { INDEX_op_qemu_ld32, { "r", "r" } },
2402 { INDEX_op_qemu_ld32u, { "r", "r" } },
2403 { INDEX_op_qemu_ld32s, { "r", "r" } },
2404 { INDEX_op_qemu_ld64, { "r", "r" } },
2405
2406 { INDEX_op_qemu_st8, { "SZ", "r" } },
2407 { INDEX_op_qemu_st16, { "SZ", "r" } },
2408 { INDEX_op_qemu_st32, { "SZ", "r" } },
2409 { INDEX_op_qemu_st64, { "SZ", "r" } },
2410
2411 { -1 },
2412 };
2413
2414 /* Generate global QEMU prologue and epilogue code */
2415 static void tcg_target_qemu_prologue(TCGContext *s)
2416 {
2417 int frame_size;
2418
2419 /* reserve some stack space */
2420 frame_size = TCG_STATIC_CALL_ARGS_SIZE +
2421 CPU_TEMP_BUF_NLONGS * sizeof(long);
2422 frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
2423 ~(TCG_TARGET_STACK_ALIGN - 1);
2424 tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE,
2425 CPU_TEMP_BUF_NLONGS * sizeof(long));
2426
2427 /* First emit adhoc function descriptor */
2428 *(uint64_t *)(s->code_ptr) = (uint64_t)s->code_ptr + 16; /* entry point */
2429 s->code_ptr += 16; /* skip GP */
2430
2431 /* prologue */
2432 tcg_out_bundle(s, miI,
2433 tcg_opc_m34(TCG_REG_P0, OPC_ALLOC_M34,
2434 TCG_REG_R34, 32, 24, 0),
2435 INSN_NOP_I,
2436 tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21,
2437 TCG_REG_B6, TCG_REG_R33, 0));
2438
2439 /* ??? If GUEST_BASE < 0x200000, we could load the register via
2440 an ADDL in the M slot of the next bundle. */
2441 if (GUEST_BASE != 0) {
2442 tcg_out_bundle(s, mlx,
2443 INSN_NOP_M,
2444 tcg_opc_l2 (GUEST_BASE),
2445 tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2,
2446 TCG_GUEST_BASE_REG, GUEST_BASE));
2447 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
2448 }
2449
2450 tcg_out_bundle(s, miB,
2451 tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4,
2452 TCG_REG_R12, -frame_size, TCG_REG_R12),
2453 tcg_opc_i22(TCG_REG_P0, OPC_MOV_I22,
2454 TCG_REG_R33, TCG_REG_B0),
2455 tcg_opc_b4 (TCG_REG_P0, OPC_BR_SPTK_MANY_B4, TCG_REG_B6));
2456
2457 /* epilogue */
2458 tb_ret_addr = s->code_ptr;
2459 tcg_out_bundle(s, miI,
2460 INSN_NOP_M,
2461 tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21,
2462 TCG_REG_B0, TCG_REG_R33, 0),
2463 tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4,
2464 TCG_REG_R12, frame_size, TCG_REG_R12));
2465 tcg_out_bundle(s, miB,
2466 INSN_NOP_M,
2467 tcg_opc_i26(TCG_REG_P0, OPC_MOV_I_I26,
2468 TCG_REG_PFS, TCG_REG_R34),
2469 tcg_opc_b4 (TCG_REG_P0, OPC_BR_RET_SPTK_MANY_B4,
2470 TCG_REG_B0));
2471 }
2472
2473 static void tcg_target_init(TCGContext *s)
2474 {
2475 tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I32],
2476 0xffffffffffffffffull);
2477 tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I64],
2478 0xffffffffffffffffull);
2479
2480 tcg_regset_clear(tcg_target_call_clobber_regs);
2481 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8);
2482 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9);
2483 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10);
2484 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11);
2485 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14);
2486 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R15);
2487 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R16);
2488 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R17);
2489 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R18);
2490 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R19);
2491 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R20);
2492 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R21);
2493 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R22);
2494 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R23);
2495 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R24);
2496 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R25);
2497 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R26);
2498 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R27);
2499 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R28);
2500 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R29);
2501 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R30);
2502 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R31);
2503 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R56);
2504 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R57);
2505 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R58);
2506 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R59);
2507 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R60);
2508 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R61);
2509 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R62);
2510 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R63);
2511
2512 tcg_regset_clear(s->reserved_regs);
2513 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* zero register */
2514 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* global pointer */
2515 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* internal use */
2516 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R3); /* internal use */
2517 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R12); /* stack pointer */
2518 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */
2519 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R33); /* return address */
2520 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R34); /* PFS */
2521
2522 /* The following 4 are not in use, are call-saved, but *not* saved
2523 by the prologue. Therefore we cannot use them without modifying
2524 the prologue. There doesn't seem to be any good reason to use
2525 these as opposed to the windowed registers. */
2526 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R4);
2527 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R5);
2528 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R6);
2529 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R7);
2530
2531 tcg_add_target_add_op_defs(ia64_op_defs);
2532 }
Qemu copy for testing