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target-openrisc: Removes a non-conforming behavior for the first page of the memory
[qemu.git] / tcg / mips / tcg-target.c
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
6 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
27 #if defined(TCG_TARGET_WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN)
28 # define TCG_NEED_BSWAP 0
29 #else
30 # define TCG_NEED_BSWAP 1
31 #endif
32
33 #ifndef NDEBUG
34 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
35 "zero",
36 "at",
37 "v0",
38 "v1",
39 "a0",
40 "a1",
41 "a2",
42 "a3",
43 "t0",
44 "t1",
45 "t2",
46 "t3",
47 "t4",
48 "t5",
49 "t6",
50 "t7",
51 "s0",
52 "s1",
53 "s2",
54 "s3",
55 "s4",
56 "s5",
57 "s6",
58 "s7",
59 "t8",
60 "t9",
61 "k0",
62 "k1",
63 "gp",
64 "sp",
65 "fp",
66 "ra",
67 };
68 #endif
69
70 /* check if we really need so many registers :P */
71 static const TCGReg tcg_target_reg_alloc_order[] = {
72 TCG_REG_S0,
73 TCG_REG_S1,
74 TCG_REG_S2,
75 TCG_REG_S3,
76 TCG_REG_S4,
77 TCG_REG_S5,
78 TCG_REG_S6,
79 TCG_REG_S7,
80 TCG_REG_T1,
81 TCG_REG_T2,
82 TCG_REG_T3,
83 TCG_REG_T4,
84 TCG_REG_T5,
85 TCG_REG_T6,
86 TCG_REG_T7,
87 TCG_REG_T8,
88 TCG_REG_T9,
89 TCG_REG_A0,
90 TCG_REG_A1,
91 TCG_REG_A2,
92 TCG_REG_A3,
93 TCG_REG_V0,
94 TCG_REG_V1
95 };
96
97 static const TCGReg tcg_target_call_iarg_regs[4] = {
98 TCG_REG_A0,
99 TCG_REG_A1,
100 TCG_REG_A2,
101 TCG_REG_A3
102 };
103
104 static const TCGReg tcg_target_call_oarg_regs[2] = {
105 TCG_REG_V0,
106 TCG_REG_V1
107 };
108
109 static uint8_t *tb_ret_addr;
110
111 static inline uint32_t reloc_lo16_val(void *pc, intptr_t target)
112 {
113 return target & 0xffff;
114 }
115
116 static inline void reloc_lo16(void *pc, intptr_t target)
117 {
118 *(uint32_t *) pc = (*(uint32_t *) pc & ~0xffff)
119 | reloc_lo16_val(pc, target);
120 }
121
122 static inline uint32_t reloc_hi16_val(void *pc, intptr_t target)
123 {
124 return (target >> 16) & 0xffff;
125 }
126
127 static inline void reloc_hi16(void *pc, intptr_t target)
128 {
129 *(uint32_t *) pc = (*(uint32_t *) pc & ~0xffff)
130 | reloc_hi16_val(pc, target);
131 }
132
133 static inline uint32_t reloc_pc16_val(void *pc, intptr_t target)
134 {
135 int32_t disp;
136
137 disp = target - (intptr_t)pc - 4;
138 if (disp != (disp << 14) >> 14) {
139 tcg_abort ();
140 }
141
142 return (disp >> 2) & 0xffff;
143 }
144
145 static inline void reloc_pc16 (void *pc, tcg_target_long target)
146 {
147 *(uint32_t *) pc = (*(uint32_t *) pc & ~0xffff)
148 | reloc_pc16_val(pc, target);
149 }
150
151 static inline uint32_t reloc_26_val (void *pc, tcg_target_long target)
152 {
153 if ((((tcg_target_long)pc + 4) & 0xf0000000) != (target & 0xf0000000)) {
154 tcg_abort ();
155 }
156
157 return (target >> 2) & 0x3ffffff;
158 }
159
160 static inline void reloc_pc26(void *pc, intptr_t target)
161 {
162 *(uint32_t *) pc = (*(uint32_t *) pc & ~0x3ffffff)
163 | reloc_26_val(pc, target);
164 }
165
166 static void patch_reloc(uint8_t *code_ptr, int type,
167 intptr_t value, intptr_t addend)
168 {
169 value += addend;
170 switch(type) {
171 case R_MIPS_LO16:
172 reloc_lo16(code_ptr, value);
173 break;
174 case R_MIPS_HI16:
175 reloc_hi16(code_ptr, value);
176 break;
177 case R_MIPS_PC16:
178 reloc_pc16(code_ptr, value);
179 break;
180 case R_MIPS_26:
181 reloc_pc26(code_ptr, value);
182 break;
183 default:
184 tcg_abort();
185 }
186 }
187
188 /* parse target specific constraints */
189 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
190 {
191 const char *ct_str;
192
193 ct_str = *pct_str;
194 switch(ct_str[0]) {
195 case 'r':
196 ct->ct |= TCG_CT_REG;
197 tcg_regset_set(ct->u.regs, 0xffffffff);
198 break;
199 case 'C':
200 ct->ct |= TCG_CT_REG;
201 tcg_regset_clear(ct->u.regs);
202 tcg_regset_set_reg(ct->u.regs, TCG_REG_T9);
203 break;
204 case 'L': /* qemu_ld output arg constraint */
205 ct->ct |= TCG_CT_REG;
206 tcg_regset_set(ct->u.regs, 0xffffffff);
207 tcg_regset_reset_reg(ct->u.regs, TCG_REG_V0);
208 break;
209 case 'l': /* qemu_ld input arg constraint */
210 ct->ct |= TCG_CT_REG;
211 tcg_regset_set(ct->u.regs, 0xffffffff);
212 #if defined(CONFIG_SOFTMMU)
213 tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0);
214 # if (TARGET_LONG_BITS == 64)
215 tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2);
216 # endif
217 #endif
218 break;
219 case 'S': /* qemu_st constraint */
220 ct->ct |= TCG_CT_REG;
221 tcg_regset_set(ct->u.regs, 0xffffffff);
222 tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0);
223 #if defined(CONFIG_SOFTMMU)
224 # if (TARGET_LONG_BITS == 32)
225 tcg_regset_reset_reg(ct->u.regs, TCG_REG_A1);
226 # endif
227 tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2);
228 # if TARGET_LONG_BITS == 64
229 tcg_regset_reset_reg(ct->u.regs, TCG_REG_A3);
230 # endif
231 #endif
232 break;
233 case 'I':
234 ct->ct |= TCG_CT_CONST_U16;
235 break;
236 case 'J':
237 ct->ct |= TCG_CT_CONST_S16;
238 break;
239 case 'Z':
240 /* We are cheating a bit here, using the fact that the register
241 ZERO is also the register number 0. Hence there is no need
242 to check for const_args in each instruction. */
243 ct->ct |= TCG_CT_CONST_ZERO;
244 break;
245 default:
246 return -1;
247 }
248 ct_str++;
249 *pct_str = ct_str;
250 return 0;
251 }
252
253 /* test if a constant matches the constraint */
254 static inline int tcg_target_const_match(tcg_target_long val,
255 const TCGArgConstraint *arg_ct)
256 {
257 int ct;
258 ct = arg_ct->ct;
259 if (ct & TCG_CT_CONST)
260 return 1;
261 else if ((ct & TCG_CT_CONST_ZERO) && val == 0)
262 return 1;
263 else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val)
264 return 1;
265 else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val)
266 return 1;
267 else
268 return 0;
269 }
270
271 /* instruction opcodes */
272 enum {
273 OPC_BEQ = 0x04 << 26,
274 OPC_BNE = 0x05 << 26,
275 OPC_BLEZ = 0x06 << 26,
276 OPC_BGTZ = 0x07 << 26,
277 OPC_ADDIU = 0x09 << 26,
278 OPC_SLTI = 0x0A << 26,
279 OPC_SLTIU = 0x0B << 26,
280 OPC_ANDI = 0x0C << 26,
281 OPC_ORI = 0x0D << 26,
282 OPC_XORI = 0x0E << 26,
283 OPC_LUI = 0x0F << 26,
284 OPC_LB = 0x20 << 26,
285 OPC_LH = 0x21 << 26,
286 OPC_LW = 0x23 << 26,
287 OPC_LBU = 0x24 << 26,
288 OPC_LHU = 0x25 << 26,
289 OPC_LWU = 0x27 << 26,
290 OPC_SB = 0x28 << 26,
291 OPC_SH = 0x29 << 26,
292 OPC_SW = 0x2B << 26,
293
294 OPC_SPECIAL = 0x00 << 26,
295 OPC_SLL = OPC_SPECIAL | 0x00,
296 OPC_SRL = OPC_SPECIAL | 0x02,
297 OPC_ROTR = OPC_SPECIAL | (0x01 << 21) | 0x02,
298 OPC_SRA = OPC_SPECIAL | 0x03,
299 OPC_SLLV = OPC_SPECIAL | 0x04,
300 OPC_SRLV = OPC_SPECIAL | 0x06,
301 OPC_ROTRV = OPC_SPECIAL | (0x01 << 6) | 0x06,
302 OPC_SRAV = OPC_SPECIAL | 0x07,
303 OPC_JR = OPC_SPECIAL | 0x08,
304 OPC_JALR = OPC_SPECIAL | 0x09,
305 OPC_MOVZ = OPC_SPECIAL | 0x0A,
306 OPC_MOVN = OPC_SPECIAL | 0x0B,
307 OPC_MFHI = OPC_SPECIAL | 0x10,
308 OPC_MFLO = OPC_SPECIAL | 0x12,
309 OPC_MULT = OPC_SPECIAL | 0x18,
310 OPC_MULTU = OPC_SPECIAL | 0x19,
311 OPC_DIV = OPC_SPECIAL | 0x1A,
312 OPC_DIVU = OPC_SPECIAL | 0x1B,
313 OPC_ADDU = OPC_SPECIAL | 0x21,
314 OPC_SUBU = OPC_SPECIAL | 0x23,
315 OPC_AND = OPC_SPECIAL | 0x24,
316 OPC_OR = OPC_SPECIAL | 0x25,
317 OPC_XOR = OPC_SPECIAL | 0x26,
318 OPC_NOR = OPC_SPECIAL | 0x27,
319 OPC_SLT = OPC_SPECIAL | 0x2A,
320 OPC_SLTU = OPC_SPECIAL | 0x2B,
321
322 OPC_REGIMM = 0x01 << 26,
323 OPC_BLTZ = OPC_REGIMM | (0x00 << 16),
324 OPC_BGEZ = OPC_REGIMM | (0x01 << 16),
325
326 OPC_SPECIAL2 = 0x1c << 26,
327 OPC_MUL = OPC_SPECIAL2 | 0x002,
328
329 OPC_SPECIAL3 = 0x1f << 26,
330 OPC_INS = OPC_SPECIAL3 | 0x004,
331 OPC_WSBH = OPC_SPECIAL3 | 0x0a0,
332 OPC_SEB = OPC_SPECIAL3 | 0x420,
333 OPC_SEH = OPC_SPECIAL3 | 0x620,
334 };
335
336 /*
337 * Type reg
338 */
339 static inline void tcg_out_opc_reg(TCGContext *s, int opc,
340 TCGReg rd, TCGReg rs, TCGReg rt)
341 {
342 int32_t inst;
343
344 inst = opc;
345 inst |= (rs & 0x1F) << 21;
346 inst |= (rt & 0x1F) << 16;
347 inst |= (rd & 0x1F) << 11;
348 tcg_out32(s, inst);
349 }
350
351 /*
352 * Type immediate
353 */
354 static inline void tcg_out_opc_imm(TCGContext *s, int opc,
355 TCGReg rt, TCGReg rs, TCGArg imm)
356 {
357 int32_t inst;
358
359 inst = opc;
360 inst |= (rs & 0x1F) << 21;
361 inst |= (rt & 0x1F) << 16;
362 inst |= (imm & 0xffff);
363 tcg_out32(s, inst);
364 }
365
366 /*
367 * Type branch
368 */
369 static inline void tcg_out_opc_br(TCGContext *s, int opc,
370 TCGReg rt, TCGReg rs)
371 {
372 /* We pay attention here to not modify the branch target by reading
373 the existing value and using it again. This ensure that caches and
374 memory are kept coherent during retranslation. */
375 uint16_t offset = (uint16_t)(*(uint32_t *) s->code_ptr);
376
377 tcg_out_opc_imm(s, opc, rt, rs, offset);
378 }
379
380 /*
381 * Type sa
382 */
383 static inline void tcg_out_opc_sa(TCGContext *s, int opc,
384 TCGReg rd, TCGReg rt, TCGArg sa)
385 {
386 int32_t inst;
387
388 inst = opc;
389 inst |= (rt & 0x1F) << 16;
390 inst |= (rd & 0x1F) << 11;
391 inst |= (sa & 0x1F) << 6;
392 tcg_out32(s, inst);
393
394 }
395
396 static inline void tcg_out_nop(TCGContext *s)
397 {
398 tcg_out32(s, 0);
399 }
400
401 static inline void tcg_out_mov(TCGContext *s, TCGType type,
402 TCGReg ret, TCGReg arg)
403 {
404 /* Simple reg-reg move, optimising out the 'do nothing' case */
405 if (ret != arg) {
406 tcg_out_opc_reg(s, OPC_ADDU, ret, arg, TCG_REG_ZERO);
407 }
408 }
409
410 static inline void tcg_out_movi(TCGContext *s, TCGType type,
411 TCGReg reg, tcg_target_long arg)
412 {
413 if (arg == (int16_t)arg) {
414 tcg_out_opc_imm(s, OPC_ADDIU, reg, TCG_REG_ZERO, arg);
415 } else if (arg == (uint16_t)arg) {
416 tcg_out_opc_imm(s, OPC_ORI, reg, TCG_REG_ZERO, arg);
417 } else {
418 tcg_out_opc_imm(s, OPC_LUI, reg, 0, arg >> 16);
419 tcg_out_opc_imm(s, OPC_ORI, reg, reg, arg & 0xffff);
420 }
421 }
422
423 static inline void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg)
424 {
425 if (use_mips32r2_instructions) {
426 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
427 } else {
428 /* ret and arg can't be register at */
429 if (ret == TCG_REG_AT || arg == TCG_REG_AT) {
430 tcg_abort();
431 }
432
433 tcg_out_opc_sa(s, OPC_SRL, TCG_REG_AT, arg, 8);
434 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8);
435 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00);
436 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_REG_AT);
437 }
438 }
439
440 static inline void tcg_out_bswap16s(TCGContext *s, TCGReg ret, TCGReg arg)
441 {
442 if (use_mips32r2_instructions) {
443 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
444 tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret);
445 } else {
446 /* ret and arg can't be register at */
447 if (ret == TCG_REG_AT || arg == TCG_REG_AT) {
448 tcg_abort();
449 }
450
451 tcg_out_opc_sa(s, OPC_SRL, TCG_REG_AT, arg, 8);
452 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24);
453 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16);
454 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_REG_AT);
455 }
456 }
457
458 static inline void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg)
459 {
460 if (use_mips32r2_instructions) {
461 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
462 tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16);
463 } else {
464 /* ret and arg must be different and can't be register at */
465 if (ret == arg || ret == TCG_REG_AT || arg == TCG_REG_AT) {
466 tcg_abort();
467 }
468
469 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24);
470
471 tcg_out_opc_sa(s, OPC_SRL, TCG_REG_AT, arg, 24);
472 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_REG_AT);
473
474 tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_AT, arg, 0xff00);
475 tcg_out_opc_sa(s, OPC_SLL, TCG_REG_AT, TCG_REG_AT, 8);
476 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_REG_AT);
477
478 tcg_out_opc_sa(s, OPC_SRL, TCG_REG_AT, arg, 8);
479 tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_AT, TCG_REG_AT, 0xff00);
480 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_REG_AT);
481 }
482 }
483
484 static inline void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg)
485 {
486 if (use_mips32r2_instructions) {
487 tcg_out_opc_reg(s, OPC_SEB, ret, 0, arg);
488 } else {
489 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24);
490 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 24);
491 }
492 }
493
494 static inline void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg)
495 {
496 if (use_mips32r2_instructions) {
497 tcg_out_opc_reg(s, OPC_SEH, ret, 0, arg);
498 } else {
499 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 16);
500 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16);
501 }
502 }
503
504 static inline void tcg_out_ldst(TCGContext *s, int opc, TCGArg arg,
505 TCGReg arg1, TCGArg arg2)
506 {
507 if (arg2 == (int16_t) arg2) {
508 tcg_out_opc_imm(s, opc, arg, arg1, arg2);
509 } else {
510 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_AT, arg2);
511 tcg_out_opc_reg(s, OPC_ADDU, TCG_REG_AT, TCG_REG_AT, arg1);
512 tcg_out_opc_imm(s, opc, arg, TCG_REG_AT, 0);
513 }
514 }
515
516 static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
517 TCGReg arg1, intptr_t arg2)
518 {
519 tcg_out_ldst(s, OPC_LW, arg, arg1, arg2);
520 }
521
522 static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
523 TCGReg arg1, intptr_t arg2)
524 {
525 tcg_out_ldst(s, OPC_SW, arg, arg1, arg2);
526 }
527
528 static inline void tcg_out_addi(TCGContext *s, TCGReg reg, TCGArg val)
529 {
530 if (val == (int16_t)val) {
531 tcg_out_opc_imm(s, OPC_ADDIU, reg, reg, val);
532 } else {
533 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_AT, val);
534 tcg_out_opc_reg(s, OPC_ADDU, reg, reg, TCG_REG_AT);
535 }
536 }
537
538 /* Helper routines for marshalling helper function arguments into
539 * the correct registers and stack.
540 * arg_num is where we want to put this argument, and is updated to be ready
541 * for the next call. arg is the argument itself. Note that arg_num 0..3 is
542 * real registers, 4+ on stack.
543 *
544 * We provide routines for arguments which are: immediate, 32 bit
545 * value in register, 16 and 8 bit values in register (which must be zero
546 * extended before use) and 64 bit value in a lo:hi register pair.
547 */
548 #define DEFINE_TCG_OUT_CALL_IARG(NAME, ARGPARAM) \
549 static inline void NAME(TCGContext *s, int *arg_num, ARGPARAM) \
550 { \
551 if (*arg_num < 4) { \
552 DEFINE_TCG_OUT_CALL_IARG_GET_ARG(tcg_target_call_iarg_regs[*arg_num]); \
553 } else { \
554 DEFINE_TCG_OUT_CALL_IARG_GET_ARG(TCG_REG_AT); \
555 tcg_out_st(s, TCG_TYPE_I32, TCG_REG_AT, TCG_REG_SP, 4 * (*arg_num)); \
556 } \
557 (*arg_num)++; \
558 }
559 #define DEFINE_TCG_OUT_CALL_IARG_GET_ARG(A) \
560 tcg_out_opc_imm(s, OPC_ANDI, A, arg, 0xff);
561 DEFINE_TCG_OUT_CALL_IARG(tcg_out_call_iarg_reg8, TCGReg arg)
562 #undef DEFINE_TCG_OUT_CALL_IARG_GET_ARG
563 #define DEFINE_TCG_OUT_CALL_IARG_GET_ARG(A) \
564 tcg_out_opc_imm(s, OPC_ANDI, A, arg, 0xffff);
565 DEFINE_TCG_OUT_CALL_IARG(tcg_out_call_iarg_reg16, TCGReg arg)
566 #undef DEFINE_TCG_OUT_CALL_IARG_GET_ARG
567 #define DEFINE_TCG_OUT_CALL_IARG_GET_ARG(A) \
568 tcg_out_movi(s, TCG_TYPE_I32, A, arg);
569 DEFINE_TCG_OUT_CALL_IARG(tcg_out_call_iarg_imm32, TCGArg arg)
570 #undef DEFINE_TCG_OUT_CALL_IARG_GET_ARG
571
572 /* We don't use the macro for this one to avoid an unnecessary reg-reg
573 move when storing to the stack. */
574 static inline void tcg_out_call_iarg_reg32(TCGContext *s, int *arg_num,
575 TCGReg arg)
576 {
577 if (*arg_num < 4) {
578 tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[*arg_num], arg);
579 } else {
580 tcg_out_st(s, TCG_TYPE_I32, arg, TCG_REG_SP, 4 * (*arg_num));
581 }
582 (*arg_num)++;
583 }
584
585 static inline void tcg_out_call_iarg_reg64(TCGContext *s, int *arg_num,
586 TCGReg arg_low, TCGReg arg_high)
587 {
588 (*arg_num) = (*arg_num + 1) & ~1;
589
590 #if defined(TCG_TARGET_WORDS_BIGENDIAN)
591 tcg_out_call_iarg_reg32(s, arg_num, arg_high);
592 tcg_out_call_iarg_reg32(s, arg_num, arg_low);
593 #else
594 tcg_out_call_iarg_reg32(s, arg_num, arg_low);
595 tcg_out_call_iarg_reg32(s, arg_num, arg_high);
596 #endif
597 }
598
599 static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGArg arg1,
600 TCGArg arg2, int label_index)
601 {
602 TCGLabel *l = &s->labels[label_index];
603
604 switch (cond) {
605 case TCG_COND_EQ:
606 tcg_out_opc_br(s, OPC_BEQ, arg1, arg2);
607 break;
608 case TCG_COND_NE:
609 tcg_out_opc_br(s, OPC_BNE, arg1, arg2);
610 break;
611 case TCG_COND_LT:
612 if (arg2 == 0) {
613 tcg_out_opc_br(s, OPC_BLTZ, 0, arg1);
614 } else {
615 tcg_out_opc_reg(s, OPC_SLT, TCG_REG_AT, arg1, arg2);
616 tcg_out_opc_br(s, OPC_BNE, TCG_REG_AT, TCG_REG_ZERO);
617 }
618 break;
619 case TCG_COND_LTU:
620 tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_AT, arg1, arg2);
621 tcg_out_opc_br(s, OPC_BNE, TCG_REG_AT, TCG_REG_ZERO);
622 break;
623 case TCG_COND_GE:
624 if (arg2 == 0) {
625 tcg_out_opc_br(s, OPC_BGEZ, 0, arg1);
626 } else {
627 tcg_out_opc_reg(s, OPC_SLT, TCG_REG_AT, arg1, arg2);
628 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_AT, TCG_REG_ZERO);
629 }
630 break;
631 case TCG_COND_GEU:
632 tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_AT, arg1, arg2);
633 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_AT, TCG_REG_ZERO);
634 break;
635 case TCG_COND_LE:
636 if (arg2 == 0) {
637 tcg_out_opc_br(s, OPC_BLEZ, 0, arg1);
638 } else {
639 tcg_out_opc_reg(s, OPC_SLT, TCG_REG_AT, arg2, arg1);
640 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_AT, TCG_REG_ZERO);
641 }
642 break;
643 case TCG_COND_LEU:
644 tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_AT, arg2, arg1);
645 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_AT, TCG_REG_ZERO);
646 break;
647 case TCG_COND_GT:
648 if (arg2 == 0) {
649 tcg_out_opc_br(s, OPC_BGTZ, 0, arg1);
650 } else {
651 tcg_out_opc_reg(s, OPC_SLT, TCG_REG_AT, arg2, arg1);
652 tcg_out_opc_br(s, OPC_BNE, TCG_REG_AT, TCG_REG_ZERO);
653 }
654 break;
655 case TCG_COND_GTU:
656 tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_AT, arg2, arg1);
657 tcg_out_opc_br(s, OPC_BNE, TCG_REG_AT, TCG_REG_ZERO);
658 break;
659 default:
660 tcg_abort();
661 break;
662 }
663 if (l->has_value) {
664 reloc_pc16(s->code_ptr - 4, l->u.value);
665 } else {
666 tcg_out_reloc(s, s->code_ptr - 4, R_MIPS_PC16, label_index, 0);
667 }
668 tcg_out_nop(s);
669 }
670
671 /* XXX: we implement it at the target level to avoid having to
672 handle cross basic blocks temporaries */
673 static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGArg arg1,
674 TCGArg arg2, TCGArg arg3, TCGArg arg4,
675 int label_index)
676 {
677 void *label_ptr;
678
679 switch(cond) {
680 case TCG_COND_NE:
681 tcg_out_brcond(s, TCG_COND_NE, arg2, arg4, label_index);
682 tcg_out_brcond(s, TCG_COND_NE, arg1, arg3, label_index);
683 return;
684 case TCG_COND_EQ:
685 break;
686 case TCG_COND_LT:
687 case TCG_COND_LE:
688 tcg_out_brcond(s, TCG_COND_LT, arg2, arg4, label_index);
689 break;
690 case TCG_COND_GT:
691 case TCG_COND_GE:
692 tcg_out_brcond(s, TCG_COND_GT, arg2, arg4, label_index);
693 break;
694 case TCG_COND_LTU:
695 case TCG_COND_LEU:
696 tcg_out_brcond(s, TCG_COND_LTU, arg2, arg4, label_index);
697 break;
698 case TCG_COND_GTU:
699 case TCG_COND_GEU:
700 tcg_out_brcond(s, TCG_COND_GTU, arg2, arg4, label_index);
701 break;
702 default:
703 tcg_abort();
704 }
705
706 label_ptr = s->code_ptr;
707 tcg_out_opc_br(s, OPC_BNE, arg2, arg4);
708 tcg_out_nop(s);
709
710 switch(cond) {
711 case TCG_COND_EQ:
712 tcg_out_brcond(s, TCG_COND_EQ, arg1, arg3, label_index);
713 break;
714 case TCG_COND_LT:
715 case TCG_COND_LTU:
716 tcg_out_brcond(s, TCG_COND_LTU, arg1, arg3, label_index);
717 break;
718 case TCG_COND_LE:
719 case TCG_COND_LEU:
720 tcg_out_brcond(s, TCG_COND_LEU, arg1, arg3, label_index);
721 break;
722 case TCG_COND_GT:
723 case TCG_COND_GTU:
724 tcg_out_brcond(s, TCG_COND_GTU, arg1, arg3, label_index);
725 break;
726 case TCG_COND_GE:
727 case TCG_COND_GEU:
728 tcg_out_brcond(s, TCG_COND_GEU, arg1, arg3, label_index);
729 break;
730 default:
731 tcg_abort();
732 }
733
734 reloc_pc16(label_ptr, (tcg_target_long) s->code_ptr);
735 }
736
737 static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret,
738 TCGArg c1, TCGArg c2, TCGArg v)
739 {
740 switch (cond) {
741 case TCG_COND_EQ:
742 if (c1 == 0) {
743 tcg_out_opc_reg(s, OPC_MOVZ, ret, v, c2);
744 } else if (c2 == 0) {
745 tcg_out_opc_reg(s, OPC_MOVZ, ret, v, c1);
746 } else {
747 tcg_out_opc_reg(s, OPC_XOR, TCG_REG_AT, c1, c2);
748 tcg_out_opc_reg(s, OPC_MOVZ, ret, v, TCG_REG_AT);
749 }
750 break;
751 case TCG_COND_NE:
752 if (c1 == 0) {
753 tcg_out_opc_reg(s, OPC_MOVN, ret, v, c2);
754 } else if (c2 == 0) {
755 tcg_out_opc_reg(s, OPC_MOVN, ret, v, c1);
756 } else {
757 tcg_out_opc_reg(s, OPC_XOR, TCG_REG_AT, c1, c2);
758 tcg_out_opc_reg(s, OPC_MOVN, ret, v, TCG_REG_AT);
759 }
760 break;
761 case TCG_COND_LT:
762 tcg_out_opc_reg(s, OPC_SLT, TCG_REG_AT, c1, c2);
763 tcg_out_opc_reg(s, OPC_MOVN, ret, v, TCG_REG_AT);
764 break;
765 case TCG_COND_LTU:
766 tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_AT, c1, c2);
767 tcg_out_opc_reg(s, OPC_MOVN, ret, v, TCG_REG_AT);
768 break;
769 case TCG_COND_GE:
770 tcg_out_opc_reg(s, OPC_SLT, TCG_REG_AT, c1, c2);
771 tcg_out_opc_reg(s, OPC_MOVZ, ret, v, TCG_REG_AT);
772 break;
773 case TCG_COND_GEU:
774 tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_AT, c1, c2);
775 tcg_out_opc_reg(s, OPC_MOVZ, ret, v, TCG_REG_AT);
776 break;
777 case TCG_COND_LE:
778 tcg_out_opc_reg(s, OPC_SLT, TCG_REG_AT, c2, c1);
779 tcg_out_opc_reg(s, OPC_MOVZ, ret, v, TCG_REG_AT);
780 break;
781 case TCG_COND_LEU:
782 tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_AT, c2, c1);
783 tcg_out_opc_reg(s, OPC_MOVZ, ret, v, TCG_REG_AT);
784 break;
785 case TCG_COND_GT:
786 tcg_out_opc_reg(s, OPC_SLT, TCG_REG_AT, c2, c1);
787 tcg_out_opc_reg(s, OPC_MOVN, ret, v, TCG_REG_AT);
788 break;
789 case TCG_COND_GTU:
790 tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_AT, c2, c1);
791 tcg_out_opc_reg(s, OPC_MOVN, ret, v, TCG_REG_AT);
792 break;
793 default:
794 tcg_abort();
795 break;
796 }
797 }
798
799 static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret,
800 TCGArg arg1, TCGArg arg2)
801 {
802 switch (cond) {
803 case TCG_COND_EQ:
804 if (arg1 == 0) {
805 tcg_out_opc_imm(s, OPC_SLTIU, ret, arg2, 1);
806 } else if (arg2 == 0) {
807 tcg_out_opc_imm(s, OPC_SLTIU, ret, arg1, 1);
808 } else {
809 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2);
810 tcg_out_opc_imm(s, OPC_SLTIU, ret, ret, 1);
811 }
812 break;
813 case TCG_COND_NE:
814 if (arg1 == 0) {
815 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, arg2);
816 } else if (arg2 == 0) {
817 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, arg1);
818 } else {
819 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2);
820 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, ret);
821 }
822 break;
823 case TCG_COND_LT:
824 tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2);
825 break;
826 case TCG_COND_LTU:
827 tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2);
828 break;
829 case TCG_COND_GE:
830 tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2);
831 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
832 break;
833 case TCG_COND_GEU:
834 tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2);
835 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
836 break;
837 case TCG_COND_LE:
838 tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1);
839 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
840 break;
841 case TCG_COND_LEU:
842 tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1);
843 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
844 break;
845 case TCG_COND_GT:
846 tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1);
847 break;
848 case TCG_COND_GTU:
849 tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1);
850 break;
851 default:
852 tcg_abort();
853 break;
854 }
855 }
856
857 /* XXX: we implement it at the target level to avoid having to
858 handle cross basic blocks temporaries */
859 static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret,
860 TCGArg arg1, TCGArg arg2, TCGArg arg3, TCGArg arg4)
861 {
862 switch (cond) {
863 case TCG_COND_EQ:
864 tcg_out_setcond(s, TCG_COND_EQ, TCG_REG_AT, arg2, arg4);
865 tcg_out_setcond(s, TCG_COND_EQ, TCG_REG_T0, arg1, arg3);
866 tcg_out_opc_reg(s, OPC_AND, ret, TCG_REG_AT, TCG_REG_T0);
867 return;
868 case TCG_COND_NE:
869 tcg_out_setcond(s, TCG_COND_NE, TCG_REG_AT, arg2, arg4);
870 tcg_out_setcond(s, TCG_COND_NE, TCG_REG_T0, arg1, arg3);
871 tcg_out_opc_reg(s, OPC_OR, ret, TCG_REG_AT, TCG_REG_T0);
872 return;
873 case TCG_COND_LT:
874 case TCG_COND_LE:
875 tcg_out_setcond(s, TCG_COND_LT, TCG_REG_AT, arg2, arg4);
876 break;
877 case TCG_COND_GT:
878 case TCG_COND_GE:
879 tcg_out_setcond(s, TCG_COND_GT, TCG_REG_AT, arg2, arg4);
880 break;
881 case TCG_COND_LTU:
882 case TCG_COND_LEU:
883 tcg_out_setcond(s, TCG_COND_LTU, TCG_REG_AT, arg2, arg4);
884 break;
885 case TCG_COND_GTU:
886 case TCG_COND_GEU:
887 tcg_out_setcond(s, TCG_COND_GTU, TCG_REG_AT, arg2, arg4);
888 break;
889 default:
890 tcg_abort();
891 break;
892 }
893
894 tcg_out_setcond(s, TCG_COND_EQ, TCG_REG_T0, arg2, arg4);
895
896 switch(cond) {
897 case TCG_COND_LT:
898 case TCG_COND_LTU:
899 tcg_out_setcond(s, TCG_COND_LTU, ret, arg1, arg3);
900 break;
901 case TCG_COND_LE:
902 case TCG_COND_LEU:
903 tcg_out_setcond(s, TCG_COND_LEU, ret, arg1, arg3);
904 break;
905 case TCG_COND_GT:
906 case TCG_COND_GTU:
907 tcg_out_setcond(s, TCG_COND_GTU, ret, arg1, arg3);
908 break;
909 case TCG_COND_GE:
910 case TCG_COND_GEU:
911 tcg_out_setcond(s, TCG_COND_GEU, ret, arg1, arg3);
912 break;
913 default:
914 tcg_abort();
915 }
916
917 tcg_out_opc_reg(s, OPC_AND, ret, ret, TCG_REG_T0);
918 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_REG_AT);
919 }
920
921 #if defined(CONFIG_SOFTMMU)
922 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
923 int mmu_idx) */
924 static const void * const qemu_ld_helpers[4] = {
925 helper_ldb_mmu,
926 helper_ldw_mmu,
927 helper_ldl_mmu,
928 helper_ldq_mmu,
929 };
930
931 /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
932 uintxx_t val, int mmu_idx) */
933 static const void * const qemu_st_helpers[4] = {
934 helper_stb_mmu,
935 helper_stw_mmu,
936 helper_stl_mmu,
937 helper_stq_mmu,
938 };
939 #endif
940
941 static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
942 int opc)
943 {
944 TCGReg addr_regl, data_regl, data_regh, data_reg1, data_reg2;
945 #if defined(CONFIG_SOFTMMU)
946 void *label1_ptr, *label2_ptr;
947 int arg_num;
948 int mem_index, s_bits;
949 int addr_meml;
950 # if TARGET_LONG_BITS == 64
951 uint8_t *label3_ptr;
952 TCGReg addr_regh;
953 int addr_memh;
954 # endif
955 #endif
956 data_regl = *args++;
957 if (opc == 3)
958 data_regh = *args++;
959 else
960 data_regh = 0;
961 addr_regl = *args++;
962 #if defined(CONFIG_SOFTMMU)
963 # if TARGET_LONG_BITS == 64
964 addr_regh = *args++;
965 # if defined(TCG_TARGET_WORDS_BIGENDIAN)
966 addr_memh = 0;
967 addr_meml = 4;
968 # else
969 addr_memh = 4;
970 addr_meml = 0;
971 # endif
972 # else
973 addr_meml = 0;
974 # endif
975 mem_index = *args;
976 s_bits = opc & 3;
977 #endif
978
979 if (opc == 3) {
980 #if defined(TCG_TARGET_WORDS_BIGENDIAN)
981 data_reg1 = data_regh;
982 data_reg2 = data_regl;
983 #else
984 data_reg1 = data_regl;
985 data_reg2 = data_regh;
986 #endif
987 } else {
988 data_reg1 = data_regl;
989 data_reg2 = 0;
990 }
991 #if defined(CONFIG_SOFTMMU)
992 tcg_out_opc_sa(s, OPC_SRL, TCG_REG_A0, addr_regl, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
993 tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_A0, TCG_REG_A0, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
994 tcg_out_opc_reg(s, OPC_ADDU, TCG_REG_A0, TCG_REG_A0, TCG_AREG0);
995 tcg_out_opc_imm(s, OPC_LW, TCG_REG_AT, TCG_REG_A0,
996 offsetof(CPUArchState, tlb_table[mem_index][0].addr_read) + addr_meml);
997 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_T0, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
998 tcg_out_opc_reg(s, OPC_AND, TCG_REG_T0, TCG_REG_T0, addr_regl);
999
1000 # if TARGET_LONG_BITS == 64
1001 label3_ptr = s->code_ptr;
1002 tcg_out_opc_br(s, OPC_BNE, TCG_REG_T0, TCG_REG_AT);
1003 tcg_out_nop(s);
1004
1005 tcg_out_opc_imm(s, OPC_LW, TCG_REG_AT, TCG_REG_A0,
1006 offsetof(CPUArchState, tlb_table[mem_index][0].addr_read) + addr_memh);
1007
1008 label1_ptr = s->code_ptr;
1009 tcg_out_opc_br(s, OPC_BEQ, addr_regh, TCG_REG_AT);
1010 tcg_out_nop(s);
1011
1012 reloc_pc16(label3_ptr, (tcg_target_long) s->code_ptr);
1013 # else
1014 label1_ptr = s->code_ptr;
1015 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_T0, TCG_REG_AT);
1016 tcg_out_nop(s);
1017 # endif
1018
1019 /* slow path */
1020 arg_num = 0;
1021 tcg_out_call_iarg_reg32(s, &arg_num, TCG_AREG0);
1022 # if TARGET_LONG_BITS == 64
1023 tcg_out_call_iarg_reg64(s, &arg_num, addr_regl, addr_regh);
1024 # else
1025 tcg_out_call_iarg_reg32(s, &arg_num, addr_regl);
1026 # endif
1027 tcg_out_call_iarg_imm32(s, &arg_num, mem_index);
1028 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_T9, (tcg_target_long)qemu_ld_helpers[s_bits]);
1029 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0);
1030 tcg_out_nop(s);
1031
1032 switch(opc) {
1033 case 0:
1034 tcg_out_opc_imm(s, OPC_ANDI, data_reg1, TCG_REG_V0, 0xff);
1035 break;
1036 case 0 | 4:
1037 tcg_out_ext8s(s, data_reg1, TCG_REG_V0);
1038 break;
1039 case 1:
1040 tcg_out_opc_imm(s, OPC_ANDI, data_reg1, TCG_REG_V0, 0xffff);
1041 break;
1042 case 1 | 4:
1043 tcg_out_ext16s(s, data_reg1, TCG_REG_V0);
1044 break;
1045 case 2:
1046 tcg_out_mov(s, TCG_TYPE_I32, data_reg1, TCG_REG_V0);
1047 break;
1048 case 3:
1049 tcg_out_mov(s, TCG_TYPE_I32, data_reg2, TCG_REG_V1);
1050 tcg_out_mov(s, TCG_TYPE_I32, data_reg1, TCG_REG_V0);
1051 break;
1052 default:
1053 tcg_abort();
1054 }
1055
1056 label2_ptr = s->code_ptr;
1057 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO);
1058 tcg_out_nop(s);
1059
1060 /* label1: fast path */
1061 reloc_pc16(label1_ptr, (tcg_target_long) s->code_ptr);
1062
1063 tcg_out_opc_imm(s, OPC_LW, TCG_REG_A0, TCG_REG_A0,
1064 offsetof(CPUArchState, tlb_table[mem_index][0].addend));
1065 tcg_out_opc_reg(s, OPC_ADDU, TCG_REG_V0, TCG_REG_A0, addr_regl);
1066 #else
1067 if (GUEST_BASE == (int16_t)GUEST_BASE) {
1068 tcg_out_opc_imm(s, OPC_ADDIU, TCG_REG_V0, addr_regl, GUEST_BASE);
1069 } else {
1070 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_V0, GUEST_BASE);
1071 tcg_out_opc_reg(s, OPC_ADDU, TCG_REG_V0, TCG_REG_V0, addr_regl);
1072 }
1073 #endif
1074
1075 switch(opc) {
1076 case 0:
1077 tcg_out_opc_imm(s, OPC_LBU, data_reg1, TCG_REG_V0, 0);
1078 break;
1079 case 0 | 4:
1080 tcg_out_opc_imm(s, OPC_LB, data_reg1, TCG_REG_V0, 0);
1081 break;
1082 case 1:
1083 if (TCG_NEED_BSWAP) {
1084 tcg_out_opc_imm(s, OPC_LHU, TCG_REG_T0, TCG_REG_V0, 0);
1085 tcg_out_bswap16(s, data_reg1, TCG_REG_T0);
1086 } else {
1087 tcg_out_opc_imm(s, OPC_LHU, data_reg1, TCG_REG_V0, 0);
1088 }
1089 break;
1090 case 1 | 4:
1091 if (TCG_NEED_BSWAP) {
1092 tcg_out_opc_imm(s, OPC_LHU, TCG_REG_T0, TCG_REG_V0, 0);
1093 tcg_out_bswap16s(s, data_reg1, TCG_REG_T0);
1094 } else {
1095 tcg_out_opc_imm(s, OPC_LH, data_reg1, TCG_REG_V0, 0);
1096 }
1097 break;
1098 case 2:
1099 if (TCG_NEED_BSWAP) {
1100 tcg_out_opc_imm(s, OPC_LW, TCG_REG_T0, TCG_REG_V0, 0);
1101 tcg_out_bswap32(s, data_reg1, TCG_REG_T0);
1102 } else {
1103 tcg_out_opc_imm(s, OPC_LW, data_reg1, TCG_REG_V0, 0);
1104 }
1105 break;
1106 case 3:
1107 if (TCG_NEED_BSWAP) {
1108 tcg_out_opc_imm(s, OPC_LW, TCG_REG_T0, TCG_REG_V0, 4);
1109 tcg_out_bswap32(s, data_reg1, TCG_REG_T0);
1110 tcg_out_opc_imm(s, OPC_LW, TCG_REG_T0, TCG_REG_V0, 0);
1111 tcg_out_bswap32(s, data_reg2, TCG_REG_T0);
1112 } else {
1113 tcg_out_opc_imm(s, OPC_LW, data_reg1, TCG_REG_V0, 0);
1114 tcg_out_opc_imm(s, OPC_LW, data_reg2, TCG_REG_V0, 4);
1115 }
1116 break;
1117 default:
1118 tcg_abort();
1119 }
1120
1121 #if defined(CONFIG_SOFTMMU)
1122 reloc_pc16(label2_ptr, (tcg_target_long) s->code_ptr);
1123 #endif
1124 }
1125
1126 static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
1127 int opc)
1128 {
1129 TCGReg addr_regl, data_regl, data_regh, data_reg1, data_reg2;
1130 #if defined(CONFIG_SOFTMMU)
1131 uint8_t *label1_ptr, *label2_ptr;
1132 int arg_num;
1133 int mem_index, s_bits;
1134 int addr_meml;
1135 #endif
1136 #if TARGET_LONG_BITS == 64
1137 # if defined(CONFIG_SOFTMMU)
1138 uint8_t *label3_ptr;
1139 TCGReg addr_regh;
1140 int addr_memh;
1141 # endif
1142 #endif
1143 data_regl = *args++;
1144 if (opc == 3) {
1145 data_regh = *args++;
1146 } else {
1147 data_regh = 0;
1148 }
1149 addr_regl = *args++;
1150 #if defined(CONFIG_SOFTMMU)
1151 # if TARGET_LONG_BITS == 64
1152 addr_regh = *args++;
1153 # if defined(TCG_TARGET_WORDS_BIGENDIAN)
1154 addr_memh = 0;
1155 addr_meml = 4;
1156 # else
1157 addr_memh = 4;
1158 addr_meml = 0;
1159 # endif
1160 # else
1161 addr_meml = 0;
1162 # endif
1163 mem_index = *args;
1164 s_bits = opc;
1165 #endif
1166
1167 if (opc == 3) {
1168 #if defined(TCG_TARGET_WORDS_BIGENDIAN)
1169 data_reg1 = data_regh;
1170 data_reg2 = data_regl;
1171 #else
1172 data_reg1 = data_regl;
1173 data_reg2 = data_regh;
1174 #endif
1175 } else {
1176 data_reg1 = data_regl;
1177 data_reg2 = 0;
1178 }
1179
1180 #if defined(CONFIG_SOFTMMU)
1181 tcg_out_opc_sa(s, OPC_SRL, TCG_REG_A0, addr_regl, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
1182 tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_A0, TCG_REG_A0, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
1183 tcg_out_opc_reg(s, OPC_ADDU, TCG_REG_A0, TCG_REG_A0, TCG_AREG0);
1184 tcg_out_opc_imm(s, OPC_LW, TCG_REG_AT, TCG_REG_A0,
1185 offsetof(CPUArchState, tlb_table[mem_index][0].addr_write) + addr_meml);
1186 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_T0, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
1187 tcg_out_opc_reg(s, OPC_AND, TCG_REG_T0, TCG_REG_T0, addr_regl);
1188
1189 # if TARGET_LONG_BITS == 64
1190 label3_ptr = s->code_ptr;
1191 tcg_out_opc_br(s, OPC_BNE, TCG_REG_T0, TCG_REG_AT);
1192 tcg_out_nop(s);
1193
1194 tcg_out_opc_imm(s, OPC_LW, TCG_REG_AT, TCG_REG_A0,
1195 offsetof(CPUArchState, tlb_table[mem_index][0].addr_write) + addr_memh);
1196
1197 label1_ptr = s->code_ptr;
1198 tcg_out_opc_br(s, OPC_BEQ, addr_regh, TCG_REG_AT);
1199 tcg_out_nop(s);
1200
1201 reloc_pc16(label3_ptr, (tcg_target_long) s->code_ptr);
1202 # else
1203 label1_ptr = s->code_ptr;
1204 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_T0, TCG_REG_AT);
1205 tcg_out_nop(s);
1206 # endif
1207
1208 /* slow path */
1209 arg_num = 0;
1210 tcg_out_call_iarg_reg32(s, &arg_num, TCG_AREG0);
1211 # if TARGET_LONG_BITS == 64
1212 tcg_out_call_iarg_reg64(s, &arg_num, addr_regl, addr_regh);
1213 # else
1214 tcg_out_call_iarg_reg32(s, &arg_num, addr_regl);
1215 # endif
1216 switch(opc) {
1217 case 0:
1218 tcg_out_call_iarg_reg8(s, &arg_num, data_regl);
1219 break;
1220 case 1:
1221 tcg_out_call_iarg_reg16(s, &arg_num, data_regl);
1222 break;
1223 case 2:
1224 tcg_out_call_iarg_reg32(s, &arg_num, data_regl);
1225 break;
1226 case 3:
1227 tcg_out_call_iarg_reg64(s, &arg_num, data_regl, data_regh);
1228 break;
1229 default:
1230 tcg_abort();
1231 }
1232 tcg_out_call_iarg_imm32(s, &arg_num, mem_index);
1233 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_T9, (tcg_target_long)qemu_st_helpers[s_bits]);
1234 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0);
1235 tcg_out_nop(s);
1236
1237 label2_ptr = s->code_ptr;
1238 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO);
1239 tcg_out_nop(s);
1240
1241 /* label1: fast path */
1242 reloc_pc16(label1_ptr, (tcg_target_long) s->code_ptr);
1243
1244 tcg_out_opc_imm(s, OPC_LW, TCG_REG_A0, TCG_REG_A0,
1245 offsetof(CPUArchState, tlb_table[mem_index][0].addend));
1246 tcg_out_opc_reg(s, OPC_ADDU, TCG_REG_A0, TCG_REG_A0, addr_regl);
1247 #else
1248 if (GUEST_BASE == (int16_t)GUEST_BASE) {
1249 tcg_out_opc_imm(s, OPC_ADDIU, TCG_REG_A0, addr_regl, GUEST_BASE);
1250 } else {
1251 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A0, GUEST_BASE);
1252 tcg_out_opc_reg(s, OPC_ADDU, TCG_REG_A0, TCG_REG_A0, addr_regl);
1253 }
1254
1255 #endif
1256
1257 switch(opc) {
1258 case 0:
1259 tcg_out_opc_imm(s, OPC_SB, data_reg1, TCG_REG_A0, 0);
1260 break;
1261 case 1:
1262 if (TCG_NEED_BSWAP) {
1263 tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_T0, data_reg1, 0xffff);
1264 tcg_out_bswap16(s, TCG_REG_T0, TCG_REG_T0);
1265 tcg_out_opc_imm(s, OPC_SH, TCG_REG_T0, TCG_REG_A0, 0);
1266 } else {
1267 tcg_out_opc_imm(s, OPC_SH, data_reg1, TCG_REG_A0, 0);
1268 }
1269 break;
1270 case 2:
1271 if (TCG_NEED_BSWAP) {
1272 tcg_out_bswap32(s, TCG_REG_T0, data_reg1);
1273 tcg_out_opc_imm(s, OPC_SW, TCG_REG_T0, TCG_REG_A0, 0);
1274 } else {
1275 tcg_out_opc_imm(s, OPC_SW, data_reg1, TCG_REG_A0, 0);
1276 }
1277 break;
1278 case 3:
1279 if (TCG_NEED_BSWAP) {
1280 tcg_out_bswap32(s, TCG_REG_T0, data_reg2);
1281 tcg_out_opc_imm(s, OPC_SW, TCG_REG_T0, TCG_REG_A0, 0);
1282 tcg_out_bswap32(s, TCG_REG_T0, data_reg1);
1283 tcg_out_opc_imm(s, OPC_SW, TCG_REG_T0, TCG_REG_A0, 4);
1284 } else {
1285 tcg_out_opc_imm(s, OPC_SW, data_reg1, TCG_REG_A0, 0);
1286 tcg_out_opc_imm(s, OPC_SW, data_reg2, TCG_REG_A0, 4);
1287 }
1288 break;
1289 default:
1290 tcg_abort();
1291 }
1292
1293 #if defined(CONFIG_SOFTMMU)
1294 reloc_pc16(label2_ptr, (tcg_target_long) s->code_ptr);
1295 #endif
1296 }
1297
1298 static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
1299 const TCGArg *args, const int *const_args)
1300 {
1301 switch(opc) {
1302 case INDEX_op_exit_tb:
1303 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_V0, args[0]);
1304 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_AT, (tcg_target_long)tb_ret_addr);
1305 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_AT, 0);
1306 tcg_out_nop(s);
1307 break;
1308 case INDEX_op_goto_tb:
1309 if (s->tb_jmp_offset) {
1310 /* direct jump method */
1311 tcg_abort();
1312 } else {
1313 /* indirect jump method */
1314 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_AT, (tcg_target_long)(s->tb_next + args[0]));
1315 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_AT, TCG_REG_AT, 0);
1316 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_AT, 0);
1317 }
1318 tcg_out_nop(s);
1319 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1320 break;
1321 case INDEX_op_call:
1322 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, args[0], 0);
1323 tcg_out_nop(s);
1324 break;
1325 case INDEX_op_br:
1326 tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO, args[0]);
1327 break;
1328
1329 case INDEX_op_mov_i32:
1330 tcg_out_mov(s, TCG_TYPE_I32, args[0], args[1]);
1331 break;
1332 case INDEX_op_movi_i32:
1333 tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
1334 break;
1335
1336 case INDEX_op_ld8u_i32:
1337 tcg_out_ldst(s, OPC_LBU, args[0], args[1], args[2]);
1338 break;
1339 case INDEX_op_ld8s_i32:
1340 tcg_out_ldst(s, OPC_LB, args[0], args[1], args[2]);
1341 break;
1342 case INDEX_op_ld16u_i32:
1343 tcg_out_ldst(s, OPC_LHU, args[0], args[1], args[2]);
1344 break;
1345 case INDEX_op_ld16s_i32:
1346 tcg_out_ldst(s, OPC_LH, args[0], args[1], args[2]);
1347 break;
1348 case INDEX_op_ld_i32:
1349 tcg_out_ldst(s, OPC_LW, args[0], args[1], args[2]);
1350 break;
1351 case INDEX_op_st8_i32:
1352 tcg_out_ldst(s, OPC_SB, args[0], args[1], args[2]);
1353 break;
1354 case INDEX_op_st16_i32:
1355 tcg_out_ldst(s, OPC_SH, args[0], args[1], args[2]);
1356 break;
1357 case INDEX_op_st_i32:
1358 tcg_out_ldst(s, OPC_SW, args[0], args[1], args[2]);
1359 break;
1360
1361 case INDEX_op_add_i32:
1362 if (const_args[2]) {
1363 tcg_out_opc_imm(s, OPC_ADDIU, args[0], args[1], args[2]);
1364 } else {
1365 tcg_out_opc_reg(s, OPC_ADDU, args[0], args[1], args[2]);
1366 }
1367 break;
1368 case INDEX_op_add2_i32:
1369 if (const_args[4]) {
1370 tcg_out_opc_imm(s, OPC_ADDIU, TCG_REG_AT, args[2], args[4]);
1371 } else {
1372 tcg_out_opc_reg(s, OPC_ADDU, TCG_REG_AT, args[2], args[4]);
1373 }
1374 tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_T0, TCG_REG_AT, args[2]);
1375 if (const_args[5]) {
1376 tcg_out_opc_imm(s, OPC_ADDIU, args[1], args[3], args[5]);
1377 } else {
1378 tcg_out_opc_reg(s, OPC_ADDU, args[1], args[3], args[5]);
1379 }
1380 tcg_out_opc_reg(s, OPC_ADDU, args[1], args[1], TCG_REG_T0);
1381 tcg_out_mov(s, TCG_TYPE_I32, args[0], TCG_REG_AT);
1382 break;
1383 case INDEX_op_sub_i32:
1384 if (const_args[2]) {
1385 tcg_out_opc_imm(s, OPC_ADDIU, args[0], args[1], -args[2]);
1386 } else {
1387 tcg_out_opc_reg(s, OPC_SUBU, args[0], args[1], args[2]);
1388 }
1389 break;
1390 case INDEX_op_sub2_i32:
1391 if (const_args[4]) {
1392 tcg_out_opc_imm(s, OPC_ADDIU, TCG_REG_AT, args[2], -args[4]);
1393 } else {
1394 tcg_out_opc_reg(s, OPC_SUBU, TCG_REG_AT, args[2], args[4]);
1395 }
1396 tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_T0, args[2], TCG_REG_AT);
1397 if (const_args[5]) {
1398 tcg_out_opc_imm(s, OPC_ADDIU, args[1], args[3], -args[5]);
1399 } else {
1400 tcg_out_opc_reg(s, OPC_SUBU, args[1], args[3], args[5]);
1401 }
1402 tcg_out_opc_reg(s, OPC_SUBU, args[1], args[1], TCG_REG_T0);
1403 tcg_out_mov(s, TCG_TYPE_I32, args[0], TCG_REG_AT);
1404 break;
1405 case INDEX_op_mul_i32:
1406 if (use_mips32_instructions) {
1407 tcg_out_opc_reg(s, OPC_MUL, args[0], args[1], args[2]);
1408 } else {
1409 tcg_out_opc_reg(s, OPC_MULT, 0, args[1], args[2]);
1410 tcg_out_opc_reg(s, OPC_MFLO, args[0], 0, 0);
1411 }
1412 break;
1413 case INDEX_op_muls2_i32:
1414 tcg_out_opc_reg(s, OPC_MULT, 0, args[2], args[3]);
1415 tcg_out_opc_reg(s, OPC_MFLO, args[0], 0, 0);
1416 tcg_out_opc_reg(s, OPC_MFHI, args[1], 0, 0);
1417 break;
1418 case INDEX_op_mulu2_i32:
1419 tcg_out_opc_reg(s, OPC_MULTU, 0, args[2], args[3]);
1420 tcg_out_opc_reg(s, OPC_MFLO, args[0], 0, 0);
1421 tcg_out_opc_reg(s, OPC_MFHI, args[1], 0, 0);
1422 break;
1423 case INDEX_op_mulsh_i32:
1424 tcg_out_opc_reg(s, OPC_MULT, 0, args[1], args[2]);
1425 tcg_out_opc_reg(s, OPC_MFHI, args[0], 0, 0);
1426 break;
1427 case INDEX_op_muluh_i32:
1428 tcg_out_opc_reg(s, OPC_MULTU, 0, args[1], args[2]);
1429 tcg_out_opc_reg(s, OPC_MFHI, args[0], 0, 0);
1430 break;
1431 case INDEX_op_div_i32:
1432 tcg_out_opc_reg(s, OPC_DIV, 0, args[1], args[2]);
1433 tcg_out_opc_reg(s, OPC_MFLO, args[0], 0, 0);
1434 break;
1435 case INDEX_op_divu_i32:
1436 tcg_out_opc_reg(s, OPC_DIVU, 0, args[1], args[2]);
1437 tcg_out_opc_reg(s, OPC_MFLO, args[0], 0, 0);
1438 break;
1439 case INDEX_op_rem_i32:
1440 tcg_out_opc_reg(s, OPC_DIV, 0, args[1], args[2]);
1441 tcg_out_opc_reg(s, OPC_MFHI, args[0], 0, 0);
1442 break;
1443 case INDEX_op_remu_i32:
1444 tcg_out_opc_reg(s, OPC_DIVU, 0, args[1], args[2]);
1445 tcg_out_opc_reg(s, OPC_MFHI, args[0], 0, 0);
1446 break;
1447
1448 case INDEX_op_and_i32:
1449 if (const_args[2]) {
1450 tcg_out_opc_imm(s, OPC_ANDI, args[0], args[1], args[2]);
1451 } else {
1452 tcg_out_opc_reg(s, OPC_AND, args[0], args[1], args[2]);
1453 }
1454 break;
1455 case INDEX_op_or_i32:
1456 if (const_args[2]) {
1457 tcg_out_opc_imm(s, OPC_ORI, args[0], args[1], args[2]);
1458 } else {
1459 tcg_out_opc_reg(s, OPC_OR, args[0], args[1], args[2]);
1460 }
1461 break;
1462 case INDEX_op_nor_i32:
1463 tcg_out_opc_reg(s, OPC_NOR, args[0], args[1], args[2]);
1464 break;
1465 case INDEX_op_not_i32:
1466 tcg_out_opc_reg(s, OPC_NOR, args[0], TCG_REG_ZERO, args[1]);
1467 break;
1468 case INDEX_op_xor_i32:
1469 if (const_args[2]) {
1470 tcg_out_opc_imm(s, OPC_XORI, args[0], args[1], args[2]);
1471 } else {
1472 tcg_out_opc_reg(s, OPC_XOR, args[0], args[1], args[2]);
1473 }
1474 break;
1475
1476 case INDEX_op_sar_i32:
1477 if (const_args[2]) {
1478 tcg_out_opc_sa(s, OPC_SRA, args[0], args[1], args[2]);
1479 } else {
1480 tcg_out_opc_reg(s, OPC_SRAV, args[0], args[2], args[1]);
1481 }
1482 break;
1483 case INDEX_op_shl_i32:
1484 if (const_args[2]) {
1485 tcg_out_opc_sa(s, OPC_SLL, args[0], args[1], args[2]);
1486 } else {
1487 tcg_out_opc_reg(s, OPC_SLLV, args[0], args[2], args[1]);
1488 }
1489 break;
1490 case INDEX_op_shr_i32:
1491 if (const_args[2]) {
1492 tcg_out_opc_sa(s, OPC_SRL, args[0], args[1], args[2]);
1493 } else {
1494 tcg_out_opc_reg(s, OPC_SRLV, args[0], args[2], args[1]);
1495 }
1496 break;
1497 case INDEX_op_rotl_i32:
1498 if (const_args[2]) {
1499 tcg_out_opc_sa(s, OPC_ROTR, args[0], args[1], 0x20 - args[2]);
1500 } else {
1501 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_AT, 32);
1502 tcg_out_opc_reg(s, OPC_SUBU, TCG_REG_AT, TCG_REG_AT, args[2]);
1503 tcg_out_opc_reg(s, OPC_ROTRV, args[0], TCG_REG_AT, args[1]);
1504 }
1505 break;
1506 case INDEX_op_rotr_i32:
1507 if (const_args[2]) {
1508 tcg_out_opc_sa(s, OPC_ROTR, args[0], args[1], args[2]);
1509 } else {
1510 tcg_out_opc_reg(s, OPC_ROTRV, args[0], args[2], args[1]);
1511 }
1512 break;
1513
1514 case INDEX_op_bswap16_i32:
1515 tcg_out_opc_reg(s, OPC_WSBH, args[0], 0, args[1]);
1516 break;
1517 case INDEX_op_bswap32_i32:
1518 tcg_out_opc_reg(s, OPC_WSBH, args[0], 0, args[1]);
1519 tcg_out_opc_sa(s, OPC_ROTR, args[0], args[0], 16);
1520 break;
1521
1522 case INDEX_op_ext8s_i32:
1523 tcg_out_opc_reg(s, OPC_SEB, args[0], 0, args[1]);
1524 break;
1525 case INDEX_op_ext16s_i32:
1526 tcg_out_opc_reg(s, OPC_SEH, args[0], 0, args[1]);
1527 break;
1528
1529 case INDEX_op_deposit_i32:
1530 tcg_out_opc_imm(s, OPC_INS, args[0], args[2],
1531 ((args[3] + args[4] - 1) << 11) | (args[3] << 6));
1532 break;
1533
1534 case INDEX_op_brcond_i32:
1535 tcg_out_brcond(s, args[2], args[0], args[1], args[3]);
1536 break;
1537 case INDEX_op_brcond2_i32:
1538 tcg_out_brcond2(s, args[4], args[0], args[1], args[2], args[3], args[5]);
1539 break;
1540
1541 case INDEX_op_movcond_i32:
1542 tcg_out_movcond(s, args[5], args[0], args[1], args[2], args[3]);
1543 break;
1544
1545 case INDEX_op_setcond_i32:
1546 tcg_out_setcond(s, args[3], args[0], args[1], args[2]);
1547 break;
1548 case INDEX_op_setcond2_i32:
1549 tcg_out_setcond2(s, args[5], args[0], args[1], args[2], args[3], args[4]);
1550 break;
1551
1552 case INDEX_op_qemu_ld8u:
1553 tcg_out_qemu_ld(s, args, 0);
1554 break;
1555 case INDEX_op_qemu_ld8s:
1556 tcg_out_qemu_ld(s, args, 0 | 4);
1557 break;
1558 case INDEX_op_qemu_ld16u:
1559 tcg_out_qemu_ld(s, args, 1);
1560 break;
1561 case INDEX_op_qemu_ld16s:
1562 tcg_out_qemu_ld(s, args, 1 | 4);
1563 break;
1564 case INDEX_op_qemu_ld32:
1565 tcg_out_qemu_ld(s, args, 2);
1566 break;
1567 case INDEX_op_qemu_ld64:
1568 tcg_out_qemu_ld(s, args, 3);
1569 break;
1570 case INDEX_op_qemu_st8:
1571 tcg_out_qemu_st(s, args, 0);
1572 break;
1573 case INDEX_op_qemu_st16:
1574 tcg_out_qemu_st(s, args, 1);
1575 break;
1576 case INDEX_op_qemu_st32:
1577 tcg_out_qemu_st(s, args, 2);
1578 break;
1579 case INDEX_op_qemu_st64:
1580 tcg_out_qemu_st(s, args, 3);
1581 break;
1582
1583 default:
1584 tcg_abort();
1585 }
1586 }
1587
1588 static const TCGTargetOpDef mips_op_defs[] = {
1589 { INDEX_op_exit_tb, { } },
1590 { INDEX_op_goto_tb, { } },
1591 { INDEX_op_call, { "C" } },
1592 { INDEX_op_br, { } },
1593
1594 { INDEX_op_mov_i32, { "r", "r" } },
1595 { INDEX_op_movi_i32, { "r" } },
1596 { INDEX_op_ld8u_i32, { "r", "r" } },
1597 { INDEX_op_ld8s_i32, { "r", "r" } },
1598 { INDEX_op_ld16u_i32, { "r", "r" } },
1599 { INDEX_op_ld16s_i32, { "r", "r" } },
1600 { INDEX_op_ld_i32, { "r", "r" } },
1601 { INDEX_op_st8_i32, { "rZ", "r" } },
1602 { INDEX_op_st16_i32, { "rZ", "r" } },
1603 { INDEX_op_st_i32, { "rZ", "r" } },
1604
1605 { INDEX_op_add_i32, { "r", "rZ", "rJ" } },
1606 { INDEX_op_mul_i32, { "r", "rZ", "rZ" } },
1607 { INDEX_op_muls2_i32, { "r", "r", "rZ", "rZ" } },
1608 { INDEX_op_mulu2_i32, { "r", "r", "rZ", "rZ" } },
1609 { INDEX_op_mulsh_i32, { "r", "rZ", "rZ" } },
1610 { INDEX_op_muluh_i32, { "r", "rZ", "rZ" } },
1611 { INDEX_op_div_i32, { "r", "rZ", "rZ" } },
1612 { INDEX_op_divu_i32, { "r", "rZ", "rZ" } },
1613 { INDEX_op_rem_i32, { "r", "rZ", "rZ" } },
1614 { INDEX_op_remu_i32, { "r", "rZ", "rZ" } },
1615 { INDEX_op_sub_i32, { "r", "rZ", "rJ" } },
1616
1617 { INDEX_op_and_i32, { "r", "rZ", "rI" } },
1618 { INDEX_op_nor_i32, { "r", "rZ", "rZ" } },
1619 { INDEX_op_not_i32, { "r", "rZ" } },
1620 { INDEX_op_or_i32, { "r", "rZ", "rIZ" } },
1621 { INDEX_op_xor_i32, { "r", "rZ", "rIZ" } },
1622
1623 { INDEX_op_shl_i32, { "r", "rZ", "ri" } },
1624 { INDEX_op_shr_i32, { "r", "rZ", "ri" } },
1625 { INDEX_op_sar_i32, { "r", "rZ", "ri" } },
1626 { INDEX_op_rotr_i32, { "r", "rZ", "ri" } },
1627 { INDEX_op_rotl_i32, { "r", "rZ", "ri" } },
1628
1629 { INDEX_op_bswap16_i32, { "r", "r" } },
1630 { INDEX_op_bswap32_i32, { "r", "r" } },
1631
1632 { INDEX_op_ext8s_i32, { "r", "rZ" } },
1633 { INDEX_op_ext16s_i32, { "r", "rZ" } },
1634
1635 { INDEX_op_deposit_i32, { "r", "0", "rZ" } },
1636
1637 { INDEX_op_brcond_i32, { "rZ", "rZ" } },
1638 { INDEX_op_movcond_i32, { "r", "rZ", "rZ", "rZ", "0" } },
1639 { INDEX_op_setcond_i32, { "r", "rZ", "rZ" } },
1640 { INDEX_op_setcond2_i32, { "r", "rZ", "rZ", "rZ", "rZ" } },
1641
1642 { INDEX_op_add2_i32, { "r", "r", "rZ", "rZ", "rJ", "rJ" } },
1643 { INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rJ", "rJ" } },
1644 { INDEX_op_brcond2_i32, { "rZ", "rZ", "rZ", "rZ" } },
1645
1646 #if TARGET_LONG_BITS == 32
1647 { INDEX_op_qemu_ld8u, { "L", "lZ" } },
1648 { INDEX_op_qemu_ld8s, { "L", "lZ" } },
1649 { INDEX_op_qemu_ld16u, { "L", "lZ" } },
1650 { INDEX_op_qemu_ld16s, { "L", "lZ" } },
1651 { INDEX_op_qemu_ld32, { "L", "lZ" } },
1652 { INDEX_op_qemu_ld64, { "L", "L", "lZ" } },
1653
1654 { INDEX_op_qemu_st8, { "SZ", "SZ" } },
1655 { INDEX_op_qemu_st16, { "SZ", "SZ" } },
1656 { INDEX_op_qemu_st32, { "SZ", "SZ" } },
1657 { INDEX_op_qemu_st64, { "SZ", "SZ", "SZ" } },
1658 #else
1659 { INDEX_op_qemu_ld8u, { "L", "lZ", "lZ" } },
1660 { INDEX_op_qemu_ld8s, { "L", "lZ", "lZ" } },
1661 { INDEX_op_qemu_ld16u, { "L", "lZ", "lZ" } },
1662 { INDEX_op_qemu_ld16s, { "L", "lZ", "lZ" } },
1663 { INDEX_op_qemu_ld32, { "L", "lZ", "lZ" } },
1664 { INDEX_op_qemu_ld64, { "L", "L", "lZ", "lZ" } },
1665
1666 { INDEX_op_qemu_st8, { "SZ", "SZ", "SZ" } },
1667 { INDEX_op_qemu_st16, { "SZ", "SZ", "SZ" } },
1668 { INDEX_op_qemu_st32, { "SZ", "SZ", "SZ" } },
1669 { INDEX_op_qemu_st64, { "SZ", "SZ", "SZ", "SZ" } },
1670 #endif
1671 { -1 },
1672 };
1673
1674 static int tcg_target_callee_save_regs[] = {
1675 TCG_REG_S0, /* used for the global env (TCG_AREG0) */
1676 TCG_REG_S1,
1677 TCG_REG_S2,
1678 TCG_REG_S3,
1679 TCG_REG_S4,
1680 TCG_REG_S5,
1681 TCG_REG_S6,
1682 TCG_REG_S7,
1683 TCG_REG_FP,
1684 TCG_REG_RA, /* should be last for ABI compliance */
1685 };
1686
1687 /* The Linux kernel doesn't provide any information about the available
1688 instruction set. Probe it using a signal handler. */
1689
1690 #include <signal.h>
1691
1692 #ifndef use_movnz_instructions
1693 bool use_movnz_instructions = false;
1694 #endif
1695
1696 #ifndef use_mips32_instructions
1697 bool use_mips32_instructions = false;
1698 #endif
1699
1700 #ifndef use_mips32r2_instructions
1701 bool use_mips32r2_instructions = false;
1702 #endif
1703
1704 static volatile sig_atomic_t got_sigill;
1705
1706 static void sigill_handler(int signo, siginfo_t *si, void *data)
1707 {
1708 /* Skip the faulty instruction */
1709 ucontext_t *uc = (ucontext_t *)data;
1710 uc->uc_mcontext.pc += 4;
1711
1712 got_sigill = 1;
1713 }
1714
1715 static void tcg_target_detect_isa(void)
1716 {
1717 struct sigaction sa_old, sa_new;
1718
1719 memset(&sa_new, 0, sizeof(sa_new));
1720 sa_new.sa_flags = SA_SIGINFO;
1721 sa_new.sa_sigaction = sigill_handler;
1722 sigaction(SIGILL, &sa_new, &sa_old);
1723
1724 /* Probe for movn/movz, necessary to implement movcond. */
1725 #ifndef use_movnz_instructions
1726 got_sigill = 0;
1727 asm volatile(".set push\n"
1728 ".set mips32\n"
1729 "movn $zero, $zero, $zero\n"
1730 "movz $zero, $zero, $zero\n"
1731 ".set pop\n"
1732 : : : );
1733 use_movnz_instructions = !got_sigill;
1734 #endif
1735
1736 /* Probe for MIPS32 instructions. As no subsetting is allowed
1737 by the specification, it is only necessary to probe for one
1738 of the instructions. */
1739 #ifndef use_mips32_instructions
1740 got_sigill = 0;
1741 asm volatile(".set push\n"
1742 ".set mips32\n"
1743 "mul $zero, $zero\n"
1744 ".set pop\n"
1745 : : : );
1746 use_mips32_instructions = !got_sigill;
1747 #endif
1748
1749 /* Probe for MIPS32r2 instructions if MIPS32 instructions are
1750 available. As no subsetting is allowed by the specification,
1751 it is only necessary to probe for one of the instructions. */
1752 #ifndef use_mips32r2_instructions
1753 if (use_mips32_instructions) {
1754 got_sigill = 0;
1755 asm volatile(".set push\n"
1756 ".set mips32r2\n"
1757 "seb $zero, $zero\n"
1758 ".set pop\n"
1759 : : : );
1760 use_mips32r2_instructions = !got_sigill;
1761 }
1762 #endif
1763
1764 sigaction(SIGILL, &sa_old, NULL);
1765 }
1766
1767 /* Generate global QEMU prologue and epilogue code */
1768 static void tcg_target_qemu_prologue(TCGContext *s)
1769 {
1770 int i, frame_size;
1771
1772 /* reserve some stack space, also for TCG temps. */
1773 frame_size = ARRAY_SIZE(tcg_target_callee_save_regs) * 4
1774 + TCG_STATIC_CALL_ARGS_SIZE
1775 + CPU_TEMP_BUF_NLONGS * sizeof(long);
1776 frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
1777 ~(TCG_TARGET_STACK_ALIGN - 1);
1778 tcg_set_frame(s, TCG_REG_SP, ARRAY_SIZE(tcg_target_callee_save_regs) * 4
1779 + TCG_STATIC_CALL_ARGS_SIZE,
1780 CPU_TEMP_BUF_NLONGS * sizeof(long));
1781
1782 /* TB prologue */
1783 tcg_out_addi(s, TCG_REG_SP, -frame_size);
1784 for(i = 0 ; i < ARRAY_SIZE(tcg_target_callee_save_regs) ; i++) {
1785 tcg_out_st(s, TCG_TYPE_I32, tcg_target_callee_save_regs[i],
1786 TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE + i * 4);
1787 }
1788
1789 /* Call generated code */
1790 tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0);
1791 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
1792 tb_ret_addr = s->code_ptr;
1793
1794 /* TB epilogue */
1795 for(i = 0 ; i < ARRAY_SIZE(tcg_target_callee_save_regs) ; i++) {
1796 tcg_out_ld(s, TCG_TYPE_I32, tcg_target_callee_save_regs[i],
1797 TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE + i * 4);
1798 }
1799
1800 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
1801 tcg_out_addi(s, TCG_REG_SP, frame_size);
1802 }
1803
1804 static void tcg_target_init(TCGContext *s)
1805 {
1806 tcg_target_detect_isa();
1807 tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I32], 0xffffffff);
1808 tcg_regset_set(tcg_target_call_clobber_regs,
1809 (1 << TCG_REG_V0) |
1810 (1 << TCG_REG_V1) |
1811 (1 << TCG_REG_A0) |
1812 (1 << TCG_REG_A1) |
1813 (1 << TCG_REG_A2) |
1814 (1 << TCG_REG_A3) |
1815 (1 << TCG_REG_T1) |
1816 (1 << TCG_REG_T2) |
1817 (1 << TCG_REG_T3) |
1818 (1 << TCG_REG_T4) |
1819 (1 << TCG_REG_T5) |
1820 (1 << TCG_REG_T6) |
1821 (1 << TCG_REG_T7) |
1822 (1 << TCG_REG_T8) |
1823 (1 << TCG_REG_T9));
1824
1825 tcg_regset_clear(s->reserved_regs);
1826 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */
1827 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */
1828 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */
1829 tcg_regset_set_reg(s->reserved_regs, TCG_REG_AT); /* internal use */
1830 tcg_regset_set_reg(s->reserved_regs, TCG_REG_T0); /* internal use */
1831 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */
1832 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */
1833 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */
1834
1835 tcg_add_target_add_op_defs(mips_op_defs);
1836 }
Qemu copy for testing