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[qemu.git] / tcg / ppc / tcg-target.c
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 static uint8_t *tb_ret_addr;
26
27 #if defined _CALL_DARWIN || defined __APPLE__
28 #define TCG_TARGET_CALL_DARWIN
29 #endif
30
31 #ifdef TCG_TARGET_CALL_DARWIN
32 #define LINKAGE_AREA_SIZE 24
33 #define LR_OFFSET 8
34 #elif defined _CALL_AIX
35 #define LINKAGE_AREA_SIZE 52
36 #define LR_OFFSET 8
37 #else
38 #define LINKAGE_AREA_SIZE 8
39 #define LR_OFFSET 4
40 #endif
41
42 #define FAST_PATH
43
44 #ifndef GUEST_BASE
45 #define GUEST_BASE 0
46 #endif
47
48 #ifdef CONFIG_USE_GUEST_BASE
49 #define TCG_GUEST_BASE_REG 30
50 #else
51 #define TCG_GUEST_BASE_REG 0
52 #endif
53
54 #ifndef NDEBUG
55 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
56 "r0",
57 "r1",
58 "r2",
59 "r3",
60 "r4",
61 "r5",
62 "r6",
63 "r7",
64 "r8",
65 "r9",
66 "r10",
67 "r11",
68 "r12",
69 "r13",
70 "r14",
71 "r15",
72 "r16",
73 "r17",
74 "r18",
75 "r19",
76 "r20",
77 "r21",
78 "r22",
79 "r23",
80 "r24",
81 "r25",
82 "r26",
83 "r27",
84 "r28",
85 "r29",
86 "r30",
87 "r31"
88 };
89 #endif
90
91 static const int tcg_target_reg_alloc_order[] = {
92 TCG_REG_R14,
93 TCG_REG_R15,
94 TCG_REG_R16,
95 TCG_REG_R17,
96 TCG_REG_R18,
97 TCG_REG_R19,
98 TCG_REG_R20,
99 TCG_REG_R21,
100 TCG_REG_R22,
101 TCG_REG_R23,
102 TCG_REG_R28,
103 TCG_REG_R29,
104 TCG_REG_R30,
105 TCG_REG_R31,
106 #ifdef TCG_TARGET_CALL_DARWIN
107 TCG_REG_R2,
108 #endif
109 TCG_REG_R3,
110 TCG_REG_R4,
111 TCG_REG_R5,
112 TCG_REG_R6,
113 TCG_REG_R7,
114 TCG_REG_R8,
115 TCG_REG_R9,
116 TCG_REG_R10,
117 #ifndef TCG_TARGET_CALL_DARWIN
118 TCG_REG_R11,
119 #endif
120 TCG_REG_R12,
121 #ifndef _CALL_SYSV
122 TCG_REG_R13,
123 #endif
124 TCG_REG_R24,
125 TCG_REG_R25,
126 TCG_REG_R26,
127 TCG_REG_R27
128 };
129
130 static const int tcg_target_call_iarg_regs[] = {
131 TCG_REG_R3,
132 TCG_REG_R4,
133 TCG_REG_R5,
134 TCG_REG_R6,
135 TCG_REG_R7,
136 TCG_REG_R8,
137 TCG_REG_R9,
138 TCG_REG_R10
139 };
140
141 static const int tcg_target_call_oarg_regs[2] = {
142 TCG_REG_R3,
143 TCG_REG_R4
144 };
145
146 static const int tcg_target_callee_save_regs[] = {
147 #ifdef TCG_TARGET_CALL_DARWIN
148 TCG_REG_R11,
149 TCG_REG_R13,
150 #endif
151 #ifdef _CALL_AIX
152 TCG_REG_R13,
153 #endif
154 TCG_REG_R14,
155 TCG_REG_R15,
156 TCG_REG_R16,
157 TCG_REG_R17,
158 TCG_REG_R18,
159 TCG_REG_R19,
160 TCG_REG_R20,
161 TCG_REG_R21,
162 TCG_REG_R22,
163 TCG_REG_R23,
164 TCG_REG_R24,
165 TCG_REG_R25,
166 TCG_REG_R26,
167 TCG_REG_R27, /* currently used for the global env */
168 TCG_REG_R28,
169 TCG_REG_R29,
170 TCG_REG_R30,
171 TCG_REG_R31
172 };
173
174 static uint32_t reloc_pc24_val (void *pc, tcg_target_long target)
175 {
176 tcg_target_long disp;
177
178 disp = target - (tcg_target_long) pc;
179 if ((disp << 6) >> 6 != disp)
180 tcg_abort ();
181
182 return disp & 0x3fffffc;
183 }
184
185 static void reloc_pc24 (void *pc, tcg_target_long target)
186 {
187 *(uint32_t *) pc = (*(uint32_t *) pc & ~0x3fffffc)
188 | reloc_pc24_val (pc, target);
189 }
190
191 static uint16_t reloc_pc14_val (void *pc, tcg_target_long target)
192 {
193 tcg_target_long disp;
194
195 disp = target - (tcg_target_long) pc;
196 if (disp != (int16_t) disp)
197 tcg_abort ();
198
199 return disp & 0xfffc;
200 }
201
202 static void reloc_pc14 (void *pc, tcg_target_long target)
203 {
204 *(uint32_t *) pc = (*(uint32_t *) pc & ~0xfffc)
205 | reloc_pc14_val (pc, target);
206 }
207
208 static void patch_reloc(uint8_t *code_ptr, int type,
209 tcg_target_long value, tcg_target_long addend)
210 {
211 value += addend;
212 switch (type) {
213 case R_PPC_REL14:
214 reloc_pc14 (code_ptr, value);
215 break;
216 case R_PPC_REL24:
217 reloc_pc24 (code_ptr, value);
218 break;
219 default:
220 tcg_abort();
221 }
222 }
223
224 /* maximum number of register used for input function arguments */
225 static int tcg_target_get_call_iarg_regs_count(int flags)
226 {
227 return ARRAY_SIZE (tcg_target_call_iarg_regs);
228 }
229
230 /* parse target specific constraints */
231 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
232 {
233 const char *ct_str;
234
235 ct_str = *pct_str;
236 switch (ct_str[0]) {
237 case 'A': case 'B': case 'C': case 'D':
238 ct->ct |= TCG_CT_REG;
239 tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
240 break;
241 case 'r':
242 ct->ct |= TCG_CT_REG;
243 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
244 break;
245 #ifdef CONFIG_SOFTMMU
246 case 'L': /* qemu_ld constraint */
247 ct->ct |= TCG_CT_REG;
248 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
249 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
250 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
251 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
252 #if TARGET_LONG_BITS == 64
253 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
254 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
255 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);
256 #endif
257 #endif
258 break;
259 case 'K': /* qemu_st[8..32] constraint */
260 ct->ct |= TCG_CT_REG;
261 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
262 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
263 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
264 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
265 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
266 #if TARGET_LONG_BITS == 64
267 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);
268 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
269 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R8);
270 #endif
271 #endif
272 break;
273 case 'M': /* qemu_st64 constraint */
274 ct->ct |= TCG_CT_REG;
275 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
276 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
277 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
278 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
279 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
280 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);
281 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R8);
282 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
283 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R9);
284 #endif
285 break;
286 #else
287 case 'L':
288 case 'K':
289 ct->ct |= TCG_CT_REG;
290 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
291 break;
292 case 'M':
293 ct->ct |= TCG_CT_REG;
294 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
295 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
296 break;
297 #endif
298 default:
299 return -1;
300 }
301 ct_str++;
302 *pct_str = ct_str;
303 return 0;
304 }
305
306 /* test if a constant matches the constraint */
307 static int tcg_target_const_match(tcg_target_long val,
308 const TCGArgConstraint *arg_ct)
309 {
310 int ct;
311
312 ct = arg_ct->ct;
313 if (ct & TCG_CT_CONST)
314 return 1;
315 return 0;
316 }
317
318 #define OPCD(opc) ((opc)<<26)
319 #define XO31(opc) (OPCD(31)|((opc)<<1))
320 #define XO19(opc) (OPCD(19)|((opc)<<1))
321
322 #define B OPCD(18)
323 #define BC OPCD(16)
324 #define LBZ OPCD(34)
325 #define LHZ OPCD(40)
326 #define LHA OPCD(42)
327 #define LWZ OPCD(32)
328 #define STB OPCD(38)
329 #define STH OPCD(44)
330 #define STW OPCD(36)
331
332 #define ADDIC OPCD(12)
333 #define ADDI OPCD(14)
334 #define ADDIS OPCD(15)
335 #define ORI OPCD(24)
336 #define ORIS OPCD(25)
337 #define XORI OPCD(26)
338 #define XORIS OPCD(27)
339 #define ANDI OPCD(28)
340 #define ANDIS OPCD(29)
341 #define MULLI OPCD( 7)
342 #define CMPLI OPCD(10)
343 #define CMPI OPCD(11)
344 #define SUBFIC OPCD( 8)
345
346 #define LWZU OPCD(33)
347 #define STWU OPCD(37)
348
349 #define RLWIMI OPCD(20)
350 #define RLWINM OPCD(21)
351 #define RLWNM OPCD(23)
352
353 #define BCLR XO19( 16)
354 #define BCCTR XO19(528)
355 #define CRAND XO19(257)
356 #define CRANDC XO19(129)
357 #define CRNAND XO19(225)
358 #define CROR XO19(449)
359 #define CRNOR XO19( 33)
360
361 #define EXTSB XO31(954)
362 #define EXTSH XO31(922)
363 #define ADD XO31(266)
364 #define ADDE XO31(138)
365 #define ADDC XO31( 10)
366 #define AND XO31( 28)
367 #define SUBF XO31( 40)
368 #define SUBFC XO31( 8)
369 #define SUBFE XO31(136)
370 #define OR XO31(444)
371 #define XOR XO31(316)
372 #define MULLW XO31(235)
373 #define MULHWU XO31( 11)
374 #define DIVW XO31(491)
375 #define DIVWU XO31(459)
376 #define CMP XO31( 0)
377 #define CMPL XO31( 32)
378 #define LHBRX XO31(790)
379 #define LWBRX XO31(534)
380 #define STHBRX XO31(918)
381 #define STWBRX XO31(662)
382 #define MFSPR XO31(339)
383 #define MTSPR XO31(467)
384 #define SRAWI XO31(824)
385 #define NEG XO31(104)
386 #define MFCR XO31( 19)
387 #define CNTLZW XO31( 26)
388 #define NOR XO31(124)
389 #define ANDC XO31( 60)
390 #define ORC XO31(412)
391 #define EQV XO31(284)
392 #define NAND XO31(476)
393
394 #define LBZX XO31( 87)
395 #define LHZX XO31(279)
396 #define LHAX XO31(343)
397 #define LWZX XO31( 23)
398 #define STBX XO31(215)
399 #define STHX XO31(407)
400 #define STWX XO31(151)
401
402 #define SPR(a,b) ((((a)<<5)|(b))<<11)
403 #define LR SPR(8, 0)
404 #define CTR SPR(9, 0)
405
406 #define SLW XO31( 24)
407 #define SRW XO31(536)
408 #define SRAW XO31(792)
409
410 #define TW XO31(4)
411 #define TRAP (TW | TO (31))
412
413 #define RT(r) ((r)<<21)
414 #define RS(r) ((r)<<21)
415 #define RA(r) ((r)<<16)
416 #define RB(r) ((r)<<11)
417 #define TO(t) ((t)<<21)
418 #define SH(s) ((s)<<11)
419 #define MB(b) ((b)<<6)
420 #define ME(e) ((e)<<1)
421 #define BO(o) ((o)<<21)
422
423 #define LK 1
424
425 #define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
426 #define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
427
428 #define BF(n) ((n)<<23)
429 #define BI(n, c) (((c)+((n)*4))<<16)
430 #define BT(n, c) (((c)+((n)*4))<<21)
431 #define BA(n, c) (((c)+((n)*4))<<16)
432 #define BB(n, c) (((c)+((n)*4))<<11)
433
434 #define BO_COND_TRUE BO (12)
435 #define BO_COND_FALSE BO (4)
436 #define BO_ALWAYS BO (20)
437
438 enum {
439 CR_LT,
440 CR_GT,
441 CR_EQ,
442 CR_SO
443 };
444
445 static const uint32_t tcg_to_bc[10] = {
446 [TCG_COND_EQ] = BC | BI (7, CR_EQ) | BO_COND_TRUE,
447 [TCG_COND_NE] = BC | BI (7, CR_EQ) | BO_COND_FALSE,
448 [TCG_COND_LT] = BC | BI (7, CR_LT) | BO_COND_TRUE,
449 [TCG_COND_GE] = BC | BI (7, CR_LT) | BO_COND_FALSE,
450 [TCG_COND_LE] = BC | BI (7, CR_GT) | BO_COND_FALSE,
451 [TCG_COND_GT] = BC | BI (7, CR_GT) | BO_COND_TRUE,
452 [TCG_COND_LTU] = BC | BI (7, CR_LT) | BO_COND_TRUE,
453 [TCG_COND_GEU] = BC | BI (7, CR_LT) | BO_COND_FALSE,
454 [TCG_COND_LEU] = BC | BI (7, CR_GT) | BO_COND_FALSE,
455 [TCG_COND_GTU] = BC | BI (7, CR_GT) | BO_COND_TRUE,
456 };
457
458 static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
459 {
460 tcg_out32 (s, OR | SAB (arg, ret, arg));
461 }
462
463 static void tcg_out_movi(TCGContext *s, TCGType type,
464 TCGReg ret, tcg_target_long arg)
465 {
466 if (arg == (int16_t) arg)
467 tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff));
468 else {
469 tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff));
470 if (arg & 0xffff)
471 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
472 }
473 }
474
475 static void tcg_out_ldst (TCGContext *s, int ret, int addr,
476 int offset, int op1, int op2)
477 {
478 if (offset == (int16_t) offset)
479 tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff));
480 else {
481 tcg_out_movi (s, TCG_TYPE_I32, 0, offset);
482 tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
483 }
484 }
485
486 static void tcg_out_b (TCGContext *s, int mask, tcg_target_long target)
487 {
488 tcg_target_long disp;
489
490 disp = target - (tcg_target_long) s->code_ptr;
491 if ((disp << 6) >> 6 == disp)
492 tcg_out32 (s, B | (disp & 0x3fffffc) | mask);
493 else {
494 tcg_out_movi (s, TCG_TYPE_I32, 0, (tcg_target_long) target);
495 tcg_out32 (s, MTSPR | RS (0) | CTR);
496 tcg_out32 (s, BCCTR | BO_ALWAYS | mask);
497 }
498 }
499
500 static void tcg_out_call (TCGContext *s, tcg_target_long arg, int const_arg)
501 {
502 #ifdef _CALL_AIX
503 int reg;
504
505 if (const_arg) {
506 reg = 2;
507 tcg_out_movi (s, TCG_TYPE_I32, reg, arg);
508 }
509 else reg = arg;
510
511 tcg_out32 (s, LWZ | RT (0) | RA (reg));
512 tcg_out32 (s, MTSPR | RA (0) | CTR);
513 tcg_out32 (s, LWZ | RT (2) | RA (reg) | 4);
514 tcg_out32 (s, BCCTR | BO_ALWAYS | LK);
515 #else
516 if (const_arg) {
517 tcg_out_b (s, LK, arg);
518 }
519 else {
520 tcg_out32 (s, MTSPR | RS (arg) | LR);
521 tcg_out32 (s, BCLR | BO_ALWAYS | LK);
522 }
523 #endif
524 }
525
526 #if defined(CONFIG_SOFTMMU)
527
528 #include "../../softmmu_defs.h"
529
530 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
531 int mmu_idx) */
532 static const void * const qemu_ld_helpers[4] = {
533 helper_ldb_mmu,
534 helper_ldw_mmu,
535 helper_ldl_mmu,
536 helper_ldq_mmu,
537 };
538
539 /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
540 uintxx_t val, int mmu_idx) */
541 static const void * const qemu_st_helpers[4] = {
542 helper_stb_mmu,
543 helper_stw_mmu,
544 helper_stl_mmu,
545 helper_stq_mmu,
546 };
547 #endif
548
549 static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
550 {
551 int addr_reg, data_reg, data_reg2, r0, r1, rbase, bswap;
552 #ifdef CONFIG_SOFTMMU
553 int mem_index, s_bits, r2, ir;
554 void *label1_ptr, *label2_ptr;
555 #if TARGET_LONG_BITS == 64
556 int addr_reg2;
557 #endif
558 #endif
559
560 data_reg = *args++;
561 if (opc == 3)
562 data_reg2 = *args++;
563 else
564 data_reg2 = 0;
565 addr_reg = *args++;
566
567 #ifdef CONFIG_SOFTMMU
568 #if TARGET_LONG_BITS == 64
569 addr_reg2 = *args++;
570 #endif
571 mem_index = *args;
572 s_bits = opc & 3;
573 r0 = 3;
574 r1 = 4;
575 r2 = 0;
576 rbase = 0;
577
578 tcg_out32 (s, (RLWINM
579 | RA (r0)
580 | RS (addr_reg)
581 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
582 | MB (32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS))
583 | ME (31 - CPU_TLB_ENTRY_BITS)
584 )
585 );
586 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
587 tcg_out32 (s, (LWZU
588 | RT (r1)
589 | RA (r0)
590 | offsetof (CPUArchState, tlb_table[mem_index][0].addr_read)
591 )
592 );
593 tcg_out32 (s, (RLWINM
594 | RA (r2)
595 | RS (addr_reg)
596 | SH (0)
597 | MB ((32 - s_bits) & 31)
598 | ME (31 - TARGET_PAGE_BITS)
599 )
600 );
601
602 tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1));
603 #if TARGET_LONG_BITS == 64
604 tcg_out32 (s, LWZ | RT (r1) | RA (r0) | 4);
605 tcg_out32 (s, CMP | BF (6) | RA (addr_reg2) | RB (r1));
606 tcg_out32 (s, CRAND | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
607 #endif
608
609 label1_ptr = s->code_ptr;
610 #ifdef FAST_PATH
611 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
612 #endif
613
614 /* slow path */
615 ir = 3;
616 tcg_out_mov (s, TCG_TYPE_I32, ir++, TCG_AREG0);
617 #if TARGET_LONG_BITS == 32
618 tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg);
619 #else
620 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
621 ir |= 1;
622 #endif
623 tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg2);
624 tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg);
625 #endif
626 tcg_out_movi (s, TCG_TYPE_I32, ir, mem_index);
627
628 tcg_out_call (s, (tcg_target_long) qemu_ld_helpers[s_bits], 1);
629 switch (opc) {
630 case 0|4:
631 tcg_out32 (s, EXTSB | RA (data_reg) | RS (3));
632 break;
633 case 1|4:
634 tcg_out32 (s, EXTSH | RA (data_reg) | RS (3));
635 break;
636 case 0:
637 case 1:
638 case 2:
639 if (data_reg != 3)
640 tcg_out_mov (s, TCG_TYPE_I32, data_reg, 3);
641 break;
642 case 3:
643 if (data_reg == 3) {
644 if (data_reg2 == 4) {
645 tcg_out_mov (s, TCG_TYPE_I32, 0, 4);
646 tcg_out_mov (s, TCG_TYPE_I32, 4, 3);
647 tcg_out_mov (s, TCG_TYPE_I32, 3, 0);
648 }
649 else {
650 tcg_out_mov (s, TCG_TYPE_I32, data_reg2, 3);
651 tcg_out_mov (s, TCG_TYPE_I32, 3, 4);
652 }
653 }
654 else {
655 if (data_reg != 4) tcg_out_mov (s, TCG_TYPE_I32, data_reg, 4);
656 if (data_reg2 != 3) tcg_out_mov (s, TCG_TYPE_I32, data_reg2, 3);
657 }
658 break;
659 }
660 label2_ptr = s->code_ptr;
661 tcg_out32 (s, B);
662
663 /* label1: fast path */
664 #ifdef FAST_PATH
665 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
666 #endif
667
668 /* r0 now contains &env->tlb_table[mem_index][index].addr_read */
669 tcg_out32 (s, (LWZ
670 | RT (r0)
671 | RA (r0)
672 | (offsetof (CPUTLBEntry, addend)
673 - offsetof (CPUTLBEntry, addr_read))
674 ));
675 /* r0 = env->tlb_table[mem_index][index].addend */
676 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
677 /* r0 = env->tlb_table[mem_index][index].addend + addr */
678
679 #else /* !CONFIG_SOFTMMU */
680 r0 = addr_reg;
681 r1 = 3;
682 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
683 #endif
684
685 #ifdef TARGET_WORDS_BIGENDIAN
686 bswap = 0;
687 #else
688 bswap = 1;
689 #endif
690
691 switch (opc) {
692 default:
693 case 0:
694 tcg_out32 (s, LBZX | TAB (data_reg, rbase, r0));
695 break;
696 case 0|4:
697 tcg_out32 (s, LBZX | TAB (data_reg, rbase, r0));
698 tcg_out32 (s, EXTSB | RA (data_reg) | RS (data_reg));
699 break;
700 case 1:
701 if (bswap)
702 tcg_out32 (s, LHBRX | TAB (data_reg, rbase, r0));
703 else
704 tcg_out32 (s, LHZX | TAB (data_reg, rbase, r0));
705 break;
706 case 1|4:
707 if (bswap) {
708 tcg_out32 (s, LHBRX | TAB (data_reg, rbase, r0));
709 tcg_out32 (s, EXTSH | RA (data_reg) | RS (data_reg));
710 }
711 else tcg_out32 (s, LHAX | TAB (data_reg, rbase, r0));
712 break;
713 case 2:
714 if (bswap)
715 tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
716 else
717 tcg_out32 (s, LWZX | TAB (data_reg, rbase, r0));
718 break;
719 case 3:
720 if (bswap) {
721 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
722 tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
723 tcg_out32 (s, LWBRX | TAB (data_reg2, rbase, r1));
724 }
725 else {
726 #ifdef CONFIG_USE_GUEST_BASE
727 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
728 tcg_out32 (s, LWZX | TAB (data_reg2, rbase, r0));
729 tcg_out32 (s, LWZX | TAB (data_reg, rbase, r1));
730 #else
731 if (r0 == data_reg2) {
732 tcg_out32 (s, LWZ | RT (0) | RA (r0));
733 tcg_out32 (s, LWZ | RT (data_reg) | RA (r0) | 4);
734 tcg_out_mov (s, TCG_TYPE_I32, data_reg2, 0);
735 }
736 else {
737 tcg_out32 (s, LWZ | RT (data_reg2) | RA (r0));
738 tcg_out32 (s, LWZ | RT (data_reg) | RA (r0) | 4);
739 }
740 #endif
741 }
742 break;
743 }
744
745 #ifdef CONFIG_SOFTMMU
746 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
747 #endif
748 }
749
750 static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
751 {
752 int addr_reg, r0, r1, data_reg, data_reg2, bswap, rbase;
753 #ifdef CONFIG_SOFTMMU
754 int mem_index, r2, ir;
755 void *label1_ptr, *label2_ptr;
756 #if TARGET_LONG_BITS == 64
757 int addr_reg2;
758 #endif
759 #endif
760
761 data_reg = *args++;
762 if (opc == 3)
763 data_reg2 = *args++;
764 else
765 data_reg2 = 0;
766 addr_reg = *args++;
767
768 #ifdef CONFIG_SOFTMMU
769 #if TARGET_LONG_BITS == 64
770 addr_reg2 = *args++;
771 #endif
772 mem_index = *args;
773 r0 = 3;
774 r1 = 4;
775 r2 = 0;
776 rbase = 0;
777
778 tcg_out32 (s, (RLWINM
779 | RA (r0)
780 | RS (addr_reg)
781 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
782 | MB (32 - (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS))
783 | ME (31 - CPU_TLB_ENTRY_BITS)
784 )
785 );
786 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
787 tcg_out32 (s, (LWZU
788 | RT (r1)
789 | RA (r0)
790 | offsetof (CPUArchState, tlb_table[mem_index][0].addr_write)
791 )
792 );
793 tcg_out32 (s, (RLWINM
794 | RA (r2)
795 | RS (addr_reg)
796 | SH (0)
797 | MB ((32 - opc) & 31)
798 | ME (31 - TARGET_PAGE_BITS)
799 )
800 );
801
802 tcg_out32 (s, CMP | (7 << 23) | RA (r2) | RB (r1));
803 #if TARGET_LONG_BITS == 64
804 tcg_out32 (s, LWZ | RT (r1) | RA (r0) | 4);
805 tcg_out32 (s, CMP | BF (6) | RA (addr_reg2) | RB (r1));
806 tcg_out32 (s, CRAND | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
807 #endif
808
809 label1_ptr = s->code_ptr;
810 #ifdef FAST_PATH
811 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
812 #endif
813
814 /* slow path */
815 ir = 3;
816 tcg_out_mov (s, TCG_TYPE_I32, ir++, TCG_AREG0);
817 #if TARGET_LONG_BITS == 32
818 tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg);
819 #else
820 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
821 ir |= 1;
822 #endif
823 tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg2);
824 tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg);
825 #endif
826
827 switch (opc) {
828 case 0:
829 tcg_out32 (s, (RLWINM
830 | RA (ir)
831 | RS (data_reg)
832 | SH (0)
833 | MB (24)
834 | ME (31)));
835 break;
836 case 1:
837 tcg_out32 (s, (RLWINM
838 | RA (ir)
839 | RS (data_reg)
840 | SH (0)
841 | MB (16)
842 | ME (31)));
843 break;
844 case 2:
845 tcg_out_mov (s, TCG_TYPE_I32, ir, data_reg);
846 break;
847 case 3:
848 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
849 ir |= 1;
850 #endif
851 tcg_out_mov (s, TCG_TYPE_I32, ir++, data_reg2);
852 tcg_out_mov (s, TCG_TYPE_I32, ir, data_reg);
853 break;
854 }
855 ir++;
856
857 tcg_out_movi (s, TCG_TYPE_I32, ir, mem_index);
858 tcg_out_call (s, (tcg_target_long) qemu_st_helpers[opc], 1);
859 label2_ptr = s->code_ptr;
860 tcg_out32 (s, B);
861
862 /* label1: fast path */
863 #ifdef FAST_PATH
864 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
865 #endif
866
867 tcg_out32 (s, (LWZ
868 | RT (r0)
869 | RA (r0)
870 | (offsetof (CPUTLBEntry, addend)
871 - offsetof (CPUTLBEntry, addr_write))
872 ));
873 /* r0 = env->tlb_table[mem_index][index].addend */
874 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
875 /* r0 = env->tlb_table[mem_index][index].addend + addr */
876
877 #else /* !CONFIG_SOFTMMU */
878 r0 = addr_reg;
879 r1 = 3;
880 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
881 #endif
882
883 #ifdef TARGET_WORDS_BIGENDIAN
884 bswap = 0;
885 #else
886 bswap = 1;
887 #endif
888 switch (opc) {
889 case 0:
890 tcg_out32 (s, STBX | SAB (data_reg, rbase, r0));
891 break;
892 case 1:
893 if (bswap)
894 tcg_out32 (s, STHBRX | SAB (data_reg, rbase, r0));
895 else
896 tcg_out32 (s, STHX | SAB (data_reg, rbase, r0));
897 break;
898 case 2:
899 if (bswap)
900 tcg_out32 (s, STWBRX | SAB (data_reg, rbase, r0));
901 else
902 tcg_out32 (s, STWX | SAB (data_reg, rbase, r0));
903 break;
904 case 3:
905 if (bswap) {
906 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
907 tcg_out32 (s, STWBRX | SAB (data_reg, rbase, r0));
908 tcg_out32 (s, STWBRX | SAB (data_reg2, rbase, r1));
909 }
910 else {
911 #ifdef CONFIG_USE_GUEST_BASE
912 tcg_out32 (s, STWX | SAB (data_reg2, rbase, r0));
913 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
914 tcg_out32 (s, STWX | SAB (data_reg, rbase, r1));
915 #else
916 tcg_out32 (s, STW | RS (data_reg2) | RA (r0));
917 tcg_out32 (s, STW | RS (data_reg) | RA (r0) | 4);
918 #endif
919 }
920 break;
921 }
922
923 #ifdef CONFIG_SOFTMMU
924 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
925 #endif
926 }
927
928 static void tcg_target_qemu_prologue (TCGContext *s)
929 {
930 int i, frame_size;
931
932 frame_size = 0
933 + LINKAGE_AREA_SIZE
934 + TCG_STATIC_CALL_ARGS_SIZE
935 + ARRAY_SIZE (tcg_target_callee_save_regs) * 4
936 + CPU_TEMP_BUF_NLONGS * sizeof(long)
937 ;
938 frame_size = (frame_size + 15) & ~15;
939
940 tcg_set_frame(s, TCG_REG_CALL_STACK, frame_size
941 - CPU_TEMP_BUF_NLONGS * sizeof(long),
942 CPU_TEMP_BUF_NLONGS * sizeof(long));
943
944 #ifdef _CALL_AIX
945 {
946 uint32_t addr;
947
948 /* First emit adhoc function descriptor */
949 addr = (uint32_t) s->code_ptr + 12;
950 tcg_out32 (s, addr); /* entry point */
951 s->code_ptr += 8; /* skip TOC and environment pointer */
952 }
953 #endif
954 tcg_out32 (s, MFSPR | RT (0) | LR);
955 tcg_out32 (s, STWU | RS (1) | RA (1) | (-frame_size & 0xffff));
956 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
957 tcg_out32 (s, (STW
958 | RS (tcg_target_callee_save_regs[i])
959 | RA (1)
960 | (i * 4 + LINKAGE_AREA_SIZE + TCG_STATIC_CALL_ARGS_SIZE)
961 )
962 );
963 tcg_out32 (s, STW | RS (0) | RA (1) | (frame_size + LR_OFFSET));
964
965 #ifdef CONFIG_USE_GUEST_BASE
966 if (GUEST_BASE) {
967 tcg_out_movi (s, TCG_TYPE_I32, TCG_GUEST_BASE_REG, GUEST_BASE);
968 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
969 }
970 #endif
971
972 tcg_out_mov (s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
973 tcg_out32 (s, MTSPR | RS (tcg_target_call_iarg_regs[1]) | CTR);
974 tcg_out32 (s, BCCTR | BO_ALWAYS);
975 tb_ret_addr = s->code_ptr;
976
977 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
978 tcg_out32 (s, (LWZ
979 | RT (tcg_target_callee_save_regs[i])
980 | RA (1)
981 | (i * 4 + LINKAGE_AREA_SIZE + TCG_STATIC_CALL_ARGS_SIZE)
982 )
983 );
984 tcg_out32 (s, LWZ | RT (0) | RA (1) | (frame_size + LR_OFFSET));
985 tcg_out32 (s, MTSPR | RS (0) | LR);
986 tcg_out32 (s, ADDI | RT (1) | RA (1) | frame_size);
987 tcg_out32 (s, BCLR | BO_ALWAYS);
988 }
989
990 static void tcg_out_ld (TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
991 tcg_target_long arg2)
992 {
993 tcg_out_ldst (s, ret, arg1, arg2, LWZ, LWZX);
994 }
995
996 static void tcg_out_st (TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1,
997 tcg_target_long arg2)
998 {
999 tcg_out_ldst (s, arg, arg1, arg2, STW, STWX);
1000 }
1001
1002 static void ppc_addi (TCGContext *s, int rt, int ra, tcg_target_long si)
1003 {
1004 if (!si && rt == ra)
1005 return;
1006
1007 if (si == (int16_t) si)
1008 tcg_out32 (s, ADDI | RT (rt) | RA (ra) | (si & 0xffff));
1009 else {
1010 uint16_t h = ((si >> 16) & 0xffff) + ((uint16_t) si >> 15);
1011 tcg_out32 (s, ADDIS | RT (rt) | RA (ra) | h);
1012 tcg_out32 (s, ADDI | RT (rt) | RA (rt) | (si & 0xffff));
1013 }
1014 }
1015
1016 static void tcg_out_cmp (TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
1017 int const_arg2, int cr)
1018 {
1019 int imm;
1020 uint32_t op;
1021
1022 switch (cond) {
1023 case TCG_COND_EQ:
1024 case TCG_COND_NE:
1025 if (const_arg2) {
1026 if ((int16_t) arg2 == arg2) {
1027 op = CMPI;
1028 imm = 1;
1029 break;
1030 }
1031 else if ((uint16_t) arg2 == arg2) {
1032 op = CMPLI;
1033 imm = 1;
1034 break;
1035 }
1036 }
1037 op = CMPL;
1038 imm = 0;
1039 break;
1040
1041 case TCG_COND_LT:
1042 case TCG_COND_GE:
1043 case TCG_COND_LE:
1044 case TCG_COND_GT:
1045 if (const_arg2) {
1046 if ((int16_t) arg2 == arg2) {
1047 op = CMPI;
1048 imm = 1;
1049 break;
1050 }
1051 }
1052 op = CMP;
1053 imm = 0;
1054 break;
1055
1056 case TCG_COND_LTU:
1057 case TCG_COND_GEU:
1058 case TCG_COND_LEU:
1059 case TCG_COND_GTU:
1060 if (const_arg2) {
1061 if ((uint16_t) arg2 == arg2) {
1062 op = CMPLI;
1063 imm = 1;
1064 break;
1065 }
1066 }
1067 op = CMPL;
1068 imm = 0;
1069 break;
1070
1071 default:
1072 tcg_abort ();
1073 }
1074 op |= BF (cr);
1075
1076 if (imm)
1077 tcg_out32 (s, op | RA (arg1) | (arg2 & 0xffff));
1078 else {
1079 if (const_arg2) {
1080 tcg_out_movi (s, TCG_TYPE_I32, 0, arg2);
1081 tcg_out32 (s, op | RA (arg1) | RB (0));
1082 }
1083 else
1084 tcg_out32 (s, op | RA (arg1) | RB (arg2));
1085 }
1086
1087 }
1088
1089 static void tcg_out_bc (TCGContext *s, int bc, int label_index)
1090 {
1091 TCGLabel *l = &s->labels[label_index];
1092
1093 if (l->has_value)
1094 tcg_out32 (s, bc | reloc_pc14_val (s->code_ptr, l->u.value));
1095 else {
1096 uint16_t val = *(uint16_t *) &s->code_ptr[2];
1097
1098 /* Thanks to Andrzej Zaborowski */
1099 tcg_out32 (s, bc | (val & 0xfffc));
1100 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL14, label_index, 0);
1101 }
1102 }
1103
1104 static void tcg_out_cr7eq_from_cond (TCGContext *s, const TCGArg *args,
1105 const int *const_args)
1106 {
1107 TCGCond cond = args[4];
1108 int op;
1109 struct { int bit1; int bit2; int cond2; } bits[] = {
1110 [TCG_COND_LT ] = { CR_LT, CR_LT, TCG_COND_LT },
1111 [TCG_COND_LE ] = { CR_LT, CR_GT, TCG_COND_LT },
1112 [TCG_COND_GT ] = { CR_GT, CR_GT, TCG_COND_GT },
1113 [TCG_COND_GE ] = { CR_GT, CR_LT, TCG_COND_GT },
1114 [TCG_COND_LTU] = { CR_LT, CR_LT, TCG_COND_LTU },
1115 [TCG_COND_LEU] = { CR_LT, CR_GT, TCG_COND_LTU },
1116 [TCG_COND_GTU] = { CR_GT, CR_GT, TCG_COND_GTU },
1117 [TCG_COND_GEU] = { CR_GT, CR_LT, TCG_COND_GTU },
1118 }, *b = &bits[cond];
1119
1120 switch (cond) {
1121 case TCG_COND_EQ:
1122 case TCG_COND_NE:
1123 op = (cond == TCG_COND_EQ) ? CRAND : CRNAND;
1124 tcg_out_cmp (s, cond, args[0], args[2], const_args[2], 6);
1125 tcg_out_cmp (s, cond, args[1], args[3], const_args[3], 7);
1126 tcg_out32 (s, op | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
1127 break;
1128 case TCG_COND_LT:
1129 case TCG_COND_LE:
1130 case TCG_COND_GT:
1131 case TCG_COND_GE:
1132 case TCG_COND_LTU:
1133 case TCG_COND_LEU:
1134 case TCG_COND_GTU:
1135 case TCG_COND_GEU:
1136 op = (b->bit1 != b->bit2) ? CRANDC : CRAND;
1137 tcg_out_cmp (s, b->cond2, args[1], args[3], const_args[3], 5);
1138 tcg_out_cmp (s, tcg_unsigned_cond (cond), args[0], args[2],
1139 const_args[2], 7);
1140 tcg_out32 (s, op | BT (7, CR_EQ) | BA (5, CR_EQ) | BB (7, b->bit2));
1141 tcg_out32 (s, CROR | BT (7, CR_EQ) | BA (5, b->bit1) | BB (7, CR_EQ));
1142 break;
1143 default:
1144 tcg_abort();
1145 }
1146 }
1147
1148 static void tcg_out_setcond (TCGContext *s, TCGCond cond, TCGArg arg0,
1149 TCGArg arg1, TCGArg arg2, int const_arg2)
1150 {
1151 int crop, sh, arg;
1152
1153 switch (cond) {
1154 case TCG_COND_EQ:
1155 if (const_arg2) {
1156 if (!arg2) {
1157 arg = arg1;
1158 }
1159 else {
1160 arg = 0;
1161 if ((uint16_t) arg2 == arg2) {
1162 tcg_out32 (s, XORI | RS (arg1) | RA (0) | arg2);
1163 }
1164 else {
1165 tcg_out_movi (s, TCG_TYPE_I32, 0, arg2);
1166 tcg_out32 (s, XOR | SAB (arg1, 0, 0));
1167 }
1168 }
1169 }
1170 else {
1171 arg = 0;
1172 tcg_out32 (s, XOR | SAB (arg1, 0, arg2));
1173 }
1174 tcg_out32 (s, CNTLZW | RS (arg) | RA (0));
1175 tcg_out32 (s, (RLWINM
1176 | RA (arg0)
1177 | RS (0)
1178 | SH (27)
1179 | MB (5)
1180 | ME (31)
1181 )
1182 );
1183 break;
1184
1185 case TCG_COND_NE:
1186 if (const_arg2) {
1187 if (!arg2) {
1188 arg = arg1;
1189 }
1190 else {
1191 arg = 0;
1192 if ((uint16_t) arg2 == arg2) {
1193 tcg_out32 (s, XORI | RS (arg1) | RA (0) | arg2);
1194 }
1195 else {
1196 tcg_out_movi (s, TCG_TYPE_I32, 0, arg2);
1197 tcg_out32 (s, XOR | SAB (arg1, 0, 0));
1198 }
1199 }
1200 }
1201 else {
1202 arg = 0;
1203 tcg_out32 (s, XOR | SAB (arg1, 0, arg2));
1204 }
1205
1206 if (arg == arg1 && arg1 == arg0) {
1207 tcg_out32 (s, ADDIC | RT (0) | RA (arg) | 0xffff);
1208 tcg_out32 (s, SUBFE | TAB (arg0, 0, arg));
1209 }
1210 else {
1211 tcg_out32 (s, ADDIC | RT (arg0) | RA (arg) | 0xffff);
1212 tcg_out32 (s, SUBFE | TAB (arg0, arg0, arg));
1213 }
1214 break;
1215
1216 case TCG_COND_GT:
1217 case TCG_COND_GTU:
1218 sh = 30;
1219 crop = 0;
1220 goto crtest;
1221
1222 case TCG_COND_LT:
1223 case TCG_COND_LTU:
1224 sh = 29;
1225 crop = 0;
1226 goto crtest;
1227
1228 case TCG_COND_GE:
1229 case TCG_COND_GEU:
1230 sh = 31;
1231 crop = CRNOR | BT (7, CR_EQ) | BA (7, CR_LT) | BB (7, CR_LT);
1232 goto crtest;
1233
1234 case TCG_COND_LE:
1235 case TCG_COND_LEU:
1236 sh = 31;
1237 crop = CRNOR | BT (7, CR_EQ) | BA (7, CR_GT) | BB (7, CR_GT);
1238 crtest:
1239 tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7);
1240 if (crop) tcg_out32 (s, crop);
1241 tcg_out32 (s, MFCR | RT (0));
1242 tcg_out32 (s, (RLWINM
1243 | RA (arg0)
1244 | RS (0)
1245 | SH (sh)
1246 | MB (31)
1247 | ME (31)
1248 )
1249 );
1250 break;
1251
1252 default:
1253 tcg_abort ();
1254 }
1255 }
1256
1257 static void tcg_out_setcond2 (TCGContext *s, const TCGArg *args,
1258 const int *const_args)
1259 {
1260 tcg_out_cr7eq_from_cond (s, args + 1, const_args + 1);
1261 tcg_out32 (s, MFCR | RT (0));
1262 tcg_out32 (s, (RLWINM
1263 | RA (args[0])
1264 | RS (0)
1265 | SH (31)
1266 | MB (31)
1267 | ME (31)
1268 )
1269 );
1270 }
1271
1272 static void tcg_out_brcond (TCGContext *s, TCGCond cond,
1273 TCGArg arg1, TCGArg arg2, int const_arg2,
1274 int label_index)
1275 {
1276 tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7);
1277 tcg_out_bc (s, tcg_to_bc[cond], label_index);
1278 }
1279
1280 /* XXX: we implement it at the target level to avoid having to
1281 handle cross basic blocks temporaries */
1282 static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args,
1283 const int *const_args)
1284 {
1285 tcg_out_cr7eq_from_cond (s, args, const_args);
1286 tcg_out_bc (s, (BC | BI (7, CR_EQ) | BO_COND_TRUE), args[5]);
1287 }
1288
1289 void ppc_tb_set_jmp_target (unsigned long jmp_addr, unsigned long addr)
1290 {
1291 uint32_t *ptr;
1292 long disp = addr - jmp_addr;
1293 unsigned long patch_size;
1294
1295 ptr = (uint32_t *)jmp_addr;
1296
1297 if ((disp << 6) >> 6 != disp) {
1298 ptr[0] = 0x3c000000 | (addr >> 16); /* lis 0,addr@ha */
1299 ptr[1] = 0x60000000 | (addr & 0xffff); /* la 0,addr@l(0) */
1300 ptr[2] = 0x7c0903a6; /* mtctr 0 */
1301 ptr[3] = 0x4e800420; /* brctr */
1302 patch_size = 16;
1303 } else {
1304 /* patch the branch destination */
1305 if (disp != 16) {
1306 *ptr = 0x48000000 | (disp & 0x03fffffc); /* b disp */
1307 patch_size = 4;
1308 } else {
1309 ptr[0] = 0x60000000; /* nop */
1310 ptr[1] = 0x60000000;
1311 ptr[2] = 0x60000000;
1312 ptr[3] = 0x60000000;
1313 patch_size = 16;
1314 }
1315 }
1316 /* flush icache */
1317 flush_icache_range(jmp_addr, jmp_addr + patch_size);
1318 }
1319
1320 static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
1321 const int *const_args)
1322 {
1323 switch (opc) {
1324 case INDEX_op_exit_tb:
1325 tcg_out_movi (s, TCG_TYPE_I32, TCG_REG_R3, args[0]);
1326 tcg_out_b (s, 0, (tcg_target_long) tb_ret_addr);
1327 break;
1328 case INDEX_op_goto_tb:
1329 if (s->tb_jmp_offset) {
1330 /* direct jump method */
1331
1332 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1333 s->code_ptr += 16;
1334 }
1335 else {
1336 tcg_abort ();
1337 }
1338 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1339 break;
1340 case INDEX_op_br:
1341 {
1342 TCGLabel *l = &s->labels[args[0]];
1343
1344 if (l->has_value) {
1345 tcg_out_b (s, 0, l->u.value);
1346 }
1347 else {
1348 uint32_t val = *(uint32_t *) s->code_ptr;
1349
1350 /* Thanks to Andrzej Zaborowski */
1351 tcg_out32 (s, B | (val & 0x3fffffc));
1352 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL24, args[0], 0);
1353 }
1354 }
1355 break;
1356 case INDEX_op_call:
1357 tcg_out_call (s, args[0], const_args[0]);
1358 break;
1359 case INDEX_op_jmp:
1360 if (const_args[0]) {
1361 tcg_out_b (s, 0, args[0]);
1362 }
1363 else {
1364 tcg_out32 (s, MTSPR | RS (args[0]) | CTR);
1365 tcg_out32 (s, BCCTR | BO_ALWAYS);
1366 }
1367 break;
1368 case INDEX_op_movi_i32:
1369 tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
1370 break;
1371 case INDEX_op_ld8u_i32:
1372 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1373 break;
1374 case INDEX_op_ld8s_i32:
1375 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1376 tcg_out32 (s, EXTSB | RS (args[0]) | RA (args[0]));
1377 break;
1378 case INDEX_op_ld16u_i32:
1379 tcg_out_ldst (s, args[0], args[1], args[2], LHZ, LHZX);
1380 break;
1381 case INDEX_op_ld16s_i32:
1382 tcg_out_ldst (s, args[0], args[1], args[2], LHA, LHAX);
1383 break;
1384 case INDEX_op_ld_i32:
1385 tcg_out_ldst (s, args[0], args[1], args[2], LWZ, LWZX);
1386 break;
1387 case INDEX_op_st8_i32:
1388 tcg_out_ldst (s, args[0], args[1], args[2], STB, STBX);
1389 break;
1390 case INDEX_op_st16_i32:
1391 tcg_out_ldst (s, args[0], args[1], args[2], STH, STHX);
1392 break;
1393 case INDEX_op_st_i32:
1394 tcg_out_ldst (s, args[0], args[1], args[2], STW, STWX);
1395 break;
1396
1397 case INDEX_op_add_i32:
1398 if (const_args[2])
1399 ppc_addi (s, args[0], args[1], args[2]);
1400 else
1401 tcg_out32 (s, ADD | TAB (args[0], args[1], args[2]));
1402 break;
1403 case INDEX_op_sub_i32:
1404 if (const_args[2])
1405 ppc_addi (s, args[0], args[1], -args[2]);
1406 else
1407 tcg_out32 (s, SUBF | TAB (args[0], args[2], args[1]));
1408 break;
1409
1410 case INDEX_op_and_i32:
1411 if (const_args[2]) {
1412 uint32_t c;
1413
1414 c = args[2];
1415
1416 if (!c) {
1417 tcg_out_movi (s, TCG_TYPE_I32, args[0], 0);
1418 break;
1419 }
1420 #ifdef __PPU__
1421 uint32_t t, n;
1422 int mb, me;
1423
1424 n = c ^ -(c & 1);
1425 t = n + (n & -n);
1426
1427 if ((t & (t - 1)) == 0) {
1428 int lzc, tzc;
1429
1430 if ((c & 0x80000001) == 0x80000001) {
1431 lzc = clz32 (n);
1432 tzc = ctz32 (n);
1433
1434 mb = 32 - tzc;
1435 me = lzc - 1;
1436 }
1437 else {
1438 lzc = clz32 (c);
1439 tzc = ctz32 (c);
1440
1441 mb = lzc;
1442 me = 31 - tzc;
1443 }
1444
1445 tcg_out32 (s, (RLWINM
1446 | RA (args[0])
1447 | RS (args[1])
1448 | SH (0)
1449 | MB (mb)
1450 | ME (me)
1451 )
1452 );
1453 }
1454 else
1455 #endif /* !__PPU__ */
1456 {
1457 if ((c & 0xffff) == c)
1458 tcg_out32 (s, ANDI | RS (args[1]) | RA (args[0]) | c);
1459 else if ((c & 0xffff0000) == c)
1460 tcg_out32 (s, ANDIS | RS (args[1]) | RA (args[0])
1461 | ((c >> 16) & 0xffff));
1462 else {
1463 tcg_out_movi (s, TCG_TYPE_I32, 0, c);
1464 tcg_out32 (s, AND | SAB (args[1], args[0], 0));
1465 }
1466 }
1467 }
1468 else
1469 tcg_out32 (s, AND | SAB (args[1], args[0], args[2]));
1470 break;
1471 case INDEX_op_or_i32:
1472 if (const_args[2]) {
1473 if (args[2] & 0xffff) {
1474 tcg_out32 (s, ORI | RS (args[1]) | RA (args[0])
1475 | (args[2] & 0xffff));
1476 if (args[2] >> 16)
1477 tcg_out32 (s, ORIS | RS (args[0]) | RA (args[0])
1478 | ((args[2] >> 16) & 0xffff));
1479 }
1480 else {
1481 tcg_out32 (s, ORIS | RS (args[1]) | RA (args[0])
1482 | ((args[2] >> 16) & 0xffff));
1483 }
1484 }
1485 else
1486 tcg_out32 (s, OR | SAB (args[1], args[0], args[2]));
1487 break;
1488 case INDEX_op_xor_i32:
1489 if (const_args[2]) {
1490 if ((args[2] & 0xffff) == args[2])
1491 tcg_out32 (s, XORI | RS (args[1]) | RA (args[0])
1492 | (args[2] & 0xffff));
1493 else if ((args[2] & 0xffff0000) == args[2])
1494 tcg_out32 (s, XORIS | RS (args[1]) | RA (args[0])
1495 | ((args[2] >> 16) & 0xffff));
1496 else {
1497 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1498 tcg_out32 (s, XOR | SAB (args[1], args[0], 0));
1499 }
1500 }
1501 else
1502 tcg_out32 (s, XOR | SAB (args[1], args[0], args[2]));
1503 break;
1504 case INDEX_op_andc_i32:
1505 tcg_out32 (s, ANDC | SAB (args[1], args[0], args[2]));
1506 break;
1507 case INDEX_op_orc_i32:
1508 tcg_out32 (s, ORC | SAB (args[1], args[0], args[2]));
1509 break;
1510 case INDEX_op_eqv_i32:
1511 tcg_out32 (s, EQV | SAB (args[1], args[0], args[2]));
1512 break;
1513 case INDEX_op_nand_i32:
1514 tcg_out32 (s, NAND | SAB (args[1], args[0], args[2]));
1515 break;
1516 case INDEX_op_nor_i32:
1517 tcg_out32 (s, NOR | SAB (args[1], args[0], args[2]));
1518 break;
1519
1520 case INDEX_op_mul_i32:
1521 if (const_args[2]) {
1522 if (args[2] == (int16_t) args[2])
1523 tcg_out32 (s, MULLI | RT (args[0]) | RA (args[1])
1524 | (args[2] & 0xffff));
1525 else {
1526 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1527 tcg_out32 (s, MULLW | TAB (args[0], args[1], 0));
1528 }
1529 }
1530 else
1531 tcg_out32 (s, MULLW | TAB (args[0], args[1], args[2]));
1532 break;
1533
1534 case INDEX_op_div_i32:
1535 tcg_out32 (s, DIVW | TAB (args[0], args[1], args[2]));
1536 break;
1537
1538 case INDEX_op_divu_i32:
1539 tcg_out32 (s, DIVWU | TAB (args[0], args[1], args[2]));
1540 break;
1541
1542 case INDEX_op_rem_i32:
1543 tcg_out32 (s, DIVW | TAB (0, args[1], args[2]));
1544 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1545 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1546 break;
1547
1548 case INDEX_op_remu_i32:
1549 tcg_out32 (s, DIVWU | TAB (0, args[1], args[2]));
1550 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1551 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1552 break;
1553
1554 case INDEX_op_mulu2_i32:
1555 if (args[0] == args[2] || args[0] == args[3]) {
1556 tcg_out32 (s, MULLW | TAB (0, args[2], args[3]));
1557 tcg_out32 (s, MULHWU | TAB (args[1], args[2], args[3]));
1558 tcg_out_mov (s, TCG_TYPE_I32, args[0], 0);
1559 }
1560 else {
1561 tcg_out32 (s, MULLW | TAB (args[0], args[2], args[3]));
1562 tcg_out32 (s, MULHWU | TAB (args[1], args[2], args[3]));
1563 }
1564 break;
1565
1566 case INDEX_op_shl_i32:
1567 if (const_args[2]) {
1568 tcg_out32 (s, (RLWINM
1569 | RA (args[0])
1570 | RS (args[1])
1571 | SH (args[2])
1572 | MB (0)
1573 | ME (31 - args[2])
1574 )
1575 );
1576 }
1577 else
1578 tcg_out32 (s, SLW | SAB (args[1], args[0], args[2]));
1579 break;
1580 case INDEX_op_shr_i32:
1581 if (const_args[2]) {
1582 tcg_out32 (s, (RLWINM
1583 | RA (args[0])
1584 | RS (args[1])
1585 | SH (32 - args[2])
1586 | MB (args[2])
1587 | ME (31)
1588 )
1589 );
1590 }
1591 else
1592 tcg_out32 (s, SRW | SAB (args[1], args[0], args[2]));
1593 break;
1594 case INDEX_op_sar_i32:
1595 if (const_args[2])
1596 tcg_out32 (s, SRAWI | RS (args[1]) | RA (args[0]) | SH (args[2]));
1597 else
1598 tcg_out32 (s, SRAW | SAB (args[1], args[0], args[2]));
1599 break;
1600 case INDEX_op_rotl_i32:
1601 {
1602 int op = 0
1603 | RA (args[0])
1604 | RS (args[1])
1605 | MB (0)
1606 | ME (31)
1607 | (const_args[2] ? RLWINM | SH (args[2])
1608 : RLWNM | RB (args[2]))
1609 ;
1610 tcg_out32 (s, op);
1611 }
1612 break;
1613 case INDEX_op_rotr_i32:
1614 if (const_args[2]) {
1615 if (!args[2]) {
1616 tcg_out_mov (s, TCG_TYPE_I32, args[0], args[1]);
1617 }
1618 else {
1619 tcg_out32 (s, RLWINM
1620 | RA (args[0])
1621 | RS (args[1])
1622 | SH (32 - args[2])
1623 | MB (0)
1624 | ME (31)
1625 );
1626 }
1627 }
1628 else {
1629 tcg_out32 (s, SUBFIC | RT (0) | RA (args[2]) | 32);
1630 tcg_out32 (s, RLWNM
1631 | RA (args[0])
1632 | RS (args[1])
1633 | RB (0)
1634 | MB (0)
1635 | ME (31)
1636 );
1637 }
1638 break;
1639
1640 case INDEX_op_add2_i32:
1641 if (args[0] == args[3] || args[0] == args[5]) {
1642 tcg_out32 (s, ADDC | TAB (0, args[2], args[4]));
1643 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5]));
1644 tcg_out_mov (s, TCG_TYPE_I32, args[0], 0);
1645 }
1646 else {
1647 tcg_out32 (s, ADDC | TAB (args[0], args[2], args[4]));
1648 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5]));
1649 }
1650 break;
1651 case INDEX_op_sub2_i32:
1652 if (args[0] == args[3] || args[0] == args[5]) {
1653 tcg_out32 (s, SUBFC | TAB (0, args[4], args[2]));
1654 tcg_out32 (s, SUBFE | TAB (args[1], args[5], args[3]));
1655 tcg_out_mov (s, TCG_TYPE_I32, args[0], 0);
1656 }
1657 else {
1658 tcg_out32 (s, SUBFC | TAB (args[0], args[4], args[2]));
1659 tcg_out32 (s, SUBFE | TAB (args[1], args[5], args[3]));
1660 }
1661 break;
1662
1663 case INDEX_op_brcond_i32:
1664 /*
1665 args[0] = r0
1666 args[1] = r1
1667 args[2] = cond
1668 args[3] = r1 is const
1669 args[4] = label_index
1670 */
1671 tcg_out_brcond (s, args[2], args[0], args[1], const_args[1], args[3]);
1672 break;
1673 case INDEX_op_brcond2_i32:
1674 tcg_out_brcond2(s, args, const_args);
1675 break;
1676
1677 case INDEX_op_neg_i32:
1678 tcg_out32 (s, NEG | RT (args[0]) | RA (args[1]));
1679 break;
1680
1681 case INDEX_op_not_i32:
1682 tcg_out32 (s, NOR | SAB (args[1], args[0], args[1]));
1683 break;
1684
1685 case INDEX_op_qemu_ld8u:
1686 tcg_out_qemu_ld(s, args, 0);
1687 break;
1688 case INDEX_op_qemu_ld8s:
1689 tcg_out_qemu_ld(s, args, 0 | 4);
1690 break;
1691 case INDEX_op_qemu_ld16u:
1692 tcg_out_qemu_ld(s, args, 1);
1693 break;
1694 case INDEX_op_qemu_ld16s:
1695 tcg_out_qemu_ld(s, args, 1 | 4);
1696 break;
1697 case INDEX_op_qemu_ld32:
1698 tcg_out_qemu_ld(s, args, 2);
1699 break;
1700 case INDEX_op_qemu_ld64:
1701 tcg_out_qemu_ld(s, args, 3);
1702 break;
1703 case INDEX_op_qemu_st8:
1704 tcg_out_qemu_st(s, args, 0);
1705 break;
1706 case INDEX_op_qemu_st16:
1707 tcg_out_qemu_st(s, args, 1);
1708 break;
1709 case INDEX_op_qemu_st32:
1710 tcg_out_qemu_st(s, args, 2);
1711 break;
1712 case INDEX_op_qemu_st64:
1713 tcg_out_qemu_st(s, args, 3);
1714 break;
1715
1716 case INDEX_op_ext8s_i32:
1717 tcg_out32 (s, EXTSB | RS (args[1]) | RA (args[0]));
1718 break;
1719 case INDEX_op_ext8u_i32:
1720 tcg_out32 (s, RLWINM
1721 | RA (args[0])
1722 | RS (args[1])
1723 | SH (0)
1724 | MB (24)
1725 | ME (31)
1726 );
1727 break;
1728 case INDEX_op_ext16s_i32:
1729 tcg_out32 (s, EXTSH | RS (args[1]) | RA (args[0]));
1730 break;
1731 case INDEX_op_ext16u_i32:
1732 tcg_out32 (s, RLWINM
1733 | RA (args[0])
1734 | RS (args[1])
1735 | SH (0)
1736 | MB (16)
1737 | ME (31)
1738 );
1739 break;
1740
1741 case INDEX_op_setcond_i32:
1742 tcg_out_setcond (s, args[3], args[0], args[1], args[2], const_args[2]);
1743 break;
1744 case INDEX_op_setcond2_i32:
1745 tcg_out_setcond2 (s, args, const_args);
1746 break;
1747
1748 case INDEX_op_bswap16_i32:
1749 /* Stolen from gcc's builtin_bswap16 */
1750
1751 /* a1 = abcd */
1752
1753 /* r0 = (a1 << 8) & 0xff00 # 00d0 */
1754 tcg_out32 (s, RLWINM
1755 | RA (0)
1756 | RS (args[1])
1757 | SH (8)
1758 | MB (16)
1759 | ME (23)
1760 );
1761
1762 /* a0 = rotate_left (a1, 24) & 0xff # 000c */
1763 tcg_out32 (s, RLWINM
1764 | RA (args[0])
1765 | RS (args[1])
1766 | SH (24)
1767 | MB (24)
1768 | ME (31)
1769 );
1770
1771 /* a0 = a0 | r0 # 00dc */
1772 tcg_out32 (s, OR | SAB (0, args[0], args[0]));
1773 break;
1774
1775 case INDEX_op_bswap32_i32:
1776 /* Stolen from gcc's builtin_bswap32 */
1777 {
1778 int a0 = args[0];
1779
1780 /* a1 = args[1] # abcd */
1781
1782 if (a0 == args[1]) {
1783 a0 = 0;
1784 }
1785
1786 /* a0 = rotate_left (a1, 8) # bcda */
1787 tcg_out32 (s, RLWINM
1788 | RA (a0)
1789 | RS (args[1])
1790 | SH (8)
1791 | MB (0)
1792 | ME (31)
1793 );
1794
1795 /* a0 = (a0 & ~0xff000000) | ((a1 << 24) & 0xff000000) # dcda */
1796 tcg_out32 (s, RLWIMI
1797 | RA (a0)
1798 | RS (args[1])
1799 | SH (24)
1800 | MB (0)
1801 | ME (7)
1802 );
1803
1804 /* a0 = (a0 & ~0x0000ff00) | ((a1 << 24) & 0x0000ff00) # dcba */
1805 tcg_out32 (s, RLWIMI
1806 | RA (a0)
1807 | RS (args[1])
1808 | SH (24)
1809 | MB (16)
1810 | ME (23)
1811 );
1812
1813 if (!a0) {
1814 tcg_out_mov (s, TCG_TYPE_I32, args[0], a0);
1815 }
1816 }
1817 break;
1818
1819 case INDEX_op_deposit_i32:
1820 tcg_out32 (s, RLWIMI
1821 | RA (args[0])
1822 | RS (args[2])
1823 | SH (args[3])
1824 | MB (32 - args[3] - args[4])
1825 | ME (31 - args[3])
1826 );
1827 break;
1828
1829 default:
1830 tcg_dump_ops (s);
1831 tcg_abort ();
1832 }
1833 }
1834
1835 static const TCGTargetOpDef ppc_op_defs[] = {
1836 { INDEX_op_exit_tb, { } },
1837 { INDEX_op_goto_tb, { } },
1838 { INDEX_op_call, { "ri" } },
1839 { INDEX_op_jmp, { "ri" } },
1840 { INDEX_op_br, { } },
1841
1842 { INDEX_op_mov_i32, { "r", "r" } },
1843 { INDEX_op_movi_i32, { "r" } },
1844 { INDEX_op_ld8u_i32, { "r", "r" } },
1845 { INDEX_op_ld8s_i32, { "r", "r" } },
1846 { INDEX_op_ld16u_i32, { "r", "r" } },
1847 { INDEX_op_ld16s_i32, { "r", "r" } },
1848 { INDEX_op_ld_i32, { "r", "r" } },
1849 { INDEX_op_st8_i32, { "r", "r" } },
1850 { INDEX_op_st16_i32, { "r", "r" } },
1851 { INDEX_op_st_i32, { "r", "r" } },
1852
1853 { INDEX_op_add_i32, { "r", "r", "ri" } },
1854 { INDEX_op_mul_i32, { "r", "r", "ri" } },
1855 { INDEX_op_div_i32, { "r", "r", "r" } },
1856 { INDEX_op_divu_i32, { "r", "r", "r" } },
1857 { INDEX_op_rem_i32, { "r", "r", "r" } },
1858 { INDEX_op_remu_i32, { "r", "r", "r" } },
1859 { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
1860 { INDEX_op_sub_i32, { "r", "r", "ri" } },
1861 { INDEX_op_and_i32, { "r", "r", "ri" } },
1862 { INDEX_op_or_i32, { "r", "r", "ri" } },
1863 { INDEX_op_xor_i32, { "r", "r", "ri" } },
1864
1865 { INDEX_op_shl_i32, { "r", "r", "ri" } },
1866 { INDEX_op_shr_i32, { "r", "r", "ri" } },
1867 { INDEX_op_sar_i32, { "r", "r", "ri" } },
1868
1869 { INDEX_op_rotl_i32, { "r", "r", "ri" } },
1870 { INDEX_op_rotr_i32, { "r", "r", "ri" } },
1871
1872 { INDEX_op_brcond_i32, { "r", "ri" } },
1873
1874 { INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } },
1875 { INDEX_op_sub2_i32, { "r", "r", "r", "r", "r", "r" } },
1876 { INDEX_op_brcond2_i32, { "r", "r", "r", "r" } },
1877
1878 { INDEX_op_neg_i32, { "r", "r" } },
1879 { INDEX_op_not_i32, { "r", "r" } },
1880
1881 { INDEX_op_andc_i32, { "r", "r", "r" } },
1882 { INDEX_op_orc_i32, { "r", "r", "r" } },
1883 { INDEX_op_eqv_i32, { "r", "r", "r" } },
1884 { INDEX_op_nand_i32, { "r", "r", "r" } },
1885 { INDEX_op_nor_i32, { "r", "r", "r" } },
1886
1887 { INDEX_op_setcond_i32, { "r", "r", "ri" } },
1888 { INDEX_op_setcond2_i32, { "r", "r", "r", "ri", "ri" } },
1889
1890 { INDEX_op_bswap16_i32, { "r", "r" } },
1891 { INDEX_op_bswap32_i32, { "r", "r" } },
1892
1893 #if TARGET_LONG_BITS == 32
1894 { INDEX_op_qemu_ld8u, { "r", "L" } },
1895 { INDEX_op_qemu_ld8s, { "r", "L" } },
1896 { INDEX_op_qemu_ld16u, { "r", "L" } },
1897 { INDEX_op_qemu_ld16s, { "r", "L" } },
1898 { INDEX_op_qemu_ld32, { "r", "L" } },
1899 { INDEX_op_qemu_ld64, { "r", "r", "L" } },
1900
1901 { INDEX_op_qemu_st8, { "K", "K" } },
1902 { INDEX_op_qemu_st16, { "K", "K" } },
1903 { INDEX_op_qemu_st32, { "K", "K" } },
1904 { INDEX_op_qemu_st64, { "M", "M", "M" } },
1905 #else
1906 { INDEX_op_qemu_ld8u, { "r", "L", "L" } },
1907 { INDEX_op_qemu_ld8s, { "r", "L", "L" } },
1908 { INDEX_op_qemu_ld16u, { "r", "L", "L" } },
1909 { INDEX_op_qemu_ld16s, { "r", "L", "L" } },
1910 { INDEX_op_qemu_ld32, { "r", "L", "L" } },
1911 { INDEX_op_qemu_ld64, { "r", "L", "L", "L" } },
1912
1913 { INDEX_op_qemu_st8, { "K", "K", "K" } },
1914 { INDEX_op_qemu_st16, { "K", "K", "K" } },
1915 { INDEX_op_qemu_st32, { "K", "K", "K" } },
1916 { INDEX_op_qemu_st64, { "M", "M", "M", "M" } },
1917 #endif
1918
1919 { INDEX_op_ext8s_i32, { "r", "r" } },
1920 { INDEX_op_ext8u_i32, { "r", "r" } },
1921 { INDEX_op_ext16s_i32, { "r", "r" } },
1922 { INDEX_op_ext16u_i32, { "r", "r" } },
1923
1924 { INDEX_op_deposit_i32, { "r", "0", "r" } },
1925
1926 { -1 },
1927 };
1928
1929 static void tcg_target_init(TCGContext *s)
1930 {
1931 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
1932 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1933 (1 << TCG_REG_R0) |
1934 #ifdef TCG_TARGET_CALL_DARWIN
1935 (1 << TCG_REG_R2) |
1936 #endif
1937 (1 << TCG_REG_R3) |
1938 (1 << TCG_REG_R4) |
1939 (1 << TCG_REG_R5) |
1940 (1 << TCG_REG_R6) |
1941 (1 << TCG_REG_R7) |
1942 (1 << TCG_REG_R8) |
1943 (1 << TCG_REG_R9) |
1944 (1 << TCG_REG_R10) |
1945 (1 << TCG_REG_R11) |
1946 (1 << TCG_REG_R12)
1947 );
1948
1949 tcg_regset_clear(s->reserved_regs);
1950 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0);
1951 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1);
1952 #ifndef TCG_TARGET_CALL_DARWIN
1953 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2);
1954 #endif
1955 #ifdef _CALL_SYSV
1956 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13);
1957 #endif
1958
1959 tcg_add_target_add_op_defs(ppc_op_defs);
1960 }
Qemu copy for testing