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Merge remote-tracking branch 'sweil/fixes' into staging
[qemu.git] / tcg / ppc / tcg-target.c
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 static uint8_t *tb_ret_addr;
26
27 #ifdef _CALL_DARWIN
28 #define LINKAGE_AREA_SIZE 24
29 #define LR_OFFSET 8
30 #elif defined _CALL_AIX
31 #define LINKAGE_AREA_SIZE 52
32 #define LR_OFFSET 8
33 #else
34 #define LINKAGE_AREA_SIZE 8
35 #define LR_OFFSET 4
36 #endif
37
38 #define FAST_PATH
39
40 #ifndef GUEST_BASE
41 #define GUEST_BASE 0
42 #endif
43
44 #ifdef CONFIG_USE_GUEST_BASE
45 #define TCG_GUEST_BASE_REG 30
46 #else
47 #define TCG_GUEST_BASE_REG 0
48 #endif
49
50 #ifndef NDEBUG
51 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
52 "r0",
53 "r1",
54 "r2",
55 "r3",
56 "r4",
57 "r5",
58 "r6",
59 "r7",
60 "r8",
61 "r9",
62 "r10",
63 "r11",
64 "r12",
65 "r13",
66 "r14",
67 "r15",
68 "r16",
69 "r17",
70 "r18",
71 "r19",
72 "r20",
73 "r21",
74 "r22",
75 "r23",
76 "r24",
77 "r25",
78 "r26",
79 "r27",
80 "r28",
81 "r29",
82 "r30",
83 "r31"
84 };
85 #endif
86
87 static const int tcg_target_reg_alloc_order[] = {
88 TCG_REG_R14,
89 TCG_REG_R15,
90 TCG_REG_R16,
91 TCG_REG_R17,
92 TCG_REG_R18,
93 TCG_REG_R19,
94 TCG_REG_R20,
95 TCG_REG_R21,
96 TCG_REG_R22,
97 TCG_REG_R23,
98 TCG_REG_R28,
99 TCG_REG_R29,
100 TCG_REG_R30,
101 TCG_REG_R31,
102 #ifdef _CALL_DARWIN
103 TCG_REG_R2,
104 #endif
105 TCG_REG_R3,
106 TCG_REG_R4,
107 TCG_REG_R5,
108 TCG_REG_R6,
109 TCG_REG_R7,
110 TCG_REG_R8,
111 TCG_REG_R9,
112 TCG_REG_R10,
113 #ifndef _CALL_DARWIN
114 TCG_REG_R11,
115 #endif
116 TCG_REG_R12,
117 #ifndef _CALL_SYSV
118 TCG_REG_R13,
119 #endif
120 TCG_REG_R24,
121 TCG_REG_R25,
122 TCG_REG_R26,
123 TCG_REG_R27
124 };
125
126 static const int tcg_target_call_iarg_regs[] = {
127 TCG_REG_R3,
128 TCG_REG_R4,
129 TCG_REG_R5,
130 TCG_REG_R6,
131 TCG_REG_R7,
132 TCG_REG_R8,
133 TCG_REG_R9,
134 TCG_REG_R10
135 };
136
137 static const int tcg_target_call_oarg_regs[2] = {
138 TCG_REG_R3,
139 TCG_REG_R4
140 };
141
142 static const int tcg_target_callee_save_regs[] = {
143 #ifdef _CALL_DARWIN
144 TCG_REG_R11,
145 TCG_REG_R13,
146 #endif
147 #ifdef _CALL_AIX
148 TCG_REG_R13,
149 #endif
150 TCG_REG_R14,
151 TCG_REG_R15,
152 TCG_REG_R16,
153 TCG_REG_R17,
154 TCG_REG_R18,
155 TCG_REG_R19,
156 TCG_REG_R20,
157 TCG_REG_R21,
158 TCG_REG_R22,
159 TCG_REG_R23,
160 TCG_REG_R24,
161 TCG_REG_R25,
162 TCG_REG_R26,
163 TCG_REG_R27, /* currently used for the global env */
164 TCG_REG_R28,
165 TCG_REG_R29,
166 TCG_REG_R30,
167 TCG_REG_R31
168 };
169
170 static uint32_t reloc_pc24_val (void *pc, tcg_target_long target)
171 {
172 tcg_target_long disp;
173
174 disp = target - (tcg_target_long) pc;
175 if ((disp << 6) >> 6 != disp)
176 tcg_abort ();
177
178 return disp & 0x3fffffc;
179 }
180
181 static void reloc_pc24 (void *pc, tcg_target_long target)
182 {
183 *(uint32_t *) pc = (*(uint32_t *) pc & ~0x3fffffc)
184 | reloc_pc24_val (pc, target);
185 }
186
187 static uint16_t reloc_pc14_val (void *pc, tcg_target_long target)
188 {
189 tcg_target_long disp;
190
191 disp = target - (tcg_target_long) pc;
192 if (disp != (int16_t) disp)
193 tcg_abort ();
194
195 return disp & 0xfffc;
196 }
197
198 static void reloc_pc14 (void *pc, tcg_target_long target)
199 {
200 *(uint32_t *) pc = (*(uint32_t *) pc & ~0xfffc)
201 | reloc_pc14_val (pc, target);
202 }
203
204 static void patch_reloc(uint8_t *code_ptr, int type,
205 tcg_target_long value, tcg_target_long addend)
206 {
207 value += addend;
208 switch (type) {
209 case R_PPC_REL14:
210 reloc_pc14 (code_ptr, value);
211 break;
212 case R_PPC_REL24:
213 reloc_pc24 (code_ptr, value);
214 break;
215 default:
216 tcg_abort();
217 }
218 }
219
220 /* maximum number of register used for input function arguments */
221 static int tcg_target_get_call_iarg_regs_count(int flags)
222 {
223 return ARRAY_SIZE (tcg_target_call_iarg_regs);
224 }
225
226 /* parse target specific constraints */
227 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
228 {
229 const char *ct_str;
230
231 ct_str = *pct_str;
232 switch (ct_str[0]) {
233 case 'A': case 'B': case 'C': case 'D':
234 ct->ct |= TCG_CT_REG;
235 tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
236 break;
237 case 'r':
238 ct->ct |= TCG_CT_REG;
239 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
240 break;
241 #ifdef CONFIG_SOFTMMU
242 case 'L': /* qemu_ld constraint */
243 ct->ct |= TCG_CT_REG;
244 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
245 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
246 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
247 break;
248 case 'K': /* qemu_st[8..32] constraint */
249 ct->ct |= TCG_CT_REG;
250 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
251 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
252 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
253 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
254 #if TARGET_LONG_BITS == 64
255 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
256 #endif
257 break;
258 case 'M': /* qemu_st64 constraint */
259 ct->ct |= TCG_CT_REG;
260 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
261 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
262 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
263 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
264 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
265 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);
266 break;
267 #else
268 case 'L':
269 case 'K':
270 ct->ct |= TCG_CT_REG;
271 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
272 break;
273 case 'M':
274 ct->ct |= TCG_CT_REG;
275 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
276 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
277 break;
278 #endif
279 default:
280 return -1;
281 }
282 ct_str++;
283 *pct_str = ct_str;
284 return 0;
285 }
286
287 /* test if a constant matches the constraint */
288 static int tcg_target_const_match(tcg_target_long val,
289 const TCGArgConstraint *arg_ct)
290 {
291 int ct;
292
293 ct = arg_ct->ct;
294 if (ct & TCG_CT_CONST)
295 return 1;
296 return 0;
297 }
298
299 #define OPCD(opc) ((opc)<<26)
300 #define XO31(opc) (OPCD(31)|((opc)<<1))
301 #define XO19(opc) (OPCD(19)|((opc)<<1))
302
303 #define B OPCD(18)
304 #define BC OPCD(16)
305 #define LBZ OPCD(34)
306 #define LHZ OPCD(40)
307 #define LHA OPCD(42)
308 #define LWZ OPCD(32)
309 #define STB OPCD(38)
310 #define STH OPCD(44)
311 #define STW OPCD(36)
312
313 #define ADDIC OPCD(12)
314 #define ADDI OPCD(14)
315 #define ADDIS OPCD(15)
316 #define ORI OPCD(24)
317 #define ORIS OPCD(25)
318 #define XORI OPCD(26)
319 #define XORIS OPCD(27)
320 #define ANDI OPCD(28)
321 #define ANDIS OPCD(29)
322 #define MULLI OPCD( 7)
323 #define CMPLI OPCD(10)
324 #define CMPI OPCD(11)
325 #define SUBFIC OPCD( 8)
326
327 #define LWZU OPCD(33)
328 #define STWU OPCD(37)
329
330 #define RLWIMI OPCD(20)
331 #define RLWINM OPCD(21)
332 #define RLWNM OPCD(23)
333
334 #define BCLR XO19( 16)
335 #define BCCTR XO19(528)
336 #define CRAND XO19(257)
337 #define CRANDC XO19(129)
338 #define CRNAND XO19(225)
339 #define CROR XO19(449)
340 #define CRNOR XO19( 33)
341
342 #define EXTSB XO31(954)
343 #define EXTSH XO31(922)
344 #define ADD XO31(266)
345 #define ADDE XO31(138)
346 #define ADDC XO31( 10)
347 #define AND XO31( 28)
348 #define SUBF XO31( 40)
349 #define SUBFC XO31( 8)
350 #define SUBFE XO31(136)
351 #define OR XO31(444)
352 #define XOR XO31(316)
353 #define MULLW XO31(235)
354 #define MULHWU XO31( 11)
355 #define DIVW XO31(491)
356 #define DIVWU XO31(459)
357 #define CMP XO31( 0)
358 #define CMPL XO31( 32)
359 #define LHBRX XO31(790)
360 #define LWBRX XO31(534)
361 #define STHBRX XO31(918)
362 #define STWBRX XO31(662)
363 #define MFSPR XO31(339)
364 #define MTSPR XO31(467)
365 #define SRAWI XO31(824)
366 #define NEG XO31(104)
367 #define MFCR XO31( 19)
368 #define CNTLZW XO31( 26)
369 #define NOR XO31(124)
370 #define ANDC XO31( 60)
371 #define ORC XO31(412)
372 #define EQV XO31(284)
373 #define NAND XO31(476)
374
375 #define LBZX XO31( 87)
376 #define LHZX XO31(279)
377 #define LHAX XO31(343)
378 #define LWZX XO31( 23)
379 #define STBX XO31(215)
380 #define STHX XO31(407)
381 #define STWX XO31(151)
382
383 #define SPR(a,b) ((((a)<<5)|(b))<<11)
384 #define LR SPR(8, 0)
385 #define CTR SPR(9, 0)
386
387 #define SLW XO31( 24)
388 #define SRW XO31(536)
389 #define SRAW XO31(792)
390
391 #define TW XO31(4)
392 #define TRAP (TW | TO (31))
393
394 #define RT(r) ((r)<<21)
395 #define RS(r) ((r)<<21)
396 #define RA(r) ((r)<<16)
397 #define RB(r) ((r)<<11)
398 #define TO(t) ((t)<<21)
399 #define SH(s) ((s)<<11)
400 #define MB(b) ((b)<<6)
401 #define ME(e) ((e)<<1)
402 #define BO(o) ((o)<<21)
403
404 #define LK 1
405
406 #define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
407 #define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
408
409 #define BF(n) ((n)<<23)
410 #define BI(n, c) (((c)+((n)*4))<<16)
411 #define BT(n, c) (((c)+((n)*4))<<21)
412 #define BA(n, c) (((c)+((n)*4))<<16)
413 #define BB(n, c) (((c)+((n)*4))<<11)
414
415 #define BO_COND_TRUE BO (12)
416 #define BO_COND_FALSE BO (4)
417 #define BO_ALWAYS BO (20)
418
419 enum {
420 CR_LT,
421 CR_GT,
422 CR_EQ,
423 CR_SO
424 };
425
426 static const uint32_t tcg_to_bc[10] = {
427 [TCG_COND_EQ] = BC | BI (7, CR_EQ) | BO_COND_TRUE,
428 [TCG_COND_NE] = BC | BI (7, CR_EQ) | BO_COND_FALSE,
429 [TCG_COND_LT] = BC | BI (7, CR_LT) | BO_COND_TRUE,
430 [TCG_COND_GE] = BC | BI (7, CR_LT) | BO_COND_FALSE,
431 [TCG_COND_LE] = BC | BI (7, CR_GT) | BO_COND_FALSE,
432 [TCG_COND_GT] = BC | BI (7, CR_GT) | BO_COND_TRUE,
433 [TCG_COND_LTU] = BC | BI (7, CR_LT) | BO_COND_TRUE,
434 [TCG_COND_GEU] = BC | BI (7, CR_LT) | BO_COND_FALSE,
435 [TCG_COND_LEU] = BC | BI (7, CR_GT) | BO_COND_FALSE,
436 [TCG_COND_GTU] = BC | BI (7, CR_GT) | BO_COND_TRUE,
437 };
438
439 static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
440 {
441 tcg_out32 (s, OR | SAB (arg, ret, arg));
442 }
443
444 static void tcg_out_movi(TCGContext *s, TCGType type,
445 TCGReg ret, tcg_target_long arg)
446 {
447 if (arg == (int16_t) arg)
448 tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff));
449 else {
450 tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff));
451 if (arg & 0xffff)
452 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
453 }
454 }
455
456 static void tcg_out_ldst (TCGContext *s, int ret, int addr,
457 int offset, int op1, int op2)
458 {
459 if (offset == (int16_t) offset)
460 tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff));
461 else {
462 tcg_out_movi (s, TCG_TYPE_I32, 0, offset);
463 tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
464 }
465 }
466
467 static void tcg_out_b (TCGContext *s, int mask, tcg_target_long target)
468 {
469 tcg_target_long disp;
470
471 disp = target - (tcg_target_long) s->code_ptr;
472 if ((disp << 6) >> 6 == disp)
473 tcg_out32 (s, B | (disp & 0x3fffffc) | mask);
474 else {
475 tcg_out_movi (s, TCG_TYPE_I32, 0, (tcg_target_long) target);
476 tcg_out32 (s, MTSPR | RS (0) | CTR);
477 tcg_out32 (s, BCCTR | BO_ALWAYS | mask);
478 }
479 }
480
481 static void tcg_out_call (TCGContext *s, tcg_target_long arg, int const_arg)
482 {
483 #ifdef _CALL_AIX
484 int reg;
485
486 if (const_arg) {
487 reg = 2;
488 tcg_out_movi (s, TCG_TYPE_I32, reg, arg);
489 }
490 else reg = arg;
491
492 tcg_out32 (s, LWZ | RT (0) | RA (reg));
493 tcg_out32 (s, MTSPR | RA (0) | CTR);
494 tcg_out32 (s, LWZ | RT (2) | RA (reg) | 4);
495 tcg_out32 (s, BCCTR | BO_ALWAYS | LK);
496 #else
497 if (const_arg) {
498 tcg_out_b (s, LK, arg);
499 }
500 else {
501 tcg_out32 (s, MTSPR | RS (arg) | LR);
502 tcg_out32 (s, BCLR | BO_ALWAYS | LK);
503 }
504 #endif
505 }
506
507 #if defined(CONFIG_SOFTMMU)
508
509 #include "../../softmmu_defs.h"
510
511 #ifdef CONFIG_TCG_PASS_AREG0
512 #error CONFIG_TCG_PASS_AREG0 is not supported
513 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
514 int mmu_idx) */
515 static const void * const qemu_ld_helpers[4] = {
516 helper_ldb_mmu,
517 helper_ldw_mmu,
518 helper_ldl_mmu,
519 helper_ldq_mmu,
520 };
521
522 /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
523 uintxx_t val, int mmu_idx) */
524 static const void * const qemu_st_helpers[4] = {
525 helper_stb_mmu,
526 helper_stw_mmu,
527 helper_stl_mmu,
528 helper_stq_mmu,
529 };
530 #else
531 /* legacy helper signature: __ld_mmu(target_ulong addr, int
532 mmu_idx) */
533 static void *qemu_ld_helpers[4] = {
534 __ldb_mmu,
535 __ldw_mmu,
536 __ldl_mmu,
537 __ldq_mmu,
538 };
539
540 /* legacy helper signature: __ld_mmu(target_ulong addr, int
541 mmu_idx) */
542 static void *qemu_st_helpers[4] = {
543 __stb_mmu,
544 __stw_mmu,
545 __stl_mmu,
546 __stq_mmu,
547 };
548 #endif
549 #endif
550
551 static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
552 {
553 int addr_reg, data_reg, data_reg2, r0, r1, rbase, bswap;
554 #ifdef CONFIG_SOFTMMU
555 int mem_index, s_bits, r2;
556 void *label1_ptr, *label2_ptr;
557 #if TARGET_LONG_BITS == 64
558 int addr_reg2;
559 #endif
560 #endif
561
562 data_reg = *args++;
563 if (opc == 3)
564 data_reg2 = *args++;
565 else
566 data_reg2 = 0;
567 addr_reg = *args++;
568
569 #ifdef CONFIG_SOFTMMU
570 #if TARGET_LONG_BITS == 64
571 addr_reg2 = *args++;
572 #endif
573 mem_index = *args;
574 s_bits = opc & 3;
575 r0 = 3;
576 r1 = 4;
577 r2 = 0;
578 rbase = 0;
579
580 tcg_out32 (s, (RLWINM
581 | RA (r0)
582 | RS (addr_reg)
583 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
584 | MB (32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS))
585 | ME (31 - CPU_TLB_ENTRY_BITS)
586 )
587 );
588 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
589 tcg_out32 (s, (LWZU
590 | RT (r1)
591 | RA (r0)
592 | offsetof (CPUArchState, tlb_table[mem_index][0].addr_read)
593 )
594 );
595 tcg_out32 (s, (RLWINM
596 | RA (r2)
597 | RS (addr_reg)
598 | SH (0)
599 | MB ((32 - s_bits) & 31)
600 | ME (31 - TARGET_PAGE_BITS)
601 )
602 );
603
604 tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1));
605 #if TARGET_LONG_BITS == 64
606 tcg_out32 (s, LWZ | RT (r1) | RA (r0) | 4);
607 tcg_out32 (s, CMP | BF (6) | RA (addr_reg2) | RB (r1));
608 tcg_out32 (s, CRAND | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
609 #endif
610
611 label1_ptr = s->code_ptr;
612 #ifdef FAST_PATH
613 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
614 #endif
615
616 /* slow path */
617 #if TARGET_LONG_BITS == 32
618 tcg_out_mov (s, TCG_TYPE_I32, 3, addr_reg);
619 tcg_out_movi (s, TCG_TYPE_I32, 4, mem_index);
620 #else
621 tcg_out_mov (s, TCG_TYPE_I32, 3, addr_reg2);
622 tcg_out_mov (s, TCG_TYPE_I32, 4, addr_reg);
623 tcg_out_movi (s, TCG_TYPE_I32, 5, mem_index);
624 #endif
625
626 tcg_out_call (s, (tcg_target_long) qemu_ld_helpers[s_bits], 1);
627 switch (opc) {
628 case 0|4:
629 tcg_out32 (s, EXTSB | RA (data_reg) | RS (3));
630 break;
631 case 1|4:
632 tcg_out32 (s, EXTSH | RA (data_reg) | RS (3));
633 break;
634 case 0:
635 case 1:
636 case 2:
637 if (data_reg != 3)
638 tcg_out_mov (s, TCG_TYPE_I32, data_reg, 3);
639 break;
640 case 3:
641 if (data_reg == 3) {
642 if (data_reg2 == 4) {
643 tcg_out_mov (s, TCG_TYPE_I32, 0, 4);
644 tcg_out_mov (s, TCG_TYPE_I32, 4, 3);
645 tcg_out_mov (s, TCG_TYPE_I32, 3, 0);
646 }
647 else {
648 tcg_out_mov (s, TCG_TYPE_I32, data_reg2, 3);
649 tcg_out_mov (s, TCG_TYPE_I32, 3, 4);
650 }
651 }
652 else {
653 if (data_reg != 4) tcg_out_mov (s, TCG_TYPE_I32, data_reg, 4);
654 if (data_reg2 != 3) tcg_out_mov (s, TCG_TYPE_I32, data_reg2, 3);
655 }
656 break;
657 }
658 label2_ptr = s->code_ptr;
659 tcg_out32 (s, B);
660
661 /* label1: fast path */
662 #ifdef FAST_PATH
663 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
664 #endif
665
666 /* r0 now contains &env->tlb_table[mem_index][index].addr_read */
667 tcg_out32 (s, (LWZ
668 | RT (r0)
669 | RA (r0)
670 | (offsetof (CPUTLBEntry, addend)
671 - offsetof (CPUTLBEntry, addr_read))
672 ));
673 /* r0 = env->tlb_table[mem_index][index].addend */
674 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
675 /* r0 = env->tlb_table[mem_index][index].addend + addr */
676
677 #else /* !CONFIG_SOFTMMU */
678 r0 = addr_reg;
679 r1 = 3;
680 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
681 #endif
682
683 #ifdef TARGET_WORDS_BIGENDIAN
684 bswap = 0;
685 #else
686 bswap = 1;
687 #endif
688
689 switch (opc) {
690 default:
691 case 0:
692 tcg_out32 (s, LBZX | TAB (data_reg, rbase, r0));
693 break;
694 case 0|4:
695 tcg_out32 (s, LBZX | TAB (data_reg, rbase, r0));
696 tcg_out32 (s, EXTSB | RA (data_reg) | RS (data_reg));
697 break;
698 case 1:
699 if (bswap)
700 tcg_out32 (s, LHBRX | TAB (data_reg, rbase, r0));
701 else
702 tcg_out32 (s, LHZX | TAB (data_reg, rbase, r0));
703 break;
704 case 1|4:
705 if (bswap) {
706 tcg_out32 (s, LHBRX | TAB (data_reg, rbase, r0));
707 tcg_out32 (s, EXTSH | RA (data_reg) | RS (data_reg));
708 }
709 else tcg_out32 (s, LHAX | TAB (data_reg, rbase, r0));
710 break;
711 case 2:
712 if (bswap)
713 tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
714 else
715 tcg_out32 (s, LWZX | TAB (data_reg, rbase, r0));
716 break;
717 case 3:
718 if (bswap) {
719 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
720 tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
721 tcg_out32 (s, LWBRX | TAB (data_reg2, rbase, r1));
722 }
723 else {
724 #ifdef CONFIG_USE_GUEST_BASE
725 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
726 tcg_out32 (s, LWZX | TAB (data_reg2, rbase, r0));
727 tcg_out32 (s, LWZX | TAB (data_reg, rbase, r1));
728 #else
729 if (r0 == data_reg2) {
730 tcg_out32 (s, LWZ | RT (0) | RA (r0));
731 tcg_out32 (s, LWZ | RT (data_reg) | RA (r0) | 4);
732 tcg_out_mov (s, TCG_TYPE_I32, data_reg2, 0);
733 }
734 else {
735 tcg_out32 (s, LWZ | RT (data_reg2) | RA (r0));
736 tcg_out32 (s, LWZ | RT (data_reg) | RA (r0) | 4);
737 }
738 #endif
739 }
740 break;
741 }
742
743 #ifdef CONFIG_SOFTMMU
744 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
745 #endif
746 }
747
748 static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
749 {
750 int addr_reg, r0, r1, data_reg, data_reg2, bswap, rbase;
751 #ifdef CONFIG_SOFTMMU
752 int mem_index, r2, ir;
753 void *label1_ptr, *label2_ptr;
754 #if TARGET_LONG_BITS == 64
755 int addr_reg2;
756 #endif
757 #endif
758
759 data_reg = *args++;
760 if (opc == 3)
761 data_reg2 = *args++;
762 else
763 data_reg2 = 0;
764 addr_reg = *args++;
765
766 #ifdef CONFIG_SOFTMMU
767 #if TARGET_LONG_BITS == 64
768 addr_reg2 = *args++;
769 #endif
770 mem_index = *args;
771 r0 = 3;
772 r1 = 4;
773 r2 = 0;
774 rbase = 0;
775
776 tcg_out32 (s, (RLWINM
777 | RA (r0)
778 | RS (addr_reg)
779 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
780 | MB (32 - (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS))
781 | ME (31 - CPU_TLB_ENTRY_BITS)
782 )
783 );
784 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
785 tcg_out32 (s, (LWZU
786 | RT (r1)
787 | RA (r0)
788 | offsetof (CPUArchState, tlb_table[mem_index][0].addr_write)
789 )
790 );
791 tcg_out32 (s, (RLWINM
792 | RA (r2)
793 | RS (addr_reg)
794 | SH (0)
795 | MB ((32 - opc) & 31)
796 | ME (31 - TARGET_PAGE_BITS)
797 )
798 );
799
800 tcg_out32 (s, CMP | (7 << 23) | RA (r2) | RB (r1));
801 #if TARGET_LONG_BITS == 64
802 tcg_out32 (s, LWZ | RT (r1) | RA (r0) | 4);
803 tcg_out32 (s, CMP | BF (6) | RA (addr_reg2) | RB (r1));
804 tcg_out32 (s, CRAND | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
805 #endif
806
807 label1_ptr = s->code_ptr;
808 #ifdef FAST_PATH
809 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
810 #endif
811
812 /* slow path */
813 #if TARGET_LONG_BITS == 32
814 tcg_out_mov (s, TCG_TYPE_I32, 3, addr_reg);
815 ir = 4;
816 #else
817 tcg_out_mov (s, TCG_TYPE_I32, 3, addr_reg2);
818 tcg_out_mov (s, TCG_TYPE_I32, 4, addr_reg);
819 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
820 ir = 5;
821 #else
822 ir = 4;
823 #endif
824 #endif
825
826 switch (opc) {
827 case 0:
828 tcg_out32 (s, (RLWINM
829 | RA (ir)
830 | RS (data_reg)
831 | SH (0)
832 | MB (24)
833 | ME (31)));
834 break;
835 case 1:
836 tcg_out32 (s, (RLWINM
837 | RA (ir)
838 | RS (data_reg)
839 | SH (0)
840 | MB (16)
841 | ME (31)));
842 break;
843 case 2:
844 tcg_out_mov (s, TCG_TYPE_I32, ir, data_reg);
845 break;
846 case 3:
847 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
848 ir = 5;
849 #endif
850 tcg_out_mov (s, TCG_TYPE_I32, ir++, data_reg2);
851 tcg_out_mov (s, TCG_TYPE_I32, ir, data_reg);
852 break;
853 }
854 ir++;
855
856 tcg_out_movi (s, TCG_TYPE_I32, ir, mem_index);
857 tcg_out_call (s, (tcg_target_long) qemu_st_helpers[opc], 1);
858 label2_ptr = s->code_ptr;
859 tcg_out32 (s, B);
860
861 /* label1: fast path */
862 #ifdef FAST_PATH
863 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
864 #endif
865
866 tcg_out32 (s, (LWZ
867 | RT (r0)
868 | RA (r0)
869 | (offsetof (CPUTLBEntry, addend)
870 - offsetof (CPUTLBEntry, addr_write))
871 ));
872 /* r0 = env->tlb_table[mem_index][index].addend */
873 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
874 /* r0 = env->tlb_table[mem_index][index].addend + addr */
875
876 #else /* !CONFIG_SOFTMMU */
877 r0 = addr_reg;
878 r1 = 3;
879 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
880 #endif
881
882 #ifdef TARGET_WORDS_BIGENDIAN
883 bswap = 0;
884 #else
885 bswap = 1;
886 #endif
887 switch (opc) {
888 case 0:
889 tcg_out32 (s, STBX | SAB (data_reg, rbase, r0));
890 break;
891 case 1:
892 if (bswap)
893 tcg_out32 (s, STHBRX | SAB (data_reg, rbase, r0));
894 else
895 tcg_out32 (s, STHX | SAB (data_reg, rbase, r0));
896 break;
897 case 2:
898 if (bswap)
899 tcg_out32 (s, STWBRX | SAB (data_reg, rbase, r0));
900 else
901 tcg_out32 (s, STWX | SAB (data_reg, rbase, r0));
902 break;
903 case 3:
904 if (bswap) {
905 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
906 tcg_out32 (s, STWBRX | SAB (data_reg, rbase, r0));
907 tcg_out32 (s, STWBRX | SAB (data_reg2, rbase, r1));
908 }
909 else {
910 #ifdef CONFIG_USE_GUEST_BASE
911 tcg_out32 (s, STWX | SAB (data_reg2, rbase, r0));
912 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
913 tcg_out32 (s, STWX | SAB (data_reg, rbase, r1));
914 #else
915 tcg_out32 (s, STW | RS (data_reg2) | RA (r0));
916 tcg_out32 (s, STW | RS (data_reg) | RA (r0) | 4);
917 #endif
918 }
919 break;
920 }
921
922 #ifdef CONFIG_SOFTMMU
923 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
924 #endif
925 }
926
927 static void tcg_target_qemu_prologue (TCGContext *s)
928 {
929 int i, frame_size;
930
931 frame_size = 0
932 + LINKAGE_AREA_SIZE
933 + TCG_STATIC_CALL_ARGS_SIZE
934 + ARRAY_SIZE (tcg_target_callee_save_regs) * 4
935 + CPU_TEMP_BUF_NLONGS * sizeof(long)
936 ;
937 frame_size = (frame_size + 15) & ~15;
938
939 tcg_set_frame(s, TCG_REG_CALL_STACK, frame_size
940 - CPU_TEMP_BUF_NLONGS * sizeof(long),
941 CPU_TEMP_BUF_NLONGS * sizeof(long));
942
943 #ifdef _CALL_AIX
944 {
945 uint32_t addr;
946
947 /* First emit adhoc function descriptor */
948 addr = (uint32_t) s->code_ptr + 12;
949 tcg_out32 (s, addr); /* entry point */
950 s->code_ptr += 8; /* skip TOC and environment pointer */
951 }
952 #endif
953 tcg_out32 (s, MFSPR | RT (0) | LR);
954 tcg_out32 (s, STWU | RS (1) | RA (1) | (-frame_size & 0xffff));
955 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
956 tcg_out32 (s, (STW
957 | RS (tcg_target_callee_save_regs[i])
958 | RA (1)
959 | (i * 4 + LINKAGE_AREA_SIZE + TCG_STATIC_CALL_ARGS_SIZE)
960 )
961 );
962 tcg_out32 (s, STW | RS (0) | RA (1) | (frame_size + LR_OFFSET));
963
964 #ifdef CONFIG_USE_GUEST_BASE
965 if (GUEST_BASE) {
966 tcg_out_movi (s, TCG_TYPE_I32, TCG_GUEST_BASE_REG, GUEST_BASE);
967 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
968 }
969 #endif
970
971 tcg_out_mov (s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
972 tcg_out32 (s, MTSPR | RS (tcg_target_call_iarg_regs[1]) | CTR);
973 tcg_out32 (s, BCCTR | BO_ALWAYS);
974 tb_ret_addr = s->code_ptr;
975
976 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
977 tcg_out32 (s, (LWZ
978 | RT (tcg_target_callee_save_regs[i])
979 | RA (1)
980 | (i * 4 + LINKAGE_AREA_SIZE + TCG_STATIC_CALL_ARGS_SIZE)
981 )
982 );
983 tcg_out32 (s, LWZ | RT (0) | RA (1) | (frame_size + LR_OFFSET));
984 tcg_out32 (s, MTSPR | RS (0) | LR);
985 tcg_out32 (s, ADDI | RT (1) | RA (1) | frame_size);
986 tcg_out32 (s, BCLR | BO_ALWAYS);
987 }
988
989 static void tcg_out_ld (TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
990 tcg_target_long arg2)
991 {
992 tcg_out_ldst (s, ret, arg1, arg2, LWZ, LWZX);
993 }
994
995 static void tcg_out_st (TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1,
996 tcg_target_long arg2)
997 {
998 tcg_out_ldst (s, arg, arg1, arg2, STW, STWX);
999 }
1000
1001 static void ppc_addi (TCGContext *s, int rt, int ra, tcg_target_long si)
1002 {
1003 if (!si && rt == ra)
1004 return;
1005
1006 if (si == (int16_t) si)
1007 tcg_out32 (s, ADDI | RT (rt) | RA (ra) | (si & 0xffff));
1008 else {
1009 uint16_t h = ((si >> 16) & 0xffff) + ((uint16_t) si >> 15);
1010 tcg_out32 (s, ADDIS | RT (rt) | RA (ra) | h);
1011 tcg_out32 (s, ADDI | RT (rt) | RA (rt) | (si & 0xffff));
1012 }
1013 }
1014
1015 static void tcg_out_cmp (TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
1016 int const_arg2, int cr)
1017 {
1018 int imm;
1019 uint32_t op;
1020
1021 switch (cond) {
1022 case TCG_COND_EQ:
1023 case TCG_COND_NE:
1024 if (const_arg2) {
1025 if ((int16_t) arg2 == arg2) {
1026 op = CMPI;
1027 imm = 1;
1028 break;
1029 }
1030 else if ((uint16_t) arg2 == arg2) {
1031 op = CMPLI;
1032 imm = 1;
1033 break;
1034 }
1035 }
1036 op = CMPL;
1037 imm = 0;
1038 break;
1039
1040 case TCG_COND_LT:
1041 case TCG_COND_GE:
1042 case TCG_COND_LE:
1043 case TCG_COND_GT:
1044 if (const_arg2) {
1045 if ((int16_t) arg2 == arg2) {
1046 op = CMPI;
1047 imm = 1;
1048 break;
1049 }
1050 }
1051 op = CMP;
1052 imm = 0;
1053 break;
1054
1055 case TCG_COND_LTU:
1056 case TCG_COND_GEU:
1057 case TCG_COND_LEU:
1058 case TCG_COND_GTU:
1059 if (const_arg2) {
1060 if ((uint16_t) arg2 == arg2) {
1061 op = CMPLI;
1062 imm = 1;
1063 break;
1064 }
1065 }
1066 op = CMPL;
1067 imm = 0;
1068 break;
1069
1070 default:
1071 tcg_abort ();
1072 }
1073 op |= BF (cr);
1074
1075 if (imm)
1076 tcg_out32 (s, op | RA (arg1) | (arg2 & 0xffff));
1077 else {
1078 if (const_arg2) {
1079 tcg_out_movi (s, TCG_TYPE_I32, 0, arg2);
1080 tcg_out32 (s, op | RA (arg1) | RB (0));
1081 }
1082 else
1083 tcg_out32 (s, op | RA (arg1) | RB (arg2));
1084 }
1085
1086 }
1087
1088 static void tcg_out_bc (TCGContext *s, int bc, int label_index)
1089 {
1090 TCGLabel *l = &s->labels[label_index];
1091
1092 if (l->has_value)
1093 tcg_out32 (s, bc | reloc_pc14_val (s->code_ptr, l->u.value));
1094 else {
1095 uint16_t val = *(uint16_t *) &s->code_ptr[2];
1096
1097 /* Thanks to Andrzej Zaborowski */
1098 tcg_out32 (s, bc | (val & 0xfffc));
1099 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL14, label_index, 0);
1100 }
1101 }
1102
1103 static void tcg_out_cr7eq_from_cond (TCGContext *s, const TCGArg *args,
1104 const int *const_args)
1105 {
1106 TCGCond cond = args[4];
1107 int op;
1108 struct { int bit1; int bit2; int cond2; } bits[] = {
1109 [TCG_COND_LT ] = { CR_LT, CR_LT, TCG_COND_LT },
1110 [TCG_COND_LE ] = { CR_LT, CR_GT, TCG_COND_LT },
1111 [TCG_COND_GT ] = { CR_GT, CR_GT, TCG_COND_GT },
1112 [TCG_COND_GE ] = { CR_GT, CR_LT, TCG_COND_GT },
1113 [TCG_COND_LTU] = { CR_LT, CR_LT, TCG_COND_LTU },
1114 [TCG_COND_LEU] = { CR_LT, CR_GT, TCG_COND_LTU },
1115 [TCG_COND_GTU] = { CR_GT, CR_GT, TCG_COND_GTU },
1116 [TCG_COND_GEU] = { CR_GT, CR_LT, TCG_COND_GTU },
1117 }, *b = &bits[cond];
1118
1119 switch (cond) {
1120 case TCG_COND_EQ:
1121 case TCG_COND_NE:
1122 op = (cond == TCG_COND_EQ) ? CRAND : CRNAND;
1123 tcg_out_cmp (s, cond, args[0], args[2], const_args[2], 6);
1124 tcg_out_cmp (s, cond, args[1], args[3], const_args[3], 7);
1125 tcg_out32 (s, op | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
1126 break;
1127 case TCG_COND_LT:
1128 case TCG_COND_LE:
1129 case TCG_COND_GT:
1130 case TCG_COND_GE:
1131 case TCG_COND_LTU:
1132 case TCG_COND_LEU:
1133 case TCG_COND_GTU:
1134 case TCG_COND_GEU:
1135 op = (b->bit1 != b->bit2) ? CRANDC : CRAND;
1136 tcg_out_cmp (s, b->cond2, args[1], args[3], const_args[3], 5);
1137 tcg_out_cmp (s, tcg_unsigned_cond (cond), args[0], args[2],
1138 const_args[2], 7);
1139 tcg_out32 (s, op | BT (7, CR_EQ) | BA (5, CR_EQ) | BB (7, b->bit2));
1140 tcg_out32 (s, CROR | BT (7, CR_EQ) | BA (5, b->bit1) | BB (7, CR_EQ));
1141 break;
1142 default:
1143 tcg_abort();
1144 }
1145 }
1146
1147 static void tcg_out_setcond (TCGContext *s, TCGCond cond, TCGArg arg0,
1148 TCGArg arg1, TCGArg arg2, int const_arg2)
1149 {
1150 int crop, sh, arg;
1151
1152 switch (cond) {
1153 case TCG_COND_EQ:
1154 if (const_arg2) {
1155 if (!arg2) {
1156 arg = arg1;
1157 }
1158 else {
1159 arg = 0;
1160 if ((uint16_t) arg2 == arg2) {
1161 tcg_out32 (s, XORI | RS (arg1) | RA (0) | arg2);
1162 }
1163 else {
1164 tcg_out_movi (s, TCG_TYPE_I32, 0, arg2);
1165 tcg_out32 (s, XOR | SAB (arg1, 0, 0));
1166 }
1167 }
1168 }
1169 else {
1170 arg = 0;
1171 tcg_out32 (s, XOR | SAB (arg1, 0, arg2));
1172 }
1173 tcg_out32 (s, CNTLZW | RS (arg) | RA (0));
1174 tcg_out32 (s, (RLWINM
1175 | RA (arg0)
1176 | RS (0)
1177 | SH (27)
1178 | MB (5)
1179 | ME (31)
1180 )
1181 );
1182 break;
1183
1184 case TCG_COND_NE:
1185 if (const_arg2) {
1186 if (!arg2) {
1187 arg = arg1;
1188 }
1189 else {
1190 arg = 0;
1191 if ((uint16_t) arg2 == arg2) {
1192 tcg_out32 (s, XORI | RS (arg1) | RA (0) | arg2);
1193 }
1194 else {
1195 tcg_out_movi (s, TCG_TYPE_I32, 0, arg2);
1196 tcg_out32 (s, XOR | SAB (arg1, 0, 0));
1197 }
1198 }
1199 }
1200 else {
1201 arg = 0;
1202 tcg_out32 (s, XOR | SAB (arg1, 0, arg2));
1203 }
1204
1205 if (arg == arg1 && arg1 == arg0) {
1206 tcg_out32 (s, ADDIC | RT (0) | RA (arg) | 0xffff);
1207 tcg_out32 (s, SUBFE | TAB (arg0, 0, arg));
1208 }
1209 else {
1210 tcg_out32 (s, ADDIC | RT (arg0) | RA (arg) | 0xffff);
1211 tcg_out32 (s, SUBFE | TAB (arg0, arg0, arg));
1212 }
1213 break;
1214
1215 case TCG_COND_GT:
1216 case TCG_COND_GTU:
1217 sh = 30;
1218 crop = 0;
1219 goto crtest;
1220
1221 case TCG_COND_LT:
1222 case TCG_COND_LTU:
1223 sh = 29;
1224 crop = 0;
1225 goto crtest;
1226
1227 case TCG_COND_GE:
1228 case TCG_COND_GEU:
1229 sh = 31;
1230 crop = CRNOR | BT (7, CR_EQ) | BA (7, CR_LT) | BB (7, CR_LT);
1231 goto crtest;
1232
1233 case TCG_COND_LE:
1234 case TCG_COND_LEU:
1235 sh = 31;
1236 crop = CRNOR | BT (7, CR_EQ) | BA (7, CR_GT) | BB (7, CR_GT);
1237 crtest:
1238 tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7);
1239 if (crop) tcg_out32 (s, crop);
1240 tcg_out32 (s, MFCR | RT (0));
1241 tcg_out32 (s, (RLWINM
1242 | RA (arg0)
1243 | RS (0)
1244 | SH (sh)
1245 | MB (31)
1246 | ME (31)
1247 )
1248 );
1249 break;
1250
1251 default:
1252 tcg_abort ();
1253 }
1254 }
1255
1256 static void tcg_out_setcond2 (TCGContext *s, const TCGArg *args,
1257 const int *const_args)
1258 {
1259 tcg_out_cr7eq_from_cond (s, args + 1, const_args + 1);
1260 tcg_out32 (s, MFCR | RT (0));
1261 tcg_out32 (s, (RLWINM
1262 | RA (args[0])
1263 | RS (0)
1264 | SH (31)
1265 | MB (31)
1266 | ME (31)
1267 )
1268 );
1269 }
1270
1271 static void tcg_out_brcond (TCGContext *s, TCGCond cond,
1272 TCGArg arg1, TCGArg arg2, int const_arg2,
1273 int label_index)
1274 {
1275 tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7);
1276 tcg_out_bc (s, tcg_to_bc[cond], label_index);
1277 }
1278
1279 /* XXX: we implement it at the target level to avoid having to
1280 handle cross basic blocks temporaries */
1281 static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args,
1282 const int *const_args)
1283 {
1284 tcg_out_cr7eq_from_cond (s, args, const_args);
1285 tcg_out_bc (s, (BC | BI (7, CR_EQ) | BO_COND_TRUE), args[5]);
1286 }
1287
1288 void ppc_tb_set_jmp_target (unsigned long jmp_addr, unsigned long addr)
1289 {
1290 uint32_t *ptr;
1291 long disp = addr - jmp_addr;
1292 unsigned long patch_size;
1293
1294 ptr = (uint32_t *)jmp_addr;
1295
1296 if ((disp << 6) >> 6 != disp) {
1297 ptr[0] = 0x3c000000 | (addr >> 16); /* lis 0,addr@ha */
1298 ptr[1] = 0x60000000 | (addr & 0xffff); /* la 0,addr@l(0) */
1299 ptr[2] = 0x7c0903a6; /* mtctr 0 */
1300 ptr[3] = 0x4e800420; /* brctr */
1301 patch_size = 16;
1302 } else {
1303 /* patch the branch destination */
1304 if (disp != 16) {
1305 *ptr = 0x48000000 | (disp & 0x03fffffc); /* b disp */
1306 patch_size = 4;
1307 } else {
1308 ptr[0] = 0x60000000; /* nop */
1309 ptr[1] = 0x60000000;
1310 ptr[2] = 0x60000000;
1311 ptr[3] = 0x60000000;
1312 patch_size = 16;
1313 }
1314 }
1315 /* flush icache */
1316 flush_icache_range(jmp_addr, jmp_addr + patch_size);
1317 }
1318
1319 static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
1320 const int *const_args)
1321 {
1322 switch (opc) {
1323 case INDEX_op_exit_tb:
1324 tcg_out_movi (s, TCG_TYPE_I32, TCG_REG_R3, args[0]);
1325 tcg_out_b (s, 0, (tcg_target_long) tb_ret_addr);
1326 break;
1327 case INDEX_op_goto_tb:
1328 if (s->tb_jmp_offset) {
1329 /* direct jump method */
1330
1331 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1332 s->code_ptr += 16;
1333 }
1334 else {
1335 tcg_abort ();
1336 }
1337 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1338 break;
1339 case INDEX_op_br:
1340 {
1341 TCGLabel *l = &s->labels[args[0]];
1342
1343 if (l->has_value) {
1344 tcg_out_b (s, 0, l->u.value);
1345 }
1346 else {
1347 uint32_t val = *(uint32_t *) s->code_ptr;
1348
1349 /* Thanks to Andrzej Zaborowski */
1350 tcg_out32 (s, B | (val & 0x3fffffc));
1351 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL24, args[0], 0);
1352 }
1353 }
1354 break;
1355 case INDEX_op_call:
1356 tcg_out_call (s, args[0], const_args[0]);
1357 break;
1358 case INDEX_op_jmp:
1359 if (const_args[0]) {
1360 tcg_out_b (s, 0, args[0]);
1361 }
1362 else {
1363 tcg_out32 (s, MTSPR | RS (args[0]) | CTR);
1364 tcg_out32 (s, BCCTR | BO_ALWAYS);
1365 }
1366 break;
1367 case INDEX_op_movi_i32:
1368 tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
1369 break;
1370 case INDEX_op_ld8u_i32:
1371 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1372 break;
1373 case INDEX_op_ld8s_i32:
1374 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1375 tcg_out32 (s, EXTSB | RS (args[0]) | RA (args[0]));
1376 break;
1377 case INDEX_op_ld16u_i32:
1378 tcg_out_ldst (s, args[0], args[1], args[2], LHZ, LHZX);
1379 break;
1380 case INDEX_op_ld16s_i32:
1381 tcg_out_ldst (s, args[0], args[1], args[2], LHA, LHAX);
1382 break;
1383 case INDEX_op_ld_i32:
1384 tcg_out_ldst (s, args[0], args[1], args[2], LWZ, LWZX);
1385 break;
1386 case INDEX_op_st8_i32:
1387 tcg_out_ldst (s, args[0], args[1], args[2], STB, STBX);
1388 break;
1389 case INDEX_op_st16_i32:
1390 tcg_out_ldst (s, args[0], args[1], args[2], STH, STHX);
1391 break;
1392 case INDEX_op_st_i32:
1393 tcg_out_ldst (s, args[0], args[1], args[2], STW, STWX);
1394 break;
1395
1396 case INDEX_op_add_i32:
1397 if (const_args[2])
1398 ppc_addi (s, args[0], args[1], args[2]);
1399 else
1400 tcg_out32 (s, ADD | TAB (args[0], args[1], args[2]));
1401 break;
1402 case INDEX_op_sub_i32:
1403 if (const_args[2])
1404 ppc_addi (s, args[0], args[1], -args[2]);
1405 else
1406 tcg_out32 (s, SUBF | TAB (args[0], args[2], args[1]));
1407 break;
1408
1409 case INDEX_op_and_i32:
1410 if (const_args[2]) {
1411 uint32_t c;
1412
1413 c = args[2];
1414
1415 if (!c) {
1416 tcg_out_movi (s, TCG_TYPE_I32, args[0], 0);
1417 break;
1418 }
1419 #ifdef __PPU__
1420 uint32_t t, n;
1421 int mb, me;
1422
1423 n = c ^ -(c & 1);
1424 t = n + (n & -n);
1425
1426 if ((t & (t - 1)) == 0) {
1427 int lzc, tzc;
1428
1429 if ((c & 0x80000001) == 0x80000001) {
1430 lzc = clz32 (n);
1431 tzc = ctz32 (n);
1432
1433 mb = 32 - tzc;
1434 me = lzc - 1;
1435 }
1436 else {
1437 lzc = clz32 (c);
1438 tzc = ctz32 (c);
1439
1440 mb = lzc;
1441 me = 31 - tzc;
1442 }
1443
1444 tcg_out32 (s, (RLWINM
1445 | RA (args[0])
1446 | RS (args[1])
1447 | SH (0)
1448 | MB (mb)
1449 | ME (me)
1450 )
1451 );
1452 }
1453 else
1454 #endif /* !__PPU__ */
1455 {
1456 if ((c & 0xffff) == c)
1457 tcg_out32 (s, ANDI | RS (args[1]) | RA (args[0]) | c);
1458 else if ((c & 0xffff0000) == c)
1459 tcg_out32 (s, ANDIS | RS (args[1]) | RA (args[0])
1460 | ((c >> 16) & 0xffff));
1461 else {
1462 tcg_out_movi (s, TCG_TYPE_I32, 0, c);
1463 tcg_out32 (s, AND | SAB (args[1], args[0], 0));
1464 }
1465 }
1466 }
1467 else
1468 tcg_out32 (s, AND | SAB (args[1], args[0], args[2]));
1469 break;
1470 case INDEX_op_or_i32:
1471 if (const_args[2]) {
1472 if (args[2] & 0xffff) {
1473 tcg_out32 (s, ORI | RS (args[1]) | RA (args[0])
1474 | (args[2] & 0xffff));
1475 if (args[2] >> 16)
1476 tcg_out32 (s, ORIS | RS (args[0]) | RA (args[0])
1477 | ((args[2] >> 16) & 0xffff));
1478 }
1479 else {
1480 tcg_out32 (s, ORIS | RS (args[1]) | RA (args[0])
1481 | ((args[2] >> 16) & 0xffff));
1482 }
1483 }
1484 else
1485 tcg_out32 (s, OR | SAB (args[1], args[0], args[2]));
1486 break;
1487 case INDEX_op_xor_i32:
1488 if (const_args[2]) {
1489 if ((args[2] & 0xffff) == args[2])
1490 tcg_out32 (s, XORI | RS (args[1]) | RA (args[0])
1491 | (args[2] & 0xffff));
1492 else if ((args[2] & 0xffff0000) == args[2])
1493 tcg_out32 (s, XORIS | RS (args[1]) | RA (args[0])
1494 | ((args[2] >> 16) & 0xffff));
1495 else {
1496 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1497 tcg_out32 (s, XOR | SAB (args[1], args[0], 0));
1498 }
1499 }
1500 else
1501 tcg_out32 (s, XOR | SAB (args[1], args[0], args[2]));
1502 break;
1503 case INDEX_op_andc_i32:
1504 tcg_out32 (s, ANDC | SAB (args[1], args[0], args[2]));
1505 break;
1506 case INDEX_op_orc_i32:
1507 tcg_out32 (s, ORC | SAB (args[1], args[0], args[2]));
1508 break;
1509 case INDEX_op_eqv_i32:
1510 tcg_out32 (s, EQV | SAB (args[1], args[0], args[2]));
1511 break;
1512 case INDEX_op_nand_i32:
1513 tcg_out32 (s, NAND | SAB (args[1], args[0], args[2]));
1514 break;
1515 case INDEX_op_nor_i32:
1516 tcg_out32 (s, NOR | SAB (args[1], args[0], args[2]));
1517 break;
1518
1519 case INDEX_op_mul_i32:
1520 if (const_args[2]) {
1521 if (args[2] == (int16_t) args[2])
1522 tcg_out32 (s, MULLI | RT (args[0]) | RA (args[1])
1523 | (args[2] & 0xffff));
1524 else {
1525 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1526 tcg_out32 (s, MULLW | TAB (args[0], args[1], 0));
1527 }
1528 }
1529 else
1530 tcg_out32 (s, MULLW | TAB (args[0], args[1], args[2]));
1531 break;
1532
1533 case INDEX_op_div_i32:
1534 tcg_out32 (s, DIVW | TAB (args[0], args[1], args[2]));
1535 break;
1536
1537 case INDEX_op_divu_i32:
1538 tcg_out32 (s, DIVWU | TAB (args[0], args[1], args[2]));
1539 break;
1540
1541 case INDEX_op_rem_i32:
1542 tcg_out32 (s, DIVW | TAB (0, args[1], args[2]));
1543 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1544 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1545 break;
1546
1547 case INDEX_op_remu_i32:
1548 tcg_out32 (s, DIVWU | TAB (0, args[1], args[2]));
1549 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1550 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1551 break;
1552
1553 case INDEX_op_mulu2_i32:
1554 if (args[0] == args[2] || args[0] == args[3]) {
1555 tcg_out32 (s, MULLW | TAB (0, args[2], args[3]));
1556 tcg_out32 (s, MULHWU | TAB (args[1], args[2], args[3]));
1557 tcg_out_mov (s, TCG_TYPE_I32, args[0], 0);
1558 }
1559 else {
1560 tcg_out32 (s, MULLW | TAB (args[0], args[2], args[3]));
1561 tcg_out32 (s, MULHWU | TAB (args[1], args[2], args[3]));
1562 }
1563 break;
1564
1565 case INDEX_op_shl_i32:
1566 if (const_args[2]) {
1567 tcg_out32 (s, (RLWINM
1568 | RA (args[0])
1569 | RS (args[1])
1570 | SH (args[2])
1571 | MB (0)
1572 | ME (31 - args[2])
1573 )
1574 );
1575 }
1576 else
1577 tcg_out32 (s, SLW | SAB (args[1], args[0], args[2]));
1578 break;
1579 case INDEX_op_shr_i32:
1580 if (const_args[2]) {
1581 tcg_out32 (s, (RLWINM
1582 | RA (args[0])
1583 | RS (args[1])
1584 | SH (32 - args[2])
1585 | MB (args[2])
1586 | ME (31)
1587 )
1588 );
1589 }
1590 else
1591 tcg_out32 (s, SRW | SAB (args[1], args[0], args[2]));
1592 break;
1593 case INDEX_op_sar_i32:
1594 if (const_args[2])
1595 tcg_out32 (s, SRAWI | RS (args[1]) | RA (args[0]) | SH (args[2]));
1596 else
1597 tcg_out32 (s, SRAW | SAB (args[1], args[0], args[2]));
1598 break;
1599 case INDEX_op_rotl_i32:
1600 {
1601 int op = 0
1602 | RA (args[0])
1603 | RS (args[1])
1604 | MB (0)
1605 | ME (31)
1606 | (const_args[2] ? RLWINM | SH (args[2])
1607 : RLWNM | RB (args[2]))
1608 ;
1609 tcg_out32 (s, op);
1610 }
1611 break;
1612 case INDEX_op_rotr_i32:
1613 if (const_args[2]) {
1614 if (!args[2]) {
1615 tcg_out_mov (s, TCG_TYPE_I32, args[0], args[1]);
1616 }
1617 else {
1618 tcg_out32 (s, RLWINM
1619 | RA (args[0])
1620 | RS (args[1])
1621 | SH (32 - args[2])
1622 | MB (0)
1623 | ME (31)
1624 );
1625 }
1626 }
1627 else {
1628 tcg_out32 (s, SUBFIC | RT (0) | RA (args[2]) | 32);
1629 tcg_out32 (s, RLWNM
1630 | RA (args[0])
1631 | RS (args[1])
1632 | RB (0)
1633 | MB (0)
1634 | ME (31)
1635 );
1636 }
1637 break;
1638
1639 case INDEX_op_add2_i32:
1640 if (args[0] == args[3] || args[0] == args[5]) {
1641 tcg_out32 (s, ADDC | TAB (0, args[2], args[4]));
1642 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5]));
1643 tcg_out_mov (s, TCG_TYPE_I32, args[0], 0);
1644 }
1645 else {
1646 tcg_out32 (s, ADDC | TAB (args[0], args[2], args[4]));
1647 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5]));
1648 }
1649 break;
1650 case INDEX_op_sub2_i32:
1651 if (args[0] == args[3] || args[0] == args[5]) {
1652 tcg_out32 (s, SUBFC | TAB (0, args[4], args[2]));
1653 tcg_out32 (s, SUBFE | TAB (args[1], args[5], args[3]));
1654 tcg_out_mov (s, TCG_TYPE_I32, args[0], 0);
1655 }
1656 else {
1657 tcg_out32 (s, SUBFC | TAB (args[0], args[4], args[2]));
1658 tcg_out32 (s, SUBFE | TAB (args[1], args[5], args[3]));
1659 }
1660 break;
1661
1662 case INDEX_op_brcond_i32:
1663 /*
1664 args[0] = r0
1665 args[1] = r1
1666 args[2] = cond
1667 args[3] = r1 is const
1668 args[4] = label_index
1669 */
1670 tcg_out_brcond (s, args[2], args[0], args[1], const_args[1], args[3]);
1671 break;
1672 case INDEX_op_brcond2_i32:
1673 tcg_out_brcond2(s, args, const_args);
1674 break;
1675
1676 case INDEX_op_neg_i32:
1677 tcg_out32 (s, NEG | RT (args[0]) | RA (args[1]));
1678 break;
1679
1680 case INDEX_op_not_i32:
1681 tcg_out32 (s, NOR | SAB (args[1], args[0], args[1]));
1682 break;
1683
1684 case INDEX_op_qemu_ld8u:
1685 tcg_out_qemu_ld(s, args, 0);
1686 break;
1687 case INDEX_op_qemu_ld8s:
1688 tcg_out_qemu_ld(s, args, 0 | 4);
1689 break;
1690 case INDEX_op_qemu_ld16u:
1691 tcg_out_qemu_ld(s, args, 1);
1692 break;
1693 case INDEX_op_qemu_ld16s:
1694 tcg_out_qemu_ld(s, args, 1 | 4);
1695 break;
1696 case INDEX_op_qemu_ld32:
1697 tcg_out_qemu_ld(s, args, 2);
1698 break;
1699 case INDEX_op_qemu_ld64:
1700 tcg_out_qemu_ld(s, args, 3);
1701 break;
1702 case INDEX_op_qemu_st8:
1703 tcg_out_qemu_st(s, args, 0);
1704 break;
1705 case INDEX_op_qemu_st16:
1706 tcg_out_qemu_st(s, args, 1);
1707 break;
1708 case INDEX_op_qemu_st32:
1709 tcg_out_qemu_st(s, args, 2);
1710 break;
1711 case INDEX_op_qemu_st64:
1712 tcg_out_qemu_st(s, args, 3);
1713 break;
1714
1715 case INDEX_op_ext8s_i32:
1716 tcg_out32 (s, EXTSB | RS (args[1]) | RA (args[0]));
1717 break;
1718 case INDEX_op_ext8u_i32:
1719 tcg_out32 (s, RLWINM
1720 | RA (args[0])
1721 | RS (args[1])
1722 | SH (0)
1723 | MB (24)
1724 | ME (31)
1725 );
1726 break;
1727 case INDEX_op_ext16s_i32:
1728 tcg_out32 (s, EXTSH | RS (args[1]) | RA (args[0]));
1729 break;
1730 case INDEX_op_ext16u_i32:
1731 tcg_out32 (s, RLWINM
1732 | RA (args[0])
1733 | RS (args[1])
1734 | SH (0)
1735 | MB (16)
1736 | ME (31)
1737 );
1738 break;
1739
1740 case INDEX_op_setcond_i32:
1741 tcg_out_setcond (s, args[3], args[0], args[1], args[2], const_args[2]);
1742 break;
1743 case INDEX_op_setcond2_i32:
1744 tcg_out_setcond2 (s, args, const_args);
1745 break;
1746
1747 case INDEX_op_bswap16_i32:
1748 /* Stolen from gcc's builtin_bswap16 */
1749
1750 /* a1 = abcd */
1751
1752 /* r0 = (a1 << 8) & 0xff00 # 00d0 */
1753 tcg_out32 (s, RLWINM
1754 | RA (0)
1755 | RS (args[1])
1756 | SH (8)
1757 | MB (16)
1758 | ME (23)
1759 );
1760
1761 /* a0 = rotate_left (a1, 24) & 0xff # 000c */
1762 tcg_out32 (s, RLWINM
1763 | RA (args[0])
1764 | RS (args[1])
1765 | SH (24)
1766 | MB (24)
1767 | ME (31)
1768 );
1769
1770 /* a0 = a0 | r0 # 00dc */
1771 tcg_out32 (s, OR | SAB (0, args[0], args[0]));
1772 break;
1773
1774 case INDEX_op_bswap32_i32:
1775 /* Stolen from gcc's builtin_bswap32 */
1776 {
1777 int a0 = args[0];
1778
1779 /* a1 = args[1] # abcd */
1780
1781 if (a0 == args[1]) {
1782 a0 = 0;
1783 }
1784
1785 /* a0 = rotate_left (a1, 8) # bcda */
1786 tcg_out32 (s, RLWINM
1787 | RA (a0)
1788 | RS (args[1])
1789 | SH (8)
1790 | MB (0)
1791 | ME (31)
1792 );
1793
1794 /* a0 = (a0 & ~0xff000000) | ((a1 << 24) & 0xff000000) # dcda */
1795 tcg_out32 (s, RLWIMI
1796 | RA (a0)
1797 | RS (args[1])
1798 | SH (24)
1799 | MB (0)
1800 | ME (7)
1801 );
1802
1803 /* a0 = (a0 & ~0x0000ff00) | ((a1 << 24) & 0x0000ff00) # dcba */
1804 tcg_out32 (s, RLWIMI
1805 | RA (a0)
1806 | RS (args[1])
1807 | SH (24)
1808 | MB (16)
1809 | ME (23)
1810 );
1811
1812 if (!a0) {
1813 tcg_out_mov (s, TCG_TYPE_I32, args[0], a0);
1814 }
1815 }
1816 break;
1817
1818 case INDEX_op_deposit_i32:
1819 tcg_out32 (s, RLWIMI
1820 | RA (args[0])
1821 | RS (args[2])
1822 | SH (args[3])
1823 | MB (32 - args[3] - args[4])
1824 | ME (31 - args[3])
1825 );
1826 break;
1827
1828 default:
1829 tcg_dump_ops (s, stderr);
1830 tcg_abort ();
1831 }
1832 }
1833
1834 static const TCGTargetOpDef ppc_op_defs[] = {
1835 { INDEX_op_exit_tb, { } },
1836 { INDEX_op_goto_tb, { } },
1837 { INDEX_op_call, { "ri" } },
1838 { INDEX_op_jmp, { "ri" } },
1839 { INDEX_op_br, { } },
1840
1841 { INDEX_op_mov_i32, { "r", "r" } },
1842 { INDEX_op_movi_i32, { "r" } },
1843 { INDEX_op_ld8u_i32, { "r", "r" } },
1844 { INDEX_op_ld8s_i32, { "r", "r" } },
1845 { INDEX_op_ld16u_i32, { "r", "r" } },
1846 { INDEX_op_ld16s_i32, { "r", "r" } },
1847 { INDEX_op_ld_i32, { "r", "r" } },
1848 { INDEX_op_st8_i32, { "r", "r" } },
1849 { INDEX_op_st16_i32, { "r", "r" } },
1850 { INDEX_op_st_i32, { "r", "r" } },
1851
1852 { INDEX_op_add_i32, { "r", "r", "ri" } },
1853 { INDEX_op_mul_i32, { "r", "r", "ri" } },
1854 { INDEX_op_div_i32, { "r", "r", "r" } },
1855 { INDEX_op_divu_i32, { "r", "r", "r" } },
1856 { INDEX_op_rem_i32, { "r", "r", "r" } },
1857 { INDEX_op_remu_i32, { "r", "r", "r" } },
1858 { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
1859 { INDEX_op_sub_i32, { "r", "r", "ri" } },
1860 { INDEX_op_and_i32, { "r", "r", "ri" } },
1861 { INDEX_op_or_i32, { "r", "r", "ri" } },
1862 { INDEX_op_xor_i32, { "r", "r", "ri" } },
1863
1864 { INDEX_op_shl_i32, { "r", "r", "ri" } },
1865 { INDEX_op_shr_i32, { "r", "r", "ri" } },
1866 { INDEX_op_sar_i32, { "r", "r", "ri" } },
1867
1868 { INDEX_op_rotl_i32, { "r", "r", "ri" } },
1869 { INDEX_op_rotr_i32, { "r", "r", "ri" } },
1870
1871 { INDEX_op_brcond_i32, { "r", "ri" } },
1872
1873 { INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } },
1874 { INDEX_op_sub2_i32, { "r", "r", "r", "r", "r", "r" } },
1875 { INDEX_op_brcond2_i32, { "r", "r", "r", "r" } },
1876
1877 { INDEX_op_neg_i32, { "r", "r" } },
1878 { INDEX_op_not_i32, { "r", "r" } },
1879
1880 { INDEX_op_andc_i32, { "r", "r", "r" } },
1881 { INDEX_op_orc_i32, { "r", "r", "r" } },
1882 { INDEX_op_eqv_i32, { "r", "r", "r" } },
1883 { INDEX_op_nand_i32, { "r", "r", "r" } },
1884 { INDEX_op_nor_i32, { "r", "r", "r" } },
1885
1886 { INDEX_op_setcond_i32, { "r", "r", "ri" } },
1887 { INDEX_op_setcond2_i32, { "r", "r", "r", "ri", "ri" } },
1888
1889 { INDEX_op_bswap16_i32, { "r", "r" } },
1890 { INDEX_op_bswap32_i32, { "r", "r" } },
1891
1892 #if TARGET_LONG_BITS == 32
1893 { INDEX_op_qemu_ld8u, { "r", "L" } },
1894 { INDEX_op_qemu_ld8s, { "r", "L" } },
1895 { INDEX_op_qemu_ld16u, { "r", "L" } },
1896 { INDEX_op_qemu_ld16s, { "r", "L" } },
1897 { INDEX_op_qemu_ld32, { "r", "L" } },
1898 { INDEX_op_qemu_ld64, { "r", "r", "L" } },
1899
1900 { INDEX_op_qemu_st8, { "K", "K" } },
1901 { INDEX_op_qemu_st16, { "K", "K" } },
1902 { INDEX_op_qemu_st32, { "K", "K" } },
1903 { INDEX_op_qemu_st64, { "M", "M", "M" } },
1904 #else
1905 { INDEX_op_qemu_ld8u, { "r", "L", "L" } },
1906 { INDEX_op_qemu_ld8s, { "r", "L", "L" } },
1907 { INDEX_op_qemu_ld16u, { "r", "L", "L" } },
1908 { INDEX_op_qemu_ld16s, { "r", "L", "L" } },
1909 { INDEX_op_qemu_ld32, { "r", "L", "L" } },
1910 { INDEX_op_qemu_ld64, { "r", "L", "L", "L" } },
1911
1912 { INDEX_op_qemu_st8, { "K", "K", "K" } },
1913 { INDEX_op_qemu_st16, { "K", "K", "K" } },
1914 { INDEX_op_qemu_st32, { "K", "K", "K" } },
1915 { INDEX_op_qemu_st64, { "M", "M", "M", "M" } },
1916 #endif
1917
1918 { INDEX_op_ext8s_i32, { "r", "r" } },
1919 { INDEX_op_ext8u_i32, { "r", "r" } },
1920 { INDEX_op_ext16s_i32, { "r", "r" } },
1921 { INDEX_op_ext16u_i32, { "r", "r" } },
1922
1923 { INDEX_op_deposit_i32, { "r", "0", "r" } },
1924
1925 { -1 },
1926 };
1927
1928 static void tcg_target_init(TCGContext *s)
1929 {
1930 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
1931 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1932 (1 << TCG_REG_R0) |
1933 #ifdef _CALL_DARWIN
1934 (1 << TCG_REG_R2) |
1935 #endif
1936 (1 << TCG_REG_R3) |
1937 (1 << TCG_REG_R4) |
1938 (1 << TCG_REG_R5) |
1939 (1 << TCG_REG_R6) |
1940 (1 << TCG_REG_R7) |
1941 (1 << TCG_REG_R8) |
1942 (1 << TCG_REG_R9) |
1943 (1 << TCG_REG_R10) |
1944 (1 << TCG_REG_R11) |
1945 (1 << TCG_REG_R12)
1946 );
1947
1948 tcg_regset_clear(s->reserved_regs);
1949 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0);
1950 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1);
1951 #ifndef _CALL_DARWIN
1952 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2);
1953 #endif
1954 #ifdef _CALL_SYSV
1955 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13);
1956 #endif
1957
1958 tcg_add_target_add_op_defs(ppc_op_defs);
1959 }
Qemu copy for testing