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softmmu templates: optionally pass CPUState to memory access functions
[qemu.git] / tcg / ppc / tcg-target.c
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 static uint8_t *tb_ret_addr;
26
27 #ifdef _CALL_DARWIN
28 #define LINKAGE_AREA_SIZE 24
29 #define LR_OFFSET 8
30 #elif defined _CALL_AIX
31 #define LINKAGE_AREA_SIZE 52
32 #define LR_OFFSET 8
33 #else
34 #define LINKAGE_AREA_SIZE 8
35 #define LR_OFFSET 4
36 #endif
37
38 #define FAST_PATH
39
40 #ifndef GUEST_BASE
41 #define GUEST_BASE 0
42 #endif
43
44 #ifdef CONFIG_USE_GUEST_BASE
45 #define TCG_GUEST_BASE_REG 30
46 #else
47 #define TCG_GUEST_BASE_REG 0
48 #endif
49
50 #ifndef NDEBUG
51 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
52 "r0",
53 "r1",
54 "r2",
55 "r3",
56 "r4",
57 "r5",
58 "r6",
59 "r7",
60 "r8",
61 "r9",
62 "r10",
63 "r11",
64 "r12",
65 "r13",
66 "r14",
67 "r15",
68 "r16",
69 "r17",
70 "r18",
71 "r19",
72 "r20",
73 "r21",
74 "r22",
75 "r23",
76 "r24",
77 "r25",
78 "r26",
79 "r27",
80 "r28",
81 "r29",
82 "r30",
83 "r31"
84 };
85 #endif
86
87 static const int tcg_target_reg_alloc_order[] = {
88 TCG_REG_R14,
89 TCG_REG_R15,
90 TCG_REG_R16,
91 TCG_REG_R17,
92 TCG_REG_R18,
93 TCG_REG_R19,
94 TCG_REG_R20,
95 TCG_REG_R21,
96 TCG_REG_R22,
97 TCG_REG_R23,
98 TCG_REG_R28,
99 TCG_REG_R29,
100 TCG_REG_R30,
101 TCG_REG_R31,
102 #ifdef _CALL_DARWIN
103 TCG_REG_R2,
104 #endif
105 TCG_REG_R3,
106 TCG_REG_R4,
107 TCG_REG_R5,
108 TCG_REG_R6,
109 TCG_REG_R7,
110 TCG_REG_R8,
111 TCG_REG_R9,
112 TCG_REG_R10,
113 #ifndef _CALL_DARWIN
114 TCG_REG_R11,
115 #endif
116 TCG_REG_R12,
117 #ifndef _CALL_SYSV
118 TCG_REG_R13,
119 #endif
120 TCG_REG_R24,
121 TCG_REG_R25,
122 TCG_REG_R26,
123 TCG_REG_R27
124 };
125
126 static const int tcg_target_call_iarg_regs[] = {
127 TCG_REG_R3,
128 TCG_REG_R4,
129 TCG_REG_R5,
130 TCG_REG_R6,
131 TCG_REG_R7,
132 TCG_REG_R8,
133 TCG_REG_R9,
134 TCG_REG_R10
135 };
136
137 static const int tcg_target_call_oarg_regs[2] = {
138 TCG_REG_R3,
139 TCG_REG_R4
140 };
141
142 static const int tcg_target_callee_save_regs[] = {
143 #ifdef _CALL_DARWIN
144 TCG_REG_R11,
145 TCG_REG_R13,
146 #endif
147 #ifdef _CALL_AIX
148 TCG_REG_R13,
149 #endif
150 TCG_REG_R14,
151 TCG_REG_R15,
152 TCG_REG_R16,
153 TCG_REG_R17,
154 TCG_REG_R18,
155 TCG_REG_R19,
156 TCG_REG_R20,
157 TCG_REG_R21,
158 TCG_REG_R22,
159 TCG_REG_R23,
160 TCG_REG_R24,
161 TCG_REG_R25,
162 TCG_REG_R26,
163 TCG_REG_R27, /* currently used for the global env */
164 TCG_REG_R28,
165 TCG_REG_R29,
166 TCG_REG_R30,
167 TCG_REG_R31
168 };
169
170 static uint32_t reloc_pc24_val (void *pc, tcg_target_long target)
171 {
172 tcg_target_long disp;
173
174 disp = target - (tcg_target_long) pc;
175 if ((disp << 6) >> 6 != disp)
176 tcg_abort ();
177
178 return disp & 0x3fffffc;
179 }
180
181 static void reloc_pc24 (void *pc, tcg_target_long target)
182 {
183 *(uint32_t *) pc = (*(uint32_t *) pc & ~0x3fffffc)
184 | reloc_pc24_val (pc, target);
185 }
186
187 static uint16_t reloc_pc14_val (void *pc, tcg_target_long target)
188 {
189 tcg_target_long disp;
190
191 disp = target - (tcg_target_long) pc;
192 if (disp != (int16_t) disp)
193 tcg_abort ();
194
195 return disp & 0xfffc;
196 }
197
198 static void reloc_pc14 (void *pc, tcg_target_long target)
199 {
200 *(uint32_t *) pc = (*(uint32_t *) pc & ~0xfffc)
201 | reloc_pc14_val (pc, target);
202 }
203
204 static void patch_reloc(uint8_t *code_ptr, int type,
205 tcg_target_long value, tcg_target_long addend)
206 {
207 value += addend;
208 switch (type) {
209 case R_PPC_REL14:
210 reloc_pc14 (code_ptr, value);
211 break;
212 case R_PPC_REL24:
213 reloc_pc24 (code_ptr, value);
214 break;
215 default:
216 tcg_abort();
217 }
218 }
219
220 /* maximum number of register used for input function arguments */
221 static int tcg_target_get_call_iarg_regs_count(int flags)
222 {
223 return ARRAY_SIZE (tcg_target_call_iarg_regs);
224 }
225
226 /* parse target specific constraints */
227 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
228 {
229 const char *ct_str;
230
231 ct_str = *pct_str;
232 switch (ct_str[0]) {
233 case 'A': case 'B': case 'C': case 'D':
234 ct->ct |= TCG_CT_REG;
235 tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
236 break;
237 case 'r':
238 ct->ct |= TCG_CT_REG;
239 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
240 break;
241 #ifdef CONFIG_SOFTMMU
242 case 'L': /* qemu_ld constraint */
243 ct->ct |= TCG_CT_REG;
244 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
245 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
246 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
247 break;
248 case 'K': /* qemu_st[8..32] constraint */
249 ct->ct |= TCG_CT_REG;
250 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
251 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
252 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
253 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
254 #if TARGET_LONG_BITS == 64
255 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
256 #endif
257 break;
258 case 'M': /* qemu_st64 constraint */
259 ct->ct |= TCG_CT_REG;
260 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
261 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
262 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
263 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
264 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
265 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);
266 break;
267 #else
268 case 'L':
269 case 'K':
270 ct->ct |= TCG_CT_REG;
271 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
272 break;
273 case 'M':
274 ct->ct |= TCG_CT_REG;
275 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
276 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
277 break;
278 #endif
279 default:
280 return -1;
281 }
282 ct_str++;
283 *pct_str = ct_str;
284 return 0;
285 }
286
287 /* test if a constant matches the constraint */
288 static int tcg_target_const_match(tcg_target_long val,
289 const TCGArgConstraint *arg_ct)
290 {
291 int ct;
292
293 ct = arg_ct->ct;
294 if (ct & TCG_CT_CONST)
295 return 1;
296 return 0;
297 }
298
299 #define OPCD(opc) ((opc)<<26)
300 #define XO31(opc) (OPCD(31)|((opc)<<1))
301 #define XO19(opc) (OPCD(19)|((opc)<<1))
302
303 #define B OPCD(18)
304 #define BC OPCD(16)
305 #define LBZ OPCD(34)
306 #define LHZ OPCD(40)
307 #define LHA OPCD(42)
308 #define LWZ OPCD(32)
309 #define STB OPCD(38)
310 #define STH OPCD(44)
311 #define STW OPCD(36)
312
313 #define ADDIC OPCD(12)
314 #define ADDI OPCD(14)
315 #define ADDIS OPCD(15)
316 #define ORI OPCD(24)
317 #define ORIS OPCD(25)
318 #define XORI OPCD(26)
319 #define XORIS OPCD(27)
320 #define ANDI OPCD(28)
321 #define ANDIS OPCD(29)
322 #define MULLI OPCD( 7)
323 #define CMPLI OPCD(10)
324 #define CMPI OPCD(11)
325 #define SUBFIC OPCD( 8)
326
327 #define LWZU OPCD(33)
328 #define STWU OPCD(37)
329
330 #define RLWIMI OPCD(20)
331 #define RLWINM OPCD(21)
332 #define RLWNM OPCD(23)
333
334 #define BCLR XO19( 16)
335 #define BCCTR XO19(528)
336 #define CRAND XO19(257)
337 #define CRANDC XO19(129)
338 #define CRNAND XO19(225)
339 #define CROR XO19(449)
340 #define CRNOR XO19( 33)
341
342 #define EXTSB XO31(954)
343 #define EXTSH XO31(922)
344 #define ADD XO31(266)
345 #define ADDE XO31(138)
346 #define ADDC XO31( 10)
347 #define AND XO31( 28)
348 #define SUBF XO31( 40)
349 #define SUBFC XO31( 8)
350 #define SUBFE XO31(136)
351 #define OR XO31(444)
352 #define XOR XO31(316)
353 #define MULLW XO31(235)
354 #define MULHWU XO31( 11)
355 #define DIVW XO31(491)
356 #define DIVWU XO31(459)
357 #define CMP XO31( 0)
358 #define CMPL XO31( 32)
359 #define LHBRX XO31(790)
360 #define LWBRX XO31(534)
361 #define STHBRX XO31(918)
362 #define STWBRX XO31(662)
363 #define MFSPR XO31(339)
364 #define MTSPR XO31(467)
365 #define SRAWI XO31(824)
366 #define NEG XO31(104)
367 #define MFCR XO31( 19)
368 #define CNTLZW XO31( 26)
369 #define NOR XO31(124)
370 #define ANDC XO31( 60)
371 #define ORC XO31(412)
372 #define EQV XO31(284)
373 #define NAND XO31(476)
374
375 #define LBZX XO31( 87)
376 #define LHZX XO31(279)
377 #define LHAX XO31(343)
378 #define LWZX XO31( 23)
379 #define STBX XO31(215)
380 #define STHX XO31(407)
381 #define STWX XO31(151)
382
383 #define SPR(a,b) ((((a)<<5)|(b))<<11)
384 #define LR SPR(8, 0)
385 #define CTR SPR(9, 0)
386
387 #define SLW XO31( 24)
388 #define SRW XO31(536)
389 #define SRAW XO31(792)
390
391 #define TW XO31(4)
392 #define TRAP (TW | TO (31))
393
394 #define RT(r) ((r)<<21)
395 #define RS(r) ((r)<<21)
396 #define RA(r) ((r)<<16)
397 #define RB(r) ((r)<<11)
398 #define TO(t) ((t)<<21)
399 #define SH(s) ((s)<<11)
400 #define MB(b) ((b)<<6)
401 #define ME(e) ((e)<<1)
402 #define BO(o) ((o)<<21)
403
404 #define LK 1
405
406 #define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
407 #define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
408
409 #define BF(n) ((n)<<23)
410 #define BI(n, c) (((c)+((n)*4))<<16)
411 #define BT(n, c) (((c)+((n)*4))<<21)
412 #define BA(n, c) (((c)+((n)*4))<<16)
413 #define BB(n, c) (((c)+((n)*4))<<11)
414
415 #define BO_COND_TRUE BO (12)
416 #define BO_COND_FALSE BO (4)
417 #define BO_ALWAYS BO (20)
418
419 enum {
420 CR_LT,
421 CR_GT,
422 CR_EQ,
423 CR_SO
424 };
425
426 static const uint32_t tcg_to_bc[10] = {
427 [TCG_COND_EQ] = BC | BI (7, CR_EQ) | BO_COND_TRUE,
428 [TCG_COND_NE] = BC | BI (7, CR_EQ) | BO_COND_FALSE,
429 [TCG_COND_LT] = BC | BI (7, CR_LT) | BO_COND_TRUE,
430 [TCG_COND_GE] = BC | BI (7, CR_LT) | BO_COND_FALSE,
431 [TCG_COND_LE] = BC | BI (7, CR_GT) | BO_COND_FALSE,
432 [TCG_COND_GT] = BC | BI (7, CR_GT) | BO_COND_TRUE,
433 [TCG_COND_LTU] = BC | BI (7, CR_LT) | BO_COND_TRUE,
434 [TCG_COND_GEU] = BC | BI (7, CR_LT) | BO_COND_FALSE,
435 [TCG_COND_LEU] = BC | BI (7, CR_GT) | BO_COND_FALSE,
436 [TCG_COND_GTU] = BC | BI (7, CR_GT) | BO_COND_TRUE,
437 };
438
439 static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
440 {
441 tcg_out32 (s, OR | SAB (arg, ret, arg));
442 }
443
444 static void tcg_out_movi(TCGContext *s, TCGType type,
445 TCGReg ret, tcg_target_long arg)
446 {
447 if (arg == (int16_t) arg)
448 tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff));
449 else {
450 tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff));
451 if (arg & 0xffff)
452 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
453 }
454 }
455
456 static void tcg_out_ldst (TCGContext *s, int ret, int addr,
457 int offset, int op1, int op2)
458 {
459 if (offset == (int16_t) offset)
460 tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff));
461 else {
462 tcg_out_movi (s, TCG_TYPE_I32, 0, offset);
463 tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
464 }
465 }
466
467 static void tcg_out_b (TCGContext *s, int mask, tcg_target_long target)
468 {
469 tcg_target_long disp;
470
471 disp = target - (tcg_target_long) s->code_ptr;
472 if ((disp << 6) >> 6 == disp)
473 tcg_out32 (s, B | (disp & 0x3fffffc) | mask);
474 else {
475 tcg_out_movi (s, TCG_TYPE_I32, 0, (tcg_target_long) target);
476 tcg_out32 (s, MTSPR | RS (0) | CTR);
477 tcg_out32 (s, BCCTR | BO_ALWAYS | mask);
478 }
479 }
480
481 static void tcg_out_call (TCGContext *s, tcg_target_long arg, int const_arg)
482 {
483 #ifdef _CALL_AIX
484 int reg;
485
486 if (const_arg) {
487 reg = 2;
488 tcg_out_movi (s, TCG_TYPE_I32, reg, arg);
489 }
490 else reg = arg;
491
492 tcg_out32 (s, LWZ | RT (0) | RA (reg));
493 tcg_out32 (s, MTSPR | RA (0) | CTR);
494 tcg_out32 (s, LWZ | RT (2) | RA (reg) | 4);
495 tcg_out32 (s, BCCTR | BO_ALWAYS | LK);
496 #else
497 if (const_arg) {
498 tcg_out_b (s, LK, arg);
499 }
500 else {
501 tcg_out32 (s, MTSPR | RS (arg) | LR);
502 tcg_out32 (s, BCLR | BO_ALWAYS | LK);
503 }
504 #endif
505 }
506
507 #if defined(CONFIG_SOFTMMU)
508
509 #include "../../softmmu_defs.h"
510
511 #ifdef CONFIG_TCG_PASS_AREG0
512 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
513 int mmu_idx) */
514 static const void * const qemu_ld_helpers[4] = {
515 helper_ldb_mmu,
516 helper_ldw_mmu,
517 helper_ldl_mmu,
518 helper_ldq_mmu,
519 };
520
521 /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
522 uintxx_t val, int mmu_idx) */
523 static const void * const qemu_st_helpers[4] = {
524 helper_stb_mmu,
525 helper_stw_mmu,
526 helper_stl_mmu,
527 helper_stq_mmu,
528 };
529 #else
530 /* legacy helper signature: __ld_mmu(target_ulong addr, int
531 mmu_idx) */
532 static void *qemu_ld_helpers[4] = {
533 __ldb_mmu,
534 __ldw_mmu,
535 __ldl_mmu,
536 __ldq_mmu,
537 };
538
539 /* legacy helper signature: __ld_mmu(target_ulong addr, int
540 mmu_idx) */
541 static void *qemu_st_helpers[4] = {
542 __stb_mmu,
543 __stw_mmu,
544 __stl_mmu,
545 __stq_mmu,
546 };
547 #endif
548 #endif
549
550 static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
551 {
552 int addr_reg, data_reg, data_reg2, r0, r1, rbase, bswap;
553 #ifdef CONFIG_SOFTMMU
554 int mem_index, s_bits, r2;
555 void *label1_ptr, *label2_ptr;
556 #if TARGET_LONG_BITS == 64
557 int addr_reg2;
558 #endif
559 #endif
560
561 data_reg = *args++;
562 if (opc == 3)
563 data_reg2 = *args++;
564 else
565 data_reg2 = 0;
566 addr_reg = *args++;
567
568 #ifdef CONFIG_SOFTMMU
569 #if TARGET_LONG_BITS == 64
570 addr_reg2 = *args++;
571 #endif
572 mem_index = *args;
573 s_bits = opc & 3;
574 r0 = 3;
575 r1 = 4;
576 r2 = 0;
577 rbase = 0;
578
579 tcg_out32 (s, (RLWINM
580 | RA (r0)
581 | RS (addr_reg)
582 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
583 | MB (32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS))
584 | ME (31 - CPU_TLB_ENTRY_BITS)
585 )
586 );
587 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
588 tcg_out32 (s, (LWZU
589 | RT (r1)
590 | RA (r0)
591 | offsetof (CPUArchState, tlb_table[mem_index][0].addr_read)
592 )
593 );
594 tcg_out32 (s, (RLWINM
595 | RA (r2)
596 | RS (addr_reg)
597 | SH (0)
598 | MB ((32 - s_bits) & 31)
599 | ME (31 - TARGET_PAGE_BITS)
600 )
601 );
602
603 tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1));
604 #if TARGET_LONG_BITS == 64
605 tcg_out32 (s, LWZ | RT (r1) | RA (r0) | 4);
606 tcg_out32 (s, CMP | BF (6) | RA (addr_reg2) | RB (r1));
607 tcg_out32 (s, CRAND | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
608 #endif
609
610 label1_ptr = s->code_ptr;
611 #ifdef FAST_PATH
612 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
613 #endif
614
615 /* slow path */
616 #if TARGET_LONG_BITS == 32
617 tcg_out_mov (s, TCG_TYPE_I32, 3, addr_reg);
618 tcg_out_movi (s, TCG_TYPE_I32, 4, mem_index);
619 #else
620 tcg_out_mov (s, TCG_TYPE_I32, 3, addr_reg2);
621 tcg_out_mov (s, TCG_TYPE_I32, 4, addr_reg);
622 tcg_out_movi (s, TCG_TYPE_I32, 5, mem_index);
623 #endif
624
625 #ifdef CONFIG_TCG_PASS_AREG0
626 /* XXX/FIXME: suboptimal */
627 tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[2],
628 tcg_target_call_iarg_regs[1]);
629 tcg_out_mov(s, TCG_TYPE_TL, tcg_target_call_iarg_regs[1],
630 tcg_target_call_iarg_regs[0]);
631 tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0],
632 TCG_AREG0);
633 #endif
634
635 tcg_out_call (s, (tcg_target_long) qemu_ld_helpers[s_bits], 1);
636 switch (opc) {
637 case 0|4:
638 tcg_out32 (s, EXTSB | RA (data_reg) | RS (3));
639 break;
640 case 1|4:
641 tcg_out32 (s, EXTSH | RA (data_reg) | RS (3));
642 break;
643 case 0:
644 case 1:
645 case 2:
646 if (data_reg != 3)
647 tcg_out_mov (s, TCG_TYPE_I32, data_reg, 3);
648 break;
649 case 3:
650 if (data_reg == 3) {
651 if (data_reg2 == 4) {
652 tcg_out_mov (s, TCG_TYPE_I32, 0, 4);
653 tcg_out_mov (s, TCG_TYPE_I32, 4, 3);
654 tcg_out_mov (s, TCG_TYPE_I32, 3, 0);
655 }
656 else {
657 tcg_out_mov (s, TCG_TYPE_I32, data_reg2, 3);
658 tcg_out_mov (s, TCG_TYPE_I32, 3, 4);
659 }
660 }
661 else {
662 if (data_reg != 4) tcg_out_mov (s, TCG_TYPE_I32, data_reg, 4);
663 if (data_reg2 != 3) tcg_out_mov (s, TCG_TYPE_I32, data_reg2, 3);
664 }
665 break;
666 }
667 label2_ptr = s->code_ptr;
668 tcg_out32 (s, B);
669
670 /* label1: fast path */
671 #ifdef FAST_PATH
672 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
673 #endif
674
675 /* r0 now contains &env->tlb_table[mem_index][index].addr_read */
676 tcg_out32 (s, (LWZ
677 | RT (r0)
678 | RA (r0)
679 | (offsetof (CPUTLBEntry, addend)
680 - offsetof (CPUTLBEntry, addr_read))
681 ));
682 /* r0 = env->tlb_table[mem_index][index].addend */
683 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
684 /* r0 = env->tlb_table[mem_index][index].addend + addr */
685
686 #else /* !CONFIG_SOFTMMU */
687 r0 = addr_reg;
688 r1 = 3;
689 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
690 #endif
691
692 #ifdef TARGET_WORDS_BIGENDIAN
693 bswap = 0;
694 #else
695 bswap = 1;
696 #endif
697
698 switch (opc) {
699 default:
700 case 0:
701 tcg_out32 (s, LBZX | TAB (data_reg, rbase, r0));
702 break;
703 case 0|4:
704 tcg_out32 (s, LBZX | TAB (data_reg, rbase, r0));
705 tcg_out32 (s, EXTSB | RA (data_reg) | RS (data_reg));
706 break;
707 case 1:
708 if (bswap)
709 tcg_out32 (s, LHBRX | TAB (data_reg, rbase, r0));
710 else
711 tcg_out32 (s, LHZX | TAB (data_reg, rbase, r0));
712 break;
713 case 1|4:
714 if (bswap) {
715 tcg_out32 (s, LHBRX | TAB (data_reg, rbase, r0));
716 tcg_out32 (s, EXTSH | RA (data_reg) | RS (data_reg));
717 }
718 else tcg_out32 (s, LHAX | TAB (data_reg, rbase, r0));
719 break;
720 case 2:
721 if (bswap)
722 tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
723 else
724 tcg_out32 (s, LWZX | TAB (data_reg, rbase, r0));
725 break;
726 case 3:
727 if (bswap) {
728 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
729 tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
730 tcg_out32 (s, LWBRX | TAB (data_reg2, rbase, r1));
731 }
732 else {
733 #ifdef CONFIG_USE_GUEST_BASE
734 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
735 tcg_out32 (s, LWZX | TAB (data_reg2, rbase, r0));
736 tcg_out32 (s, LWZX | TAB (data_reg, rbase, r1));
737 #else
738 if (r0 == data_reg2) {
739 tcg_out32 (s, LWZ | RT (0) | RA (r0));
740 tcg_out32 (s, LWZ | RT (data_reg) | RA (r0) | 4);
741 tcg_out_mov (s, TCG_TYPE_I32, data_reg2, 0);
742 }
743 else {
744 tcg_out32 (s, LWZ | RT (data_reg2) | RA (r0));
745 tcg_out32 (s, LWZ | RT (data_reg) | RA (r0) | 4);
746 }
747 #endif
748 }
749 break;
750 }
751
752 #ifdef CONFIG_SOFTMMU
753 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
754 #endif
755 }
756
757 static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
758 {
759 int addr_reg, r0, r1, data_reg, data_reg2, bswap, rbase;
760 #ifdef CONFIG_SOFTMMU
761 int mem_index, r2, ir;
762 void *label1_ptr, *label2_ptr;
763 #if TARGET_LONG_BITS == 64
764 int addr_reg2;
765 #endif
766 #endif
767
768 data_reg = *args++;
769 if (opc == 3)
770 data_reg2 = *args++;
771 else
772 data_reg2 = 0;
773 addr_reg = *args++;
774
775 #ifdef CONFIG_SOFTMMU
776 #if TARGET_LONG_BITS == 64
777 addr_reg2 = *args++;
778 #endif
779 mem_index = *args;
780 r0 = 3;
781 r1 = 4;
782 r2 = 0;
783 rbase = 0;
784
785 tcg_out32 (s, (RLWINM
786 | RA (r0)
787 | RS (addr_reg)
788 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
789 | MB (32 - (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS))
790 | ME (31 - CPU_TLB_ENTRY_BITS)
791 )
792 );
793 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
794 tcg_out32 (s, (LWZU
795 | RT (r1)
796 | RA (r0)
797 | offsetof (CPUArchState, tlb_table[mem_index][0].addr_write)
798 )
799 );
800 tcg_out32 (s, (RLWINM
801 | RA (r2)
802 | RS (addr_reg)
803 | SH (0)
804 | MB ((32 - opc) & 31)
805 | ME (31 - TARGET_PAGE_BITS)
806 )
807 );
808
809 tcg_out32 (s, CMP | (7 << 23) | RA (r2) | RB (r1));
810 #if TARGET_LONG_BITS == 64
811 tcg_out32 (s, LWZ | RT (r1) | RA (r0) | 4);
812 tcg_out32 (s, CMP | BF (6) | RA (addr_reg2) | RB (r1));
813 tcg_out32 (s, CRAND | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
814 #endif
815
816 label1_ptr = s->code_ptr;
817 #ifdef FAST_PATH
818 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
819 #endif
820
821 /* slow path */
822 #if TARGET_LONG_BITS == 32
823 tcg_out_mov (s, TCG_TYPE_I32, 3, addr_reg);
824 ir = 4;
825 #else
826 tcg_out_mov (s, TCG_TYPE_I32, 3, addr_reg2);
827 tcg_out_mov (s, TCG_TYPE_I32, 4, addr_reg);
828 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
829 ir = 5;
830 #else
831 ir = 4;
832 #endif
833 #endif
834
835 switch (opc) {
836 case 0:
837 tcg_out32 (s, (RLWINM
838 | RA (ir)
839 | RS (data_reg)
840 | SH (0)
841 | MB (24)
842 | ME (31)));
843 break;
844 case 1:
845 tcg_out32 (s, (RLWINM
846 | RA (ir)
847 | RS (data_reg)
848 | SH (0)
849 | MB (16)
850 | ME (31)));
851 break;
852 case 2:
853 tcg_out_mov (s, TCG_TYPE_I32, ir, data_reg);
854 break;
855 case 3:
856 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
857 ir = 5;
858 #endif
859 tcg_out_mov (s, TCG_TYPE_I32, ir++, data_reg2);
860 tcg_out_mov (s, TCG_TYPE_I32, ir, data_reg);
861 break;
862 }
863 ir++;
864
865 tcg_out_movi (s, TCG_TYPE_I32, ir, mem_index);
866 #ifdef CONFIG_TCG_PASS_AREG0
867 /* XXX/FIXME: suboptimal */
868 tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3],
869 tcg_target_call_iarg_regs[2]);
870 tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[2],
871 tcg_target_call_iarg_regs[1]);
872 tcg_out_mov(s, TCG_TYPE_TL, tcg_target_call_iarg_regs[1],
873 tcg_target_call_iarg_regs[0]);
874 tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0],
875 TCG_AREG0);
876 #endif
877 tcg_out_call (s, (tcg_target_long) qemu_st_helpers[opc], 1);
878 label2_ptr = s->code_ptr;
879 tcg_out32 (s, B);
880
881 /* label1: fast path */
882 #ifdef FAST_PATH
883 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
884 #endif
885
886 tcg_out32 (s, (LWZ
887 | RT (r0)
888 | RA (r0)
889 | (offsetof (CPUTLBEntry, addend)
890 - offsetof (CPUTLBEntry, addr_write))
891 ));
892 /* r0 = env->tlb_table[mem_index][index].addend */
893 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
894 /* r0 = env->tlb_table[mem_index][index].addend + addr */
895
896 #else /* !CONFIG_SOFTMMU */
897 r0 = addr_reg;
898 r1 = 3;
899 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
900 #endif
901
902 #ifdef TARGET_WORDS_BIGENDIAN
903 bswap = 0;
904 #else
905 bswap = 1;
906 #endif
907 switch (opc) {
908 case 0:
909 tcg_out32 (s, STBX | SAB (data_reg, rbase, r0));
910 break;
911 case 1:
912 if (bswap)
913 tcg_out32 (s, STHBRX | SAB (data_reg, rbase, r0));
914 else
915 tcg_out32 (s, STHX | SAB (data_reg, rbase, r0));
916 break;
917 case 2:
918 if (bswap)
919 tcg_out32 (s, STWBRX | SAB (data_reg, rbase, r0));
920 else
921 tcg_out32 (s, STWX | SAB (data_reg, rbase, r0));
922 break;
923 case 3:
924 if (bswap) {
925 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
926 tcg_out32 (s, STWBRX | SAB (data_reg, rbase, r0));
927 tcg_out32 (s, STWBRX | SAB (data_reg2, rbase, r1));
928 }
929 else {
930 #ifdef CONFIG_USE_GUEST_BASE
931 tcg_out32 (s, STWX | SAB (data_reg2, rbase, r0));
932 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
933 tcg_out32 (s, STWX | SAB (data_reg, rbase, r1));
934 #else
935 tcg_out32 (s, STW | RS (data_reg2) | RA (r0));
936 tcg_out32 (s, STW | RS (data_reg) | RA (r0) | 4);
937 #endif
938 }
939 break;
940 }
941
942 #ifdef CONFIG_SOFTMMU
943 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
944 #endif
945 }
946
947 static void tcg_target_qemu_prologue (TCGContext *s)
948 {
949 int i, frame_size;
950
951 frame_size = 0
952 + LINKAGE_AREA_SIZE
953 + TCG_STATIC_CALL_ARGS_SIZE
954 + ARRAY_SIZE (tcg_target_callee_save_regs) * 4
955 + CPU_TEMP_BUF_NLONGS * sizeof(long)
956 ;
957 frame_size = (frame_size + 15) & ~15;
958
959 tcg_set_frame(s, TCG_REG_CALL_STACK, frame_size
960 - CPU_TEMP_BUF_NLONGS * sizeof(long),
961 CPU_TEMP_BUF_NLONGS * sizeof(long));
962
963 #ifdef _CALL_AIX
964 {
965 uint32_t addr;
966
967 /* First emit adhoc function descriptor */
968 addr = (uint32_t) s->code_ptr + 12;
969 tcg_out32 (s, addr); /* entry point */
970 s->code_ptr += 8; /* skip TOC and environment pointer */
971 }
972 #endif
973 tcg_out32 (s, MFSPR | RT (0) | LR);
974 tcg_out32 (s, STWU | RS (1) | RA (1) | (-frame_size & 0xffff));
975 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
976 tcg_out32 (s, (STW
977 | RS (tcg_target_callee_save_regs[i])
978 | RA (1)
979 | (i * 4 + LINKAGE_AREA_SIZE + TCG_STATIC_CALL_ARGS_SIZE)
980 )
981 );
982 tcg_out32 (s, STW | RS (0) | RA (1) | (frame_size + LR_OFFSET));
983
984 #ifdef CONFIG_USE_GUEST_BASE
985 if (GUEST_BASE) {
986 tcg_out_movi (s, TCG_TYPE_I32, TCG_GUEST_BASE_REG, GUEST_BASE);
987 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
988 }
989 #endif
990
991 tcg_out_mov (s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
992 tcg_out32 (s, MTSPR | RS (tcg_target_call_iarg_regs[1]) | CTR);
993 tcg_out32 (s, BCCTR | BO_ALWAYS);
994 tb_ret_addr = s->code_ptr;
995
996 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
997 tcg_out32 (s, (LWZ
998 | RT (tcg_target_callee_save_regs[i])
999 | RA (1)
1000 | (i * 4 + LINKAGE_AREA_SIZE + TCG_STATIC_CALL_ARGS_SIZE)
1001 )
1002 );
1003 tcg_out32 (s, LWZ | RT (0) | RA (1) | (frame_size + LR_OFFSET));
1004 tcg_out32 (s, MTSPR | RS (0) | LR);
1005 tcg_out32 (s, ADDI | RT (1) | RA (1) | frame_size);
1006 tcg_out32 (s, BCLR | BO_ALWAYS);
1007 }
1008
1009 static void tcg_out_ld (TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
1010 tcg_target_long arg2)
1011 {
1012 tcg_out_ldst (s, ret, arg1, arg2, LWZ, LWZX);
1013 }
1014
1015 static void tcg_out_st (TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1,
1016 tcg_target_long arg2)
1017 {
1018 tcg_out_ldst (s, arg, arg1, arg2, STW, STWX);
1019 }
1020
1021 static void ppc_addi (TCGContext *s, int rt, int ra, tcg_target_long si)
1022 {
1023 if (!si && rt == ra)
1024 return;
1025
1026 if (si == (int16_t) si)
1027 tcg_out32 (s, ADDI | RT (rt) | RA (ra) | (si & 0xffff));
1028 else {
1029 uint16_t h = ((si >> 16) & 0xffff) + ((uint16_t) si >> 15);
1030 tcg_out32 (s, ADDIS | RT (rt) | RA (ra) | h);
1031 tcg_out32 (s, ADDI | RT (rt) | RA (rt) | (si & 0xffff));
1032 }
1033 }
1034
1035 static void tcg_out_cmp (TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
1036 int const_arg2, int cr)
1037 {
1038 int imm;
1039 uint32_t op;
1040
1041 switch (cond) {
1042 case TCG_COND_EQ:
1043 case TCG_COND_NE:
1044 if (const_arg2) {
1045 if ((int16_t) arg2 == arg2) {
1046 op = CMPI;
1047 imm = 1;
1048 break;
1049 }
1050 else if ((uint16_t) arg2 == arg2) {
1051 op = CMPLI;
1052 imm = 1;
1053 break;
1054 }
1055 }
1056 op = CMPL;
1057 imm = 0;
1058 break;
1059
1060 case TCG_COND_LT:
1061 case TCG_COND_GE:
1062 case TCG_COND_LE:
1063 case TCG_COND_GT:
1064 if (const_arg2) {
1065 if ((int16_t) arg2 == arg2) {
1066 op = CMPI;
1067 imm = 1;
1068 break;
1069 }
1070 }
1071 op = CMP;
1072 imm = 0;
1073 break;
1074
1075 case TCG_COND_LTU:
1076 case TCG_COND_GEU:
1077 case TCG_COND_LEU:
1078 case TCG_COND_GTU:
1079 if (const_arg2) {
1080 if ((uint16_t) arg2 == arg2) {
1081 op = CMPLI;
1082 imm = 1;
1083 break;
1084 }
1085 }
1086 op = CMPL;
1087 imm = 0;
1088 break;
1089
1090 default:
1091 tcg_abort ();
1092 }
1093 op |= BF (cr);
1094
1095 if (imm)
1096 tcg_out32 (s, op | RA (arg1) | (arg2 & 0xffff));
1097 else {
1098 if (const_arg2) {
1099 tcg_out_movi (s, TCG_TYPE_I32, 0, arg2);
1100 tcg_out32 (s, op | RA (arg1) | RB (0));
1101 }
1102 else
1103 tcg_out32 (s, op | RA (arg1) | RB (arg2));
1104 }
1105
1106 }
1107
1108 static void tcg_out_bc (TCGContext *s, int bc, int label_index)
1109 {
1110 TCGLabel *l = &s->labels[label_index];
1111
1112 if (l->has_value)
1113 tcg_out32 (s, bc | reloc_pc14_val (s->code_ptr, l->u.value));
1114 else {
1115 uint16_t val = *(uint16_t *) &s->code_ptr[2];
1116
1117 /* Thanks to Andrzej Zaborowski */
1118 tcg_out32 (s, bc | (val & 0xfffc));
1119 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL14, label_index, 0);
1120 }
1121 }
1122
1123 static void tcg_out_cr7eq_from_cond (TCGContext *s, const TCGArg *args,
1124 const int *const_args)
1125 {
1126 TCGCond cond = args[4];
1127 int op;
1128 struct { int bit1; int bit2; int cond2; } bits[] = {
1129 [TCG_COND_LT ] = { CR_LT, CR_LT, TCG_COND_LT },
1130 [TCG_COND_LE ] = { CR_LT, CR_GT, TCG_COND_LT },
1131 [TCG_COND_GT ] = { CR_GT, CR_GT, TCG_COND_GT },
1132 [TCG_COND_GE ] = { CR_GT, CR_LT, TCG_COND_GT },
1133 [TCG_COND_LTU] = { CR_LT, CR_LT, TCG_COND_LTU },
1134 [TCG_COND_LEU] = { CR_LT, CR_GT, TCG_COND_LTU },
1135 [TCG_COND_GTU] = { CR_GT, CR_GT, TCG_COND_GTU },
1136 [TCG_COND_GEU] = { CR_GT, CR_LT, TCG_COND_GTU },
1137 }, *b = &bits[cond];
1138
1139 switch (cond) {
1140 case TCG_COND_EQ:
1141 case TCG_COND_NE:
1142 op = (cond == TCG_COND_EQ) ? CRAND : CRNAND;
1143 tcg_out_cmp (s, cond, args[0], args[2], const_args[2], 6);
1144 tcg_out_cmp (s, cond, args[1], args[3], const_args[3], 7);
1145 tcg_out32 (s, op | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
1146 break;
1147 case TCG_COND_LT:
1148 case TCG_COND_LE:
1149 case TCG_COND_GT:
1150 case TCG_COND_GE:
1151 case TCG_COND_LTU:
1152 case TCG_COND_LEU:
1153 case TCG_COND_GTU:
1154 case TCG_COND_GEU:
1155 op = (b->bit1 != b->bit2) ? CRANDC : CRAND;
1156 tcg_out_cmp (s, b->cond2, args[1], args[3], const_args[3], 5);
1157 tcg_out_cmp (s, tcg_unsigned_cond (cond), args[0], args[2],
1158 const_args[2], 7);
1159 tcg_out32 (s, op | BT (7, CR_EQ) | BA (5, CR_EQ) | BB (7, b->bit2));
1160 tcg_out32 (s, CROR | BT (7, CR_EQ) | BA (5, b->bit1) | BB (7, CR_EQ));
1161 break;
1162 default:
1163 tcg_abort();
1164 }
1165 }
1166
1167 static void tcg_out_setcond (TCGContext *s, TCGCond cond, TCGArg arg0,
1168 TCGArg arg1, TCGArg arg2, int const_arg2)
1169 {
1170 int crop, sh, arg;
1171
1172 switch (cond) {
1173 case TCG_COND_EQ:
1174 if (const_arg2) {
1175 if (!arg2) {
1176 arg = arg1;
1177 }
1178 else {
1179 arg = 0;
1180 if ((uint16_t) arg2 == arg2) {
1181 tcg_out32 (s, XORI | RS (arg1) | RA (0) | arg2);
1182 }
1183 else {
1184 tcg_out_movi (s, TCG_TYPE_I32, 0, arg2);
1185 tcg_out32 (s, XOR | SAB (arg1, 0, 0));
1186 }
1187 }
1188 }
1189 else {
1190 arg = 0;
1191 tcg_out32 (s, XOR | SAB (arg1, 0, arg2));
1192 }
1193 tcg_out32 (s, CNTLZW | RS (arg) | RA (0));
1194 tcg_out32 (s, (RLWINM
1195 | RA (arg0)
1196 | RS (0)
1197 | SH (27)
1198 | MB (5)
1199 | ME (31)
1200 )
1201 );
1202 break;
1203
1204 case TCG_COND_NE:
1205 if (const_arg2) {
1206 if (!arg2) {
1207 arg = arg1;
1208 }
1209 else {
1210 arg = 0;
1211 if ((uint16_t) arg2 == arg2) {
1212 tcg_out32 (s, XORI | RS (arg1) | RA (0) | arg2);
1213 }
1214 else {
1215 tcg_out_movi (s, TCG_TYPE_I32, 0, arg2);
1216 tcg_out32 (s, XOR | SAB (arg1, 0, 0));
1217 }
1218 }
1219 }
1220 else {
1221 arg = 0;
1222 tcg_out32 (s, XOR | SAB (arg1, 0, arg2));
1223 }
1224
1225 if (arg == arg1 && arg1 == arg0) {
1226 tcg_out32 (s, ADDIC | RT (0) | RA (arg) | 0xffff);
1227 tcg_out32 (s, SUBFE | TAB (arg0, 0, arg));
1228 }
1229 else {
1230 tcg_out32 (s, ADDIC | RT (arg0) | RA (arg) | 0xffff);
1231 tcg_out32 (s, SUBFE | TAB (arg0, arg0, arg));
1232 }
1233 break;
1234
1235 case TCG_COND_GT:
1236 case TCG_COND_GTU:
1237 sh = 30;
1238 crop = 0;
1239 goto crtest;
1240
1241 case TCG_COND_LT:
1242 case TCG_COND_LTU:
1243 sh = 29;
1244 crop = 0;
1245 goto crtest;
1246
1247 case TCG_COND_GE:
1248 case TCG_COND_GEU:
1249 sh = 31;
1250 crop = CRNOR | BT (7, CR_EQ) | BA (7, CR_LT) | BB (7, CR_LT);
1251 goto crtest;
1252
1253 case TCG_COND_LE:
1254 case TCG_COND_LEU:
1255 sh = 31;
1256 crop = CRNOR | BT (7, CR_EQ) | BA (7, CR_GT) | BB (7, CR_GT);
1257 crtest:
1258 tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7);
1259 if (crop) tcg_out32 (s, crop);
1260 tcg_out32 (s, MFCR | RT (0));
1261 tcg_out32 (s, (RLWINM
1262 | RA (arg0)
1263 | RS (0)
1264 | SH (sh)
1265 | MB (31)
1266 | ME (31)
1267 )
1268 );
1269 break;
1270
1271 default:
1272 tcg_abort ();
1273 }
1274 }
1275
1276 static void tcg_out_setcond2 (TCGContext *s, const TCGArg *args,
1277 const int *const_args)
1278 {
1279 tcg_out_cr7eq_from_cond (s, args + 1, const_args + 1);
1280 tcg_out32 (s, MFCR | RT (0));
1281 tcg_out32 (s, (RLWINM
1282 | RA (args[0])
1283 | RS (0)
1284 | SH (31)
1285 | MB (31)
1286 | ME (31)
1287 )
1288 );
1289 }
1290
1291 static void tcg_out_brcond (TCGContext *s, TCGCond cond,
1292 TCGArg arg1, TCGArg arg2, int const_arg2,
1293 int label_index)
1294 {
1295 tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7);
1296 tcg_out_bc (s, tcg_to_bc[cond], label_index);
1297 }
1298
1299 /* XXX: we implement it at the target level to avoid having to
1300 handle cross basic blocks temporaries */
1301 static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args,
1302 const int *const_args)
1303 {
1304 tcg_out_cr7eq_from_cond (s, args, const_args);
1305 tcg_out_bc (s, (BC | BI (7, CR_EQ) | BO_COND_TRUE), args[5]);
1306 }
1307
1308 void ppc_tb_set_jmp_target (unsigned long jmp_addr, unsigned long addr)
1309 {
1310 uint32_t *ptr;
1311 long disp = addr - jmp_addr;
1312 unsigned long patch_size;
1313
1314 ptr = (uint32_t *)jmp_addr;
1315
1316 if ((disp << 6) >> 6 != disp) {
1317 ptr[0] = 0x3c000000 | (addr >> 16); /* lis 0,addr@ha */
1318 ptr[1] = 0x60000000 | (addr & 0xffff); /* la 0,addr@l(0) */
1319 ptr[2] = 0x7c0903a6; /* mtctr 0 */
1320 ptr[3] = 0x4e800420; /* brctr */
1321 patch_size = 16;
1322 } else {
1323 /* patch the branch destination */
1324 if (disp != 16) {
1325 *ptr = 0x48000000 | (disp & 0x03fffffc); /* b disp */
1326 patch_size = 4;
1327 } else {
1328 ptr[0] = 0x60000000; /* nop */
1329 ptr[1] = 0x60000000;
1330 ptr[2] = 0x60000000;
1331 ptr[3] = 0x60000000;
1332 patch_size = 16;
1333 }
1334 }
1335 /* flush icache */
1336 flush_icache_range(jmp_addr, jmp_addr + patch_size);
1337 }
1338
1339 static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
1340 const int *const_args)
1341 {
1342 switch (opc) {
1343 case INDEX_op_exit_tb:
1344 tcg_out_movi (s, TCG_TYPE_I32, TCG_REG_R3, args[0]);
1345 tcg_out_b (s, 0, (tcg_target_long) tb_ret_addr);
1346 break;
1347 case INDEX_op_goto_tb:
1348 if (s->tb_jmp_offset) {
1349 /* direct jump method */
1350
1351 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1352 s->code_ptr += 16;
1353 }
1354 else {
1355 tcg_abort ();
1356 }
1357 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1358 break;
1359 case INDEX_op_br:
1360 {
1361 TCGLabel *l = &s->labels[args[0]];
1362
1363 if (l->has_value) {
1364 tcg_out_b (s, 0, l->u.value);
1365 }
1366 else {
1367 uint32_t val = *(uint32_t *) s->code_ptr;
1368
1369 /* Thanks to Andrzej Zaborowski */
1370 tcg_out32 (s, B | (val & 0x3fffffc));
1371 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL24, args[0], 0);
1372 }
1373 }
1374 break;
1375 case INDEX_op_call:
1376 tcg_out_call (s, args[0], const_args[0]);
1377 break;
1378 case INDEX_op_jmp:
1379 if (const_args[0]) {
1380 tcg_out_b (s, 0, args[0]);
1381 }
1382 else {
1383 tcg_out32 (s, MTSPR | RS (args[0]) | CTR);
1384 tcg_out32 (s, BCCTR | BO_ALWAYS);
1385 }
1386 break;
1387 case INDEX_op_movi_i32:
1388 tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
1389 break;
1390 case INDEX_op_ld8u_i32:
1391 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1392 break;
1393 case INDEX_op_ld8s_i32:
1394 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1395 tcg_out32 (s, EXTSB | RS (args[0]) | RA (args[0]));
1396 break;
1397 case INDEX_op_ld16u_i32:
1398 tcg_out_ldst (s, args[0], args[1], args[2], LHZ, LHZX);
1399 break;
1400 case INDEX_op_ld16s_i32:
1401 tcg_out_ldst (s, args[0], args[1], args[2], LHA, LHAX);
1402 break;
1403 case INDEX_op_ld_i32:
1404 tcg_out_ldst (s, args[0], args[1], args[2], LWZ, LWZX);
1405 break;
1406 case INDEX_op_st8_i32:
1407 tcg_out_ldst (s, args[0], args[1], args[2], STB, STBX);
1408 break;
1409 case INDEX_op_st16_i32:
1410 tcg_out_ldst (s, args[0], args[1], args[2], STH, STHX);
1411 break;
1412 case INDEX_op_st_i32:
1413 tcg_out_ldst (s, args[0], args[1], args[2], STW, STWX);
1414 break;
1415
1416 case INDEX_op_add_i32:
1417 if (const_args[2])
1418 ppc_addi (s, args[0], args[1], args[2]);
1419 else
1420 tcg_out32 (s, ADD | TAB (args[0], args[1], args[2]));
1421 break;
1422 case INDEX_op_sub_i32:
1423 if (const_args[2])
1424 ppc_addi (s, args[0], args[1], -args[2]);
1425 else
1426 tcg_out32 (s, SUBF | TAB (args[0], args[2], args[1]));
1427 break;
1428
1429 case INDEX_op_and_i32:
1430 if (const_args[2]) {
1431 uint32_t c;
1432
1433 c = args[2];
1434
1435 if (!c) {
1436 tcg_out_movi (s, TCG_TYPE_I32, args[0], 0);
1437 break;
1438 }
1439 #ifdef __PPU__
1440 uint32_t t, n;
1441 int mb, me;
1442
1443 n = c ^ -(c & 1);
1444 t = n + (n & -n);
1445
1446 if ((t & (t - 1)) == 0) {
1447 int lzc, tzc;
1448
1449 if ((c & 0x80000001) == 0x80000001) {
1450 lzc = clz32 (n);
1451 tzc = ctz32 (n);
1452
1453 mb = 32 - tzc;
1454 me = lzc - 1;
1455 }
1456 else {
1457 lzc = clz32 (c);
1458 tzc = ctz32 (c);
1459
1460 mb = lzc;
1461 me = 31 - tzc;
1462 }
1463
1464 tcg_out32 (s, (RLWINM
1465 | RA (args[0])
1466 | RS (args[1])
1467 | SH (0)
1468 | MB (mb)
1469 | ME (me)
1470 )
1471 );
1472 }
1473 else
1474 #endif /* !__PPU__ */
1475 {
1476 if ((c & 0xffff) == c)
1477 tcg_out32 (s, ANDI | RS (args[1]) | RA (args[0]) | c);
1478 else if ((c & 0xffff0000) == c)
1479 tcg_out32 (s, ANDIS | RS (args[1]) | RA (args[0])
1480 | ((c >> 16) & 0xffff));
1481 else {
1482 tcg_out_movi (s, TCG_TYPE_I32, 0, c);
1483 tcg_out32 (s, AND | SAB (args[1], args[0], 0));
1484 }
1485 }
1486 }
1487 else
1488 tcg_out32 (s, AND | SAB (args[1], args[0], args[2]));
1489 break;
1490 case INDEX_op_or_i32:
1491 if (const_args[2]) {
1492 if (args[2] & 0xffff) {
1493 tcg_out32 (s, ORI | RS (args[1]) | RA (args[0])
1494 | (args[2] & 0xffff));
1495 if (args[2] >> 16)
1496 tcg_out32 (s, ORIS | RS (args[0]) | RA (args[0])
1497 | ((args[2] >> 16) & 0xffff));
1498 }
1499 else {
1500 tcg_out32 (s, ORIS | RS (args[1]) | RA (args[0])
1501 | ((args[2] >> 16) & 0xffff));
1502 }
1503 }
1504 else
1505 tcg_out32 (s, OR | SAB (args[1], args[0], args[2]));
1506 break;
1507 case INDEX_op_xor_i32:
1508 if (const_args[2]) {
1509 if ((args[2] & 0xffff) == args[2])
1510 tcg_out32 (s, XORI | RS (args[1]) | RA (args[0])
1511 | (args[2] & 0xffff));
1512 else if ((args[2] & 0xffff0000) == args[2])
1513 tcg_out32 (s, XORIS | RS (args[1]) | RA (args[0])
1514 | ((args[2] >> 16) & 0xffff));
1515 else {
1516 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1517 tcg_out32 (s, XOR | SAB (args[1], args[0], 0));
1518 }
1519 }
1520 else
1521 tcg_out32 (s, XOR | SAB (args[1], args[0], args[2]));
1522 break;
1523 case INDEX_op_andc_i32:
1524 tcg_out32 (s, ANDC | SAB (args[1], args[0], args[2]));
1525 break;
1526 case INDEX_op_orc_i32:
1527 tcg_out32 (s, ORC | SAB (args[1], args[0], args[2]));
1528 break;
1529 case INDEX_op_eqv_i32:
1530 tcg_out32 (s, EQV | SAB (args[1], args[0], args[2]));
1531 break;
1532 case INDEX_op_nand_i32:
1533 tcg_out32 (s, NAND | SAB (args[1], args[0], args[2]));
1534 break;
1535 case INDEX_op_nor_i32:
1536 tcg_out32 (s, NOR | SAB (args[1], args[0], args[2]));
1537 break;
1538
1539 case INDEX_op_mul_i32:
1540 if (const_args[2]) {
1541 if (args[2] == (int16_t) args[2])
1542 tcg_out32 (s, MULLI | RT (args[0]) | RA (args[1])
1543 | (args[2] & 0xffff));
1544 else {
1545 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1546 tcg_out32 (s, MULLW | TAB (args[0], args[1], 0));
1547 }
1548 }
1549 else
1550 tcg_out32 (s, MULLW | TAB (args[0], args[1], args[2]));
1551 break;
1552
1553 case INDEX_op_div_i32:
1554 tcg_out32 (s, DIVW | TAB (args[0], args[1], args[2]));
1555 break;
1556
1557 case INDEX_op_divu_i32:
1558 tcg_out32 (s, DIVWU | TAB (args[0], args[1], args[2]));
1559 break;
1560
1561 case INDEX_op_rem_i32:
1562 tcg_out32 (s, DIVW | TAB (0, args[1], args[2]));
1563 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1564 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1565 break;
1566
1567 case INDEX_op_remu_i32:
1568 tcg_out32 (s, DIVWU | TAB (0, args[1], args[2]));
1569 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1570 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1571 break;
1572
1573 case INDEX_op_mulu2_i32:
1574 if (args[0] == args[2] || args[0] == args[3]) {
1575 tcg_out32 (s, MULLW | TAB (0, args[2], args[3]));
1576 tcg_out32 (s, MULHWU | TAB (args[1], args[2], args[3]));
1577 tcg_out_mov (s, TCG_TYPE_I32, args[0], 0);
1578 }
1579 else {
1580 tcg_out32 (s, MULLW | TAB (args[0], args[2], args[3]));
1581 tcg_out32 (s, MULHWU | TAB (args[1], args[2], args[3]));
1582 }
1583 break;
1584
1585 case INDEX_op_shl_i32:
1586 if (const_args[2]) {
1587 tcg_out32 (s, (RLWINM
1588 | RA (args[0])
1589 | RS (args[1])
1590 | SH (args[2])
1591 | MB (0)
1592 | ME (31 - args[2])
1593 )
1594 );
1595 }
1596 else
1597 tcg_out32 (s, SLW | SAB (args[1], args[0], args[2]));
1598 break;
1599 case INDEX_op_shr_i32:
1600 if (const_args[2]) {
1601 tcg_out32 (s, (RLWINM
1602 | RA (args[0])
1603 | RS (args[1])
1604 | SH (32 - args[2])
1605 | MB (args[2])
1606 | ME (31)
1607 )
1608 );
1609 }
1610 else
1611 tcg_out32 (s, SRW | SAB (args[1], args[0], args[2]));
1612 break;
1613 case INDEX_op_sar_i32:
1614 if (const_args[2])
1615 tcg_out32 (s, SRAWI | RS (args[1]) | RA (args[0]) | SH (args[2]));
1616 else
1617 tcg_out32 (s, SRAW | SAB (args[1], args[0], args[2]));
1618 break;
1619 case INDEX_op_rotl_i32:
1620 {
1621 int op = 0
1622 | RA (args[0])
1623 | RS (args[1])
1624 | MB (0)
1625 | ME (31)
1626 | (const_args[2] ? RLWINM | SH (args[2])
1627 : RLWNM | RB (args[2]))
1628 ;
1629 tcg_out32 (s, op);
1630 }
1631 break;
1632 case INDEX_op_rotr_i32:
1633 if (const_args[2]) {
1634 if (!args[2]) {
1635 tcg_out_mov (s, TCG_TYPE_I32, args[0], args[1]);
1636 }
1637 else {
1638 tcg_out32 (s, RLWINM
1639 | RA (args[0])
1640 | RS (args[1])
1641 | SH (32 - args[2])
1642 | MB (0)
1643 | ME (31)
1644 );
1645 }
1646 }
1647 else {
1648 tcg_out32 (s, SUBFIC | RT (0) | RA (args[2]) | 32);
1649 tcg_out32 (s, RLWNM
1650 | RA (args[0])
1651 | RS (args[1])
1652 | RB (0)
1653 | MB (0)
1654 | ME (31)
1655 );
1656 }
1657 break;
1658
1659 case INDEX_op_add2_i32:
1660 if (args[0] == args[3] || args[0] == args[5]) {
1661 tcg_out32 (s, ADDC | TAB (0, args[2], args[4]));
1662 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5]));
1663 tcg_out_mov (s, TCG_TYPE_I32, args[0], 0);
1664 }
1665 else {
1666 tcg_out32 (s, ADDC | TAB (args[0], args[2], args[4]));
1667 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5]));
1668 }
1669 break;
1670 case INDEX_op_sub2_i32:
1671 if (args[0] == args[3] || args[0] == args[5]) {
1672 tcg_out32 (s, SUBFC | TAB (0, args[4], args[2]));
1673 tcg_out32 (s, SUBFE | TAB (args[1], args[5], args[3]));
1674 tcg_out_mov (s, TCG_TYPE_I32, args[0], 0);
1675 }
1676 else {
1677 tcg_out32 (s, SUBFC | TAB (args[0], args[4], args[2]));
1678 tcg_out32 (s, SUBFE | TAB (args[1], args[5], args[3]));
1679 }
1680 break;
1681
1682 case INDEX_op_brcond_i32:
1683 /*
1684 args[0] = r0
1685 args[1] = r1
1686 args[2] = cond
1687 args[3] = r1 is const
1688 args[4] = label_index
1689 */
1690 tcg_out_brcond (s, args[2], args[0], args[1], const_args[1], args[3]);
1691 break;
1692 case INDEX_op_brcond2_i32:
1693 tcg_out_brcond2(s, args, const_args);
1694 break;
1695
1696 case INDEX_op_neg_i32:
1697 tcg_out32 (s, NEG | RT (args[0]) | RA (args[1]));
1698 break;
1699
1700 case INDEX_op_not_i32:
1701 tcg_out32 (s, NOR | SAB (args[1], args[0], args[1]));
1702 break;
1703
1704 case INDEX_op_qemu_ld8u:
1705 tcg_out_qemu_ld(s, args, 0);
1706 break;
1707 case INDEX_op_qemu_ld8s:
1708 tcg_out_qemu_ld(s, args, 0 | 4);
1709 break;
1710 case INDEX_op_qemu_ld16u:
1711 tcg_out_qemu_ld(s, args, 1);
1712 break;
1713 case INDEX_op_qemu_ld16s:
1714 tcg_out_qemu_ld(s, args, 1 | 4);
1715 break;
1716 case INDEX_op_qemu_ld32:
1717 tcg_out_qemu_ld(s, args, 2);
1718 break;
1719 case INDEX_op_qemu_ld64:
1720 tcg_out_qemu_ld(s, args, 3);
1721 break;
1722 case INDEX_op_qemu_st8:
1723 tcg_out_qemu_st(s, args, 0);
1724 break;
1725 case INDEX_op_qemu_st16:
1726 tcg_out_qemu_st(s, args, 1);
1727 break;
1728 case INDEX_op_qemu_st32:
1729 tcg_out_qemu_st(s, args, 2);
1730 break;
1731 case INDEX_op_qemu_st64:
1732 tcg_out_qemu_st(s, args, 3);
1733 break;
1734
1735 case INDEX_op_ext8s_i32:
1736 tcg_out32 (s, EXTSB | RS (args[1]) | RA (args[0]));
1737 break;
1738 case INDEX_op_ext8u_i32:
1739 tcg_out32 (s, RLWINM
1740 | RA (args[0])
1741 | RS (args[1])
1742 | SH (0)
1743 | MB (24)
1744 | ME (31)
1745 );
1746 break;
1747 case INDEX_op_ext16s_i32:
1748 tcg_out32 (s, EXTSH | RS (args[1]) | RA (args[0]));
1749 break;
1750 case INDEX_op_ext16u_i32:
1751 tcg_out32 (s, RLWINM
1752 | RA (args[0])
1753 | RS (args[1])
1754 | SH (0)
1755 | MB (16)
1756 | ME (31)
1757 );
1758 break;
1759
1760 case INDEX_op_setcond_i32:
1761 tcg_out_setcond (s, args[3], args[0], args[1], args[2], const_args[2]);
1762 break;
1763 case INDEX_op_setcond2_i32:
1764 tcg_out_setcond2 (s, args, const_args);
1765 break;
1766
1767 case INDEX_op_bswap16_i32:
1768 /* Stolen from gcc's builtin_bswap16 */
1769
1770 /* a1 = abcd */
1771
1772 /* r0 = (a1 << 8) & 0xff00 # 00d0 */
1773 tcg_out32 (s, RLWINM
1774 | RA (0)
1775 | RS (args[1])
1776 | SH (8)
1777 | MB (16)
1778 | ME (23)
1779 );
1780
1781 /* a0 = rotate_left (a1, 24) & 0xff # 000c */
1782 tcg_out32 (s, RLWINM
1783 | RA (args[0])
1784 | RS (args[1])
1785 | SH (24)
1786 | MB (24)
1787 | ME (31)
1788 );
1789
1790 /* a0 = a0 | r0 # 00dc */
1791 tcg_out32 (s, OR | SAB (0, args[0], args[0]));
1792 break;
1793
1794 case INDEX_op_bswap32_i32:
1795 /* Stolen from gcc's builtin_bswap32 */
1796 {
1797 int a0 = args[0];
1798
1799 /* a1 = args[1] # abcd */
1800
1801 if (a0 == args[1]) {
1802 a0 = 0;
1803 }
1804
1805 /* a0 = rotate_left (a1, 8) # bcda */
1806 tcg_out32 (s, RLWINM
1807 | RA (a0)
1808 | RS (args[1])
1809 | SH (8)
1810 | MB (0)
1811 | ME (31)
1812 );
1813
1814 /* a0 = (a0 & ~0xff000000) | ((a1 << 24) & 0xff000000) # dcda */
1815 tcg_out32 (s, RLWIMI
1816 | RA (a0)
1817 | RS (args[1])
1818 | SH (24)
1819 | MB (0)
1820 | ME (7)
1821 );
1822
1823 /* a0 = (a0 & ~0x0000ff00) | ((a1 << 24) & 0x0000ff00) # dcba */
1824 tcg_out32 (s, RLWIMI
1825 | RA (a0)
1826 | RS (args[1])
1827 | SH (24)
1828 | MB (16)
1829 | ME (23)
1830 );
1831
1832 if (!a0) {
1833 tcg_out_mov (s, TCG_TYPE_I32, args[0], a0);
1834 }
1835 }
1836 break;
1837
1838 case INDEX_op_deposit_i32:
1839 tcg_out32 (s, RLWIMI
1840 | RA (args[0])
1841 | RS (args[2])
1842 | SH (args[3])
1843 | MB (32 - args[3] - args[4])
1844 | ME (31 - args[3])
1845 );
1846 break;
1847
1848 default:
1849 tcg_dump_ops (s, stderr);
1850 tcg_abort ();
1851 }
1852 }
1853
1854 static const TCGTargetOpDef ppc_op_defs[] = {
1855 { INDEX_op_exit_tb, { } },
1856 { INDEX_op_goto_tb, { } },
1857 { INDEX_op_call, { "ri" } },
1858 { INDEX_op_jmp, { "ri" } },
1859 { INDEX_op_br, { } },
1860
1861 { INDEX_op_mov_i32, { "r", "r" } },
1862 { INDEX_op_movi_i32, { "r" } },
1863 { INDEX_op_ld8u_i32, { "r", "r" } },
1864 { INDEX_op_ld8s_i32, { "r", "r" } },
1865 { INDEX_op_ld16u_i32, { "r", "r" } },
1866 { INDEX_op_ld16s_i32, { "r", "r" } },
1867 { INDEX_op_ld_i32, { "r", "r" } },
1868 { INDEX_op_st8_i32, { "r", "r" } },
1869 { INDEX_op_st16_i32, { "r", "r" } },
1870 { INDEX_op_st_i32, { "r", "r" } },
1871
1872 { INDEX_op_add_i32, { "r", "r", "ri" } },
1873 { INDEX_op_mul_i32, { "r", "r", "ri" } },
1874 { INDEX_op_div_i32, { "r", "r", "r" } },
1875 { INDEX_op_divu_i32, { "r", "r", "r" } },
1876 { INDEX_op_rem_i32, { "r", "r", "r" } },
1877 { INDEX_op_remu_i32, { "r", "r", "r" } },
1878 { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
1879 { INDEX_op_sub_i32, { "r", "r", "ri" } },
1880 { INDEX_op_and_i32, { "r", "r", "ri" } },
1881 { INDEX_op_or_i32, { "r", "r", "ri" } },
1882 { INDEX_op_xor_i32, { "r", "r", "ri" } },
1883
1884 { INDEX_op_shl_i32, { "r", "r", "ri" } },
1885 { INDEX_op_shr_i32, { "r", "r", "ri" } },
1886 { INDEX_op_sar_i32, { "r", "r", "ri" } },
1887
1888 { INDEX_op_rotl_i32, { "r", "r", "ri" } },
1889 { INDEX_op_rotr_i32, { "r", "r", "ri" } },
1890
1891 { INDEX_op_brcond_i32, { "r", "ri" } },
1892
1893 { INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } },
1894 { INDEX_op_sub2_i32, { "r", "r", "r", "r", "r", "r" } },
1895 { INDEX_op_brcond2_i32, { "r", "r", "r", "r" } },
1896
1897 { INDEX_op_neg_i32, { "r", "r" } },
1898 { INDEX_op_not_i32, { "r", "r" } },
1899
1900 { INDEX_op_andc_i32, { "r", "r", "r" } },
1901 { INDEX_op_orc_i32, { "r", "r", "r" } },
1902 { INDEX_op_eqv_i32, { "r", "r", "r" } },
1903 { INDEX_op_nand_i32, { "r", "r", "r" } },
1904 { INDEX_op_nor_i32, { "r", "r", "r" } },
1905
1906 { INDEX_op_setcond_i32, { "r", "r", "ri" } },
1907 { INDEX_op_setcond2_i32, { "r", "r", "r", "ri", "ri" } },
1908
1909 { INDEX_op_bswap16_i32, { "r", "r" } },
1910 { INDEX_op_bswap32_i32, { "r", "r" } },
1911
1912 #if TARGET_LONG_BITS == 32
1913 { INDEX_op_qemu_ld8u, { "r", "L" } },
1914 { INDEX_op_qemu_ld8s, { "r", "L" } },
1915 { INDEX_op_qemu_ld16u, { "r", "L" } },
1916 { INDEX_op_qemu_ld16s, { "r", "L" } },
1917 { INDEX_op_qemu_ld32, { "r", "L" } },
1918 { INDEX_op_qemu_ld64, { "r", "r", "L" } },
1919
1920 { INDEX_op_qemu_st8, { "K", "K" } },
1921 { INDEX_op_qemu_st16, { "K", "K" } },
1922 { INDEX_op_qemu_st32, { "K", "K" } },
1923 { INDEX_op_qemu_st64, { "M", "M", "M" } },
1924 #else
1925 { INDEX_op_qemu_ld8u, { "r", "L", "L" } },
1926 { INDEX_op_qemu_ld8s, { "r", "L", "L" } },
1927 { INDEX_op_qemu_ld16u, { "r", "L", "L" } },
1928 { INDEX_op_qemu_ld16s, { "r", "L", "L" } },
1929 { INDEX_op_qemu_ld32, { "r", "L", "L" } },
1930 { INDEX_op_qemu_ld64, { "r", "L", "L", "L" } },
1931
1932 { INDEX_op_qemu_st8, { "K", "K", "K" } },
1933 { INDEX_op_qemu_st16, { "K", "K", "K" } },
1934 { INDEX_op_qemu_st32, { "K", "K", "K" } },
1935 { INDEX_op_qemu_st64, { "M", "M", "M", "M" } },
1936 #endif
1937
1938 { INDEX_op_ext8s_i32, { "r", "r" } },
1939 { INDEX_op_ext8u_i32, { "r", "r" } },
1940 { INDEX_op_ext16s_i32, { "r", "r" } },
1941 { INDEX_op_ext16u_i32, { "r", "r" } },
1942
1943 { INDEX_op_deposit_i32, { "r", "0", "r" } },
1944
1945 { -1 },
1946 };
1947
1948 static void tcg_target_init(TCGContext *s)
1949 {
1950 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
1951 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1952 (1 << TCG_REG_R0) |
1953 #ifdef _CALL_DARWIN
1954 (1 << TCG_REG_R2) |
1955 #endif
1956 (1 << TCG_REG_R3) |
1957 (1 << TCG_REG_R4) |
1958 (1 << TCG_REG_R5) |
1959 (1 << TCG_REG_R6) |
1960 (1 << TCG_REG_R7) |
1961 (1 << TCG_REG_R8) |
1962 (1 << TCG_REG_R9) |
1963 (1 << TCG_REG_R10) |
1964 (1 << TCG_REG_R11) |
1965 (1 << TCG_REG_R12)
1966 );
1967
1968 tcg_regset_clear(s->reserved_regs);
1969 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0);
1970 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1);
1971 #ifndef _CALL_DARWIN
1972 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2);
1973 #endif
1974 #ifdef _CALL_SYSV
1975 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13);
1976 #endif
1977
1978 tcg_add_target_add_op_defs(ppc_op_defs);
1979 }
Qemu copy for testing