2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 static uint8_t *tb_ret_addr
;
28 #define LINKAGE_AREA_SIZE 24
31 #define LINKAGE_AREA_SIZE 52
34 #define LINKAGE_AREA_SIZE 8
39 #if TARGET_PHYS_ADDR_BITS <= 32
40 #define ADDEND_OFFSET 0
42 #define ADDEND_OFFSET 4
49 #ifdef CONFIG_USE_GUEST_BASE
50 #define TCG_GUEST_BASE_REG 30
52 #define TCG_GUEST_BASE_REG 0
56 static const char * const tcg_target_reg_names
[TCG_TARGET_NB_REGS
] = {
92 static const int tcg_target_reg_alloc_order
[] = {
131 static const int tcg_target_call_iarg_regs
[] = {
142 static const int tcg_target_call_oarg_regs
[2] = {
147 static const int tcg_target_callee_save_regs
[] = {
168 /* TCG_REG_R27, */ /* currently used for the global env, so no
176 static uint32_t reloc_pc24_val (void *pc
, tcg_target_long target
)
178 tcg_target_long disp
;
180 disp
= target
- (tcg_target_long
) pc
;
181 if ((disp
<< 6) >> 6 != disp
)
184 return disp
& 0x3fffffc;
187 static void reloc_pc24 (void *pc
, tcg_target_long target
)
189 *(uint32_t *) pc
= (*(uint32_t *) pc
& ~0x3fffffc)
190 | reloc_pc24_val (pc
, target
);
193 static uint16_t reloc_pc14_val (void *pc
, tcg_target_long target
)
195 tcg_target_long disp
;
197 disp
= target
- (tcg_target_long
) pc
;
198 if (disp
!= (int16_t) disp
)
201 return disp
& 0xfffc;
204 static void reloc_pc14 (void *pc
, tcg_target_long target
)
206 *(uint32_t *) pc
= (*(uint32_t *) pc
& ~0xfffc)
207 | reloc_pc14_val (pc
, target
);
210 static void patch_reloc(uint8_t *code_ptr
, int type
,
211 tcg_target_long value
, tcg_target_long addend
)
216 reloc_pc14 (code_ptr
, value
);
219 reloc_pc24 (code_ptr
, value
);
226 /* maximum number of register used for input function arguments */
227 static int tcg_target_get_call_iarg_regs_count(int flags
)
229 return ARRAY_SIZE (tcg_target_call_iarg_regs
);
232 /* parse target specific constraints */
233 static int target_parse_constraint(TCGArgConstraint
*ct
, const char **pct_str
)
239 case 'A': case 'B': case 'C': case 'D':
240 ct
->ct
|= TCG_CT_REG
;
241 tcg_regset_set_reg(ct
->u
.regs
, 3 + ct_str
[0] - 'A');
244 ct
->ct
|= TCG_CT_REG
;
245 tcg_regset_set32(ct
->u
.regs
, 0, 0xffffffff);
247 #ifdef CONFIG_SOFTMMU
248 case 'L': /* qemu_ld constraint */
249 ct
->ct
|= TCG_CT_REG
;
250 tcg_regset_set32(ct
->u
.regs
, 0, 0xffffffff);
251 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R3
);
252 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R4
);
254 case 'K': /* qemu_st[8..32] constraint */
255 ct
->ct
|= TCG_CT_REG
;
256 tcg_regset_set32(ct
->u
.regs
, 0, 0xffffffff);
257 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R3
);
258 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R4
);
259 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R5
);
260 #if TARGET_LONG_BITS == 64
261 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R6
);
264 case 'M': /* qemu_st64 constraint */
265 ct
->ct
|= TCG_CT_REG
;
266 tcg_regset_set32(ct
->u
.regs
, 0, 0xffffffff);
267 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R3
);
268 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R4
);
269 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R5
);
270 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R6
);
271 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R7
);
276 ct
->ct
|= TCG_CT_REG
;
277 tcg_regset_set32(ct
->u
.regs
, 0, 0xffffffff);
280 ct
->ct
|= TCG_CT_REG
;
281 tcg_regset_set32(ct
->u
.regs
, 0, 0xffffffff);
282 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R3
);
293 /* test if a constant matches the constraint */
294 static int tcg_target_const_match(tcg_target_long val
,
295 const TCGArgConstraint
*arg_ct
)
300 if (ct
& TCG_CT_CONST
)
305 #define OPCD(opc) ((opc)<<26)
306 #define XO31(opc) (OPCD(31)|((opc)<<1))
307 #define XO19(opc) (OPCD(19)|((opc)<<1))
319 #define ADDI OPCD(14)
320 #define ADDIS OPCD(15)
322 #define ORIS OPCD(25)
323 #define XORI OPCD(26)
324 #define XORIS OPCD(27)
325 #define ANDI OPCD(28)
326 #define ANDIS OPCD(29)
327 #define MULLI OPCD( 7)
328 #define CMPLI OPCD(10)
329 #define CMPI OPCD(11)
331 #define LWZU OPCD(33)
332 #define STWU OPCD(37)
334 #define RLWINM OPCD(21)
336 #define BCLR XO19( 16)
337 #define BCCTR XO19(528)
338 #define CRAND XO19(257)
339 #define CRANDC XO19(129)
340 #define CRNAND XO19(225)
341 #define CROR XO19(449)
343 #define EXTSB XO31(954)
344 #define EXTSH XO31(922)
345 #define ADD XO31(266)
346 #define ADDE XO31(138)
347 #define ADDC XO31( 10)
348 #define AND XO31( 28)
349 #define SUBF XO31( 40)
350 #define SUBFC XO31( 8)
351 #define SUBFE XO31(136)
353 #define XOR XO31(316)
354 #define MULLW XO31(235)
355 #define MULHWU XO31( 11)
356 #define DIVW XO31(491)
357 #define DIVWU XO31(459)
359 #define CMPL XO31( 32)
360 #define LHBRX XO31(790)
361 #define LWBRX XO31(534)
362 #define STHBRX XO31(918)
363 #define STWBRX XO31(662)
364 #define MFSPR XO31(339)
365 #define MTSPR XO31(467)
366 #define SRAWI XO31(824)
367 #define NEG XO31(104)
369 #define LBZX XO31( 87)
370 #define LHZX XO31(279)
371 #define LHAX XO31(343)
372 #define LWZX XO31( 23)
373 #define STBX XO31(215)
374 #define STHX XO31(407)
375 #define STWX XO31(151)
377 #define SPR(a,b) ((((a)<<5)|(b))<<11)
379 #define CTR SPR(9, 0)
381 #define SLW XO31( 24)
382 #define SRW XO31(536)
383 #define SRAW XO31(792)
386 #define TRAP (TW | TO (31))
388 #define RT(r) ((r)<<21)
389 #define RS(r) ((r)<<21)
390 #define RA(r) ((r)<<16)
391 #define RB(r) ((r)<<11)
392 #define TO(t) ((t)<<21)
393 #define SH(s) ((s)<<11)
394 #define MB(b) ((b)<<6)
395 #define ME(e) ((e)<<1)
396 #define BO(o) ((o)<<21)
400 #define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
401 #define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
403 #define BF(n) ((n)<<23)
404 #define BI(n, c) (((c)+((n)*4))<<16)
405 #define BT(n, c) (((c)+((n)*4))<<21)
406 #define BA(n, c) (((c)+((n)*4))<<16)
407 #define BB(n, c) (((c)+((n)*4))<<11)
409 #define BO_COND_TRUE BO (12)
410 #define BO_COND_FALSE BO (4)
411 #define BO_ALWAYS BO (20)
420 static const uint32_t tcg_to_bc
[10] = {
421 [TCG_COND_EQ
] = BC
| BI (7, CR_EQ
) | BO_COND_TRUE
,
422 [TCG_COND_NE
] = BC
| BI (7, CR_EQ
) | BO_COND_FALSE
,
423 [TCG_COND_LT
] = BC
| BI (7, CR_LT
) | BO_COND_TRUE
,
424 [TCG_COND_GE
] = BC
| BI (7, CR_LT
) | BO_COND_FALSE
,
425 [TCG_COND_LE
] = BC
| BI (7, CR_GT
) | BO_COND_FALSE
,
426 [TCG_COND_GT
] = BC
| BI (7, CR_GT
) | BO_COND_TRUE
,
427 [TCG_COND_LTU
] = BC
| BI (7, CR_LT
) | BO_COND_TRUE
,
428 [TCG_COND_GEU
] = BC
| BI (7, CR_LT
) | BO_COND_FALSE
,
429 [TCG_COND_LEU
] = BC
| BI (7, CR_GT
) | BO_COND_FALSE
,
430 [TCG_COND_GTU
] = BC
| BI (7, CR_GT
) | BO_COND_TRUE
,
433 static void tcg_out_mov(TCGContext
*s
, int ret
, int arg
)
435 tcg_out32 (s
, OR
| SAB (arg
, ret
, arg
));
438 static void tcg_out_movi(TCGContext
*s
, TCGType type
,
439 int ret
, tcg_target_long arg
)
441 if (arg
== (int16_t) arg
)
442 tcg_out32 (s
, ADDI
| RT (ret
) | RA (0) | (arg
& 0xffff));
444 tcg_out32 (s
, ADDIS
| RT (ret
) | RA (0) | ((arg
>> 16) & 0xffff));
446 tcg_out32 (s
, ORI
| RS (ret
) | RA (ret
) | (arg
& 0xffff));
450 static void tcg_out_ldst (TCGContext
*s
, int ret
, int addr
,
451 int offset
, int op1
, int op2
)
453 if (offset
== (int16_t) offset
)
454 tcg_out32 (s
, op1
| RT (ret
) | RA (addr
) | (offset
& 0xffff));
456 tcg_out_movi (s
, TCG_TYPE_I32
, 0, offset
);
457 tcg_out32 (s
, op2
| RT (ret
) | RA (addr
) | RB (0));
461 static void tcg_out_b (TCGContext
*s
, int mask
, tcg_target_long target
)
463 tcg_target_long disp
;
465 disp
= target
- (tcg_target_long
) s
->code_ptr
;
466 if ((disp
<< 6) >> 6 == disp
)
467 tcg_out32 (s
, B
| (disp
& 0x3fffffc) | mask
);
469 tcg_out_movi (s
, TCG_TYPE_I32
, 0, (tcg_target_long
) target
);
470 tcg_out32 (s
, MTSPR
| RS (0) | CTR
);
471 tcg_out32 (s
, BCCTR
| BO_ALWAYS
| mask
);
476 static void tcg_out_call (TCGContext
*s
, tcg_target_long arg
, int const_arg
)
482 tcg_out_movi (s
, TCG_TYPE_I32
, reg
, arg
);
486 tcg_out32 (s
, LWZ
| RT (0) | RA (reg
));
487 tcg_out32 (s
, MTSPR
| RA (0) | CTR
);
488 tcg_out32 (s
, LWZ
| RT (2) | RA (reg
) | 4);
489 tcg_out32 (s
, BCCTR
| BO_ALWAYS
| LK
);
493 #if defined(CONFIG_SOFTMMU)
495 #include "../../softmmu_defs.h"
497 static void *qemu_ld_helpers
[4] = {
504 static void *qemu_st_helpers
[4] = {
512 static void tcg_out_qemu_ld (TCGContext
*s
, const TCGArg
*args
, int opc
)
514 int addr_reg
, data_reg
, data_reg2
, r0
, r1
, rbase
, mem_index
, s_bits
, bswap
;
515 #ifdef CONFIG_SOFTMMU
517 void *label1_ptr
, *label2_ptr
;
519 #if TARGET_LONG_BITS == 64
529 #if TARGET_LONG_BITS == 64
535 #ifdef CONFIG_SOFTMMU
541 tcg_out32 (s
, (RLWINM
544 | SH (32 - (TARGET_PAGE_BITS
- CPU_TLB_ENTRY_BITS
))
545 | MB (32 - (CPU_TLB_BITS
+ CPU_TLB_ENTRY_BITS
))
546 | ME (31 - CPU_TLB_ENTRY_BITS
)
549 tcg_out32 (s
, ADD
| RT (r0
) | RA (r0
) | RB (TCG_AREG0
));
553 | offsetof (CPUState
, tlb_table
[mem_index
][0].addr_read
)
556 tcg_out32 (s
, (RLWINM
560 | MB ((32 - s_bits
) & 31)
561 | ME (31 - TARGET_PAGE_BITS
)
565 tcg_out32 (s
, CMP
| BF (7) | RA (r2
) | RB (r1
));
566 #if TARGET_LONG_BITS == 64
567 tcg_out32 (s
, LWZ
| RT (r1
) | RA (r0
) | 4);
568 tcg_out32 (s
, CMP
| BF (6) | RA (addr_reg2
) | RB (r1
));
569 tcg_out32 (s
, CRAND
| BT (7, CR_EQ
) | BA (6, CR_EQ
) | BB (7, CR_EQ
));
572 label1_ptr
= s
->code_ptr
;
574 tcg_out32 (s
, BC
| BI (7, CR_EQ
) | BO_COND_TRUE
);
578 #if TARGET_LONG_BITS == 32
579 tcg_out_mov (s
, 3, addr_reg
);
580 tcg_out_movi (s
, TCG_TYPE_I32
, 4, mem_index
);
582 tcg_out_mov (s
, 3, addr_reg2
);
583 tcg_out_mov (s
, 4, addr_reg
);
584 tcg_out_movi (s
, TCG_TYPE_I32
, 5, mem_index
);
588 tcg_out_call (s
, (tcg_target_long
) qemu_ld_helpers
[s_bits
], 1);
590 tcg_out_b (s
, LK
, (tcg_target_long
) qemu_ld_helpers
[s_bits
]);
594 tcg_out32 (s
, EXTSB
| RA (data_reg
) | RS (3));
597 tcg_out32 (s
, EXTSH
| RA (data_reg
) | RS (3));
603 tcg_out_mov (s
, data_reg
, 3);
607 if (data_reg2
== 4) {
608 tcg_out_mov (s
, 0, 4);
609 tcg_out_mov (s
, 4, 3);
610 tcg_out_mov (s
, 3, 0);
613 tcg_out_mov (s
, data_reg2
, 3);
614 tcg_out_mov (s
, 3, 4);
618 if (data_reg
!= 4) tcg_out_mov (s
, data_reg
, 4);
619 if (data_reg2
!= 3) tcg_out_mov (s
, data_reg2
, 3);
623 label2_ptr
= s
->code_ptr
;
626 /* label1: fast path */
628 reloc_pc14 (label1_ptr
, (tcg_target_long
) s
->code_ptr
);
631 /* r0 now contains &env->tlb_table[mem_index][index].addr_read */
635 | (ADDEND_OFFSET
+ offsetof (CPUTLBEntry
, addend
)
636 - offsetof (CPUTLBEntry
, addr_read
))
638 /* r0 = env->tlb_table[mem_index][index].addend */
639 tcg_out32 (s
, ADD
| RT (r0
) | RA (r0
) | RB (addr_reg
));
640 /* r0 = env->tlb_table[mem_index][index].addend + addr */
642 #else /* !CONFIG_SOFTMMU */
645 rbase
= GUEST_BASE
? TCG_GUEST_BASE_REG
: 0;
648 #ifdef TARGET_WORDS_BIGENDIAN
657 tcg_out32 (s
, LBZX
| TAB (data_reg
, rbase
, r0
));
660 tcg_out32 (s
, LBZX
| TAB (data_reg
, rbase
, r0
));
661 tcg_out32 (s
, EXTSB
| RA (data_reg
) | RS (data_reg
));
665 tcg_out32 (s
, LHBRX
| TAB (data_reg
, rbase
, r0
));
667 tcg_out32 (s
, LHZX
| TAB (data_reg
, rbase
, r0
));
671 tcg_out32 (s
, LHBRX
| TAB (data_reg
, rbase
, r0
));
672 tcg_out32 (s
, EXTSH
| RA (data_reg
) | RS (data_reg
));
674 else tcg_out32 (s
, LHAX
| TAB (data_reg
, rbase
, r0
));
678 tcg_out32 (s
, LWBRX
| TAB (data_reg
, rbase
, r0
));
680 tcg_out32 (s
, LWZX
| TAB (data_reg
, rbase
, r0
));
684 tcg_out32 (s
, ADDI
| RT (r1
) | RA (r0
) | 4);
685 tcg_out32 (s
, LWBRX
| TAB (data_reg
, rbase
, r0
));
686 tcg_out32 (s
, LWBRX
| TAB (data_reg2
, rbase
, r1
));
689 #ifdef CONFIG_USE_GUEST_BASE
690 tcg_out32 (s
, ADDI
| RT (r1
) | RA (r0
) | 4);
691 tcg_out32 (s
, LWZX
| TAB (data_reg2
, rbase
, r0
));
692 tcg_out32 (s
, LWZX
| TAB (data_reg
, rbase
, r1
));
694 if (r0
== data_reg2
) {
695 tcg_out32 (s
, LWZ
| RT (0) | RA (r0
));
696 tcg_out32 (s
, LWZ
| RT (data_reg
) | RA (r0
) | 4);
697 tcg_out_mov (s
, data_reg2
, 0);
700 tcg_out32 (s
, LWZ
| RT (data_reg2
) | RA (r0
));
701 tcg_out32 (s
, LWZ
| RT (data_reg
) | RA (r0
) | 4);
708 #ifdef CONFIG_SOFTMMU
709 reloc_pc24 (label2_ptr
, (tcg_target_long
) s
->code_ptr
);
713 static void tcg_out_qemu_st (TCGContext
*s
, const TCGArg
*args
, int opc
)
715 int addr_reg
, r0
, r1
, data_reg
, data_reg2
, mem_index
, bswap
, rbase
;
716 #ifdef CONFIG_SOFTMMU
718 void *label1_ptr
, *label2_ptr
;
720 #if TARGET_LONG_BITS == 64
730 #if TARGET_LONG_BITS == 64
735 #ifdef CONFIG_SOFTMMU
741 tcg_out32 (s
, (RLWINM
744 | SH (32 - (TARGET_PAGE_BITS
- CPU_TLB_ENTRY_BITS
))
745 | MB (32 - (CPU_TLB_ENTRY_BITS
+ CPU_TLB_BITS
))
746 | ME (31 - CPU_TLB_ENTRY_BITS
)
749 tcg_out32 (s
, ADD
| RT (r0
) | RA (r0
) | RB (TCG_AREG0
));
753 | offsetof (CPUState
, tlb_table
[mem_index
][0].addr_write
)
756 tcg_out32 (s
, (RLWINM
760 | MB ((32 - opc
) & 31)
761 | ME (31 - TARGET_PAGE_BITS
)
765 tcg_out32 (s
, CMP
| (7 << 23) | RA (r2
) | RB (r1
));
766 #if TARGET_LONG_BITS == 64
767 tcg_out32 (s
, LWZ
| RT (r1
) | RA (r0
) | 4);
768 tcg_out32 (s
, CMP
| BF (6) | RA (addr_reg2
) | RB (r1
));
769 tcg_out32 (s
, CRAND
| BT (7, CR_EQ
) | BA (6, CR_EQ
) | BB (7, CR_EQ
));
772 label1_ptr
= s
->code_ptr
;
774 tcg_out32 (s
, BC
| BI (7, CR_EQ
) | BO_COND_TRUE
);
778 #if TARGET_LONG_BITS == 32
779 tcg_out_mov (s
, 3, addr_reg
);
782 tcg_out_mov (s
, 3, addr_reg2
);
783 tcg_out_mov (s
, 4, addr_reg
);
784 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
793 tcg_out32 (s
, (RLWINM
801 tcg_out32 (s
, (RLWINM
809 tcg_out_mov (s
, ir
, data_reg
);
812 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
815 tcg_out_mov (s
, ir
++, data_reg2
);
816 tcg_out_mov (s
, ir
, data_reg
);
821 tcg_out_movi (s
, TCG_TYPE_I32
, ir
, mem_index
);
823 tcg_out_call (s
, (tcg_target_long
) qemu_st_helpers
[opc
], 1);
825 tcg_out_b (s
, LK
, (tcg_target_long
) qemu_st_helpers
[opc
]);
827 label2_ptr
= s
->code_ptr
;
830 /* label1: fast path */
832 reloc_pc14 (label1_ptr
, (tcg_target_long
) s
->code_ptr
);
838 | (ADDEND_OFFSET
+ offsetof (CPUTLBEntry
, addend
)
839 - offsetof (CPUTLBEntry
, addr_write
))
841 /* r0 = env->tlb_table[mem_index][index].addend */
842 tcg_out32 (s
, ADD
| RT (r0
) | RA (r0
) | RB (addr_reg
));
843 /* r0 = env->tlb_table[mem_index][index].addend + addr */
845 #else /* !CONFIG_SOFTMMU */
848 rbase
= GUEST_BASE
? rbase
: 0;
851 #ifdef TARGET_WORDS_BIGENDIAN
858 tcg_out32 (s
, STBX
| SAB (data_reg
, rbase
, r0
));
862 tcg_out32 (s
, STHBRX
| SAB (data_reg
, rbase
, r0
));
864 tcg_out32 (s
, STHX
| SAB (data_reg
, rbase
, r0
));
868 tcg_out32 (s
, STWBRX
| SAB (data_reg
, rbase
, r0
));
870 tcg_out32 (s
, STWX
| SAB (data_reg
, rbase
, r0
));
874 tcg_out32 (s
, ADDI
| RT (r1
) | RA (r0
) | 4);
875 tcg_out32 (s
, STWBRX
| SAB (data_reg
, rbase
, r0
));
876 tcg_out32 (s
, STWBRX
| SAB (data_reg2
, rbase
, r1
));
879 #ifdef CONFIG_USE_GUEST_BASE
880 tcg_out32 (s
, STWX
| SAB (data_reg2
, rbase
, r0
));
881 tcg_out32 (s
, ADDI
| RT (r1
) | RA (r0
) | 4);
882 tcg_out32 (s
, STWX
| SAB (data_reg
, rbase
, r1
));
884 tcg_out32 (s
, STW
| RS (data_reg2
) | RA (r0
));
885 tcg_out32 (s
, STW
| RS (data_reg
) | RA (r0
) | 4);
891 #ifdef CONFIG_SOFTMMU
892 reloc_pc24 (label2_ptr
, (tcg_target_long
) s
->code_ptr
);
896 void tcg_target_qemu_prologue (TCGContext
*s
)
902 + TCG_STATIC_CALL_ARGS_SIZE
903 + ARRAY_SIZE (tcg_target_callee_save_regs
) * 4
905 frame_size
= (frame_size
+ 15) & ~15;
911 /* First emit adhoc function descriptor */
912 addr
= (uint32_t) s
->code_ptr
+ 12;
913 tcg_out32 (s
, addr
); /* entry point */
914 s
->code_ptr
+= 8; /* skip TOC and environment pointer */
917 tcg_out32 (s
, MFSPR
| RT (0) | LR
);
918 tcg_out32 (s
, STWU
| RS (1) | RA (1) | (-frame_size
& 0xffff));
919 for (i
= 0; i
< ARRAY_SIZE (tcg_target_callee_save_regs
); ++i
)
921 | RS (tcg_target_callee_save_regs
[i
])
923 | (i
* 4 + LINKAGE_AREA_SIZE
+ TCG_STATIC_CALL_ARGS_SIZE
)
926 tcg_out32 (s
, STW
| RS (0) | RA (1) | (frame_size
+ LR_OFFSET
));
928 #ifdef CONFIG_USE_GUEST_BASE
929 tcg_out_movi (s
, TCG_TYPE_I32
, TCG_GUEST_BASE_REG
, GUEST_BASE
);
932 tcg_out32 (s
, MTSPR
| RS (3) | CTR
);
933 tcg_out32 (s
, BCCTR
| BO_ALWAYS
);
934 tb_ret_addr
= s
->code_ptr
;
936 for (i
= 0; i
< ARRAY_SIZE (tcg_target_callee_save_regs
); ++i
)
938 | RT (tcg_target_callee_save_regs
[i
])
940 | (i
* 4 + LINKAGE_AREA_SIZE
+ TCG_STATIC_CALL_ARGS_SIZE
)
943 tcg_out32 (s
, LWZ
| RT (0) | RA (1) | (frame_size
+ LR_OFFSET
));
944 tcg_out32 (s
, MTSPR
| RS (0) | LR
);
945 tcg_out32 (s
, ADDI
| RT (1) | RA (1) | frame_size
);
946 tcg_out32 (s
, BCLR
| BO_ALWAYS
);
949 static void tcg_out_ld (TCGContext
*s
, TCGType type
, int ret
, int arg1
,
950 tcg_target_long arg2
)
952 tcg_out_ldst (s
, ret
, arg1
, arg2
, LWZ
, LWZX
);
955 static void tcg_out_st (TCGContext
*s
, TCGType type
, int arg
, int arg1
,
956 tcg_target_long arg2
)
958 tcg_out_ldst (s
, arg
, arg1
, arg2
, STW
, STWX
);
961 static void ppc_addi (TCGContext
*s
, int rt
, int ra
, tcg_target_long si
)
966 if (si
== (int16_t) si
)
967 tcg_out32 (s
, ADDI
| RT (rt
) | RA (ra
) | (si
& 0xffff));
969 uint16_t h
= ((si
>> 16) & 0xffff) + ((uint16_t) si
>> 15);
970 tcg_out32 (s
, ADDIS
| RT (rt
) | RA (ra
) | h
);
971 tcg_out32 (s
, ADDI
| RT (rt
) | RA (rt
) | (si
& 0xffff));
975 static void tcg_out_addi(TCGContext
*s
, int reg
, tcg_target_long val
)
977 ppc_addi (s
, reg
, reg
, val
);
980 static void tcg_out_cmp (TCGContext
*s
, int cond
, TCGArg arg1
, TCGArg arg2
,
981 int const_arg2
, int cr
)
990 if ((int16_t) arg2
== arg2
) {
995 else if ((uint16_t) arg2
== arg2
) {
1010 if ((int16_t) arg2
== arg2
) {
1025 if ((uint16_t) arg2
== arg2
) {
1041 tcg_out32 (s
, op
| RA (arg1
) | (arg2
& 0xffff));
1044 tcg_out_movi (s
, TCG_TYPE_I32
, 0, arg2
);
1045 tcg_out32 (s
, op
| RA (arg1
) | RB (0));
1048 tcg_out32 (s
, op
| RA (arg1
) | RB (arg2
));
1053 static void tcg_out_bc (TCGContext
*s
, int bc
, int label_index
)
1055 TCGLabel
*l
= &s
->labels
[label_index
];
1058 tcg_out32 (s
, bc
| reloc_pc14_val (s
->code_ptr
, l
->u
.value
));
1060 uint16_t val
= *(uint16_t *) &s
->code_ptr
[2];
1062 /* Thanks to Andrzej Zaborowski */
1063 tcg_out32 (s
, bc
| (val
& 0xfffc));
1064 tcg_out_reloc (s
, s
->code_ptr
- 4, R_PPC_REL14
, label_index
, 0);
1068 static void tcg_out_brcond (TCGContext
*s
, int cond
,
1069 TCGArg arg1
, TCGArg arg2
, int const_arg2
,
1072 tcg_out_cmp (s
, cond
, arg1
, arg2
, const_arg2
, 7);
1073 tcg_out_bc (s
, tcg_to_bc
[cond
], label_index
);
1076 /* XXX: we implement it at the target level to avoid having to
1077 handle cross basic blocks temporaries */
1078 static void tcg_out_brcond2 (TCGContext
*s
, const TCGArg
*args
,
1079 const int *const_args
)
1081 int cond
= args
[4], label_index
= args
[5], op
;
1082 struct { int bit1
; int bit2
; int cond2
; } bits
[] = {
1083 [TCG_COND_LT
] = { CR_LT
, CR_LT
, TCG_COND_LT
},
1084 [TCG_COND_LE
] = { CR_LT
, CR_GT
, TCG_COND_LT
},
1085 [TCG_COND_GT
] = { CR_GT
, CR_GT
, TCG_COND_GT
},
1086 [TCG_COND_GE
] = { CR_GT
, CR_LT
, TCG_COND_GT
},
1087 [TCG_COND_LTU
] = { CR_LT
, CR_LT
, TCG_COND_LTU
},
1088 [TCG_COND_LEU
] = { CR_LT
, CR_GT
, TCG_COND_LTU
},
1089 [TCG_COND_GTU
] = { CR_GT
, CR_GT
, TCG_COND_GTU
},
1090 [TCG_COND_GEU
] = { CR_GT
, CR_LT
, TCG_COND_GTU
},
1091 }, *b
= &bits
[cond
];
1096 op
= (cond
== TCG_COND_EQ
) ? CRAND
: CRNAND
;
1097 tcg_out_cmp (s
, cond
, args
[0], args
[2], const_args
[2], 6);
1098 tcg_out_cmp (s
, cond
, args
[1], args
[3], const_args
[3], 7);
1099 tcg_out32 (s
, op
| BT (7, CR_EQ
) | BA (6, CR_EQ
) | BB (7, CR_EQ
));
1109 op
= (b
->bit1
!= b
->bit2
) ? CRANDC
: CRAND
;
1110 tcg_out_cmp (s
, b
->cond2
, args
[1], args
[3], const_args
[3], 5);
1111 tcg_out_cmp (s
, TCG_COND_EQ
, args
[1], args
[3], const_args
[3], 6);
1112 tcg_out_cmp (s
, cond
, args
[0], args
[2], const_args
[2], 7);
1113 tcg_out32 (s
, op
| BT (7, CR_EQ
) | BA (6, CR_EQ
) | BB (7, b
->bit2
));
1114 tcg_out32 (s
, CROR
| BT (7, CR_EQ
) | BA (5, b
->bit1
) | BB (7, CR_EQ
));
1120 tcg_out_bc (s
, (BC
| BI (7, CR_EQ
) | BO_COND_TRUE
), label_index
);
1123 void ppc_tb_set_jmp_target (unsigned long jmp_addr
, unsigned long addr
)
1126 long disp
= addr
- jmp_addr
;
1127 unsigned long patch_size
;
1129 ptr
= (uint32_t *)jmp_addr
;
1131 if ((disp
<< 6) >> 6 != disp
) {
1132 ptr
[0] = 0x3c000000 | (addr
>> 16); /* lis 0,addr@ha */
1133 ptr
[1] = 0x60000000 | (addr
& 0xffff); /* la 0,addr@l(0) */
1134 ptr
[2] = 0x7c0903a6; /* mtctr 0 */
1135 ptr
[3] = 0x4e800420; /* brctr */
1138 /* patch the branch destination */
1140 *ptr
= 0x48000000 | (disp
& 0x03fffffc); /* b disp */
1143 ptr
[0] = 0x60000000; /* nop */
1144 ptr
[1] = 0x60000000;
1145 ptr
[2] = 0x60000000;
1146 ptr
[3] = 0x60000000;
1151 flush_icache_range(jmp_addr
, jmp_addr
+ patch_size
);
1154 static void tcg_out_op(TCGContext
*s
, int opc
, const TCGArg
*args
,
1155 const int *const_args
)
1158 case INDEX_op_exit_tb
:
1159 tcg_out_movi (s
, TCG_TYPE_I32
, TCG_REG_R3
, args
[0]);
1160 tcg_out_b (s
, 0, (tcg_target_long
) tb_ret_addr
);
1162 case INDEX_op_goto_tb
:
1163 if (s
->tb_jmp_offset
) {
1164 /* direct jump method */
1166 s
->tb_jmp_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
1172 s
->tb_next_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
1176 TCGLabel
*l
= &s
->labels
[args
[0]];
1179 tcg_out_b (s
, 0, l
->u
.value
);
1182 uint32_t val
= *(uint32_t *) s
->code_ptr
;
1184 /* Thanks to Andrzej Zaborowski */
1185 tcg_out32 (s
, B
| (val
& 0x3fffffc));
1186 tcg_out_reloc (s
, s
->code_ptr
- 4, R_PPC_REL24
, args
[0], 0);
1192 tcg_out_call (s
, args
[0], const_args
[0]);
1194 if (const_args
[0]) {
1195 tcg_out_b (s
, LK
, args
[0]);
1198 tcg_out32 (s
, MTSPR
| RS (args
[0]) | LR
);
1199 tcg_out32 (s
, BCLR
| BO_ALWAYS
| LK
);
1204 if (const_args
[0]) {
1205 tcg_out_b (s
, 0, args
[0]);
1208 tcg_out32 (s
, MTSPR
| RS (args
[0]) | CTR
);
1209 tcg_out32 (s
, BCCTR
| BO_ALWAYS
);
1212 case INDEX_op_movi_i32
:
1213 tcg_out_movi(s
, TCG_TYPE_I32
, args
[0], args
[1]);
1215 case INDEX_op_ld8u_i32
:
1216 tcg_out_ldst (s
, args
[0], args
[1], args
[2], LBZ
, LBZX
);
1218 case INDEX_op_ld8s_i32
:
1219 tcg_out_ldst (s
, args
[0], args
[1], args
[2], LBZ
, LBZX
);
1220 tcg_out32 (s
, EXTSB
| RS (args
[0]) | RA (args
[0]));
1222 case INDEX_op_ld16u_i32
:
1223 tcg_out_ldst (s
, args
[0], args
[1], args
[2], LHZ
, LHZX
);
1225 case INDEX_op_ld16s_i32
:
1226 tcg_out_ldst (s
, args
[0], args
[1], args
[2], LHA
, LHAX
);
1228 case INDEX_op_ld_i32
:
1229 tcg_out_ldst (s
, args
[0], args
[1], args
[2], LWZ
, LWZX
);
1231 case INDEX_op_st8_i32
:
1232 tcg_out_ldst (s
, args
[0], args
[1], args
[2], STB
, STBX
);
1234 case INDEX_op_st16_i32
:
1235 tcg_out_ldst (s
, args
[0], args
[1], args
[2], STH
, STHX
);
1237 case INDEX_op_st_i32
:
1238 tcg_out_ldst (s
, args
[0], args
[1], args
[2], STW
, STWX
);
1241 case INDEX_op_add_i32
:
1243 ppc_addi (s
, args
[0], args
[1], args
[2]);
1245 tcg_out32 (s
, ADD
| TAB (args
[0], args
[1], args
[2]));
1247 case INDEX_op_sub_i32
:
1249 ppc_addi (s
, args
[0], args
[1], -args
[2]);
1251 tcg_out32 (s
, SUBF
| TAB (args
[0], args
[2], args
[1]));
1254 case INDEX_op_and_i32
:
1255 if (const_args
[2]) {
1256 if ((args
[2] & 0xffff) == args
[2])
1257 tcg_out32 (s
, ANDI
| RS (args
[1]) | RA (args
[0]) | args
[2]);
1258 else if ((args
[2] & 0xffff0000) == args
[2])
1259 tcg_out32 (s
, ANDIS
| RS (args
[1]) | RA (args
[0])
1260 | ((args
[2] >> 16) & 0xffff));
1262 tcg_out_movi (s
, TCG_TYPE_I32
, 0, args
[2]);
1263 tcg_out32 (s
, AND
| SAB (args
[1], args
[0], 0));
1267 tcg_out32 (s
, AND
| SAB (args
[1], args
[0], args
[2]));
1269 case INDEX_op_or_i32
:
1270 if (const_args
[2]) {
1271 if (args
[2] & 0xffff) {
1272 tcg_out32 (s
, ORI
| RS (args
[1]) | RA (args
[0])
1273 | (args
[2] & 0xffff));
1275 tcg_out32 (s
, ORIS
| RS (args
[0]) | RA (args
[0])
1276 | ((args
[2] >> 16) & 0xffff));
1279 tcg_out32 (s
, ORIS
| RS (args
[1]) | RA (args
[0])
1280 | ((args
[2] >> 16) & 0xffff));
1284 tcg_out32 (s
, OR
| SAB (args
[1], args
[0], args
[2]));
1286 case INDEX_op_xor_i32
:
1287 if (const_args
[2]) {
1288 if ((args
[2] & 0xffff) == args
[2])
1289 tcg_out32 (s
, XORI
| RS (args
[1]) | RA (args
[0])
1290 | (args
[2] & 0xffff));
1291 else if ((args
[2] & 0xffff0000) == args
[2])
1292 tcg_out32 (s
, XORIS
| RS (args
[1]) | RA (args
[0])
1293 | ((args
[2] >> 16) & 0xffff));
1295 tcg_out_movi (s
, TCG_TYPE_I32
, 0, args
[2]);
1296 tcg_out32 (s
, XOR
| SAB (args
[1], args
[0], 0));
1300 tcg_out32 (s
, XOR
| SAB (args
[1], args
[0], args
[2]));
1303 case INDEX_op_mul_i32
:
1304 if (const_args
[2]) {
1305 if (args
[2] == (int16_t) args
[2])
1306 tcg_out32 (s
, MULLI
| RT (args
[0]) | RA (args
[1])
1307 | (args
[2] & 0xffff));
1309 tcg_out_movi (s
, TCG_TYPE_I32
, 0, args
[2]);
1310 tcg_out32 (s
, MULLW
| TAB (args
[0], args
[1], 0));
1314 tcg_out32 (s
, MULLW
| TAB (args
[0], args
[1], args
[2]));
1317 case INDEX_op_div_i32
:
1318 tcg_out32 (s
, DIVW
| TAB (args
[0], args
[1], args
[2]));
1321 case INDEX_op_divu_i32
:
1322 tcg_out32 (s
, DIVWU
| TAB (args
[0], args
[1], args
[2]));
1325 case INDEX_op_rem_i32
:
1326 tcg_out32 (s
, DIVW
| TAB (0, args
[1], args
[2]));
1327 tcg_out32 (s
, MULLW
| TAB (0, 0, args
[2]));
1328 tcg_out32 (s
, SUBF
| TAB (args
[0], 0, args
[1]));
1331 case INDEX_op_remu_i32
:
1332 tcg_out32 (s
, DIVWU
| TAB (0, args
[1], args
[2]));
1333 tcg_out32 (s
, MULLW
| TAB (0, 0, args
[2]));
1334 tcg_out32 (s
, SUBF
| TAB (args
[0], 0, args
[1]));
1337 case INDEX_op_mulu2_i32
:
1338 if (args
[0] == args
[2] || args
[0] == args
[3]) {
1339 tcg_out32 (s
, MULLW
| TAB (0, args
[2], args
[3]));
1340 tcg_out32 (s
, MULHWU
| TAB (args
[1], args
[2], args
[3]));
1341 tcg_out_mov (s
, args
[0], 0);
1344 tcg_out32 (s
, MULLW
| TAB (args
[0], args
[2], args
[3]));
1345 tcg_out32 (s
, MULHWU
| TAB (args
[1], args
[2], args
[3]));
1349 case INDEX_op_shl_i32
:
1350 if (const_args
[2]) {
1351 tcg_out32 (s
, (RLWINM
1361 tcg_out32 (s
, SLW
| SAB (args
[1], args
[0], args
[2]));
1363 case INDEX_op_shr_i32
:
1364 if (const_args
[2]) {
1365 tcg_out32 (s
, (RLWINM
1375 tcg_out32 (s
, SRW
| SAB (args
[1], args
[0], args
[2]));
1377 case INDEX_op_sar_i32
:
1379 tcg_out32 (s
, SRAWI
| RS (args
[1]) | RA (args
[0]) | SH (args
[2]));
1381 tcg_out32 (s
, SRAW
| SAB (args
[1], args
[0], args
[2]));
1384 case INDEX_op_add2_i32
:
1385 if (args
[0] == args
[3] || args
[0] == args
[5]) {
1386 tcg_out32 (s
, ADDC
| TAB (0, args
[2], args
[4]));
1387 tcg_out32 (s
, ADDE
| TAB (args
[1], args
[3], args
[5]));
1388 tcg_out_mov (s
, args
[0], 0);
1391 tcg_out32 (s
, ADDC
| TAB (args
[0], args
[2], args
[4]));
1392 tcg_out32 (s
, ADDE
| TAB (args
[1], args
[3], args
[5]));
1395 case INDEX_op_sub2_i32
:
1396 if (args
[0] == args
[3] || args
[0] == args
[5]) {
1397 tcg_out32 (s
, SUBFC
| TAB (0, args
[4], args
[2]));
1398 tcg_out32 (s
, SUBFE
| TAB (args
[1], args
[5], args
[3]));
1399 tcg_out_mov (s
, args
[0], 0);
1402 tcg_out32 (s
, SUBFC
| TAB (args
[0], args
[4], args
[2]));
1403 tcg_out32 (s
, SUBFE
| TAB (args
[1], args
[5], args
[3]));
1407 case INDEX_op_brcond_i32
:
1412 args[3] = r1 is const
1413 args[4] = label_index
1415 tcg_out_brcond (s
, args
[2], args
[0], args
[1], const_args
[1], args
[3]);
1417 case INDEX_op_brcond2_i32
:
1418 tcg_out_brcond2(s
, args
, const_args
);
1421 case INDEX_op_neg_i32
:
1422 tcg_out32 (s
, NEG
| RT (args
[0]) | RA (args
[1]));
1425 case INDEX_op_qemu_ld8u
:
1426 tcg_out_qemu_ld(s
, args
, 0);
1428 case INDEX_op_qemu_ld8s
:
1429 tcg_out_qemu_ld(s
, args
, 0 | 4);
1431 case INDEX_op_qemu_ld16u
:
1432 tcg_out_qemu_ld(s
, args
, 1);
1434 case INDEX_op_qemu_ld16s
:
1435 tcg_out_qemu_ld(s
, args
, 1 | 4);
1437 case INDEX_op_qemu_ld32u
:
1438 tcg_out_qemu_ld(s
, args
, 2);
1440 case INDEX_op_qemu_ld64
:
1441 tcg_out_qemu_ld(s
, args
, 3);
1443 case INDEX_op_qemu_st8
:
1444 tcg_out_qemu_st(s
, args
, 0);
1446 case INDEX_op_qemu_st16
:
1447 tcg_out_qemu_st(s
, args
, 1);
1449 case INDEX_op_qemu_st32
:
1450 tcg_out_qemu_st(s
, args
, 2);
1452 case INDEX_op_qemu_st64
:
1453 tcg_out_qemu_st(s
, args
, 3);
1456 case INDEX_op_ext8s_i32
:
1457 tcg_out32 (s
, EXTSB
| RS (args
[1]) | RA (args
[0]));
1459 case INDEX_op_ext16s_i32
:
1460 tcg_out32 (s
, EXTSH
| RS (args
[1]) | RA (args
[0]));
1464 tcg_dump_ops (s
, stderr
);
1469 static const TCGTargetOpDef ppc_op_defs
[] = {
1470 { INDEX_op_exit_tb
, { } },
1471 { INDEX_op_goto_tb
, { } },
1472 { INDEX_op_call
, { "ri" } },
1473 { INDEX_op_jmp
, { "ri" } },
1474 { INDEX_op_br
, { } },
1476 { INDEX_op_mov_i32
, { "r", "r" } },
1477 { INDEX_op_movi_i32
, { "r" } },
1478 { INDEX_op_ld8u_i32
, { "r", "r" } },
1479 { INDEX_op_ld8s_i32
, { "r", "r" } },
1480 { INDEX_op_ld16u_i32
, { "r", "r" } },
1481 { INDEX_op_ld16s_i32
, { "r", "r" } },
1482 { INDEX_op_ld_i32
, { "r", "r" } },
1483 { INDEX_op_st8_i32
, { "r", "r" } },
1484 { INDEX_op_st16_i32
, { "r", "r" } },
1485 { INDEX_op_st_i32
, { "r", "r" } },
1487 { INDEX_op_add_i32
, { "r", "r", "ri" } },
1488 { INDEX_op_mul_i32
, { "r", "r", "ri" } },
1489 { INDEX_op_div_i32
, { "r", "r", "r" } },
1490 { INDEX_op_divu_i32
, { "r", "r", "r" } },
1491 { INDEX_op_rem_i32
, { "r", "r", "r" } },
1492 { INDEX_op_remu_i32
, { "r", "r", "r" } },
1493 { INDEX_op_mulu2_i32
, { "r", "r", "r", "r" } },
1494 { INDEX_op_sub_i32
, { "r", "r", "ri" } },
1495 { INDEX_op_and_i32
, { "r", "r", "ri" } },
1496 { INDEX_op_or_i32
, { "r", "r", "ri" } },
1497 { INDEX_op_xor_i32
, { "r", "r", "ri" } },
1499 { INDEX_op_shl_i32
, { "r", "r", "ri" } },
1500 { INDEX_op_shr_i32
, { "r", "r", "ri" } },
1501 { INDEX_op_sar_i32
, { "r", "r", "ri" } },
1503 { INDEX_op_brcond_i32
, { "r", "ri" } },
1505 { INDEX_op_add2_i32
, { "r", "r", "r", "r", "r", "r" } },
1506 { INDEX_op_sub2_i32
, { "r", "r", "r", "r", "r", "r" } },
1507 { INDEX_op_brcond2_i32
, { "r", "r", "r", "r" } },
1509 { INDEX_op_neg_i32
, { "r", "r" } },
1511 #if TARGET_LONG_BITS == 32
1512 { INDEX_op_qemu_ld8u
, { "r", "L" } },
1513 { INDEX_op_qemu_ld8s
, { "r", "L" } },
1514 { INDEX_op_qemu_ld16u
, { "r", "L" } },
1515 { INDEX_op_qemu_ld16s
, { "r", "L" } },
1516 { INDEX_op_qemu_ld32u
, { "r", "L" } },
1517 { INDEX_op_qemu_ld32s
, { "r", "L" } },
1518 { INDEX_op_qemu_ld64
, { "r", "r", "L" } },
1520 { INDEX_op_qemu_st8
, { "K", "K" } },
1521 { INDEX_op_qemu_st16
, { "K", "K" } },
1522 { INDEX_op_qemu_st32
, { "K", "K" } },
1523 { INDEX_op_qemu_st64
, { "M", "M", "M" } },
1525 { INDEX_op_qemu_ld8u
, { "r", "L", "L" } },
1526 { INDEX_op_qemu_ld8s
, { "r", "L", "L" } },
1527 { INDEX_op_qemu_ld16u
, { "r", "L", "L" } },
1528 { INDEX_op_qemu_ld16s
, { "r", "L", "L" } },
1529 { INDEX_op_qemu_ld32u
, { "r", "L", "L" } },
1530 { INDEX_op_qemu_ld32s
, { "r", "L", "L" } },
1531 { INDEX_op_qemu_ld64
, { "r", "L", "L", "L" } },
1533 { INDEX_op_qemu_st8
, { "K", "K", "K" } },
1534 { INDEX_op_qemu_st16
, { "K", "K", "K" } },
1535 { INDEX_op_qemu_st32
, { "K", "K", "K" } },
1536 { INDEX_op_qemu_st64
, { "M", "M", "M", "M" } },
1539 { INDEX_op_ext8s_i32
, { "r", "r" } },
1540 { INDEX_op_ext16s_i32
, { "r", "r" } },
1545 void tcg_target_init(TCGContext
*s
)
1547 tcg_regset_set32(tcg_target_available_regs
[TCG_TYPE_I32
], 0, 0xffffffff);
1548 tcg_regset_set32(tcg_target_call_clobber_regs
, 0,
1560 (1 << TCG_REG_R10
) |
1561 (1 << TCG_REG_R11
) |
1565 tcg_regset_clear(s
->reserved_regs
);
1566 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R0
);
1567 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R1
);
1569 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R2
);
1572 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R13
);
1574 #ifdef CONFIG_USE_GUEST_BASE
1575 tcg_regset_set_reg(s
->reserved_regs
, TCG_GUEST_BASE_REG
);
1578 tcg_add_target_add_op_defs(ppc_op_defs
);