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tcg: Add tcg-be-ldst.h
[qemu.git] / tcg / ppc64 / tcg-target.c
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "tcg-be-ldst.h"
26
27 #define TCG_CT_CONST_S16 0x100
28 #define TCG_CT_CONST_U16 0x200
29 #define TCG_CT_CONST_S32 0x400
30 #define TCG_CT_CONST_U32 0x800
31 #define TCG_CT_CONST_ZERO 0x1000
32 #define TCG_CT_CONST_MONE 0x2000
33
34 static uint8_t *tb_ret_addr;
35
36 #if TARGET_LONG_BITS == 32
37 #define LD_ADDR LWZ
38 #define CMP_L 0
39 #else
40 #define LD_ADDR LD
41 #define CMP_L (1<<21)
42 #endif
43
44 #ifndef GUEST_BASE
45 #define GUEST_BASE 0
46 #endif
47
48 #ifdef CONFIG_GETAUXVAL
49 #include <sys/auxv.h>
50 static bool have_isa_2_06;
51 #define HAVE_ISA_2_06 have_isa_2_06
52 #define HAVE_ISEL have_isa_2_06
53 #else
54 #define HAVE_ISA_2_06 0
55 #define HAVE_ISEL 0
56 #endif
57
58 #ifdef CONFIG_USE_GUEST_BASE
59 #define TCG_GUEST_BASE_REG 30
60 #else
61 #define TCG_GUEST_BASE_REG 0
62 #endif
63
64 #ifndef NDEBUG
65 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
66 "r0",
67 "r1",
68 "r2",
69 "r3",
70 "r4",
71 "r5",
72 "r6",
73 "r7",
74 "r8",
75 "r9",
76 "r10",
77 "r11",
78 "r12",
79 "r13",
80 "r14",
81 "r15",
82 "r16",
83 "r17",
84 "r18",
85 "r19",
86 "r20",
87 "r21",
88 "r22",
89 "r23",
90 "r24",
91 "r25",
92 "r26",
93 "r27",
94 "r28",
95 "r29",
96 "r30",
97 "r31"
98 };
99 #endif
100
101 static const int tcg_target_reg_alloc_order[] = {
102 TCG_REG_R14, /* call saved registers */
103 TCG_REG_R15,
104 TCG_REG_R16,
105 TCG_REG_R17,
106 TCG_REG_R18,
107 TCG_REG_R19,
108 TCG_REG_R20,
109 TCG_REG_R21,
110 TCG_REG_R22,
111 TCG_REG_R23,
112 TCG_REG_R24,
113 TCG_REG_R25,
114 TCG_REG_R26,
115 TCG_REG_R27,
116 TCG_REG_R28,
117 TCG_REG_R29,
118 TCG_REG_R30,
119 TCG_REG_R31,
120 TCG_REG_R12, /* call clobbered, non-arguments */
121 TCG_REG_R11,
122 TCG_REG_R10, /* call clobbered, arguments */
123 TCG_REG_R9,
124 TCG_REG_R8,
125 TCG_REG_R7,
126 TCG_REG_R6,
127 TCG_REG_R5,
128 TCG_REG_R4,
129 TCG_REG_R3,
130 };
131
132 static const int tcg_target_call_iarg_regs[] = {
133 TCG_REG_R3,
134 TCG_REG_R4,
135 TCG_REG_R5,
136 TCG_REG_R6,
137 TCG_REG_R7,
138 TCG_REG_R8,
139 TCG_REG_R9,
140 TCG_REG_R10
141 };
142
143 static const int tcg_target_call_oarg_regs[] = {
144 TCG_REG_R3
145 };
146
147 static const int tcg_target_callee_save_regs[] = {
148 #ifdef __APPLE__
149 TCG_REG_R11,
150 #endif
151 TCG_REG_R14,
152 TCG_REG_R15,
153 TCG_REG_R16,
154 TCG_REG_R17,
155 TCG_REG_R18,
156 TCG_REG_R19,
157 TCG_REG_R20,
158 TCG_REG_R21,
159 TCG_REG_R22,
160 TCG_REG_R23,
161 TCG_REG_R24,
162 TCG_REG_R25,
163 TCG_REG_R26,
164 TCG_REG_R27, /* currently used for the global env */
165 TCG_REG_R28,
166 TCG_REG_R29,
167 TCG_REG_R30,
168 TCG_REG_R31
169 };
170
171 static inline bool in_range_b(tcg_target_long target)
172 {
173 return target == sextract64(target, 0, 26);
174 }
175
176 static uint32_t reloc_pc24_val(void *pc, tcg_target_long target)
177 {
178 tcg_target_long disp;
179
180 disp = target - (tcg_target_long)pc;
181 assert(in_range_b(disp));
182
183 return disp & 0x3fffffc;
184 }
185
186 static void reloc_pc24(void *pc, tcg_target_long target)
187 {
188 *(uint32_t *)pc = (*(uint32_t *)pc & ~0x3fffffc)
189 | reloc_pc24_val(pc, target);
190 }
191
192 static uint16_t reloc_pc14_val(void *pc, tcg_target_long target)
193 {
194 tcg_target_long disp;
195
196 disp = target - (tcg_target_long)pc;
197 if (disp != (int16_t) disp) {
198 tcg_abort();
199 }
200
201 return disp & 0xfffc;
202 }
203
204 static void reloc_pc14(void *pc, tcg_target_long target)
205 {
206 *(uint32_t *)pc = (*(uint32_t *)pc & ~0xfffc) | reloc_pc14_val(pc, target);
207 }
208
209 static inline void tcg_out_b_noaddr(TCGContext *s, int insn)
210 {
211 unsigned retrans = *(uint32_t *)s->code_ptr & 0x3fffffc;
212 tcg_out32(s, insn | retrans);
213 }
214
215 static inline void tcg_out_bc_noaddr(TCGContext *s, int insn)
216 {
217 unsigned retrans = *(uint32_t *)s->code_ptr & 0xfffc;
218 tcg_out32(s, insn | retrans);
219 }
220
221 static void patch_reloc(uint8_t *code_ptr, int type,
222 intptr_t value, intptr_t addend)
223 {
224 value += addend;
225 switch (type) {
226 case R_PPC_REL14:
227 reloc_pc14(code_ptr, value);
228 break;
229 case R_PPC_REL24:
230 reloc_pc24(code_ptr, value);
231 break;
232 default:
233 tcg_abort();
234 }
235 }
236
237 /* parse target specific constraints */
238 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
239 {
240 const char *ct_str;
241
242 ct_str = *pct_str;
243 switch (ct_str[0]) {
244 case 'A': case 'B': case 'C': case 'D':
245 ct->ct |= TCG_CT_REG;
246 tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
247 break;
248 case 'r':
249 ct->ct |= TCG_CT_REG;
250 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
251 break;
252 case 'L': /* qemu_ld constraint */
253 ct->ct |= TCG_CT_REG;
254 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
255 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
256 #ifdef CONFIG_SOFTMMU
257 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
258 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
259 #endif
260 break;
261 case 'S': /* qemu_st constraint */
262 ct->ct |= TCG_CT_REG;
263 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
264 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
265 #ifdef CONFIG_SOFTMMU
266 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
267 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
268 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
269 #endif
270 break;
271 case 'I':
272 ct->ct |= TCG_CT_CONST_S16;
273 break;
274 case 'J':
275 ct->ct |= TCG_CT_CONST_U16;
276 break;
277 case 'M':
278 ct->ct |= TCG_CT_CONST_MONE;
279 break;
280 case 'T':
281 ct->ct |= TCG_CT_CONST_S32;
282 break;
283 case 'U':
284 ct->ct |= TCG_CT_CONST_U32;
285 break;
286 case 'Z':
287 ct->ct |= TCG_CT_CONST_ZERO;
288 break;
289 default:
290 return -1;
291 }
292 ct_str++;
293 *pct_str = ct_str;
294 return 0;
295 }
296
297 /* test if a constant matches the constraint */
298 static int tcg_target_const_match(tcg_target_long val,
299 const TCGArgConstraint *arg_ct)
300 {
301 int ct = arg_ct->ct;
302 if (ct & TCG_CT_CONST) {
303 return 1;
304 } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {
305 return 1;
306 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) {
307 return 1;
308 } else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
309 return 1;
310 } else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
311 return 1;
312 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
313 return 1;
314 } else if ((ct & TCG_CT_CONST_MONE) && val == -1) {
315 return 1;
316 }
317 return 0;
318 }
319
320 #define OPCD(opc) ((opc)<<26)
321 #define XO19(opc) (OPCD(19)|((opc)<<1))
322 #define MD30(opc) (OPCD(30)|((opc)<<2))
323 #define MDS30(opc) (OPCD(30)|((opc)<<1))
324 #define XO31(opc) (OPCD(31)|((opc)<<1))
325 #define XO58(opc) (OPCD(58)|(opc))
326 #define XO62(opc) (OPCD(62)|(opc))
327
328 #define B OPCD( 18)
329 #define BC OPCD( 16)
330 #define LBZ OPCD( 34)
331 #define LHZ OPCD( 40)
332 #define LHA OPCD( 42)
333 #define LWZ OPCD( 32)
334 #define STB OPCD( 38)
335 #define STH OPCD( 44)
336 #define STW OPCD( 36)
337
338 #define STD XO62( 0)
339 #define STDU XO62( 1)
340 #define STDX XO31(149)
341
342 #define LD XO58( 0)
343 #define LDX XO31( 21)
344 #define LDU XO58( 1)
345 #define LWA XO58( 2)
346 #define LWAX XO31(341)
347
348 #define ADDIC OPCD( 12)
349 #define ADDI OPCD( 14)
350 #define ADDIS OPCD( 15)
351 #define ORI OPCD( 24)
352 #define ORIS OPCD( 25)
353 #define XORI OPCD( 26)
354 #define XORIS OPCD( 27)
355 #define ANDI OPCD( 28)
356 #define ANDIS OPCD( 29)
357 #define MULLI OPCD( 7)
358 #define CMPLI OPCD( 10)
359 #define CMPI OPCD( 11)
360 #define SUBFIC OPCD( 8)
361
362 #define LWZU OPCD( 33)
363 #define STWU OPCD( 37)
364
365 #define RLWIMI OPCD( 20)
366 #define RLWINM OPCD( 21)
367 #define RLWNM OPCD( 23)
368
369 #define RLDICL MD30( 0)
370 #define RLDICR MD30( 1)
371 #define RLDIMI MD30( 3)
372 #define RLDCL MDS30( 8)
373
374 #define BCLR XO19( 16)
375 #define BCCTR XO19(528)
376 #define CRAND XO19(257)
377 #define CRANDC XO19(129)
378 #define CRNAND XO19(225)
379 #define CROR XO19(449)
380 #define CRNOR XO19( 33)
381
382 #define EXTSB XO31(954)
383 #define EXTSH XO31(922)
384 #define EXTSW XO31(986)
385 #define ADD XO31(266)
386 #define ADDE XO31(138)
387 #define ADDME XO31(234)
388 #define ADDZE XO31(202)
389 #define ADDC XO31( 10)
390 #define AND XO31( 28)
391 #define SUBF XO31( 40)
392 #define SUBFC XO31( 8)
393 #define SUBFE XO31(136)
394 #define SUBFME XO31(232)
395 #define SUBFZE XO31(200)
396 #define OR XO31(444)
397 #define XOR XO31(316)
398 #define MULLW XO31(235)
399 #define MULHWU XO31( 11)
400 #define DIVW XO31(491)
401 #define DIVWU XO31(459)
402 #define CMP XO31( 0)
403 #define CMPL XO31( 32)
404 #define LHBRX XO31(790)
405 #define LWBRX XO31(534)
406 #define LDBRX XO31(532)
407 #define STHBRX XO31(918)
408 #define STWBRX XO31(662)
409 #define STDBRX XO31(660)
410 #define MFSPR XO31(339)
411 #define MTSPR XO31(467)
412 #define SRAWI XO31(824)
413 #define NEG XO31(104)
414 #define MFCR XO31( 19)
415 #define MFOCRF (MFCR | (1u << 20))
416 #define NOR XO31(124)
417 #define CNTLZW XO31( 26)
418 #define CNTLZD XO31( 58)
419 #define ANDC XO31( 60)
420 #define ORC XO31(412)
421 #define EQV XO31(284)
422 #define NAND XO31(476)
423 #define ISEL XO31( 15)
424
425 #define MULLD XO31(233)
426 #define MULHD XO31( 73)
427 #define MULHDU XO31( 9)
428 #define DIVD XO31(489)
429 #define DIVDU XO31(457)
430
431 #define LBZX XO31( 87)
432 #define LHZX XO31(279)
433 #define LHAX XO31(343)
434 #define LWZX XO31( 23)
435 #define STBX XO31(215)
436 #define STHX XO31(407)
437 #define STWX XO31(151)
438
439 #define SPR(a, b) ((((a)<<5)|(b))<<11)
440 #define LR SPR(8, 0)
441 #define CTR SPR(9, 0)
442
443 #define SLW XO31( 24)
444 #define SRW XO31(536)
445 #define SRAW XO31(792)
446
447 #define SLD XO31( 27)
448 #define SRD XO31(539)
449 #define SRAD XO31(794)
450 #define SRADI XO31(413<<1)
451
452 #define TW XO31( 4)
453 #define TRAP (TW | TO(31))
454
455 #define RT(r) ((r)<<21)
456 #define RS(r) ((r)<<21)
457 #define RA(r) ((r)<<16)
458 #define RB(r) ((r)<<11)
459 #define TO(t) ((t)<<21)
460 #define SH(s) ((s)<<11)
461 #define MB(b) ((b)<<6)
462 #define ME(e) ((e)<<1)
463 #define BO(o) ((o)<<21)
464 #define MB64(b) ((b)<<5)
465 #define FXM(b) (1 << (19 - (b)))
466
467 #define LK 1
468
469 #define TAB(t, a, b) (RT(t) | RA(a) | RB(b))
470 #define SAB(s, a, b) (RS(s) | RA(a) | RB(b))
471 #define TAI(s, a, i) (RT(s) | RA(a) | ((i) & 0xffff))
472 #define SAI(s, a, i) (RS(s) | RA(a) | ((i) & 0xffff))
473
474 #define BF(n) ((n)<<23)
475 #define BI(n, c) (((c)+((n)*4))<<16)
476 #define BT(n, c) (((c)+((n)*4))<<21)
477 #define BA(n, c) (((c)+((n)*4))<<16)
478 #define BB(n, c) (((c)+((n)*4))<<11)
479 #define BC_(n, c) (((c)+((n)*4))<<6)
480
481 #define BO_COND_TRUE BO(12)
482 #define BO_COND_FALSE BO( 4)
483 #define BO_ALWAYS BO(20)
484
485 enum {
486 CR_LT,
487 CR_GT,
488 CR_EQ,
489 CR_SO
490 };
491
492 static const uint32_t tcg_to_bc[] = {
493 [TCG_COND_EQ] = BC | BI(7, CR_EQ) | BO_COND_TRUE,
494 [TCG_COND_NE] = BC | BI(7, CR_EQ) | BO_COND_FALSE,
495 [TCG_COND_LT] = BC | BI(7, CR_LT) | BO_COND_TRUE,
496 [TCG_COND_GE] = BC | BI(7, CR_LT) | BO_COND_FALSE,
497 [TCG_COND_LE] = BC | BI(7, CR_GT) | BO_COND_FALSE,
498 [TCG_COND_GT] = BC | BI(7, CR_GT) | BO_COND_TRUE,
499 [TCG_COND_LTU] = BC | BI(7, CR_LT) | BO_COND_TRUE,
500 [TCG_COND_GEU] = BC | BI(7, CR_LT) | BO_COND_FALSE,
501 [TCG_COND_LEU] = BC | BI(7, CR_GT) | BO_COND_FALSE,
502 [TCG_COND_GTU] = BC | BI(7, CR_GT) | BO_COND_TRUE,
503 };
504
505 /* The low bit here is set if the RA and RB fields must be inverted. */
506 static const uint32_t tcg_to_isel[] = {
507 [TCG_COND_EQ] = ISEL | BC_(7, CR_EQ),
508 [TCG_COND_NE] = ISEL | BC_(7, CR_EQ) | 1,
509 [TCG_COND_LT] = ISEL | BC_(7, CR_LT),
510 [TCG_COND_GE] = ISEL | BC_(7, CR_LT) | 1,
511 [TCG_COND_LE] = ISEL | BC_(7, CR_GT) | 1,
512 [TCG_COND_GT] = ISEL | BC_(7, CR_GT),
513 [TCG_COND_LTU] = ISEL | BC_(7, CR_LT),
514 [TCG_COND_GEU] = ISEL | BC_(7, CR_LT) | 1,
515 [TCG_COND_LEU] = ISEL | BC_(7, CR_GT) | 1,
516 [TCG_COND_GTU] = ISEL | BC_(7, CR_GT),
517 };
518
519 static inline void tcg_out_mov(TCGContext *s, TCGType type,
520 TCGReg ret, TCGReg arg)
521 {
522 if (ret != arg) {
523 tcg_out32(s, OR | SAB(arg, ret, arg));
524 }
525 }
526
527 static inline void tcg_out_rld(TCGContext *s, int op, TCGReg ra, TCGReg rs,
528 int sh, int mb)
529 {
530 sh = SH(sh & 0x1f) | (((sh >> 5) & 1) << 1);
531 mb = MB64((mb >> 5) | ((mb << 1) & 0x3f));
532 tcg_out32(s, op | RA(ra) | RS(rs) | sh | mb);
533 }
534
535 static inline void tcg_out_rlw(TCGContext *s, int op, TCGReg ra, TCGReg rs,
536 int sh, int mb, int me)
537 {
538 tcg_out32(s, op | RA(ra) | RS(rs) | SH(sh) | MB(mb) | ME(me));
539 }
540
541 static inline void tcg_out_ext32u(TCGContext *s, TCGReg dst, TCGReg src)
542 {
543 tcg_out_rld(s, RLDICL, dst, src, 0, 32);
544 }
545
546 static inline void tcg_out_shli64(TCGContext *s, TCGReg dst, TCGReg src, int c)
547 {
548 tcg_out_rld(s, RLDICR, dst, src, c, 63 - c);
549 }
550
551 static inline void tcg_out_shri64(TCGContext *s, TCGReg dst, TCGReg src, int c)
552 {
553 tcg_out_rld(s, RLDICL, dst, src, 64 - c, c);
554 }
555
556 static void tcg_out_movi32(TCGContext *s, TCGReg ret, int32_t arg)
557 {
558 if (arg == (int16_t) arg) {
559 tcg_out32(s, ADDI | TAI(ret, 0, arg));
560 } else {
561 tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16));
562 if (arg & 0xffff) {
563 tcg_out32(s, ORI | SAI(ret, ret, arg));
564 }
565 }
566 }
567
568 static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret,
569 tcg_target_long arg)
570 {
571 if (type == TCG_TYPE_I32 || arg == (int32_t)arg) {
572 tcg_out_movi32(s, ret, arg);
573 } else if (arg == (uint32_t)arg && !(arg & 0x8000)) {
574 tcg_out32(s, ADDI | TAI(ret, 0, arg));
575 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
576 } else {
577 int32_t high = arg >> 32;
578 tcg_out_movi32(s, ret, high);
579 if (high) {
580 tcg_out_shli64(s, ret, ret, 32);
581 }
582 if (arg & 0xffff0000) {
583 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
584 }
585 if (arg & 0xffff) {
586 tcg_out32(s, ORI | SAI(ret, ret, arg));
587 }
588 }
589 }
590
591 static bool mask_operand(uint32_t c, int *mb, int *me)
592 {
593 uint32_t lsb, test;
594
595 /* Accept a bit pattern like:
596 0....01....1
597 1....10....0
598 0..01..10..0
599 Keep track of the transitions. */
600 if (c == 0 || c == -1) {
601 return false;
602 }
603 test = c;
604 lsb = test & -test;
605 test += lsb;
606 if (test & (test - 1)) {
607 return false;
608 }
609
610 *me = clz32(lsb);
611 *mb = test ? clz32(test & -test) + 1 : 0;
612 return true;
613 }
614
615 static bool mask64_operand(uint64_t c, int *mb, int *me)
616 {
617 uint64_t lsb;
618
619 if (c == 0) {
620 return false;
621 }
622
623 lsb = c & -c;
624 /* Accept 1..10..0. */
625 if (c == -lsb) {
626 *mb = 0;
627 *me = clz64(lsb);
628 return true;
629 }
630 /* Accept 0..01..1. */
631 if (lsb == 1 && (c & (c + 1)) == 0) {
632 *mb = clz64(c + 1) + 1;
633 *me = 63;
634 return true;
635 }
636 return false;
637 }
638
639 static void tcg_out_andi32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
640 {
641 int mb, me;
642
643 if ((c & 0xffff) == c) {
644 tcg_out32(s, ANDI | SAI(src, dst, c));
645 return;
646 } else if ((c & 0xffff0000) == c) {
647 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
648 return;
649 } else if (mask_operand(c, &mb, &me)) {
650 tcg_out_rlw(s, RLWINM, dst, src, 0, mb, me);
651 } else {
652 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R0, c);
653 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
654 }
655 }
656
657 static void tcg_out_andi64(TCGContext *s, TCGReg dst, TCGReg src, uint64_t c)
658 {
659 int mb, me;
660
661 if ((c & 0xffff) == c) {
662 tcg_out32(s, ANDI | SAI(src, dst, c));
663 return;
664 } else if ((c & 0xffff0000) == c) {
665 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
666 return;
667 } else if (mask64_operand(c, &mb, &me)) {
668 if (mb == 0) {
669 tcg_out_rld(s, RLDICR, dst, src, 0, me);
670 } else {
671 tcg_out_rld(s, RLDICL, dst, src, 0, mb);
672 }
673 } else {
674 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, c);
675 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
676 }
677 }
678
679 static void tcg_out_zori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c,
680 int op_lo, int op_hi)
681 {
682 if (c >> 16) {
683 tcg_out32(s, op_hi | SAI(src, dst, c >> 16));
684 src = dst;
685 }
686 if (c & 0xffff) {
687 tcg_out32(s, op_lo | SAI(src, dst, c));
688 src = dst;
689 }
690 }
691
692 static void tcg_out_ori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
693 {
694 tcg_out_zori32(s, dst, src, c, ORI, ORIS);
695 }
696
697 static void tcg_out_xori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
698 {
699 tcg_out_zori32(s, dst, src, c, XORI, XORIS);
700 }
701
702 static void tcg_out_b(TCGContext *s, int mask, tcg_target_long target)
703 {
704 tcg_target_long disp;
705
706 disp = target - (tcg_target_long)s->code_ptr;
707 if (in_range_b(disp)) {
708 tcg_out32(s, B | (disp & 0x3fffffc) | mask);
709 } else {
710 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, (tcg_target_long)target);
711 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | CTR);
712 tcg_out32(s, BCCTR | BO_ALWAYS | mask);
713 }
714 }
715
716 static void tcg_out_call(TCGContext *s, tcg_target_long arg, int const_arg)
717 {
718 #ifdef __APPLE__
719 if (const_arg) {
720 tcg_out_b(s, LK, arg);
721 } else {
722 tcg_out32(s, MTSPR | RS(arg) | LR);
723 tcg_out32(s, BCLR | BO_ALWAYS | LK);
724 }
725 #else
726 TCGReg reg = arg;
727 int ofs = 0;
728
729 if (const_arg) {
730 /* Look through the descriptor. If the branch is in range, and we
731 don't have to spend too much effort on building the toc. */
732 intptr_t tgt = ((intptr_t *)arg)[0];
733 intptr_t toc = ((intptr_t *)arg)[1];
734 intptr_t diff = tgt - (intptr_t)s->code_ptr;
735
736 if (in_range_b(diff) && toc == (uint32_t)toc) {
737 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R2, toc);
738 tcg_out_b(s, LK, tgt);
739 return;
740 }
741
742 /* Fold the low bits of the constant into the addresses below. */
743 ofs = (int16_t)arg;
744 if (ofs + 8 < 0x8000) {
745 arg -= ofs;
746 } else {
747 ofs = 0;
748 }
749 reg = TCG_REG_R2;
750 tcg_out_movi(s, TCG_TYPE_I64, reg, arg);
751 }
752
753 tcg_out32(s, LD | TAI(TCG_REG_R0, reg, ofs));
754 tcg_out32(s, MTSPR | RA(TCG_REG_R0) | CTR);
755 tcg_out32(s, LD | TAI(TCG_REG_R2, reg, ofs + 8));
756 tcg_out32(s, BCCTR | BO_ALWAYS | LK);
757 #endif
758 }
759
760 static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
761 TCGReg base, tcg_target_long offset)
762 {
763 tcg_target_long orig = offset, l0, l1, extra = 0, align = 0;
764 TCGReg rs = TCG_REG_R2;
765
766 assert(rt != TCG_REG_R2 && base != TCG_REG_R2);
767
768 switch (opi) {
769 case LD: case LWA:
770 align = 3;
771 /* FALLTHRU */
772 default:
773 if (rt != TCG_REG_R0) {
774 rs = rt;
775 }
776 break;
777 case STD:
778 align = 3;
779 break;
780 case STB: case STH: case STW:
781 break;
782 }
783
784 /* For unaligned, or very large offsets, use the indexed form. */
785 if (offset & align || offset != (int32_t)offset) {
786 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R2, orig);
787 tcg_out32(s, opx | TAB(rt, base, TCG_REG_R2));
788 return;
789 }
790
791 l0 = (int16_t)offset;
792 offset = (offset - l0) >> 16;
793 l1 = (int16_t)offset;
794
795 if (l1 < 0 && orig >= 0) {
796 extra = 0x4000;
797 l1 = (int16_t)(offset - 0x4000);
798 }
799 if (l1) {
800 tcg_out32(s, ADDIS | TAI(rs, base, l1));
801 base = rs;
802 }
803 if (extra) {
804 tcg_out32(s, ADDIS | TAI(rs, base, extra));
805 base = rs;
806 }
807 if (opi != ADDI || base != rt || l0 != 0) {
808 tcg_out32(s, opi | TAI(rt, base, l0));
809 }
810 }
811
812 static const uint32_t qemu_ldx_opc[8] = {
813 #ifdef TARGET_WORDS_BIGENDIAN
814 LBZX, LHZX, LWZX, LDX,
815 0, LHAX, LWAX, LDX
816 #else
817 LBZX, LHBRX, LWBRX, LDBRX,
818 0, 0, 0, LDBRX,
819 #endif
820 };
821
822 static const uint32_t qemu_stx_opc[4] = {
823 #ifdef TARGET_WORDS_BIGENDIAN
824 STBX, STHX, STWX, STDX
825 #else
826 STBX, STHBRX, STWBRX, STDBRX,
827 #endif
828 };
829
830 static const uint32_t qemu_exts_opc[4] = {
831 EXTSB, EXTSH, EXTSW, 0
832 };
833
834 #if defined (CONFIG_SOFTMMU)
835 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
836 * int mmu_idx, uintptr_t ra)
837 */
838 static const void * const qemu_ld_helpers[4] = {
839 helper_ret_ldub_mmu,
840 helper_ret_lduw_mmu,
841 helper_ret_ldul_mmu,
842 helper_ret_ldq_mmu,
843 };
844
845 /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
846 * uintxx_t val, int mmu_idx, uintptr_t ra)
847 */
848 static const void * const qemu_st_helpers[4] = {
849 helper_ret_stb_mmu,
850 helper_ret_stw_mmu,
851 helper_ret_stl_mmu,
852 helper_ret_stq_mmu,
853 };
854
855 /* Perform the TLB load and compare. Places the result of the comparison
856 in CR7, loads the addend of the TLB into R3, and returns the register
857 containing the guest address (zero-extended into R4). Clobbers R0 and R2. */
858
859 static TCGReg tcg_out_tlb_read(TCGContext *s, int s_bits, TCGReg addr_reg,
860 int mem_index, bool is_read)
861 {
862 int cmp_off
863 = (is_read
864 ? offsetof(CPUArchState, tlb_table[mem_index][0].addr_read)
865 : offsetof(CPUArchState, tlb_table[mem_index][0].addr_write));
866 int add_off = offsetof(CPUArchState, tlb_table[mem_index][0].addend);
867 TCGReg base = TCG_AREG0;
868
869 /* Extract the page index, shifted into place for tlb index. */
870 if (TARGET_LONG_BITS == 32) {
871 /* Zero-extend the address into a place helpful for further use. */
872 tcg_out_ext32u(s, TCG_REG_R4, addr_reg);
873 addr_reg = TCG_REG_R4;
874 } else {
875 tcg_out_rld(s, RLDICL, TCG_REG_R3, addr_reg,
876 64 - TARGET_PAGE_BITS, 64 - CPU_TLB_BITS);
877 }
878
879 /* Compensate for very large offsets. */
880 if (add_off >= 0x8000) {
881 /* Most target env are smaller than 32k; none are larger than 64k.
882 Simplify the logic here merely to offset by 0x7ff0, giving us a
883 range just shy of 64k. Check this assumption. */
884 QEMU_BUILD_BUG_ON(offsetof(CPUArchState,
885 tlb_table[NB_MMU_MODES - 1][1])
886 > 0x7ff0 + 0x7fff);
887 tcg_out32(s, ADDI | TAI(TCG_REG_R2, base, 0x7ff0));
888 base = TCG_REG_R2;
889 cmp_off -= 0x7ff0;
890 add_off -= 0x7ff0;
891 }
892
893 /* Extraction and shifting, part 2. */
894 if (TARGET_LONG_BITS == 32) {
895 tcg_out_rlw(s, RLWINM, TCG_REG_R3, addr_reg,
896 32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
897 32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS),
898 31 - CPU_TLB_ENTRY_BITS);
899 } else {
900 tcg_out_shli64(s, TCG_REG_R3, TCG_REG_R3, CPU_TLB_ENTRY_BITS);
901 }
902
903 tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, base));
904
905 /* Load the tlb comparator. */
906 tcg_out32(s, LD_ADDR | TAI(TCG_REG_R2, TCG_REG_R3, cmp_off));
907
908 /* Load the TLB addend for use on the fast path. Do this asap
909 to minimize any load use delay. */
910 tcg_out32(s, LD | TAI(TCG_REG_R3, TCG_REG_R3, add_off));
911
912 /* Clear the non-page, non-alignment bits from the address. */
913 if (TARGET_LONG_BITS == 32) {
914 tcg_out_rlw(s, RLWINM, TCG_REG_R0, addr_reg, 0,
915 (32 - s_bits) & 31, 31 - TARGET_PAGE_BITS);
916 } else if (!s_bits) {
917 tcg_out_rld(s, RLDICR, TCG_REG_R0, addr_reg, 0, 63 - TARGET_PAGE_BITS);
918 } else {
919 tcg_out_rld(s, RLDICL, TCG_REG_R0, addr_reg,
920 64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - s_bits);
921 tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BITS, 0);
922 }
923
924 tcg_out32(s, CMP | BF(7) | RA(TCG_REG_R0) | RB(TCG_REG_R2) | CMP_L);
925
926 return addr_reg;
927 }
928
929 /* Record the context of a call to the out of line helper code for the slow
930 path for a load or store, so that we can later generate the correct
931 helper code. */
932 static void add_qemu_ldst_label(TCGContext *s, bool is_ld, int opc,
933 int data_reg, int addr_reg, int mem_index,
934 uint8_t *raddr, uint8_t *label_ptr)
935 {
936 TCGLabelQemuLdst *label = new_ldst_label(s);
937
938 label->is_ld = is_ld;
939 label->opc = opc;
940 label->datalo_reg = data_reg;
941 label->addrlo_reg = addr_reg;
942 label->mem_index = mem_index;
943 label->raddr = raddr;
944 label->label_ptr[0] = label_ptr;
945 }
946
947 static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
948 {
949 int opc = lb->opc;
950 int s_bits = opc & 3;
951
952 reloc_pc14(lb->label_ptr[0], (uintptr_t)s->code_ptr);
953
954 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_AREG0);
955
956 /* If the address needed to be zero-extended, we'll have already
957 placed it in R4. The only remaining case is 64-bit guest. */
958 tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R4, lb->addrlo_reg);
959
960 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R5, lb->mem_index);
961 tcg_out32(s, MFSPR | RT(TCG_REG_R6) | LR);
962
963 tcg_out_call(s, (tcg_target_long)qemu_ld_helpers[s_bits], 1);
964
965 if (opc & 4) {
966 uint32_t insn = qemu_exts_opc[s_bits];
967 tcg_out32(s, insn | RA(lb->datalo_reg) | RS(TCG_REG_R3));
968 } else {
969 tcg_out_mov(s, TCG_TYPE_I64, lb->datalo_reg, TCG_REG_R3);
970 }
971
972 tcg_out_b(s, 0, (uintptr_t)lb->raddr);
973 }
974
975 static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
976 {
977 int opc = lb->opc;
978
979 reloc_pc14(lb->label_ptr[0], (uintptr_t)s->code_ptr);
980
981 tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R3, TCG_AREG0);
982
983 /* If the address needed to be zero-extended, we'll have already
984 placed it in R4. The only remaining case is 64-bit guest. */
985 tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R4, lb->addrlo_reg);
986
987 tcg_out_rld(s, RLDICL, TCG_REG_R5, lb->datalo_reg,
988 0, 64 - (1 << (3 + opc)));
989 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R6, lb->mem_index);
990 tcg_out32(s, MFSPR | RT(TCG_REG_R7) | LR);
991
992 tcg_out_call(s, (tcg_target_long)qemu_st_helpers[opc], 1);
993
994 tcg_out_b(s, 0, (uintptr_t)lb->raddr);
995 }
996 #endif /* SOFTMMU */
997
998 static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
999 {
1000 TCGReg addr_reg, data_reg, rbase;
1001 uint32_t insn, s_bits;
1002 #ifdef CONFIG_SOFTMMU
1003 int mem_index;
1004 void *label_ptr;
1005 #endif
1006
1007 data_reg = *args++;
1008 addr_reg = *args++;
1009 s_bits = opc & 3;
1010
1011 #ifdef CONFIG_SOFTMMU
1012 mem_index = *args;
1013
1014 addr_reg = tcg_out_tlb_read(s, s_bits, addr_reg, mem_index, true);
1015
1016 /* Load a pointer into the current opcode w/conditional branch-link. */
1017 label_ptr = s->code_ptr;
1018 tcg_out_bc_noaddr(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
1019
1020 rbase = TCG_REG_R3;
1021 #else /* !CONFIG_SOFTMMU */
1022 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
1023 if (TARGET_LONG_BITS == 32) {
1024 tcg_out_ext32u(s, TCG_REG_R2, addr_reg);
1025 addr_reg = TCG_REG_R2;
1026 }
1027 #endif
1028
1029 insn = qemu_ldx_opc[opc];
1030 if (!HAVE_ISA_2_06 && insn == LDBRX) {
1031 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addr_reg, 4));
1032 tcg_out32(s, LWBRX | TAB(data_reg, rbase, addr_reg));
1033 tcg_out32(s, LWBRX | TAB(TCG_REG_R0, rbase, TCG_REG_R0));
1034 tcg_out_rld(s, RLDIMI, data_reg, TCG_REG_R0, 32, 0);
1035 } else if (insn) {
1036 tcg_out32(s, insn | TAB(data_reg, rbase, addr_reg));
1037 } else {
1038 insn = qemu_ldx_opc[s_bits];
1039 tcg_out32(s, insn | TAB(data_reg, rbase, addr_reg));
1040 insn = qemu_exts_opc[s_bits];
1041 tcg_out32(s, insn | RA(data_reg) | RS(data_reg));
1042 }
1043
1044 #ifdef CONFIG_SOFTMMU
1045 add_qemu_ldst_label(s, true, opc, data_reg, addr_reg, mem_index,
1046 s->code_ptr, label_ptr);
1047 #endif
1048 }
1049
1050 static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
1051 {
1052 TCGReg addr_reg, rbase, data_reg;
1053 uint32_t insn;
1054 #ifdef CONFIG_SOFTMMU
1055 int mem_index;
1056 void *label_ptr;
1057 #endif
1058
1059 data_reg = *args++;
1060 addr_reg = *args++;
1061
1062 #ifdef CONFIG_SOFTMMU
1063 mem_index = *args;
1064
1065 addr_reg = tcg_out_tlb_read(s, opc, addr_reg, mem_index, false);
1066
1067 /* Load a pointer into the current opcode w/conditional branch-link. */
1068 label_ptr = s->code_ptr;
1069 tcg_out_bc_noaddr(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
1070
1071 rbase = TCG_REG_R3;
1072 #else /* !CONFIG_SOFTMMU */
1073 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
1074 if (TARGET_LONG_BITS == 32) {
1075 tcg_out_ext32u(s, TCG_REG_R2, addr_reg);
1076 addr_reg = TCG_REG_R2;
1077 }
1078 #endif
1079
1080 insn = qemu_stx_opc[opc];
1081 if (!HAVE_ISA_2_06 && insn == STDBRX) {
1082 tcg_out32(s, STWBRX | SAB(data_reg, rbase, addr_reg));
1083 tcg_out32(s, ADDI | TAI(TCG_REG_R2, addr_reg, 4));
1084 tcg_out_shri64(s, TCG_REG_R0, data_reg, 32);
1085 tcg_out32(s, STWBRX | SAB(TCG_REG_R0, rbase, TCG_REG_R2));
1086 } else {
1087 tcg_out32(s, insn | SAB(data_reg, rbase, addr_reg));
1088 }
1089
1090 #ifdef CONFIG_SOFTMMU
1091 add_qemu_ldst_label(s, false, opc, data_reg, addr_reg, mem_index,
1092 s->code_ptr, label_ptr);
1093 #endif
1094 }
1095
1096 #define FRAME_SIZE ((int) \
1097 ((8 /* back chain */ \
1098 + 8 /* CR */ \
1099 + 8 /* LR */ \
1100 + 8 /* compiler doubleword */ \
1101 + 8 /* link editor doubleword */ \
1102 + 8 /* TOC save area */ \
1103 + TCG_STATIC_CALL_ARGS_SIZE \
1104 + CPU_TEMP_BUF_NLONGS * sizeof(long) \
1105 + ARRAY_SIZE(tcg_target_callee_save_regs) * 8 \
1106 + 15) & ~15))
1107
1108 #define REG_SAVE_BOT (FRAME_SIZE - ARRAY_SIZE(tcg_target_callee_save_regs) * 8)
1109
1110 static void tcg_target_qemu_prologue(TCGContext *s)
1111 {
1112 int i;
1113
1114 tcg_set_frame(s, TCG_REG_CALL_STACK,
1115 REG_SAVE_BOT - CPU_TEMP_BUF_NLONGS * sizeof(long),
1116 CPU_TEMP_BUF_NLONGS * sizeof(long));
1117
1118 #ifndef __APPLE__
1119 /* First emit adhoc function descriptor */
1120 tcg_out64(s, (uint64_t)s->code_ptr + 24); /* entry point */
1121 s->code_ptr += 16; /* skip TOC and environment pointer */
1122 #endif
1123
1124 /* Prologue */
1125 tcg_out32(s, MFSPR | RT(TCG_REG_R0) | LR);
1126 tcg_out32(s, STDU | SAI(TCG_REG_R1, TCG_REG_R1, -FRAME_SIZE));
1127 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
1128 tcg_out32(s, STD | SAI(tcg_target_callee_save_regs[i], 1,
1129 REG_SAVE_BOT + i * 8));
1130 }
1131 tcg_out32(s, STD | SAI(TCG_REG_R0, TCG_REG_R1, FRAME_SIZE + 16));
1132
1133 #ifdef CONFIG_USE_GUEST_BASE
1134 if (GUEST_BASE) {
1135 tcg_out_movi(s, TCG_TYPE_I64, TCG_GUEST_BASE_REG, GUEST_BASE);
1136 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
1137 }
1138 #endif
1139
1140 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
1141 tcg_out32(s, MTSPR | RS(tcg_target_call_iarg_regs[1]) | CTR);
1142 tcg_out32(s, BCCTR | BO_ALWAYS);
1143
1144 /* Epilogue */
1145 tb_ret_addr = s->code_ptr;
1146
1147 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
1148 tcg_out32(s, LD | TAI(tcg_target_callee_save_regs[i], TCG_REG_R1,
1149 REG_SAVE_BOT + i * 8));
1150 }
1151 tcg_out32(s, LD | TAI(TCG_REG_R0, TCG_REG_R1, FRAME_SIZE + 16));
1152 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | LR);
1153 tcg_out32(s, ADDI | TAI(TCG_REG_R1, TCG_REG_R1, FRAME_SIZE));
1154 tcg_out32(s, BCLR | BO_ALWAYS);
1155 }
1156
1157 static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
1158 TCGReg arg1, intptr_t arg2)
1159 {
1160 int opi, opx;
1161
1162 if (type == TCG_TYPE_I32) {
1163 opi = LWZ, opx = LWZX;
1164 } else {
1165 opi = LD, opx = LDX;
1166 }
1167 tcg_out_mem_long(s, opi, opx, ret, arg1, arg2);
1168 }
1169
1170 static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
1171 TCGReg arg1, intptr_t arg2)
1172 {
1173 int opi, opx;
1174
1175 if (type == TCG_TYPE_I32) {
1176 opi = STW, opx = STWX;
1177 } else {
1178 opi = STD, opx = STDX;
1179 }
1180 tcg_out_mem_long(s, opi, opx, arg, arg1, arg2);
1181 }
1182
1183 static void tcg_out_cmp(TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
1184 int const_arg2, int cr, TCGType type)
1185 {
1186 int imm;
1187 uint32_t op;
1188
1189 /* Simplify the comparisons below wrt CMPI. */
1190 if (type == TCG_TYPE_I32) {
1191 arg2 = (int32_t)arg2;
1192 }
1193
1194 switch (cond) {
1195 case TCG_COND_EQ:
1196 case TCG_COND_NE:
1197 if (const_arg2) {
1198 if ((int16_t) arg2 == arg2) {
1199 op = CMPI;
1200 imm = 1;
1201 break;
1202 } else if ((uint16_t) arg2 == arg2) {
1203 op = CMPLI;
1204 imm = 1;
1205 break;
1206 }
1207 }
1208 op = CMPL;
1209 imm = 0;
1210 break;
1211
1212 case TCG_COND_LT:
1213 case TCG_COND_GE:
1214 case TCG_COND_LE:
1215 case TCG_COND_GT:
1216 if (const_arg2) {
1217 if ((int16_t) arg2 == arg2) {
1218 op = CMPI;
1219 imm = 1;
1220 break;
1221 }
1222 }
1223 op = CMP;
1224 imm = 0;
1225 break;
1226
1227 case TCG_COND_LTU:
1228 case TCG_COND_GEU:
1229 case TCG_COND_LEU:
1230 case TCG_COND_GTU:
1231 if (const_arg2) {
1232 if ((uint16_t) arg2 == arg2) {
1233 op = CMPLI;
1234 imm = 1;
1235 break;
1236 }
1237 }
1238 op = CMPL;
1239 imm = 0;
1240 break;
1241
1242 default:
1243 tcg_abort();
1244 }
1245 op |= BF(cr) | ((type == TCG_TYPE_I64) << 21);
1246
1247 if (imm) {
1248 tcg_out32(s, op | RA(arg1) | (arg2 & 0xffff));
1249 } else {
1250 if (const_arg2) {
1251 tcg_out_movi(s, type, TCG_REG_R0, arg2);
1252 arg2 = TCG_REG_R0;
1253 }
1254 tcg_out32(s, op | RA(arg1) | RB(arg2));
1255 }
1256 }
1257
1258 static void tcg_out_setcond_eq0(TCGContext *s, TCGType type,
1259 TCGReg dst, TCGReg src)
1260 {
1261 tcg_out32(s, (type == TCG_TYPE_I64 ? CNTLZD : CNTLZW) | RS(src) | RA(dst));
1262 tcg_out_shri64(s, dst, dst, type == TCG_TYPE_I64 ? 6 : 5);
1263 }
1264
1265 static void tcg_out_setcond_ne0(TCGContext *s, TCGReg dst, TCGReg src)
1266 {
1267 /* X != 0 implies X + -1 generates a carry. Extra addition
1268 trickery means: R = X-1 + ~X + C = X-1 + (-X+1) + C = C. */
1269 if (dst != src) {
1270 tcg_out32(s, ADDIC | TAI(dst, src, -1));
1271 tcg_out32(s, SUBFE | TAB(dst, dst, src));
1272 } else {
1273 tcg_out32(s, ADDIC | TAI(TCG_REG_R0, src, -1));
1274 tcg_out32(s, SUBFE | TAB(dst, TCG_REG_R0, src));
1275 }
1276 }
1277
1278 static TCGReg tcg_gen_setcond_xor(TCGContext *s, TCGReg arg1, TCGArg arg2,
1279 bool const_arg2)
1280 {
1281 if (const_arg2) {
1282 if ((uint32_t)arg2 == arg2) {
1283 tcg_out_xori32(s, TCG_REG_R0, arg1, arg2);
1284 } else {
1285 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, arg2);
1286 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, TCG_REG_R0));
1287 }
1288 } else {
1289 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, arg2));
1290 }
1291 return TCG_REG_R0;
1292 }
1293
1294 static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond,
1295 TCGArg arg0, TCGArg arg1, TCGArg arg2,
1296 int const_arg2)
1297 {
1298 int crop, sh;
1299
1300 /* Ignore high bits of a potential constant arg2. */
1301 if (type == TCG_TYPE_I32) {
1302 arg2 = (uint32_t)arg2;
1303 }
1304
1305 /* Handle common and trivial cases before handling anything else. */
1306 if (arg2 == 0) {
1307 switch (cond) {
1308 case TCG_COND_EQ:
1309 tcg_out_setcond_eq0(s, type, arg0, arg1);
1310 return;
1311 case TCG_COND_NE:
1312 if (type == TCG_TYPE_I32) {
1313 tcg_out_ext32u(s, TCG_REG_R0, arg1);
1314 arg1 = TCG_REG_R0;
1315 }
1316 tcg_out_setcond_ne0(s, arg0, arg1);
1317 return;
1318 case TCG_COND_GE:
1319 tcg_out32(s, NOR | SAB(arg1, arg0, arg1));
1320 arg1 = arg0;
1321 /* FALLTHRU */
1322 case TCG_COND_LT:
1323 /* Extract the sign bit. */
1324 tcg_out_rld(s, RLDICL, arg0, arg1,
1325 type == TCG_TYPE_I64 ? 1 : 33, 63);
1326 return;
1327 default:
1328 break;
1329 }
1330 }
1331
1332 /* If we have ISEL, we can implement everything with 3 or 4 insns.
1333 All other cases below are also at least 3 insns, so speed up the
1334 code generator by not considering them and always using ISEL. */
1335 if (HAVE_ISEL) {
1336 int isel, tab;
1337
1338 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1339
1340 isel = tcg_to_isel[cond];
1341
1342 tcg_out_movi(s, type, arg0, 1);
1343 if (isel & 1) {
1344 /* arg0 = (bc ? 0 : 1) */
1345 tab = TAB(arg0, 0, arg0);
1346 isel &= ~1;
1347 } else {
1348 /* arg0 = (bc ? 1 : 0) */
1349 tcg_out_movi(s, type, TCG_REG_R0, 0);
1350 tab = TAB(arg0, arg0, TCG_REG_R0);
1351 }
1352 tcg_out32(s, isel | tab);
1353 return;
1354 }
1355
1356 switch (cond) {
1357 case TCG_COND_EQ:
1358 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
1359 tcg_out_setcond_eq0(s, type, arg0, arg1);
1360 return;
1361
1362 case TCG_COND_NE:
1363 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
1364 /* Discard the high bits only once, rather than both inputs. */
1365 if (type == TCG_TYPE_I32) {
1366 tcg_out_ext32u(s, TCG_REG_R0, arg1);
1367 arg1 = TCG_REG_R0;
1368 }
1369 tcg_out_setcond_ne0(s, arg0, arg1);
1370 return;
1371
1372 case TCG_COND_GT:
1373 case TCG_COND_GTU:
1374 sh = 30;
1375 crop = 0;
1376 goto crtest;
1377
1378 case TCG_COND_LT:
1379 case TCG_COND_LTU:
1380 sh = 29;
1381 crop = 0;
1382 goto crtest;
1383
1384 case TCG_COND_GE:
1385 case TCG_COND_GEU:
1386 sh = 31;
1387 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_LT) | BB(7, CR_LT);
1388 goto crtest;
1389
1390 case TCG_COND_LE:
1391 case TCG_COND_LEU:
1392 sh = 31;
1393 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_GT) | BB(7, CR_GT);
1394 crtest:
1395 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1396 if (crop) {
1397 tcg_out32(s, crop);
1398 }
1399 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7));
1400 tcg_out_rlw(s, RLWINM, arg0, TCG_REG_R0, sh, 31, 31);
1401 break;
1402
1403 default:
1404 tcg_abort();
1405 }
1406 }
1407
1408 static void tcg_out_bc(TCGContext *s, int bc, int label_index)
1409 {
1410 TCGLabel *l = &s->labels[label_index];
1411
1412 if (l->has_value) {
1413 tcg_out32(s, bc | reloc_pc14_val(s->code_ptr, l->u.value));
1414 } else {
1415 tcg_out_reloc(s, s->code_ptr, R_PPC_REL14, label_index, 0);
1416 tcg_out_bc_noaddr(s, bc);
1417 }
1418 }
1419
1420 static void tcg_out_brcond(TCGContext *s, TCGCond cond,
1421 TCGArg arg1, TCGArg arg2, int const_arg2,
1422 int label_index, TCGType type)
1423 {
1424 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1425 tcg_out_bc(s, tcg_to_bc[cond], label_index);
1426 }
1427
1428 static void tcg_out_movcond(TCGContext *s, TCGType type, TCGCond cond,
1429 TCGArg dest, TCGArg c1, TCGArg c2, TCGArg v1,
1430 TCGArg v2, bool const_c2)
1431 {
1432 /* If for some reason both inputs are zero, don't produce bad code. */
1433 if (v1 == 0 && v2 == 0) {
1434 tcg_out_movi(s, type, dest, 0);
1435 return;
1436 }
1437
1438 tcg_out_cmp(s, cond, c1, c2, const_c2, 7, type);
1439
1440 if (HAVE_ISEL) {
1441 int isel = tcg_to_isel[cond];
1442
1443 /* Swap the V operands if the operation indicates inversion. */
1444 if (isel & 1) {
1445 int t = v1;
1446 v1 = v2;
1447 v2 = t;
1448 isel &= ~1;
1449 }
1450 /* V1 == 0 is handled by isel; V2 == 0 must be handled by hand. */
1451 if (v2 == 0) {
1452 tcg_out_movi(s, type, TCG_REG_R0, 0);
1453 }
1454 tcg_out32(s, isel | TAB(dest, v1, v2));
1455 } else {
1456 if (dest == v2) {
1457 cond = tcg_invert_cond(cond);
1458 v2 = v1;
1459 } else if (dest != v1) {
1460 if (v1 == 0) {
1461 tcg_out_movi(s, type, dest, 0);
1462 } else {
1463 tcg_out_mov(s, type, dest, v1);
1464 }
1465 }
1466 /* Branch forward over one insn */
1467 tcg_out32(s, tcg_to_bc[cond] | 8);
1468 if (v2 == 0) {
1469 tcg_out_movi(s, type, dest, 0);
1470 } else {
1471 tcg_out_mov(s, type, dest, v2);
1472 }
1473 }
1474 }
1475
1476 void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr)
1477 {
1478 TCGContext s;
1479 unsigned long patch_size;
1480
1481 s.code_ptr = (uint8_t *) jmp_addr;
1482 tcg_out_b(&s, 0, addr);
1483 patch_size = s.code_ptr - (uint8_t *) jmp_addr;
1484 flush_icache_range(jmp_addr, jmp_addr + patch_size);
1485 }
1486
1487 static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
1488 const int *const_args)
1489 {
1490 TCGArg a0, a1, a2;
1491 int c;
1492
1493 switch (opc) {
1494 case INDEX_op_exit_tb:
1495 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R3, args[0]);
1496 tcg_out_b(s, 0, (tcg_target_long)tb_ret_addr);
1497 break;
1498 case INDEX_op_goto_tb:
1499 if (s->tb_jmp_offset) {
1500 /* Direct jump method. */
1501 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1502 s->code_ptr += 28;
1503 } else {
1504 /* Indirect jump method. */
1505 tcg_abort();
1506 }
1507 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1508 break;
1509 case INDEX_op_br:
1510 {
1511 TCGLabel *l = &s->labels[args[0]];
1512
1513 if (l->has_value) {
1514 tcg_out_b(s, 0, l->u.value);
1515 } else {
1516 tcg_out_reloc(s, s->code_ptr, R_PPC_REL24, args[0], 0);
1517 tcg_out_b_noaddr(s, B);
1518 }
1519 }
1520 break;
1521 case INDEX_op_call:
1522 tcg_out_call(s, args[0], const_args[0]);
1523 break;
1524 case INDEX_op_movi_i32:
1525 tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
1526 break;
1527 case INDEX_op_movi_i64:
1528 tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
1529 break;
1530 case INDEX_op_ld8u_i32:
1531 case INDEX_op_ld8u_i64:
1532 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
1533 break;
1534 case INDEX_op_ld8s_i32:
1535 case INDEX_op_ld8s_i64:
1536 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
1537 tcg_out32(s, EXTSB | RS(args[0]) | RA(args[0]));
1538 break;
1539 case INDEX_op_ld16u_i32:
1540 case INDEX_op_ld16u_i64:
1541 tcg_out_mem_long(s, LHZ, LHZX, args[0], args[1], args[2]);
1542 break;
1543 case INDEX_op_ld16s_i32:
1544 case INDEX_op_ld16s_i64:
1545 tcg_out_mem_long(s, LHA, LHAX, args[0], args[1], args[2]);
1546 break;
1547 case INDEX_op_ld_i32:
1548 case INDEX_op_ld32u_i64:
1549 tcg_out_mem_long(s, LWZ, LWZX, args[0], args[1], args[2]);
1550 break;
1551 case INDEX_op_ld32s_i64:
1552 tcg_out_mem_long(s, LWA, LWAX, args[0], args[1], args[2]);
1553 break;
1554 case INDEX_op_ld_i64:
1555 tcg_out_mem_long(s, LD, LDX, args[0], args[1], args[2]);
1556 break;
1557 case INDEX_op_st8_i32:
1558 case INDEX_op_st8_i64:
1559 tcg_out_mem_long(s, STB, STBX, args[0], args[1], args[2]);
1560 break;
1561 case INDEX_op_st16_i32:
1562 case INDEX_op_st16_i64:
1563 tcg_out_mem_long(s, STH, STHX, args[0], args[1], args[2]);
1564 break;
1565 case INDEX_op_st_i32:
1566 case INDEX_op_st32_i64:
1567 tcg_out_mem_long(s, STW, STWX, args[0], args[1], args[2]);
1568 break;
1569 case INDEX_op_st_i64:
1570 tcg_out_mem_long(s, STD, STDX, args[0], args[1], args[2]);
1571 break;
1572
1573 case INDEX_op_add_i32:
1574 a0 = args[0], a1 = args[1], a2 = args[2];
1575 if (const_args[2]) {
1576 do_addi_32:
1577 tcg_out_mem_long(s, ADDI, ADD, a0, a1, (int32_t)a2);
1578 } else {
1579 tcg_out32(s, ADD | TAB(a0, a1, a2));
1580 }
1581 break;
1582 case INDEX_op_sub_i32:
1583 a0 = args[0], a1 = args[1], a2 = args[2];
1584 if (const_args[1]) {
1585 if (const_args[2]) {
1586 tcg_out_movi(s, TCG_TYPE_I32, a0, a1 - a2);
1587 } else {
1588 tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
1589 }
1590 } else if (const_args[2]) {
1591 a2 = -a2;
1592 goto do_addi_32;
1593 } else {
1594 tcg_out32(s, SUBF | TAB(a0, a2, a1));
1595 }
1596 break;
1597
1598 case INDEX_op_and_i32:
1599 a0 = args[0], a1 = args[1], a2 = args[2];
1600 if (const_args[2]) {
1601 tcg_out_andi32(s, a0, a1, a2);
1602 } else {
1603 tcg_out32(s, AND | SAB(a1, a0, a2));
1604 }
1605 break;
1606 case INDEX_op_and_i64:
1607 a0 = args[0], a1 = args[1], a2 = args[2];
1608 if (const_args[2]) {
1609 tcg_out_andi64(s, a0, a1, a2);
1610 } else {
1611 tcg_out32(s, AND | SAB(a1, a0, a2));
1612 }
1613 break;
1614 case INDEX_op_or_i64:
1615 case INDEX_op_or_i32:
1616 a0 = args[0], a1 = args[1], a2 = args[2];
1617 if (const_args[2]) {
1618 tcg_out_ori32(s, a0, a1, a2);
1619 } else {
1620 tcg_out32(s, OR | SAB(a1, a0, a2));
1621 }
1622 break;
1623 case INDEX_op_xor_i64:
1624 case INDEX_op_xor_i32:
1625 a0 = args[0], a1 = args[1], a2 = args[2];
1626 if (const_args[2]) {
1627 tcg_out_xori32(s, a0, a1, a2);
1628 } else {
1629 tcg_out32(s, XOR | SAB(a1, a0, a2));
1630 }
1631 break;
1632 case INDEX_op_andc_i32:
1633 a0 = args[0], a1 = args[1], a2 = args[2];
1634 if (const_args[2]) {
1635 tcg_out_andi32(s, a0, a1, ~a2);
1636 } else {
1637 tcg_out32(s, ANDC | SAB(a1, a0, a2));
1638 }
1639 break;
1640 case INDEX_op_andc_i64:
1641 a0 = args[0], a1 = args[1], a2 = args[2];
1642 if (const_args[2]) {
1643 tcg_out_andi64(s, a0, a1, ~a2);
1644 } else {
1645 tcg_out32(s, ANDC | SAB(a1, a0, a2));
1646 }
1647 break;
1648 case INDEX_op_orc_i32:
1649 if (const_args[2]) {
1650 tcg_out_ori32(s, args[0], args[1], ~args[2]);
1651 break;
1652 }
1653 /* FALLTHRU */
1654 case INDEX_op_orc_i64:
1655 tcg_out32(s, ORC | SAB(args[1], args[0], args[2]));
1656 break;
1657 case INDEX_op_eqv_i32:
1658 if (const_args[2]) {
1659 tcg_out_xori32(s, args[0], args[1], ~args[2]);
1660 break;
1661 }
1662 /* FALLTHRU */
1663 case INDEX_op_eqv_i64:
1664 tcg_out32(s, EQV | SAB(args[1], args[0], args[2]));
1665 break;
1666 case INDEX_op_nand_i32:
1667 case INDEX_op_nand_i64:
1668 tcg_out32(s, NAND | SAB(args[1], args[0], args[2]));
1669 break;
1670 case INDEX_op_nor_i32:
1671 case INDEX_op_nor_i64:
1672 tcg_out32(s, NOR | SAB(args[1], args[0], args[2]));
1673 break;
1674
1675 case INDEX_op_mul_i32:
1676 a0 = args[0], a1 = args[1], a2 = args[2];
1677 if (const_args[2]) {
1678 tcg_out32(s, MULLI | TAI(a0, a1, a2));
1679 } else {
1680 tcg_out32(s, MULLW | TAB(a0, a1, a2));
1681 }
1682 break;
1683
1684 case INDEX_op_div_i32:
1685 tcg_out32(s, DIVW | TAB(args[0], args[1], args[2]));
1686 break;
1687
1688 case INDEX_op_divu_i32:
1689 tcg_out32(s, DIVWU | TAB(args[0], args[1], args[2]));
1690 break;
1691
1692 case INDEX_op_shl_i32:
1693 if (const_args[2]) {
1694 tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31 - args[2]);
1695 } else {
1696 tcg_out32(s, SLW | SAB(args[1], args[0], args[2]));
1697 }
1698 break;
1699 case INDEX_op_shr_i32:
1700 if (const_args[2]) {
1701 tcg_out_rlw(s, RLWINM, args[0], args[1], 32 - args[2], args[2], 31);
1702 } else {
1703 tcg_out32(s, SRW | SAB(args[1], args[0], args[2]));
1704 }
1705 break;
1706 case INDEX_op_sar_i32:
1707 if (const_args[2]) {
1708 tcg_out32(s, SRAWI | RS(args[1]) | RA(args[0]) | SH(args[2]));
1709 } else {
1710 tcg_out32(s, SRAW | SAB(args[1], args[0], args[2]));
1711 }
1712 break;
1713 case INDEX_op_rotl_i32:
1714 if (const_args[2]) {
1715 tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31);
1716 } else {
1717 tcg_out32(s, RLWNM | SAB(args[1], args[0], args[2])
1718 | MB(0) | ME(31));
1719 }
1720 break;
1721 case INDEX_op_rotr_i32:
1722 if (const_args[2]) {
1723 tcg_out_rlw(s, RLWINM, args[0], args[1], 32 - args[2], 0, 31);
1724 } else {
1725 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 32));
1726 tcg_out32(s, RLWNM | SAB(args[1], args[0], TCG_REG_R0)
1727 | MB(0) | ME(31));
1728 }
1729 break;
1730
1731 case INDEX_op_brcond_i32:
1732 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
1733 args[3], TCG_TYPE_I32);
1734 break;
1735
1736 case INDEX_op_brcond_i64:
1737 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
1738 args[3], TCG_TYPE_I64);
1739 break;
1740
1741 case INDEX_op_neg_i32:
1742 case INDEX_op_neg_i64:
1743 tcg_out32(s, NEG | RT(args[0]) | RA(args[1]));
1744 break;
1745
1746 case INDEX_op_not_i32:
1747 case INDEX_op_not_i64:
1748 tcg_out32(s, NOR | SAB(args[1], args[0], args[1]));
1749 break;
1750
1751 case INDEX_op_add_i64:
1752 a0 = args[0], a1 = args[1], a2 = args[2];
1753 if (const_args[2]) {
1754 do_addi_64:
1755 tcg_out_mem_long(s, ADDI, ADD, a0, a1, a2);
1756 } else {
1757 tcg_out32(s, ADD | TAB(a0, a1, a2));
1758 }
1759 break;
1760 case INDEX_op_sub_i64:
1761 a0 = args[0], a1 = args[1], a2 = args[2];
1762 if (const_args[1]) {
1763 if (const_args[2]) {
1764 tcg_out_movi(s, TCG_TYPE_I64, a0, a1 - a2);
1765 } else {
1766 tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
1767 }
1768 } else if (const_args[2]) {
1769 a2 = -a2;
1770 goto do_addi_64;
1771 } else {
1772 tcg_out32(s, SUBF | TAB(a0, a2, a1));
1773 }
1774 break;
1775
1776 case INDEX_op_shl_i64:
1777 if (const_args[2]) {
1778 tcg_out_shli64(s, args[0], args[1], args[2]);
1779 } else {
1780 tcg_out32(s, SLD | SAB(args[1], args[0], args[2]));
1781 }
1782 break;
1783 case INDEX_op_shr_i64:
1784 if (const_args[2]) {
1785 tcg_out_shri64(s, args[0], args[1], args[2]);
1786 } else {
1787 tcg_out32(s, SRD | SAB(args[1], args[0], args[2]));
1788 }
1789 break;
1790 case INDEX_op_sar_i64:
1791 if (const_args[2]) {
1792 int sh = SH(args[2] & 0x1f) | (((args[2] >> 5) & 1) << 1);
1793 tcg_out32(s, SRADI | RA(args[0]) | RS(args[1]) | sh);
1794 } else {
1795 tcg_out32(s, SRAD | SAB(args[1], args[0], args[2]));
1796 }
1797 break;
1798 case INDEX_op_rotl_i64:
1799 if (const_args[2]) {
1800 tcg_out_rld(s, RLDICL, args[0], args[1], args[2], 0);
1801 } else {
1802 tcg_out32(s, RLDCL | SAB(args[1], args[0], args[2]) | MB64(0));
1803 }
1804 break;
1805 case INDEX_op_rotr_i64:
1806 if (const_args[2]) {
1807 tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 0);
1808 } else {
1809 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 64));
1810 tcg_out32(s, RLDCL | SAB(args[1], args[0], TCG_REG_R0) | MB64(0));
1811 }
1812 break;
1813
1814 case INDEX_op_mul_i64:
1815 a0 = args[0], a1 = args[1], a2 = args[2];
1816 if (const_args[2]) {
1817 tcg_out32(s, MULLI | TAI(a0, a1, a2));
1818 } else {
1819 tcg_out32(s, MULLD | TAB(a0, a1, a2));
1820 }
1821 break;
1822 case INDEX_op_div_i64:
1823 tcg_out32(s, DIVD | TAB(args[0], args[1], args[2]));
1824 break;
1825 case INDEX_op_divu_i64:
1826 tcg_out32(s, DIVDU | TAB(args[0], args[1], args[2]));
1827 break;
1828
1829 case INDEX_op_qemu_ld8u:
1830 tcg_out_qemu_ld(s, args, 0);
1831 break;
1832 case INDEX_op_qemu_ld8s:
1833 tcg_out_qemu_ld(s, args, 0 | 4);
1834 break;
1835 case INDEX_op_qemu_ld16u:
1836 tcg_out_qemu_ld(s, args, 1);
1837 break;
1838 case INDEX_op_qemu_ld16s:
1839 tcg_out_qemu_ld(s, args, 1 | 4);
1840 break;
1841 case INDEX_op_qemu_ld32:
1842 case INDEX_op_qemu_ld32u:
1843 tcg_out_qemu_ld(s, args, 2);
1844 break;
1845 case INDEX_op_qemu_ld32s:
1846 tcg_out_qemu_ld(s, args, 2 | 4);
1847 break;
1848 case INDEX_op_qemu_ld64:
1849 tcg_out_qemu_ld(s, args, 3);
1850 break;
1851 case INDEX_op_qemu_st8:
1852 tcg_out_qemu_st(s, args, 0);
1853 break;
1854 case INDEX_op_qemu_st16:
1855 tcg_out_qemu_st(s, args, 1);
1856 break;
1857 case INDEX_op_qemu_st32:
1858 tcg_out_qemu_st(s, args, 2);
1859 break;
1860 case INDEX_op_qemu_st64:
1861 tcg_out_qemu_st(s, args, 3);
1862 break;
1863
1864 case INDEX_op_ext8s_i32:
1865 case INDEX_op_ext8s_i64:
1866 c = EXTSB;
1867 goto gen_ext;
1868 case INDEX_op_ext16s_i32:
1869 case INDEX_op_ext16s_i64:
1870 c = EXTSH;
1871 goto gen_ext;
1872 case INDEX_op_ext32s_i64:
1873 c = EXTSW;
1874 goto gen_ext;
1875 gen_ext:
1876 tcg_out32(s, c | RS(args[1]) | RA(args[0]));
1877 break;
1878
1879 case INDEX_op_setcond_i32:
1880 tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2],
1881 const_args[2]);
1882 break;
1883 case INDEX_op_setcond_i64:
1884 tcg_out_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], args[2],
1885 const_args[2]);
1886 break;
1887
1888 case INDEX_op_bswap16_i32:
1889 case INDEX_op_bswap16_i64:
1890 a0 = args[0], a1 = args[1];
1891 /* a1 = abcd */
1892 if (a0 != a1) {
1893 /* a0 = (a1 r<< 24) & 0xff # 000c */
1894 tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
1895 /* a0 = (a0 & ~0xff00) | (a1 r<< 8) & 0xff00 # 00dc */
1896 tcg_out_rlw(s, RLWIMI, a0, a1, 8, 16, 23);
1897 } else {
1898 /* r0 = (a1 r<< 8) & 0xff00 # 00d0 */
1899 tcg_out_rlw(s, RLWINM, TCG_REG_R0, a1, 8, 16, 23);
1900 /* a0 = (a1 r<< 24) & 0xff # 000c */
1901 tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
1902 /* a0 = a0 | r0 # 00dc */
1903 tcg_out32(s, OR | SAB(TCG_REG_R0, a0, a0));
1904 }
1905 break;
1906
1907 case INDEX_op_bswap32_i32:
1908 case INDEX_op_bswap32_i64:
1909 /* Stolen from gcc's builtin_bswap32 */
1910 a1 = args[1];
1911 a0 = args[0] == a1 ? TCG_REG_R0 : args[0];
1912
1913 /* a1 = args[1] # abcd */
1914 /* a0 = rotate_left (a1, 8) # bcda */
1915 tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
1916 /* a0 = (a0 & ~0xff000000) | ((a1 r<< 24) & 0xff000000) # dcda */
1917 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
1918 /* a0 = (a0 & ~0x0000ff00) | ((a1 r<< 24) & 0x0000ff00) # dcba */
1919 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
1920
1921 if (a0 == TCG_REG_R0) {
1922 tcg_out_mov(s, TCG_TYPE_I64, args[0], a0);
1923 }
1924 break;
1925
1926 case INDEX_op_bswap64_i64:
1927 a0 = args[0], a1 = args[1], a2 = TCG_REG_R0;
1928 if (a0 == a1) {
1929 a0 = TCG_REG_R0;
1930 a2 = a1;
1931 }
1932
1933 /* a1 = # abcd efgh */
1934 /* a0 = rl32(a1, 8) # 0000 fghe */
1935 tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
1936 /* a0 = dep(a0, rl32(a1, 24), 0xff000000) # 0000 hghe */
1937 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
1938 /* a0 = dep(a0, rl32(a1, 24), 0x0000ff00) # 0000 hgfe */
1939 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
1940
1941 /* a0 = rl64(a0, 32) # hgfe 0000 */
1942 /* a2 = rl64(a1, 32) # efgh abcd */
1943 tcg_out_rld(s, RLDICL, a0, a0, 32, 0);
1944 tcg_out_rld(s, RLDICL, a2, a1, 32, 0);
1945
1946 /* a0 = dep(a0, rl32(a2, 8), 0xffffffff) # hgfe bcda */
1947 tcg_out_rlw(s, RLWIMI, a0, a2, 8, 0, 31);
1948 /* a0 = dep(a0, rl32(a2, 24), 0xff000000) # hgfe dcda */
1949 tcg_out_rlw(s, RLWIMI, a0, a2, 24, 0, 7);
1950 /* a0 = dep(a0, rl32(a2, 24), 0x0000ff00) # hgfe dcba */
1951 tcg_out_rlw(s, RLWIMI, a0, a2, 24, 16, 23);
1952
1953 if (a0 == 0) {
1954 tcg_out_mov(s, TCG_TYPE_I64, args[0], a0);
1955 }
1956 break;
1957
1958 case INDEX_op_deposit_i32:
1959 if (const_args[2]) {
1960 uint32_t mask = ((2u << (args[4] - 1)) - 1) << args[3];
1961 tcg_out_andi32(s, args[0], args[0], ~mask);
1962 } else {
1963 tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3],
1964 32 - args[3] - args[4], 31 - args[3]);
1965 }
1966 break;
1967 case INDEX_op_deposit_i64:
1968 if (const_args[2]) {
1969 uint64_t mask = ((2ull << (args[4] - 1)) - 1) << args[3];
1970 tcg_out_andi64(s, args[0], args[0], ~mask);
1971 } else {
1972 tcg_out_rld(s, RLDIMI, args[0], args[2], args[3],
1973 64 - args[3] - args[4]);
1974 }
1975 break;
1976
1977 case INDEX_op_movcond_i32:
1978 tcg_out_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], args[2],
1979 args[3], args[4], const_args[2]);
1980 break;
1981 case INDEX_op_movcond_i64:
1982 tcg_out_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], args[2],
1983 args[3], args[4], const_args[2]);
1984 break;
1985
1986 case INDEX_op_add2_i64:
1987 /* Note that the CA bit is defined based on the word size of the
1988 environment. So in 64-bit mode it's always carry-out of bit 63.
1989 The fallback code using deposit works just as well for 32-bit. */
1990 a0 = args[0], a1 = args[1];
1991 if (a0 == args[3] || (!const_args[5] && a0 == args[5])) {
1992 a0 = TCG_REG_R0;
1993 }
1994 if (const_args[4]) {
1995 tcg_out32(s, ADDIC | TAI(a0, args[2], args[4]));
1996 } else {
1997 tcg_out32(s, ADDC | TAB(a0, args[2], args[4]));
1998 }
1999 if (const_args[5]) {
2000 tcg_out32(s, (args[5] ? ADDME : ADDZE) | RT(a1) | RA(args[3]));
2001 } else {
2002 tcg_out32(s, ADDE | TAB(a1, args[3], args[5]));
2003 }
2004 if (a0 != args[0]) {
2005 tcg_out_mov(s, TCG_TYPE_I64, args[0], a0);
2006 }
2007 break;
2008
2009 case INDEX_op_sub2_i64:
2010 a0 = args[0], a1 = args[1];
2011 if (a0 == args[5] || (!const_args[4] && a0 == args[4])) {
2012 a0 = TCG_REG_R0;
2013 }
2014 if (const_args[2]) {
2015 tcg_out32(s, SUBFIC | TAI(a0, args[3], args[2]));
2016 } else {
2017 tcg_out32(s, SUBFC | TAB(a0, args[3], args[2]));
2018 }
2019 if (const_args[4]) {
2020 tcg_out32(s, (args[4] ? SUBFME : SUBFZE) | RT(a1) | RA(args[5]));
2021 } else {
2022 tcg_out32(s, SUBFE | TAB(a1, args[5], args[4]));
2023 }
2024 if (a0 != args[0]) {
2025 tcg_out_mov(s, TCG_TYPE_I64, args[0], a0);
2026 }
2027 break;
2028
2029 case INDEX_op_muluh_i64:
2030 tcg_out32(s, MULHDU | TAB(args[0], args[1], args[2]));
2031 break;
2032 case INDEX_op_mulsh_i64:
2033 tcg_out32(s, MULHD | TAB(args[0], args[1], args[2]));
2034 break;
2035
2036 default:
2037 tcg_dump_ops(s);
2038 tcg_abort();
2039 }
2040 }
2041
2042 static const TCGTargetOpDef ppc_op_defs[] = {
2043 { INDEX_op_exit_tb, { } },
2044 { INDEX_op_goto_tb, { } },
2045 { INDEX_op_call, { "ri" } },
2046 { INDEX_op_br, { } },
2047
2048 { INDEX_op_mov_i32, { "r", "r" } },
2049 { INDEX_op_mov_i64, { "r", "r" } },
2050 { INDEX_op_movi_i32, { "r" } },
2051 { INDEX_op_movi_i64, { "r" } },
2052
2053 { INDEX_op_ld8u_i32, { "r", "r" } },
2054 { INDEX_op_ld8s_i32, { "r", "r" } },
2055 { INDEX_op_ld16u_i32, { "r", "r" } },
2056 { INDEX_op_ld16s_i32, { "r", "r" } },
2057 { INDEX_op_ld_i32, { "r", "r" } },
2058 { INDEX_op_ld_i64, { "r", "r" } },
2059 { INDEX_op_st8_i32, { "r", "r" } },
2060 { INDEX_op_st8_i64, { "r", "r" } },
2061 { INDEX_op_st16_i32, { "r", "r" } },
2062 { INDEX_op_st16_i64, { "r", "r" } },
2063 { INDEX_op_st_i32, { "r", "r" } },
2064 { INDEX_op_st_i64, { "r", "r" } },
2065 { INDEX_op_st32_i64, { "r", "r" } },
2066
2067 { INDEX_op_ld8u_i64, { "r", "r" } },
2068 { INDEX_op_ld8s_i64, { "r", "r" } },
2069 { INDEX_op_ld16u_i64, { "r", "r" } },
2070 { INDEX_op_ld16s_i64, { "r", "r" } },
2071 { INDEX_op_ld32u_i64, { "r", "r" } },
2072 { INDEX_op_ld32s_i64, { "r", "r" } },
2073
2074 { INDEX_op_add_i32, { "r", "r", "ri" } },
2075 { INDEX_op_mul_i32, { "r", "r", "rI" } },
2076 { INDEX_op_div_i32, { "r", "r", "r" } },
2077 { INDEX_op_divu_i32, { "r", "r", "r" } },
2078 { INDEX_op_sub_i32, { "r", "rI", "ri" } },
2079 { INDEX_op_and_i32, { "r", "r", "ri" } },
2080 { INDEX_op_or_i32, { "r", "r", "ri" } },
2081 { INDEX_op_xor_i32, { "r", "r", "ri" } },
2082 { INDEX_op_andc_i32, { "r", "r", "ri" } },
2083 { INDEX_op_orc_i32, { "r", "r", "ri" } },
2084 { INDEX_op_eqv_i32, { "r", "r", "ri" } },
2085 { INDEX_op_nand_i32, { "r", "r", "r" } },
2086 { INDEX_op_nor_i32, { "r", "r", "r" } },
2087
2088 { INDEX_op_shl_i32, { "r", "r", "ri" } },
2089 { INDEX_op_shr_i32, { "r", "r", "ri" } },
2090 { INDEX_op_sar_i32, { "r", "r", "ri" } },
2091 { INDEX_op_rotl_i32, { "r", "r", "ri" } },
2092 { INDEX_op_rotr_i32, { "r", "r", "ri" } },
2093
2094 { INDEX_op_brcond_i32, { "r", "ri" } },
2095 { INDEX_op_brcond_i64, { "r", "ri" } },
2096
2097 { INDEX_op_neg_i32, { "r", "r" } },
2098 { INDEX_op_not_i32, { "r", "r" } },
2099
2100 { INDEX_op_add_i64, { "r", "r", "rT" } },
2101 { INDEX_op_sub_i64, { "r", "rI", "rT" } },
2102 { INDEX_op_and_i64, { "r", "r", "ri" } },
2103 { INDEX_op_or_i64, { "r", "r", "rU" } },
2104 { INDEX_op_xor_i64, { "r", "r", "rU" } },
2105 { INDEX_op_andc_i64, { "r", "r", "ri" } },
2106 { INDEX_op_orc_i64, { "r", "r", "r" } },
2107 { INDEX_op_eqv_i64, { "r", "r", "r" } },
2108 { INDEX_op_nand_i64, { "r", "r", "r" } },
2109 { INDEX_op_nor_i64, { "r", "r", "r" } },
2110
2111 { INDEX_op_shl_i64, { "r", "r", "ri" } },
2112 { INDEX_op_shr_i64, { "r", "r", "ri" } },
2113 { INDEX_op_sar_i64, { "r", "r", "ri" } },
2114 { INDEX_op_rotl_i64, { "r", "r", "ri" } },
2115 { INDEX_op_rotr_i64, { "r", "r", "ri" } },
2116
2117 { INDEX_op_mul_i64, { "r", "r", "rI" } },
2118 { INDEX_op_div_i64, { "r", "r", "r" } },
2119 { INDEX_op_divu_i64, { "r", "r", "r" } },
2120
2121 { INDEX_op_neg_i64, { "r", "r" } },
2122 { INDEX_op_not_i64, { "r", "r" } },
2123
2124 { INDEX_op_qemu_ld8u, { "r", "L" } },
2125 { INDEX_op_qemu_ld8s, { "r", "L" } },
2126 { INDEX_op_qemu_ld16u, { "r", "L" } },
2127 { INDEX_op_qemu_ld16s, { "r", "L" } },
2128 { INDEX_op_qemu_ld32, { "r", "L" } },
2129 { INDEX_op_qemu_ld32u, { "r", "L" } },
2130 { INDEX_op_qemu_ld32s, { "r", "L" } },
2131 { INDEX_op_qemu_ld64, { "r", "L" } },
2132
2133 { INDEX_op_qemu_st8, { "S", "S" } },
2134 { INDEX_op_qemu_st16, { "S", "S" } },
2135 { INDEX_op_qemu_st32, { "S", "S" } },
2136 { INDEX_op_qemu_st64, { "S", "S" } },
2137
2138 { INDEX_op_ext8s_i32, { "r", "r" } },
2139 { INDEX_op_ext16s_i32, { "r", "r" } },
2140 { INDEX_op_ext8s_i64, { "r", "r" } },
2141 { INDEX_op_ext16s_i64, { "r", "r" } },
2142 { INDEX_op_ext32s_i64, { "r", "r" } },
2143
2144 { INDEX_op_setcond_i32, { "r", "r", "ri" } },
2145 { INDEX_op_setcond_i64, { "r", "r", "ri" } },
2146 { INDEX_op_movcond_i32, { "r", "r", "ri", "rZ", "rZ" } },
2147 { INDEX_op_movcond_i64, { "r", "r", "ri", "rZ", "rZ" } },
2148
2149 { INDEX_op_bswap16_i32, { "r", "r" } },
2150 { INDEX_op_bswap16_i64, { "r", "r" } },
2151 { INDEX_op_bswap32_i32, { "r", "r" } },
2152 { INDEX_op_bswap32_i64, { "r", "r" } },
2153 { INDEX_op_bswap64_i64, { "r", "r" } },
2154
2155 { INDEX_op_deposit_i32, { "r", "0", "rZ" } },
2156 { INDEX_op_deposit_i64, { "r", "0", "rZ" } },
2157
2158 { INDEX_op_add2_i64, { "r", "r", "r", "r", "rI", "rZM" } },
2159 { INDEX_op_sub2_i64, { "r", "r", "rI", "r", "rZM", "r" } },
2160 { INDEX_op_mulsh_i64, { "r", "r", "r" } },
2161 { INDEX_op_muluh_i64, { "r", "r", "r" } },
2162
2163 { -1 },
2164 };
2165
2166 static void tcg_target_init(TCGContext *s)
2167 {
2168 #ifdef CONFIG_GETAUXVAL
2169 unsigned long hwcap = getauxval(AT_HWCAP);
2170 if (hwcap & PPC_FEATURE_ARCH_2_06) {
2171 have_isa_2_06 = true;
2172 }
2173 #endif
2174
2175 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
2176 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
2177 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
2178 (1 << TCG_REG_R0) |
2179 (1 << TCG_REG_R2) |
2180 (1 << TCG_REG_R3) |
2181 (1 << TCG_REG_R4) |
2182 (1 << TCG_REG_R5) |
2183 (1 << TCG_REG_R6) |
2184 (1 << TCG_REG_R7) |
2185 (1 << TCG_REG_R8) |
2186 (1 << TCG_REG_R9) |
2187 (1 << TCG_REG_R10) |
2188 (1 << TCG_REG_R11) |
2189 (1 << TCG_REG_R12));
2190
2191 tcg_regset_clear(s->reserved_regs);
2192 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */
2193 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */
2194 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* mem temp */
2195 #ifdef __APPLE__
2196 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R11); /* ??? */
2197 #endif
2198 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */
2199
2200 tcg_add_target_add_op_defs(ppc_op_defs);
2201 }
2202
2203 typedef struct {
2204 DebugFrameCIE cie;
2205 DebugFrameFDEHeader fde;
2206 uint8_t fde_def_cfa[4];
2207 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2 + 3];
2208 } DebugFrame;
2209
2210 /* We're expecting a 2 byte uleb128 encoded value. */
2211 QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14));
2212
2213 #define ELF_HOST_MACHINE EM_PPC64
2214
2215 static DebugFrame debug_frame = {
2216 .cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
2217 .cie.id = -1,
2218 .cie.version = 1,
2219 .cie.code_align = 1,
2220 .cie.data_align = 0x78, /* sleb128 -8 */
2221 .cie.return_column = 65,
2222
2223 /* Total FDE size does not include the "len" member. */
2224 .fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, fde.cie_offset),
2225
2226 .fde_def_cfa = {
2227 12, 1, /* DW_CFA_def_cfa r1, ... */
2228 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2229 (FRAME_SIZE >> 7)
2230 },
2231 .fde_reg_ofs = {
2232 0x11, 65, 0x7e, /* DW_CFA_offset_extended_sf, lr, 16 */
2233 }
2234 };
2235
2236 void tcg_register_jit(void *buf, size_t buf_size)
2237 {
2238 uint8_t *p = &debug_frame.fde_reg_ofs[3];
2239 int i;
2240
2241 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i, p += 2) {
2242 p[0] = 0x80 + tcg_target_callee_save_regs[i];
2243 p[1] = (FRAME_SIZE - (REG_SAVE_BOT + i * 8)) / 8;
2244 }
2245
2246 debug_frame.fde.func_start = (tcg_target_long) buf;
2247 debug_frame.fde.func_len = buf_size;
2248
2249 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
2250 }
Qemu copy for testing