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tcg-ppc64: Use getauxval for ISA detection
[qemu.git] / tcg / ppc64 / tcg-target.c
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #define TCG_CT_CONST_S16 0x100
26 #define TCG_CT_CONST_U16 0x200
27 #define TCG_CT_CONST_S32 0x400
28 #define TCG_CT_CONST_U32 0x800
29 #define TCG_CT_CONST_ZERO 0x1000
30
31 static uint8_t *tb_ret_addr;
32
33 #define FAST_PATH
34
35 #if TARGET_LONG_BITS == 32
36 #define LD_ADDR LWZU
37 #define CMP_L 0
38 #else
39 #define LD_ADDR LDU
40 #define CMP_L (1<<21)
41 #endif
42
43 #ifndef GUEST_BASE
44 #define GUEST_BASE 0
45 #endif
46
47 #ifdef CONFIG_GETAUXVAL
48 #include <sys/auxv.h>
49 static bool have_isa_2_06;
50 #define HAVE_ISA_2_06 have_isa_2_06
51 #define HAVE_ISEL have_isa_2_06
52 #else
53 #define HAVE_ISA_2_06 0
54 #define HAVE_ISEL 0
55 #endif
56
57 #ifdef CONFIG_USE_GUEST_BASE
58 #define TCG_GUEST_BASE_REG 30
59 #else
60 #define TCG_GUEST_BASE_REG 0
61 #endif
62
63 #ifndef NDEBUG
64 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
65 "r0",
66 "r1",
67 "r2",
68 "r3",
69 "r4",
70 "r5",
71 "r6",
72 "r7",
73 "r8",
74 "r9",
75 "r10",
76 "r11",
77 "r12",
78 "r13",
79 "r14",
80 "r15",
81 "r16",
82 "r17",
83 "r18",
84 "r19",
85 "r20",
86 "r21",
87 "r22",
88 "r23",
89 "r24",
90 "r25",
91 "r26",
92 "r27",
93 "r28",
94 "r29",
95 "r30",
96 "r31"
97 };
98 #endif
99
100 static const int tcg_target_reg_alloc_order[] = {
101 TCG_REG_R14,
102 TCG_REG_R15,
103 TCG_REG_R16,
104 TCG_REG_R17,
105 TCG_REG_R18,
106 TCG_REG_R19,
107 TCG_REG_R20,
108 TCG_REG_R21,
109 TCG_REG_R22,
110 TCG_REG_R23,
111 TCG_REG_R28,
112 TCG_REG_R29,
113 TCG_REG_R30,
114 TCG_REG_R31,
115 #ifdef __APPLE__
116 TCG_REG_R2,
117 #endif
118 TCG_REG_R3,
119 TCG_REG_R4,
120 TCG_REG_R5,
121 TCG_REG_R6,
122 TCG_REG_R7,
123 TCG_REG_R8,
124 TCG_REG_R9,
125 TCG_REG_R10,
126 #ifndef __APPLE__
127 TCG_REG_R11,
128 #endif
129 TCG_REG_R12,
130 TCG_REG_R24,
131 TCG_REG_R25,
132 TCG_REG_R26,
133 TCG_REG_R27
134 };
135
136 static const int tcg_target_call_iarg_regs[] = {
137 TCG_REG_R3,
138 TCG_REG_R4,
139 TCG_REG_R5,
140 TCG_REG_R6,
141 TCG_REG_R7,
142 TCG_REG_R8,
143 TCG_REG_R9,
144 TCG_REG_R10
145 };
146
147 static const int tcg_target_call_oarg_regs[] = {
148 TCG_REG_R3
149 };
150
151 static const int tcg_target_callee_save_regs[] = {
152 #ifdef __APPLE__
153 TCG_REG_R11,
154 #endif
155 TCG_REG_R14,
156 TCG_REG_R15,
157 TCG_REG_R16,
158 TCG_REG_R17,
159 TCG_REG_R18,
160 TCG_REG_R19,
161 TCG_REG_R20,
162 TCG_REG_R21,
163 TCG_REG_R22,
164 TCG_REG_R23,
165 TCG_REG_R24,
166 TCG_REG_R25,
167 TCG_REG_R26,
168 TCG_REG_R27, /* currently used for the global env */
169 TCG_REG_R28,
170 TCG_REG_R29,
171 TCG_REG_R30,
172 TCG_REG_R31
173 };
174
175 static uint32_t reloc_pc24_val (void *pc, tcg_target_long target)
176 {
177 tcg_target_long disp;
178
179 disp = target - (tcg_target_long) pc;
180 if ((disp << 38) >> 38 != disp)
181 tcg_abort ();
182
183 return disp & 0x3fffffc;
184 }
185
186 static void reloc_pc24 (void *pc, tcg_target_long target)
187 {
188 *(uint32_t *) pc = (*(uint32_t *) pc & ~0x3fffffc)
189 | reloc_pc24_val (pc, target);
190 }
191
192 static uint16_t reloc_pc14_val (void *pc, tcg_target_long target)
193 {
194 tcg_target_long disp;
195
196 disp = target - (tcg_target_long) pc;
197 if (disp != (int16_t) disp)
198 tcg_abort ();
199
200 return disp & 0xfffc;
201 }
202
203 static void reloc_pc14 (void *pc, tcg_target_long target)
204 {
205 *(uint32_t *) pc = (*(uint32_t *) pc & ~0xfffc)
206 | reloc_pc14_val (pc, target);
207 }
208
209 static void patch_reloc (uint8_t *code_ptr, int type,
210 tcg_target_long value, tcg_target_long addend)
211 {
212 value += addend;
213 switch (type) {
214 case R_PPC_REL14:
215 reloc_pc14 (code_ptr, value);
216 break;
217 case R_PPC_REL24:
218 reloc_pc24 (code_ptr, value);
219 break;
220 default:
221 tcg_abort ();
222 }
223 }
224
225 /* parse target specific constraints */
226 static int target_parse_constraint (TCGArgConstraint *ct, const char **pct_str)
227 {
228 const char *ct_str;
229
230 ct_str = *pct_str;
231 switch (ct_str[0]) {
232 case 'A': case 'B': case 'C': case 'D':
233 ct->ct |= TCG_CT_REG;
234 tcg_regset_set_reg (ct->u.regs, 3 + ct_str[0] - 'A');
235 break;
236 case 'r':
237 ct->ct |= TCG_CT_REG;
238 tcg_regset_set32 (ct->u.regs, 0, 0xffffffff);
239 break;
240 case 'L': /* qemu_ld constraint */
241 ct->ct |= TCG_CT_REG;
242 tcg_regset_set32 (ct->u.regs, 0, 0xffffffff);
243 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3);
244 #ifdef CONFIG_SOFTMMU
245 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4);
246 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R5);
247 #endif
248 break;
249 case 'S': /* qemu_st constraint */
250 ct->ct |= TCG_CT_REG;
251 tcg_regset_set32 (ct->u.regs, 0, 0xffffffff);
252 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3);
253 #ifdef CONFIG_SOFTMMU
254 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4);
255 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R5);
256 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R6);
257 #endif
258 break;
259 case 'I':
260 ct->ct |= TCG_CT_CONST_S16;
261 break;
262 case 'J':
263 ct->ct |= TCG_CT_CONST_U16;
264 break;
265 case 'T':
266 ct->ct |= TCG_CT_CONST_S32;
267 break;
268 case 'U':
269 ct->ct |= TCG_CT_CONST_U32;
270 break;
271 case 'Z':
272 ct->ct |= TCG_CT_CONST_ZERO;
273 break;
274 default:
275 return -1;
276 }
277 ct_str++;
278 *pct_str = ct_str;
279 return 0;
280 }
281
282 /* test if a constant matches the constraint */
283 static int tcg_target_const_match (tcg_target_long val,
284 const TCGArgConstraint *arg_ct)
285 {
286 int ct = arg_ct->ct;
287 if (ct & TCG_CT_CONST) {
288 return 1;
289 } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {
290 return 1;
291 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) {
292 return 1;
293 } else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
294 return 1;
295 } else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
296 return 1;
297 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
298 return 1;
299 }
300 return 0;
301 }
302
303 #define OPCD(opc) ((opc)<<26)
304 #define XO19(opc) (OPCD(19)|((opc)<<1))
305 #define XO30(opc) (OPCD(30)|((opc)<<2))
306 #define XO31(opc) (OPCD(31)|((opc)<<1))
307 #define XO58(opc) (OPCD(58)|(opc))
308 #define XO62(opc) (OPCD(62)|(opc))
309
310 #define B OPCD( 18)
311 #define BC OPCD( 16)
312 #define LBZ OPCD( 34)
313 #define LHZ OPCD( 40)
314 #define LHA OPCD( 42)
315 #define LWZ OPCD( 32)
316 #define STB OPCD( 38)
317 #define STH OPCD( 44)
318 #define STW OPCD( 36)
319
320 #define STD XO62( 0)
321 #define STDU XO62( 1)
322 #define STDX XO31(149)
323
324 #define LD XO58( 0)
325 #define LDX XO31( 21)
326 #define LDU XO58( 1)
327 #define LWA XO58( 2)
328 #define LWAX XO31(341)
329
330 #define ADDIC OPCD( 12)
331 #define ADDI OPCD( 14)
332 #define ADDIS OPCD( 15)
333 #define ORI OPCD( 24)
334 #define ORIS OPCD( 25)
335 #define XORI OPCD( 26)
336 #define XORIS OPCD( 27)
337 #define ANDI OPCD( 28)
338 #define ANDIS OPCD( 29)
339 #define MULLI OPCD( 7)
340 #define CMPLI OPCD( 10)
341 #define CMPI OPCD( 11)
342 #define SUBFIC OPCD( 8)
343
344 #define LWZU OPCD( 33)
345 #define STWU OPCD( 37)
346
347 #define RLWIMI OPCD( 20)
348 #define RLWINM OPCD( 21)
349 #define RLWNM OPCD( 23)
350
351 #define RLDICL XO30( 0)
352 #define RLDICR XO30( 1)
353 #define RLDIMI XO30( 3)
354 #define RLDCL XO30( 8)
355
356 #define BCLR XO19( 16)
357 #define BCCTR XO19(528)
358 #define CRAND XO19(257)
359 #define CRANDC XO19(129)
360 #define CRNAND XO19(225)
361 #define CROR XO19(449)
362 #define CRNOR XO19( 33)
363
364 #define EXTSB XO31(954)
365 #define EXTSH XO31(922)
366 #define EXTSW XO31(986)
367 #define ADD XO31(266)
368 #define ADDE XO31(138)
369 #define ADDC XO31( 10)
370 #define AND XO31( 28)
371 #define SUBF XO31( 40)
372 #define SUBFC XO31( 8)
373 #define SUBFE XO31(136)
374 #define OR XO31(444)
375 #define XOR XO31(316)
376 #define MULLW XO31(235)
377 #define MULHWU XO31( 11)
378 #define DIVW XO31(491)
379 #define DIVWU XO31(459)
380 #define CMP XO31( 0)
381 #define CMPL XO31( 32)
382 #define LHBRX XO31(790)
383 #define LWBRX XO31(534)
384 #define LDBRX XO31(532)
385 #define STHBRX XO31(918)
386 #define STWBRX XO31(662)
387 #define STDBRX XO31(660)
388 #define MFSPR XO31(339)
389 #define MTSPR XO31(467)
390 #define SRAWI XO31(824)
391 #define NEG XO31(104)
392 #define MFCR XO31( 19)
393 #define MFOCRF (MFCR | (1u << 20))
394 #define NOR XO31(124)
395 #define CNTLZW XO31( 26)
396 #define CNTLZD XO31( 58)
397 #define ANDC XO31( 60)
398 #define ORC XO31(412)
399 #define EQV XO31(284)
400 #define NAND XO31(476)
401 #define ISEL XO31( 15)
402
403 #define MULLD XO31(233)
404 #define MULHD XO31( 73)
405 #define MULHDU XO31( 9)
406 #define DIVD XO31(489)
407 #define DIVDU XO31(457)
408
409 #define LBZX XO31( 87)
410 #define LHZX XO31(279)
411 #define LHAX XO31(343)
412 #define LWZX XO31( 23)
413 #define STBX XO31(215)
414 #define STHX XO31(407)
415 #define STWX XO31(151)
416
417 #define SPR(a,b) ((((a)<<5)|(b))<<11)
418 #define LR SPR(8, 0)
419 #define CTR SPR(9, 0)
420
421 #define SLW XO31( 24)
422 #define SRW XO31(536)
423 #define SRAW XO31(792)
424
425 #define SLD XO31( 27)
426 #define SRD XO31(539)
427 #define SRAD XO31(794)
428 #define SRADI XO31(413<<1)
429
430 #define TW XO31( 4)
431 #define TRAP (TW | TO (31))
432
433 #define RT(r) ((r)<<21)
434 #define RS(r) ((r)<<21)
435 #define RA(r) ((r)<<16)
436 #define RB(r) ((r)<<11)
437 #define TO(t) ((t)<<21)
438 #define SH(s) ((s)<<11)
439 #define MB(b) ((b)<<6)
440 #define ME(e) ((e)<<1)
441 #define BO(o) ((o)<<21)
442 #define MB64(b) ((b)<<5)
443 #define FXM(b) (1 << (19 - (b)))
444
445 #define LK 1
446
447 #define TAB(t, a, b) (RT(t) | RA(a) | RB(b))
448 #define SAB(s, a, b) (RS(s) | RA(a) | RB(b))
449 #define TAI(s, a, i) (RT(s) | RA(a) | ((i) & 0xffff))
450 #define SAI(s, a, i) (RS(s) | RA(a) | ((i) & 0xffff))
451
452 #define BF(n) ((n)<<23)
453 #define BI(n, c) (((c)+((n)*4))<<16)
454 #define BT(n, c) (((c)+((n)*4))<<21)
455 #define BA(n, c) (((c)+((n)*4))<<16)
456 #define BB(n, c) (((c)+((n)*4))<<11)
457 #define BC_(n, c) (((c)+((n)*4))<<6)
458
459 #define BO_COND_TRUE BO (12)
460 #define BO_COND_FALSE BO ( 4)
461 #define BO_ALWAYS BO (20)
462
463 enum {
464 CR_LT,
465 CR_GT,
466 CR_EQ,
467 CR_SO
468 };
469
470 static const uint32_t tcg_to_bc[] = {
471 [TCG_COND_EQ] = BC | BI (7, CR_EQ) | BO_COND_TRUE,
472 [TCG_COND_NE] = BC | BI (7, CR_EQ) | BO_COND_FALSE,
473 [TCG_COND_LT] = BC | BI (7, CR_LT) | BO_COND_TRUE,
474 [TCG_COND_GE] = BC | BI (7, CR_LT) | BO_COND_FALSE,
475 [TCG_COND_LE] = BC | BI (7, CR_GT) | BO_COND_FALSE,
476 [TCG_COND_GT] = BC | BI (7, CR_GT) | BO_COND_TRUE,
477 [TCG_COND_LTU] = BC | BI (7, CR_LT) | BO_COND_TRUE,
478 [TCG_COND_GEU] = BC | BI (7, CR_LT) | BO_COND_FALSE,
479 [TCG_COND_LEU] = BC | BI (7, CR_GT) | BO_COND_FALSE,
480 [TCG_COND_GTU] = BC | BI (7, CR_GT) | BO_COND_TRUE,
481 };
482
483 /* The low bit here is set if the RA and RB fields must be inverted. */
484 static const uint32_t tcg_to_isel[] = {
485 [TCG_COND_EQ] = ISEL | BC_(7, CR_EQ),
486 [TCG_COND_NE] = ISEL | BC_(7, CR_EQ) | 1,
487 [TCG_COND_LT] = ISEL | BC_(7, CR_LT),
488 [TCG_COND_GE] = ISEL | BC_(7, CR_LT) | 1,
489 [TCG_COND_LE] = ISEL | BC_(7, CR_GT) | 1,
490 [TCG_COND_GT] = ISEL | BC_(7, CR_GT),
491 [TCG_COND_LTU] = ISEL | BC_(7, CR_LT),
492 [TCG_COND_GEU] = ISEL | BC_(7, CR_LT) | 1,
493 [TCG_COND_LEU] = ISEL | BC_(7, CR_GT) | 1,
494 [TCG_COND_GTU] = ISEL | BC_(7, CR_GT),
495 };
496
497 static inline void tcg_out_mov(TCGContext *s, TCGType type,
498 TCGReg ret, TCGReg arg)
499 {
500 tcg_out32 (s, OR | SAB (arg, ret, arg));
501 }
502
503 static inline void tcg_out_rld(TCGContext *s, int op, TCGReg ra, TCGReg rs,
504 int sh, int mb)
505 {
506 sh = SH (sh & 0x1f) | (((sh >> 5) & 1) << 1);
507 mb = MB64 ((mb >> 5) | ((mb << 1) & 0x3f));
508 tcg_out32 (s, op | RA (ra) | RS (rs) | sh | mb);
509 }
510
511 static inline void tcg_out_rlw(TCGContext *s, int op, TCGReg ra, TCGReg rs,
512 int sh, int mb, int me)
513 {
514 tcg_out32(s, op | RA(ra) | RS(rs) | SH(sh) | MB(mb) | ME(me));
515 }
516
517 static inline void tcg_out_ext32u(TCGContext *s, TCGReg dst, TCGReg src)
518 {
519 tcg_out_rld(s, RLDICL, dst, src, 0, 32);
520 }
521
522 static inline void tcg_out_shli64(TCGContext *s, TCGReg dst, TCGReg src, int c)
523 {
524 tcg_out_rld(s, RLDICR, dst, src, c, 63 - c);
525 }
526
527 static inline void tcg_out_shri64(TCGContext *s, TCGReg dst, TCGReg src, int c)
528 {
529 tcg_out_rld(s, RLDICL, dst, src, 64 - c, c);
530 }
531
532 static void tcg_out_movi32(TCGContext *s, TCGReg ret, int32_t arg)
533 {
534 if (arg == (int16_t) arg) {
535 tcg_out32(s, ADDI | TAI(ret, 0, arg));
536 } else {
537 tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16));
538 if (arg & 0xffff) {
539 tcg_out32(s, ORI | SAI(ret, ret, arg));
540 }
541 }
542 }
543
544 static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret,
545 tcg_target_long arg)
546 {
547 if (type == TCG_TYPE_I32 || arg == (int32_t)arg) {
548 tcg_out_movi32(s, ret, arg);
549 } else if (arg == (uint32_t)arg && !(arg & 0x8000)) {
550 tcg_out32(s, ADDI | TAI(ret, 0, arg));
551 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
552 } else {
553 int32_t high = arg >> 32;
554 tcg_out_movi32(s, ret, high);
555 if (high) {
556 tcg_out_shli64(s, ret, ret, 32);
557 }
558 if (arg & 0xffff0000) {
559 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
560 }
561 if (arg & 0xffff) {
562 tcg_out32(s, ORI | SAI(ret, ret, arg));
563 }
564 }
565 }
566
567 static bool mask_operand(uint32_t c, int *mb, int *me)
568 {
569 uint32_t lsb, test;
570
571 /* Accept a bit pattern like:
572 0....01....1
573 1....10....0
574 0..01..10..0
575 Keep track of the transitions. */
576 if (c == 0 || c == -1) {
577 return false;
578 }
579 test = c;
580 lsb = test & -test;
581 test += lsb;
582 if (test & (test - 1)) {
583 return false;
584 }
585
586 *me = clz32(lsb);
587 *mb = test ? clz32(test & -test) + 1 : 0;
588 return true;
589 }
590
591 static bool mask64_operand(uint64_t c, int *mb, int *me)
592 {
593 uint64_t lsb;
594
595 if (c == 0) {
596 return false;
597 }
598
599 lsb = c & -c;
600 /* Accept 1..10..0. */
601 if (c == -lsb) {
602 *mb = 0;
603 *me = clz64(lsb);
604 return true;
605 }
606 /* Accept 0..01..1. */
607 if (lsb == 1 && (c & (c + 1)) == 0) {
608 *mb = clz64(c + 1) + 1;
609 *me = 63;
610 return true;
611 }
612 return false;
613 }
614
615 static void tcg_out_andi32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
616 {
617 int mb, me;
618
619 if ((c & 0xffff) == c) {
620 tcg_out32(s, ANDI | SAI(src, dst, c));
621 return;
622 } else if ((c & 0xffff0000) == c) {
623 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
624 return;
625 } else if (mask_operand(c, &mb, &me)) {
626 tcg_out_rlw(s, RLWINM, dst, src, 0, mb, me);
627 } else {
628 tcg_out_movi(s, TCG_TYPE_I32, 0, c);
629 tcg_out32(s, AND | SAB(src, dst, 0));
630 }
631 }
632
633 static void tcg_out_andi64(TCGContext *s, TCGReg dst, TCGReg src, uint64_t c)
634 {
635 int mb, me;
636
637 if ((c & 0xffff) == c) {
638 tcg_out32(s, ANDI | SAI(src, dst, c));
639 return;
640 } else if ((c & 0xffff0000) == c) {
641 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
642 return;
643 } else if (mask64_operand(c, &mb, &me)) {
644 if (mb == 0) {
645 tcg_out_rld(s, RLDICR, dst, src, 0, me);
646 } else {
647 tcg_out_rld(s, RLDICL, dst, src, 0, mb);
648 }
649 } else {
650 tcg_out_movi(s, TCG_TYPE_I64, 0, c);
651 tcg_out32(s, AND | SAB(src, dst, 0));
652 }
653 }
654
655 static void tcg_out_zori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c,
656 int op_lo, int op_hi)
657 {
658 if (c >> 16) {
659 tcg_out32(s, op_hi | SAI(src, dst, c >> 16));
660 src = dst;
661 }
662 if (c & 0xffff) {
663 tcg_out32(s, op_lo | SAI(src, dst, c));
664 src = dst;
665 }
666 }
667
668 static void tcg_out_ori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
669 {
670 tcg_out_zori32(s, dst, src, c, ORI, ORIS);
671 }
672
673 static void tcg_out_xori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
674 {
675 tcg_out_zori32(s, dst, src, c, XORI, XORIS);
676 }
677
678 static void tcg_out_b (TCGContext *s, int mask, tcg_target_long target)
679 {
680 tcg_target_long disp;
681
682 disp = target - (tcg_target_long) s->code_ptr;
683 if ((disp << 38) >> 38 == disp)
684 tcg_out32 (s, B | (disp & 0x3fffffc) | mask);
685 else {
686 tcg_out_movi (s, TCG_TYPE_I64, 0, (tcg_target_long) target);
687 tcg_out32 (s, MTSPR | RS (0) | CTR);
688 tcg_out32 (s, BCCTR | BO_ALWAYS | mask);
689 }
690 }
691
692 static void tcg_out_call (TCGContext *s, tcg_target_long arg, int const_arg)
693 {
694 #ifdef __APPLE__
695 if (const_arg) {
696 tcg_out_b (s, LK, arg);
697 }
698 else {
699 tcg_out32 (s, MTSPR | RS (arg) | LR);
700 tcg_out32 (s, BCLR | BO_ALWAYS | LK);
701 }
702 #else
703 int reg;
704
705 if (const_arg) {
706 reg = 2;
707 tcg_out_movi (s, TCG_TYPE_I64, reg, arg);
708 }
709 else reg = arg;
710
711 tcg_out32 (s, LD | RT (0) | RA (reg));
712 tcg_out32 (s, MTSPR | RA (0) | CTR);
713 tcg_out32 (s, LD | RT (11) | RA (reg) | 16);
714 tcg_out32 (s, LD | RT (2) | RA (reg) | 8);
715 tcg_out32 (s, BCCTR | BO_ALWAYS | LK);
716 #endif
717 }
718
719 static void tcg_out_ldst(TCGContext *s, TCGReg ret, TCGReg addr,
720 int offset, int op1, int op2)
721 {
722 if (offset == (int16_t) offset) {
723 tcg_out32(s, op1 | TAI(ret, addr, offset));
724 } else {
725 tcg_out_movi(s, TCG_TYPE_I64, 0, offset);
726 tcg_out32(s, op2 | TAB(ret, addr, 0));
727 }
728 }
729
730 static void tcg_out_ldsta(TCGContext *s, TCGReg ret, TCGReg addr,
731 int offset, int op1, int op2)
732 {
733 if (offset == (int16_t) (offset & ~3)) {
734 tcg_out32(s, op1 | TAI(ret, addr, offset));
735 } else {
736 tcg_out_movi(s, TCG_TYPE_I64, 0, offset);
737 tcg_out32(s, op2 | TAB(ret, addr, 0));
738 }
739 }
740
741 #if defined (CONFIG_SOFTMMU)
742
743 #include "exec/softmmu_defs.h"
744
745 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
746 int mmu_idx) */
747 static const void * const qemu_ld_helpers[4] = {
748 helper_ldb_mmu,
749 helper_ldw_mmu,
750 helper_ldl_mmu,
751 helper_ldq_mmu,
752 };
753
754 /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
755 uintxx_t val, int mmu_idx) */
756 static const void * const qemu_st_helpers[4] = {
757 helper_stb_mmu,
758 helper_stw_mmu,
759 helper_stl_mmu,
760 helper_stq_mmu,
761 };
762
763 static void tcg_out_tlb_read(TCGContext *s, TCGReg r0, TCGReg r1, TCGReg r2,
764 TCGReg addr_reg, int s_bits, int offset)
765 {
766 #if TARGET_LONG_BITS == 32
767 tcg_out_ext32u(s, addr_reg, addr_reg);
768
769 tcg_out_rlw(s, RLWINM, r0, addr_reg,
770 32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
771 32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS),
772 31 - CPU_TLB_ENTRY_BITS);
773 tcg_out32(s, ADD | TAB(r0, r0, TCG_AREG0));
774 tcg_out32(s, LWZU | TAI(r1, r0, offset));
775 tcg_out_rlw(s, RLWINM, r2, addr_reg, 0,
776 (32 - s_bits) & 31, 31 - TARGET_PAGE_BITS);
777 #else
778 tcg_out_rld (s, RLDICL, r0, addr_reg,
779 64 - TARGET_PAGE_BITS,
780 64 - CPU_TLB_BITS);
781 tcg_out_shli64(s, r0, r0, CPU_TLB_ENTRY_BITS);
782
783 tcg_out32(s, ADD | TAB(r0, r0, TCG_AREG0));
784 tcg_out32(s, LD_ADDR | TAI(r1, r0, offset));
785
786 if (!s_bits) {
787 tcg_out_rld (s, RLDICR, r2, addr_reg, 0, 63 - TARGET_PAGE_BITS);
788 }
789 else {
790 tcg_out_rld (s, RLDICL, r2, addr_reg,
791 64 - TARGET_PAGE_BITS,
792 TARGET_PAGE_BITS - s_bits);
793 tcg_out_rld (s, RLDICL, r2, r2, TARGET_PAGE_BITS, 0);
794 }
795 #endif
796 }
797 #endif
798
799 static const uint32_t qemu_ldx_opc[8] = {
800 #ifdef TARGET_WORDS_BIGENDIAN
801 LBZX, LHZX, LWZX, LDX,
802 0, LHAX, LWAX, LDX
803 #else
804 LBZX, LHBRX, LWBRX, LDBRX,
805 0, 0, 0, LDBRX,
806 #endif
807 };
808
809 static const uint32_t qemu_stx_opc[4] = {
810 #ifdef TARGET_WORDS_BIGENDIAN
811 STBX, STHX, STWX, STDX
812 #else
813 STBX, STHBRX, STWBRX, STDBRX,
814 #endif
815 };
816
817 static const uint32_t qemu_exts_opc[4] = {
818 EXTSB, EXTSH, EXTSW, 0
819 };
820
821 static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
822 {
823 TCGReg addr_reg, data_reg, r0, r1, rbase;
824 uint32_t insn, s_bits;
825 #ifdef CONFIG_SOFTMMU
826 TCGReg r2, ir;
827 int mem_index;
828 void *label1_ptr, *label2_ptr;
829 #endif
830
831 data_reg = *args++;
832 addr_reg = *args++;
833 s_bits = opc & 3;
834
835 #ifdef CONFIG_SOFTMMU
836 mem_index = *args;
837
838 r0 = 3;
839 r1 = 4;
840 r2 = 0;
841 rbase = 0;
842
843 tcg_out_tlb_read (s, r0, r1, r2, addr_reg, s_bits,
844 offsetof (CPUArchState, tlb_table[mem_index][0].addr_read));
845
846 tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1) | CMP_L);
847
848 label1_ptr = s->code_ptr;
849 #ifdef FAST_PATH
850 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
851 #endif
852
853 /* slow path */
854 ir = 3;
855 tcg_out_mov (s, TCG_TYPE_I64, ir++, TCG_AREG0);
856 tcg_out_mov (s, TCG_TYPE_I64, ir++, addr_reg);
857 tcg_out_movi (s, TCG_TYPE_I64, ir++, mem_index);
858
859 tcg_out_call (s, (tcg_target_long) qemu_ld_helpers[s_bits], 1);
860
861 if (opc & 4) {
862 insn = qemu_exts_opc[s_bits];
863 tcg_out32(s, insn | RA(data_reg) | RS(3));
864 } else if (data_reg != 3) {
865 tcg_out_mov(s, TCG_TYPE_I64, data_reg, 3);
866 }
867 label2_ptr = s->code_ptr;
868 tcg_out32 (s, B);
869
870 /* label1: fast path */
871 #ifdef FAST_PATH
872 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
873 #endif
874
875 /* r0 now contains &env->tlb_table[mem_index][index].addr_read */
876 tcg_out32(s, LD | TAI(r0, r0,
877 offsetof(CPUTLBEntry, addend)
878 - offsetof(CPUTLBEntry, addr_read)));
879 /* r0 = env->tlb_table[mem_index][index].addend */
880 tcg_out32(s, ADD | TAB(r0, r0, addr_reg));
881 /* r0 = env->tlb_table[mem_index][index].addend + addr */
882
883 #else /* !CONFIG_SOFTMMU */
884 #if TARGET_LONG_BITS == 32
885 tcg_out_ext32u(s, addr_reg, addr_reg);
886 #endif
887 r0 = addr_reg;
888 r1 = 3;
889 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
890 #endif
891
892 insn = qemu_ldx_opc[opc];
893 if (!HAVE_ISA_2_06 && insn == LDBRX) {
894 tcg_out32(s, ADDI | TAI(r1, r0, 4));
895 tcg_out32(s, LWBRX | TAB(data_reg, rbase, r0));
896 tcg_out32(s, LWBRX | TAB( r1, rbase, r1));
897 tcg_out_rld(s, RLDIMI, data_reg, r1, 32, 0);
898 } else if (insn) {
899 tcg_out32(s, insn | TAB(data_reg, rbase, r0));
900 } else {
901 insn = qemu_ldx_opc[s_bits];
902 tcg_out32(s, insn | TAB(data_reg, rbase, r0));
903 insn = qemu_exts_opc[s_bits];
904 tcg_out32 (s, insn | RA(data_reg) | RS(data_reg));
905 }
906
907 #ifdef CONFIG_SOFTMMU
908 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
909 #endif
910 }
911
912 static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
913 {
914 TCGReg addr_reg, r0, r1, rbase, data_reg;
915 uint32_t insn;
916 #ifdef CONFIG_SOFTMMU
917 TCGReg r2, ir;
918 int mem_index;
919 void *label1_ptr, *label2_ptr;
920 #endif
921
922 data_reg = *args++;
923 addr_reg = *args++;
924
925 #ifdef CONFIG_SOFTMMU
926 mem_index = *args;
927
928 r0 = 3;
929 r1 = 4;
930 r2 = 0;
931 rbase = 0;
932
933 tcg_out_tlb_read (s, r0, r1, r2, addr_reg, opc,
934 offsetof (CPUArchState, tlb_table[mem_index][0].addr_write));
935
936 tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1) | CMP_L);
937
938 label1_ptr = s->code_ptr;
939 #ifdef FAST_PATH
940 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
941 #endif
942
943 /* slow path */
944 ir = 3;
945 tcg_out_mov (s, TCG_TYPE_I64, ir++, TCG_AREG0);
946 tcg_out_mov (s, TCG_TYPE_I64, ir++, addr_reg);
947 tcg_out_rld (s, RLDICL, ir++, data_reg, 0, 64 - (1 << (3 + opc)));
948 tcg_out_movi (s, TCG_TYPE_I64, ir++, mem_index);
949
950 tcg_out_call (s, (tcg_target_long) qemu_st_helpers[opc], 1);
951
952 label2_ptr = s->code_ptr;
953 tcg_out32 (s, B);
954
955 /* label1: fast path */
956 #ifdef FAST_PATH
957 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
958 #endif
959
960 tcg_out32 (s, (LD
961 | RT (r0)
962 | RA (r0)
963 | (offsetof (CPUTLBEntry, addend)
964 - offsetof (CPUTLBEntry, addr_write))
965 ));
966 /* r0 = env->tlb_table[mem_index][index].addend */
967 tcg_out32(s, ADD | TAB(r0, r0, addr_reg));
968 /* r0 = env->tlb_table[mem_index][index].addend + addr */
969
970 #else /* !CONFIG_SOFTMMU */
971 #if TARGET_LONG_BITS == 32
972 tcg_out_ext32u(s, addr_reg, addr_reg);
973 #endif
974 r1 = 3;
975 r0 = addr_reg;
976 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
977 #endif
978
979 insn = qemu_stx_opc[opc];
980 if (!HAVE_ISA_2_06 && insn == STDBRX) {
981 tcg_out32(s, STWBRX | SAB(data_reg, rbase, r0));
982 tcg_out32(s, ADDI | TAI(r1, r0, 4));
983 tcg_out_shri64(s, 0, data_reg, 32);
984 tcg_out32(s, STWBRX | SAB(0, rbase, r1));
985 } else {
986 tcg_out32(s, insn | SAB(data_reg, rbase, r0));
987 }
988
989 #ifdef CONFIG_SOFTMMU
990 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
991 #endif
992 }
993
994 static void tcg_target_qemu_prologue (TCGContext *s)
995 {
996 int i, frame_size;
997 #ifndef __APPLE__
998 uint64_t addr;
999 #endif
1000
1001 frame_size = 0
1002 + 8 /* back chain */
1003 + 8 /* CR */
1004 + 8 /* LR */
1005 + 8 /* compiler doubleword */
1006 + 8 /* link editor doubleword */
1007 + 8 /* TOC save area */
1008 + TCG_STATIC_CALL_ARGS_SIZE
1009 + ARRAY_SIZE (tcg_target_callee_save_regs) * 8
1010 + CPU_TEMP_BUF_NLONGS * sizeof(long)
1011 ;
1012 frame_size = (frame_size + 15) & ~15;
1013
1014 tcg_set_frame (s, TCG_REG_CALL_STACK, frame_size
1015 - CPU_TEMP_BUF_NLONGS * sizeof (long),
1016 CPU_TEMP_BUF_NLONGS * sizeof (long));
1017
1018 #ifndef __APPLE__
1019 /* First emit adhoc function descriptor */
1020 addr = (uint64_t) s->code_ptr + 24;
1021 tcg_out32 (s, addr >> 32); tcg_out32 (s, addr); /* entry point */
1022 s->code_ptr += 16; /* skip TOC and environment pointer */
1023 #endif
1024
1025 /* Prologue */
1026 tcg_out32 (s, MFSPR | RT (0) | LR);
1027 tcg_out32 (s, STDU | RS (1) | RA (1) | (-frame_size & 0xffff));
1028 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
1029 tcg_out32 (s, (STD
1030 | RS (tcg_target_callee_save_regs[i])
1031 | RA (1)
1032 | (i * 8 + 48 + TCG_STATIC_CALL_ARGS_SIZE)
1033 )
1034 );
1035 tcg_out32 (s, STD | RS (0) | RA (1) | (frame_size + 16));
1036
1037 #ifdef CONFIG_USE_GUEST_BASE
1038 if (GUEST_BASE) {
1039 tcg_out_movi (s, TCG_TYPE_I64, TCG_GUEST_BASE_REG, GUEST_BASE);
1040 tcg_regset_set_reg (s->reserved_regs, TCG_GUEST_BASE_REG);
1041 }
1042 #endif
1043
1044 tcg_out_mov (s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
1045 tcg_out32 (s, MTSPR | RS (tcg_target_call_iarg_regs[1]) | CTR);
1046 tcg_out32 (s, BCCTR | BO_ALWAYS);
1047
1048 /* Epilogue */
1049 tb_ret_addr = s->code_ptr;
1050
1051 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
1052 tcg_out32 (s, (LD
1053 | RT (tcg_target_callee_save_regs[i])
1054 | RA (1)
1055 | (i * 8 + 48 + TCG_STATIC_CALL_ARGS_SIZE)
1056 )
1057 );
1058 tcg_out32(s, LD | TAI(0, 1, frame_size + 16));
1059 tcg_out32(s, MTSPR | RS(0) | LR);
1060 tcg_out32(s, ADDI | TAI(1, 1, frame_size));
1061 tcg_out32(s, BCLR | BO_ALWAYS);
1062 }
1063
1064 static void tcg_out_ld (TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
1065 tcg_target_long arg2)
1066 {
1067 if (type == TCG_TYPE_I32)
1068 tcg_out_ldst (s, ret, arg1, arg2, LWZ, LWZX);
1069 else
1070 tcg_out_ldsta (s, ret, arg1, arg2, LD, LDX);
1071 }
1072
1073 static void tcg_out_st (TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1,
1074 tcg_target_long arg2)
1075 {
1076 if (type == TCG_TYPE_I32)
1077 tcg_out_ldst (s, arg, arg1, arg2, STW, STWX);
1078 else
1079 tcg_out_ldsta (s, arg, arg1, arg2, STD, STDX);
1080 }
1081
1082 static void tcg_out_cmp(TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
1083 int const_arg2, int cr, TCGType type)
1084 {
1085 int imm;
1086 uint32_t op;
1087
1088 /* Simplify the comparisons below wrt CMPI. */
1089 if (type == TCG_TYPE_I32) {
1090 arg2 = (int32_t)arg2;
1091 }
1092
1093 switch (cond) {
1094 case TCG_COND_EQ:
1095 case TCG_COND_NE:
1096 if (const_arg2) {
1097 if ((int16_t) arg2 == arg2) {
1098 op = CMPI;
1099 imm = 1;
1100 break;
1101 }
1102 else if ((uint16_t) arg2 == arg2) {
1103 op = CMPLI;
1104 imm = 1;
1105 break;
1106 }
1107 }
1108 op = CMPL;
1109 imm = 0;
1110 break;
1111
1112 case TCG_COND_LT:
1113 case TCG_COND_GE:
1114 case TCG_COND_LE:
1115 case TCG_COND_GT:
1116 if (const_arg2) {
1117 if ((int16_t) arg2 == arg2) {
1118 op = CMPI;
1119 imm = 1;
1120 break;
1121 }
1122 }
1123 op = CMP;
1124 imm = 0;
1125 break;
1126
1127 case TCG_COND_LTU:
1128 case TCG_COND_GEU:
1129 case TCG_COND_LEU:
1130 case TCG_COND_GTU:
1131 if (const_arg2) {
1132 if ((uint16_t) arg2 == arg2) {
1133 op = CMPLI;
1134 imm = 1;
1135 break;
1136 }
1137 }
1138 op = CMPL;
1139 imm = 0;
1140 break;
1141
1142 default:
1143 tcg_abort ();
1144 }
1145 op |= BF(cr) | ((type == TCG_TYPE_I64) << 21);
1146
1147 if (imm) {
1148 tcg_out32(s, op | RA(arg1) | (arg2 & 0xffff));
1149 } else {
1150 if (const_arg2) {
1151 tcg_out_movi(s, type, 0, arg2);
1152 arg2 = 0;
1153 }
1154 tcg_out32(s, op | RA(arg1) | RB(arg2));
1155 }
1156 }
1157
1158 static void tcg_out_setcond_eq0(TCGContext *s, TCGType type,
1159 TCGReg dst, TCGReg src)
1160 {
1161 tcg_out32(s, (type == TCG_TYPE_I64 ? CNTLZD : CNTLZW) | RS(src) | RA(dst));
1162 tcg_out_shri64(s, dst, dst, type == TCG_TYPE_I64 ? 6 : 5);
1163 }
1164
1165 static void tcg_out_setcond_ne0(TCGContext *s, TCGReg dst, TCGReg src)
1166 {
1167 /* X != 0 implies X + -1 generates a carry. Extra addition
1168 trickery means: R = X-1 + ~X + C = X-1 + (-X+1) + C = C. */
1169 if (dst != src) {
1170 tcg_out32(s, ADDIC | TAI(dst, src, -1));
1171 tcg_out32(s, SUBFE | TAB(dst, dst, src));
1172 } else {
1173 tcg_out32(s, ADDIC | TAI(0, src, -1));
1174 tcg_out32(s, SUBFE | TAB(dst, 0, src));
1175 }
1176 }
1177
1178 static TCGReg tcg_gen_setcond_xor(TCGContext *s, TCGReg arg1, TCGArg arg2,
1179 bool const_arg2)
1180 {
1181 if (const_arg2) {
1182 if ((uint32_t)arg2 == arg2) {
1183 tcg_out_xori32(s, TCG_REG_R0, arg1, arg2);
1184 } else {
1185 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, arg2);
1186 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, TCG_REG_R0));
1187 }
1188 } else {
1189 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, arg2));
1190 }
1191 return TCG_REG_R0;
1192 }
1193
1194 static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond,
1195 TCGArg arg0, TCGArg arg1, TCGArg arg2,
1196 int const_arg2)
1197 {
1198 int crop, sh;
1199
1200 /* Ignore high bits of a potential constant arg2. */
1201 if (type == TCG_TYPE_I32) {
1202 arg2 = (uint32_t)arg2;
1203 }
1204
1205 /* Handle common and trivial cases before handling anything else. */
1206 if (arg2 == 0) {
1207 switch (cond) {
1208 case TCG_COND_EQ:
1209 tcg_out_setcond_eq0(s, type, arg0, arg1);
1210 return;
1211 case TCG_COND_NE:
1212 if (type == TCG_TYPE_I32) {
1213 tcg_out_ext32u(s, TCG_REG_R0, arg1);
1214 arg1 = TCG_REG_R0;
1215 }
1216 tcg_out_setcond_ne0(s, arg0, arg1);
1217 return;
1218 case TCG_COND_GE:
1219 tcg_out32(s, NOR | SAB(arg1, arg0, arg1));
1220 arg1 = arg0;
1221 /* FALLTHRU */
1222 case TCG_COND_LT:
1223 /* Extract the sign bit. */
1224 tcg_out_rld(s, RLDICL, arg0, arg1,
1225 type == TCG_TYPE_I64 ? 1 : 33, 63);
1226 return;
1227 default:
1228 break;
1229 }
1230 }
1231
1232 /* If we have ISEL, we can implement everything with 3 or 4 insns.
1233 All other cases below are also at least 3 insns, so speed up the
1234 code generator by not considering them and always using ISEL. */
1235 if (HAVE_ISEL) {
1236 int isel, tab;
1237
1238 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1239
1240 isel = tcg_to_isel[cond];
1241
1242 tcg_out_movi(s, type, arg0, 1);
1243 if (isel & 1) {
1244 /* arg0 = (bc ? 0 : 1) */
1245 tab = TAB(arg0, 0, arg0);
1246 isel &= ~1;
1247 } else {
1248 /* arg0 = (bc ? 1 : 0) */
1249 tcg_out_movi(s, type, TCG_REG_R0, 0);
1250 tab = TAB(arg0, arg0, TCG_REG_R0);
1251 }
1252 tcg_out32(s, isel | tab);
1253 return;
1254 }
1255
1256 switch (cond) {
1257 case TCG_COND_EQ:
1258 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
1259 tcg_out_setcond_eq0(s, type, arg0, arg1);
1260 return;
1261
1262 case TCG_COND_NE:
1263 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
1264 /* Discard the high bits only once, rather than both inputs. */
1265 if (type == TCG_TYPE_I32) {
1266 tcg_out_ext32u(s, TCG_REG_R0, arg1);
1267 arg1 = TCG_REG_R0;
1268 }
1269 tcg_out_setcond_ne0(s, arg0, arg1);
1270 return;
1271
1272 case TCG_COND_GT:
1273 case TCG_COND_GTU:
1274 sh = 30;
1275 crop = 0;
1276 goto crtest;
1277
1278 case TCG_COND_LT:
1279 case TCG_COND_LTU:
1280 sh = 29;
1281 crop = 0;
1282 goto crtest;
1283
1284 case TCG_COND_GE:
1285 case TCG_COND_GEU:
1286 sh = 31;
1287 crop = CRNOR | BT (7, CR_EQ) | BA (7, CR_LT) | BB (7, CR_LT);
1288 goto crtest;
1289
1290 case TCG_COND_LE:
1291 case TCG_COND_LEU:
1292 sh = 31;
1293 crop = CRNOR | BT (7, CR_EQ) | BA (7, CR_GT) | BB (7, CR_GT);
1294 crtest:
1295 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1296 if (crop) {
1297 tcg_out32(s, crop);
1298 }
1299 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7));
1300 tcg_out_rlw(s, RLWINM, arg0, TCG_REG_R0, sh, 31, 31);
1301 break;
1302
1303 default:
1304 tcg_abort ();
1305 }
1306 }
1307
1308 static void tcg_out_bc (TCGContext *s, int bc, int label_index)
1309 {
1310 TCGLabel *l = &s->labels[label_index];
1311
1312 if (l->has_value)
1313 tcg_out32 (s, bc | reloc_pc14_val (s->code_ptr, l->u.value));
1314 else {
1315 uint16_t val = *(uint16_t *) &s->code_ptr[2];
1316
1317 /* Thanks to Andrzej Zaborowski */
1318 tcg_out32 (s, bc | (val & 0xfffc));
1319 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL14, label_index, 0);
1320 }
1321 }
1322
1323 static void tcg_out_brcond(TCGContext *s, TCGCond cond,
1324 TCGArg arg1, TCGArg arg2, int const_arg2,
1325 int label_index, TCGType type)
1326 {
1327 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1328 tcg_out_bc(s, tcg_to_bc[cond], label_index);
1329 }
1330
1331 static void tcg_out_movcond(TCGContext *s, TCGType type, TCGCond cond,
1332 TCGArg dest, TCGArg c1, TCGArg c2, TCGArg v1,
1333 TCGArg v2, bool const_c2)
1334 {
1335 /* If for some reason both inputs are zero, don't produce bad code. */
1336 if (v1 == 0 && v2 == 0) {
1337 tcg_out_movi(s, type, dest, 0);
1338 return;
1339 }
1340
1341 tcg_out_cmp(s, cond, c1, c2, const_c2, 7, type);
1342
1343 if (HAVE_ISEL) {
1344 int isel = tcg_to_isel[cond];
1345
1346 /* Swap the V operands if the operation indicates inversion. */
1347 if (isel & 1) {
1348 int t = v1;
1349 v1 = v2;
1350 v2 = t;
1351 isel &= ~1;
1352 }
1353 /* V1 == 0 is handled by isel; V2 == 0 must be handled by hand. */
1354 if (v2 == 0) {
1355 tcg_out_movi(s, type, 0, 0);
1356 }
1357 tcg_out32(s, isel | TAB(dest, v1, v2));
1358 } else {
1359 if (dest == v2) {
1360 cond = tcg_invert_cond(cond);
1361 v2 = v1;
1362 } else if (dest != v1) {
1363 if (v1 == 0) {
1364 tcg_out_movi(s, type, dest, 0);
1365 } else {
1366 tcg_out_mov(s, type, dest, v1);
1367 }
1368 }
1369 /* Branch forward over one insn */
1370 tcg_out32(s, tcg_to_bc[cond] | 8);
1371 if (v2 == 0) {
1372 tcg_out_movi(s, type, dest, 0);
1373 } else {
1374 tcg_out_mov(s, type, dest, v2);
1375 }
1376 }
1377 }
1378
1379 void ppc_tb_set_jmp_target (unsigned long jmp_addr, unsigned long addr)
1380 {
1381 TCGContext s;
1382 unsigned long patch_size;
1383
1384 s.code_ptr = (uint8_t *) jmp_addr;
1385 tcg_out_b (&s, 0, addr);
1386 patch_size = s.code_ptr - (uint8_t *) jmp_addr;
1387 flush_icache_range (jmp_addr, jmp_addr + patch_size);
1388 }
1389
1390 static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args,
1391 const int *const_args)
1392 {
1393 TCGArg a0, a1, a2;
1394 int c;
1395
1396 switch (opc) {
1397 case INDEX_op_exit_tb:
1398 tcg_out_movi (s, TCG_TYPE_I64, TCG_REG_R3, args[0]);
1399 tcg_out_b (s, 0, (tcg_target_long) tb_ret_addr);
1400 break;
1401 case INDEX_op_goto_tb:
1402 if (s->tb_jmp_offset) {
1403 /* direct jump method */
1404
1405 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1406 s->code_ptr += 28;
1407 }
1408 else {
1409 tcg_abort ();
1410 }
1411 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1412 break;
1413 case INDEX_op_br:
1414 {
1415 TCGLabel *l = &s->labels[args[0]];
1416
1417 if (l->has_value) {
1418 tcg_out_b (s, 0, l->u.value);
1419 }
1420 else {
1421 uint32_t val = *(uint32_t *) s->code_ptr;
1422
1423 /* Thanks to Andrzej Zaborowski */
1424 tcg_out32 (s, B | (val & 0x3fffffc));
1425 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL24, args[0], 0);
1426 }
1427 }
1428 break;
1429 case INDEX_op_call:
1430 tcg_out_call (s, args[0], const_args[0]);
1431 break;
1432 case INDEX_op_movi_i32:
1433 tcg_out_movi (s, TCG_TYPE_I32, args[0], args[1]);
1434 break;
1435 case INDEX_op_movi_i64:
1436 tcg_out_movi (s, TCG_TYPE_I64, args[0], args[1]);
1437 break;
1438 case INDEX_op_ld8u_i32:
1439 case INDEX_op_ld8u_i64:
1440 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1441 break;
1442 case INDEX_op_ld8s_i32:
1443 case INDEX_op_ld8s_i64:
1444 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1445 tcg_out32 (s, EXTSB | RS (args[0]) | RA (args[0]));
1446 break;
1447 case INDEX_op_ld16u_i32:
1448 case INDEX_op_ld16u_i64:
1449 tcg_out_ldst (s, args[0], args[1], args[2], LHZ, LHZX);
1450 break;
1451 case INDEX_op_ld16s_i32:
1452 case INDEX_op_ld16s_i64:
1453 tcg_out_ldst (s, args[0], args[1], args[2], LHA, LHAX);
1454 break;
1455 case INDEX_op_ld_i32:
1456 case INDEX_op_ld32u_i64:
1457 tcg_out_ldst (s, args[0], args[1], args[2], LWZ, LWZX);
1458 break;
1459 case INDEX_op_ld32s_i64:
1460 tcg_out_ldsta (s, args[0], args[1], args[2], LWA, LWAX);
1461 break;
1462 case INDEX_op_ld_i64:
1463 tcg_out_ldsta (s, args[0], args[1], args[2], LD, LDX);
1464 break;
1465 case INDEX_op_st8_i32:
1466 case INDEX_op_st8_i64:
1467 tcg_out_ldst (s, args[0], args[1], args[2], STB, STBX);
1468 break;
1469 case INDEX_op_st16_i32:
1470 case INDEX_op_st16_i64:
1471 tcg_out_ldst (s, args[0], args[1], args[2], STH, STHX);
1472 break;
1473 case INDEX_op_st_i32:
1474 case INDEX_op_st32_i64:
1475 tcg_out_ldst (s, args[0], args[1], args[2], STW, STWX);
1476 break;
1477 case INDEX_op_st_i64:
1478 tcg_out_ldsta (s, args[0], args[1], args[2], STD, STDX);
1479 break;
1480
1481 case INDEX_op_add_i32:
1482 a0 = args[0], a1 = args[1], a2 = args[2];
1483 if (const_args[2]) {
1484 int32_t l, h;
1485 do_addi_32:
1486 l = (int16_t)a2;
1487 h = a2 - l;
1488 if (h) {
1489 tcg_out32(s, ADDIS | TAI(a0, a1, h >> 16));
1490 a1 = a0;
1491 }
1492 if (l || a0 != a1) {
1493 tcg_out32(s, ADDI | TAI(a0, a1, l));
1494 }
1495 } else {
1496 tcg_out32(s, ADD | TAB(a0, a1, a2));
1497 }
1498 break;
1499 case INDEX_op_sub_i32:
1500 a0 = args[0], a1 = args[1], a2 = args[2];
1501 if (const_args[1]) {
1502 if (const_args[2]) {
1503 tcg_out_movi(s, TCG_TYPE_I32, a0, a1 - a2);
1504 } else {
1505 tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
1506 }
1507 } else if (const_args[2]) {
1508 a2 = -a2;
1509 goto do_addi_32;
1510 } else {
1511 tcg_out32(s, SUBF | TAB(a0, a2, a1));
1512 }
1513 break;
1514
1515 case INDEX_op_and_i32:
1516 a0 = args[0], a1 = args[1], a2 = args[2];
1517 if (const_args[2]) {
1518 tcg_out_andi32(s, a0, a1, a2);
1519 } else {
1520 tcg_out32(s, AND | SAB(a1, a0, a2));
1521 }
1522 break;
1523 case INDEX_op_and_i64:
1524 a0 = args[0], a1 = args[1], a2 = args[2];
1525 if (const_args[2]) {
1526 tcg_out_andi64(s, a0, a1, a2);
1527 } else {
1528 tcg_out32(s, AND | SAB(a1, a0, a2));
1529 }
1530 break;
1531 case INDEX_op_or_i64:
1532 case INDEX_op_or_i32:
1533 a0 = args[0], a1 = args[1], a2 = args[2];
1534 if (const_args[2]) {
1535 tcg_out_ori32(s, a0, a1, a2);
1536 } else {
1537 tcg_out32(s, OR | SAB(a1, a0, a2));
1538 }
1539 break;
1540 case INDEX_op_xor_i64:
1541 case INDEX_op_xor_i32:
1542 a0 = args[0], a1 = args[1], a2 = args[2];
1543 if (const_args[2]) {
1544 tcg_out_xori32(s, a0, a1, a2);
1545 } else {
1546 tcg_out32(s, XOR | SAB(a1, a0, a2));
1547 }
1548 break;
1549 case INDEX_op_andc_i32:
1550 a0 = args[0], a1 = args[1], a2 = args[2];
1551 if (const_args[2]) {
1552 tcg_out_andi32(s, a0, a1, ~a2);
1553 } else {
1554 tcg_out32(s, ANDC | SAB(a1, a0, a2));
1555 }
1556 break;
1557 case INDEX_op_andc_i64:
1558 a0 = args[0], a1 = args[1], a2 = args[2];
1559 if (const_args[2]) {
1560 tcg_out_andi64(s, a0, a1, ~a2);
1561 } else {
1562 tcg_out32(s, ANDC | SAB(a1, a0, a2));
1563 }
1564 break;
1565 case INDEX_op_orc_i32:
1566 if (const_args[2]) {
1567 tcg_out_ori32(s, args[0], args[1], ~args[2]);
1568 break;
1569 }
1570 /* FALLTHRU */
1571 case INDEX_op_orc_i64:
1572 tcg_out32(s, ORC | SAB(args[1], args[0], args[2]));
1573 break;
1574 case INDEX_op_eqv_i32:
1575 if (const_args[2]) {
1576 tcg_out_xori32(s, args[0], args[1], ~args[2]);
1577 break;
1578 }
1579 /* FALLTHRU */
1580 case INDEX_op_eqv_i64:
1581 tcg_out32(s, EQV | SAB(args[1], args[0], args[2]));
1582 break;
1583 case INDEX_op_nand_i32:
1584 case INDEX_op_nand_i64:
1585 tcg_out32(s, NAND | SAB(args[1], args[0], args[2]));
1586 break;
1587 case INDEX_op_nor_i32:
1588 case INDEX_op_nor_i64:
1589 tcg_out32(s, NOR | SAB(args[1], args[0], args[2]));
1590 break;
1591
1592 case INDEX_op_mul_i32:
1593 a0 = args[0], a1 = args[1], a2 = args[2];
1594 if (const_args[2]) {
1595 tcg_out32(s, MULLI | TAI(a0, a1, a2));
1596 } else {
1597 tcg_out32(s, MULLW | TAB(a0, a1, a2));
1598 }
1599 break;
1600
1601 case INDEX_op_div_i32:
1602 tcg_out32 (s, DIVW | TAB (args[0], args[1], args[2]));
1603 break;
1604
1605 case INDEX_op_divu_i32:
1606 tcg_out32 (s, DIVWU | TAB (args[0], args[1], args[2]));
1607 break;
1608
1609 case INDEX_op_rem_i32:
1610 tcg_out32 (s, DIVW | TAB (0, args[1], args[2]));
1611 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1612 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1613 break;
1614
1615 case INDEX_op_remu_i32:
1616 tcg_out32 (s, DIVWU | TAB (0, args[1], args[2]));
1617 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1618 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1619 break;
1620
1621 case INDEX_op_shl_i32:
1622 if (const_args[2]) {
1623 tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31 - args[2]);
1624 } else {
1625 tcg_out32 (s, SLW | SAB (args[1], args[0], args[2]));
1626 }
1627 break;
1628 case INDEX_op_shr_i32:
1629 if (const_args[2]) {
1630 tcg_out_rlw(s, RLWINM, args[0], args[1], 32 - args[2], args[2], 31);
1631 } else {
1632 tcg_out32 (s, SRW | SAB (args[1], args[0], args[2]));
1633 }
1634 break;
1635 case INDEX_op_sar_i32:
1636 if (const_args[2])
1637 tcg_out32 (s, SRAWI | RS (args[1]) | RA (args[0]) | SH (args[2]));
1638 else
1639 tcg_out32 (s, SRAW | SAB (args[1], args[0], args[2]));
1640 break;
1641 case INDEX_op_rotl_i32:
1642 if (const_args[2]) {
1643 tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31);
1644 } else {
1645 tcg_out32(s, RLWNM | SAB(args[1], args[0], args[2])
1646 | MB(0) | ME(31));
1647 }
1648 break;
1649 case INDEX_op_rotr_i32:
1650 if (const_args[2]) {
1651 tcg_out_rlw(s, RLWINM, args[0], args[1], 32 - args[2], 0, 31);
1652 } else {
1653 tcg_out32(s, SUBFIC | TAI(0, args[2], 32));
1654 tcg_out32(s, RLWNM | SAB(args[1], args[0], args[2])
1655 | MB(0) | ME(31));
1656 }
1657 break;
1658
1659 case INDEX_op_brcond_i32:
1660 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
1661 args[3], TCG_TYPE_I32);
1662 break;
1663
1664 case INDEX_op_brcond_i64:
1665 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
1666 args[3], TCG_TYPE_I64);
1667 break;
1668
1669 case INDEX_op_neg_i32:
1670 case INDEX_op_neg_i64:
1671 tcg_out32 (s, NEG | RT (args[0]) | RA (args[1]));
1672 break;
1673
1674 case INDEX_op_not_i32:
1675 case INDEX_op_not_i64:
1676 tcg_out32 (s, NOR | SAB (args[1], args[0], args[1]));
1677 break;
1678
1679 case INDEX_op_add_i64:
1680 a0 = args[0], a1 = args[1], a2 = args[2];
1681 if (const_args[2]) {
1682 int32_t l0, h1, h2;
1683 do_addi_64:
1684 /* We can always split any 32-bit signed constant into 3 pieces.
1685 Note the positive 0x80000000 coming from the sub_i64 path,
1686 handled with the same code we need for eg 0x7fff8000. */
1687 assert(a2 == (int32_t)a2 || a2 == 0x80000000);
1688 l0 = (int16_t)a2;
1689 h1 = a2 - l0;
1690 h2 = 0;
1691 if (h1 < 0 && (int64_t)a2 > 0) {
1692 h2 = 0x40000000;
1693 h1 = a2 - h2 - l0;
1694 }
1695 assert((TCGArg)h2 + h1 + l0 == a2);
1696
1697 if (h2) {
1698 tcg_out32(s, ADDIS | TAI(a0, a1, h2 >> 16));
1699 a1 = a0;
1700 }
1701 if (h1) {
1702 tcg_out32(s, ADDIS | TAI(a0, a1, h1 >> 16));
1703 a1 = a0;
1704 }
1705 if (l0 || a0 != a1) {
1706 tcg_out32(s, ADDI | TAI(a0, a1, l0));
1707 }
1708 } else {
1709 tcg_out32(s, ADD | TAB(a0, a1, a2));
1710 }
1711 break;
1712 case INDEX_op_sub_i64:
1713 a0 = args[0], a1 = args[1], a2 = args[2];
1714 if (const_args[1]) {
1715 if (const_args[2]) {
1716 tcg_out_movi(s, TCG_TYPE_I64, a0, a1 - a2);
1717 } else {
1718 tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
1719 }
1720 } else if (const_args[2]) {
1721 a2 = -a2;
1722 goto do_addi_64;
1723 } else {
1724 tcg_out32(s, SUBF | TAB(a0, a2, a1));
1725 }
1726 break;
1727
1728 case INDEX_op_shl_i64:
1729 if (const_args[2])
1730 tcg_out_shli64(s, args[0], args[1], args[2]);
1731 else
1732 tcg_out32 (s, SLD | SAB (args[1], args[0], args[2]));
1733 break;
1734 case INDEX_op_shr_i64:
1735 if (const_args[2])
1736 tcg_out_shri64(s, args[0], args[1], args[2]);
1737 else
1738 tcg_out32 (s, SRD | SAB (args[1], args[0], args[2]));
1739 break;
1740 case INDEX_op_sar_i64:
1741 if (const_args[2]) {
1742 int sh = SH (args[2] & 0x1f) | (((args[2] >> 5) & 1) << 1);
1743 tcg_out32 (s, SRADI | RA (args[0]) | RS (args[1]) | sh);
1744 }
1745 else
1746 tcg_out32 (s, SRAD | SAB (args[1], args[0], args[2]));
1747 break;
1748 case INDEX_op_rotl_i64:
1749 if (const_args[2]) {
1750 tcg_out_rld(s, RLDICL, args[0], args[1], args[2], 0);
1751 } else {
1752 tcg_out32(s, RLDCL | SAB(args[1], args[0], args[2]) | MB64(0));
1753 }
1754 break;
1755 case INDEX_op_rotr_i64:
1756 if (const_args[2]) {
1757 tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 0);
1758 } else {
1759 tcg_out32(s, SUBFIC | TAI(0, args[2], 64));
1760 tcg_out32(s, RLDCL | SAB(args[1], args[0], 0) | MB64(0));
1761 }
1762 break;
1763
1764 case INDEX_op_mul_i64:
1765 a0 = args[0], a1 = args[1], a2 = args[2];
1766 if (const_args[2]) {
1767 tcg_out32(s, MULLI | TAI(a0, a1, a2));
1768 } else {
1769 tcg_out32(s, MULLD | TAB(a0, a1, a2));
1770 }
1771 break;
1772 case INDEX_op_div_i64:
1773 tcg_out32 (s, DIVD | TAB (args[0], args[1], args[2]));
1774 break;
1775 case INDEX_op_divu_i64:
1776 tcg_out32 (s, DIVDU | TAB (args[0], args[1], args[2]));
1777 break;
1778 case INDEX_op_rem_i64:
1779 tcg_out32 (s, DIVD | TAB (0, args[1], args[2]));
1780 tcg_out32 (s, MULLD | TAB (0, 0, args[2]));
1781 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1782 break;
1783 case INDEX_op_remu_i64:
1784 tcg_out32 (s, DIVDU | TAB (0, args[1], args[2]));
1785 tcg_out32 (s, MULLD | TAB (0, 0, args[2]));
1786 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1787 break;
1788
1789 case INDEX_op_qemu_ld8u:
1790 tcg_out_qemu_ld (s, args, 0);
1791 break;
1792 case INDEX_op_qemu_ld8s:
1793 tcg_out_qemu_ld (s, args, 0 | 4);
1794 break;
1795 case INDEX_op_qemu_ld16u:
1796 tcg_out_qemu_ld (s, args, 1);
1797 break;
1798 case INDEX_op_qemu_ld16s:
1799 tcg_out_qemu_ld (s, args, 1 | 4);
1800 break;
1801 case INDEX_op_qemu_ld32:
1802 case INDEX_op_qemu_ld32u:
1803 tcg_out_qemu_ld (s, args, 2);
1804 break;
1805 case INDEX_op_qemu_ld32s:
1806 tcg_out_qemu_ld (s, args, 2 | 4);
1807 break;
1808 case INDEX_op_qemu_ld64:
1809 tcg_out_qemu_ld (s, args, 3);
1810 break;
1811 case INDEX_op_qemu_st8:
1812 tcg_out_qemu_st (s, args, 0);
1813 break;
1814 case INDEX_op_qemu_st16:
1815 tcg_out_qemu_st (s, args, 1);
1816 break;
1817 case INDEX_op_qemu_st32:
1818 tcg_out_qemu_st (s, args, 2);
1819 break;
1820 case INDEX_op_qemu_st64:
1821 tcg_out_qemu_st (s, args, 3);
1822 break;
1823
1824 case INDEX_op_ext8s_i32:
1825 case INDEX_op_ext8s_i64:
1826 c = EXTSB;
1827 goto gen_ext;
1828 case INDEX_op_ext16s_i32:
1829 case INDEX_op_ext16s_i64:
1830 c = EXTSH;
1831 goto gen_ext;
1832 case INDEX_op_ext32s_i64:
1833 c = EXTSW;
1834 goto gen_ext;
1835 gen_ext:
1836 tcg_out32 (s, c | RS (args[1]) | RA (args[0]));
1837 break;
1838
1839 case INDEX_op_setcond_i32:
1840 tcg_out_setcond (s, TCG_TYPE_I32, args[3], args[0], args[1], args[2],
1841 const_args[2]);
1842 break;
1843 case INDEX_op_setcond_i64:
1844 tcg_out_setcond (s, TCG_TYPE_I64, args[3], args[0], args[1], args[2],
1845 const_args[2]);
1846 break;
1847
1848 case INDEX_op_bswap16_i32:
1849 case INDEX_op_bswap16_i64:
1850 a0 = args[0], a1 = args[1];
1851 /* a1 = abcd */
1852 if (a0 != a1) {
1853 /* a0 = (a1 r<< 24) & 0xff # 000c */
1854 tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
1855 /* a0 = (a0 & ~0xff00) | (a1 r<< 8) & 0xff00 # 00dc */
1856 tcg_out_rlw(s, RLWIMI, a0, a1, 8, 16, 23);
1857 } else {
1858 /* r0 = (a1 r<< 8) & 0xff00 # 00d0 */
1859 tcg_out_rlw(s, RLWINM, TCG_REG_R0, a1, 8, 16, 23);
1860 /* a0 = (a1 r<< 24) & 0xff # 000c */
1861 tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
1862 /* a0 = a0 | r0 # 00dc */
1863 tcg_out32(s, OR | SAB(TCG_REG_R0, a0, a0));
1864 }
1865 break;
1866
1867 case INDEX_op_bswap32_i32:
1868 case INDEX_op_bswap32_i64:
1869 /* Stolen from gcc's builtin_bswap32 */
1870 a1 = args[1];
1871 a0 = args[0] == a1 ? TCG_REG_R0 : args[0];
1872
1873 /* a1 = args[1] # abcd */
1874 /* a0 = rotate_left (a1, 8) # bcda */
1875 tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
1876 /* a0 = (a0 & ~0xff000000) | ((a1 r<< 24) & 0xff000000) # dcda */
1877 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
1878 /* a0 = (a0 & ~0x0000ff00) | ((a1 r<< 24) & 0x0000ff00) # dcba */
1879 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
1880
1881 if (a0 == TCG_REG_R0) {
1882 tcg_out_mov(s, TCG_TYPE_I64, args[0], a0);
1883 }
1884 break;
1885
1886 case INDEX_op_bswap64_i64:
1887 a0 = args[0], a1 = args[1], a2 = 0;
1888 if (a0 == a1) {
1889 a0 = 0;
1890 a2 = a1;
1891 }
1892
1893 /* a1 = # abcd efgh */
1894 /* a0 = rl32(a1, 8) # 0000 fghe */
1895 tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
1896 /* a0 = dep(a0, rl32(a1, 24), 0xff000000) # 0000 hghe */
1897 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
1898 /* a0 = dep(a0, rl32(a1, 24), 0x0000ff00) # 0000 hgfe */
1899 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
1900
1901 /* a0 = rl64(a0, 32) # hgfe 0000 */
1902 /* a2 = rl64(a1, 32) # efgh abcd */
1903 tcg_out_rld(s, RLDICL, a0, a0, 32, 0);
1904 tcg_out_rld(s, RLDICL, a2, a1, 32, 0);
1905
1906 /* a0 = dep(a0, rl32(a2, 8), 0xffffffff) # hgfe bcda */
1907 tcg_out_rlw(s, RLWIMI, a0, a2, 8, 0, 31);
1908 /* a0 = dep(a0, rl32(a2, 24), 0xff000000) # hgfe dcda */
1909 tcg_out_rlw(s, RLWIMI, a0, a2, 24, 0, 7);
1910 /* a0 = dep(a0, rl32(a2, 24), 0x0000ff00) # hgfe dcba */
1911 tcg_out_rlw(s, RLWIMI, a0, a2, 24, 16, 23);
1912
1913 if (a0 == 0) {
1914 tcg_out_mov(s, TCG_TYPE_I64, args[0], a0);
1915 /* Revert the source rotate that we performed above. */
1916 tcg_out_rld(s, RLDICL, a1, a1, 32, 0);
1917 }
1918 break;
1919
1920 case INDEX_op_deposit_i32:
1921 tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3],
1922 32 - args[3] - args[4], 31 - args[3]);
1923 break;
1924 case INDEX_op_deposit_i64:
1925 tcg_out_rld(s, RLDIMI, args[0], args[2], args[3],
1926 64 - args[3] - args[4]);
1927 break;
1928
1929 case INDEX_op_movcond_i32:
1930 tcg_out_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], args[2],
1931 args[3], args[4], const_args[2]);
1932 break;
1933 case INDEX_op_movcond_i64:
1934 tcg_out_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], args[2],
1935 args[3], args[4], const_args[2]);
1936 break;
1937
1938 default:
1939 tcg_dump_ops (s);
1940 tcg_abort ();
1941 }
1942 }
1943
1944 static const TCGTargetOpDef ppc_op_defs[] = {
1945 { INDEX_op_exit_tb, { } },
1946 { INDEX_op_goto_tb, { } },
1947 { INDEX_op_call, { "ri" } },
1948 { INDEX_op_br, { } },
1949
1950 { INDEX_op_mov_i32, { "r", "r" } },
1951 { INDEX_op_mov_i64, { "r", "r" } },
1952 { INDEX_op_movi_i32, { "r" } },
1953 { INDEX_op_movi_i64, { "r" } },
1954
1955 { INDEX_op_ld8u_i32, { "r", "r" } },
1956 { INDEX_op_ld8s_i32, { "r", "r" } },
1957 { INDEX_op_ld16u_i32, { "r", "r" } },
1958 { INDEX_op_ld16s_i32, { "r", "r" } },
1959 { INDEX_op_ld_i32, { "r", "r" } },
1960 { INDEX_op_ld_i64, { "r", "r" } },
1961 { INDEX_op_st8_i32, { "r", "r" } },
1962 { INDEX_op_st8_i64, { "r", "r" } },
1963 { INDEX_op_st16_i32, { "r", "r" } },
1964 { INDEX_op_st16_i64, { "r", "r" } },
1965 { INDEX_op_st_i32, { "r", "r" } },
1966 { INDEX_op_st_i64, { "r", "r" } },
1967 { INDEX_op_st32_i64, { "r", "r" } },
1968
1969 { INDEX_op_ld8u_i64, { "r", "r" } },
1970 { INDEX_op_ld8s_i64, { "r", "r" } },
1971 { INDEX_op_ld16u_i64, { "r", "r" } },
1972 { INDEX_op_ld16s_i64, { "r", "r" } },
1973 { INDEX_op_ld32u_i64, { "r", "r" } },
1974 { INDEX_op_ld32s_i64, { "r", "r" } },
1975
1976 { INDEX_op_add_i32, { "r", "r", "ri" } },
1977 { INDEX_op_mul_i32, { "r", "r", "rI" } },
1978 { INDEX_op_div_i32, { "r", "r", "r" } },
1979 { INDEX_op_divu_i32, { "r", "r", "r" } },
1980 { INDEX_op_rem_i32, { "r", "r", "r" } },
1981 { INDEX_op_remu_i32, { "r", "r", "r" } },
1982 { INDEX_op_sub_i32, { "r", "rI", "ri" } },
1983 { INDEX_op_and_i32, { "r", "r", "ri" } },
1984 { INDEX_op_or_i32, { "r", "r", "ri" } },
1985 { INDEX_op_xor_i32, { "r", "r", "ri" } },
1986 { INDEX_op_andc_i32, { "r", "r", "ri" } },
1987 { INDEX_op_orc_i32, { "r", "r", "ri" } },
1988 { INDEX_op_eqv_i32, { "r", "r", "ri" } },
1989 { INDEX_op_nand_i32, { "r", "r", "r" } },
1990 { INDEX_op_nor_i32, { "r", "r", "r" } },
1991
1992 { INDEX_op_shl_i32, { "r", "r", "ri" } },
1993 { INDEX_op_shr_i32, { "r", "r", "ri" } },
1994 { INDEX_op_sar_i32, { "r", "r", "ri" } },
1995 { INDEX_op_rotl_i32, { "r", "r", "ri" } },
1996 { INDEX_op_rotr_i32, { "r", "r", "ri" } },
1997
1998 { INDEX_op_brcond_i32, { "r", "ri" } },
1999 { INDEX_op_brcond_i64, { "r", "ri" } },
2000
2001 { INDEX_op_neg_i32, { "r", "r" } },
2002 { INDEX_op_not_i32, { "r", "r" } },
2003
2004 { INDEX_op_add_i64, { "r", "r", "rT" } },
2005 { INDEX_op_sub_i64, { "r", "rI", "rT" } },
2006 { INDEX_op_and_i64, { "r", "r", "ri" } },
2007 { INDEX_op_or_i64, { "r", "r", "rU" } },
2008 { INDEX_op_xor_i64, { "r", "r", "rU" } },
2009 { INDEX_op_andc_i64, { "r", "r", "ri" } },
2010 { INDEX_op_orc_i64, { "r", "r", "r" } },
2011 { INDEX_op_eqv_i64, { "r", "r", "r" } },
2012 { INDEX_op_nand_i64, { "r", "r", "r" } },
2013 { INDEX_op_nor_i64, { "r", "r", "r" } },
2014
2015 { INDEX_op_shl_i64, { "r", "r", "ri" } },
2016 { INDEX_op_shr_i64, { "r", "r", "ri" } },
2017 { INDEX_op_sar_i64, { "r", "r", "ri" } },
2018 { INDEX_op_rotl_i64, { "r", "r", "ri" } },
2019 { INDEX_op_rotr_i64, { "r", "r", "ri" } },
2020
2021 { INDEX_op_mul_i64, { "r", "r", "rI" } },
2022 { INDEX_op_div_i64, { "r", "r", "r" } },
2023 { INDEX_op_divu_i64, { "r", "r", "r" } },
2024 { INDEX_op_rem_i64, { "r", "r", "r" } },
2025 { INDEX_op_remu_i64, { "r", "r", "r" } },
2026
2027 { INDEX_op_neg_i64, { "r", "r" } },
2028 { INDEX_op_not_i64, { "r", "r" } },
2029
2030 { INDEX_op_qemu_ld8u, { "r", "L" } },
2031 { INDEX_op_qemu_ld8s, { "r", "L" } },
2032 { INDEX_op_qemu_ld16u, { "r", "L" } },
2033 { INDEX_op_qemu_ld16s, { "r", "L" } },
2034 { INDEX_op_qemu_ld32, { "r", "L" } },
2035 { INDEX_op_qemu_ld32u, { "r", "L" } },
2036 { INDEX_op_qemu_ld32s, { "r", "L" } },
2037 { INDEX_op_qemu_ld64, { "r", "L" } },
2038
2039 { INDEX_op_qemu_st8, { "S", "S" } },
2040 { INDEX_op_qemu_st16, { "S", "S" } },
2041 { INDEX_op_qemu_st32, { "S", "S" } },
2042 { INDEX_op_qemu_st64, { "S", "S" } },
2043
2044 { INDEX_op_ext8s_i32, { "r", "r" } },
2045 { INDEX_op_ext16s_i32, { "r", "r" } },
2046 { INDEX_op_ext8s_i64, { "r", "r" } },
2047 { INDEX_op_ext16s_i64, { "r", "r" } },
2048 { INDEX_op_ext32s_i64, { "r", "r" } },
2049
2050 { INDEX_op_setcond_i32, { "r", "r", "ri" } },
2051 { INDEX_op_setcond_i64, { "r", "r", "ri" } },
2052 { INDEX_op_movcond_i32, { "r", "r", "ri", "rZ", "rZ" } },
2053 { INDEX_op_movcond_i64, { "r", "r", "ri", "rZ", "rZ" } },
2054
2055 { INDEX_op_bswap16_i32, { "r", "r" } },
2056 { INDEX_op_bswap16_i64, { "r", "r" } },
2057 { INDEX_op_bswap32_i32, { "r", "r" } },
2058 { INDEX_op_bswap32_i64, { "r", "r" } },
2059 { INDEX_op_bswap64_i64, { "r", "r" } },
2060
2061 { INDEX_op_deposit_i32, { "r", "0", "r" } },
2062 { INDEX_op_deposit_i64, { "r", "0", "r" } },
2063
2064 { -1 },
2065 };
2066
2067 static void tcg_target_init (TCGContext *s)
2068 {
2069 #ifdef CONFIG_GETAUXVAL
2070 unsigned long hwcap = getauxval(AT_HWCAP);
2071 if (hwcap & PPC_FEATURE_ARCH_2_06) {
2072 have_isa_2_06 = true;
2073 }
2074 #endif
2075
2076 tcg_regset_set32 (tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
2077 tcg_regset_set32 (tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
2078 tcg_regset_set32 (tcg_target_call_clobber_regs, 0,
2079 (1 << TCG_REG_R0) |
2080 #ifdef __APPLE__
2081 (1 << TCG_REG_R2) |
2082 #endif
2083 (1 << TCG_REG_R3) |
2084 (1 << TCG_REG_R4) |
2085 (1 << TCG_REG_R5) |
2086 (1 << TCG_REG_R6) |
2087 (1 << TCG_REG_R7) |
2088 (1 << TCG_REG_R8) |
2089 (1 << TCG_REG_R9) |
2090 (1 << TCG_REG_R10) |
2091 (1 << TCG_REG_R11) |
2092 (1 << TCG_REG_R12)
2093 );
2094
2095 tcg_regset_clear (s->reserved_regs);
2096 tcg_regset_set_reg (s->reserved_regs, TCG_REG_R0);
2097 tcg_regset_set_reg (s->reserved_regs, TCG_REG_R1);
2098 #ifndef __APPLE__
2099 tcg_regset_set_reg (s->reserved_regs, TCG_REG_R2);
2100 #endif
2101 tcg_regset_set_reg (s->reserved_regs, TCG_REG_R13);
2102
2103 tcg_add_target_add_op_defs (ppc_op_defs);
2104 }
Qemu copy for testing