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Reduce amount of space reserved for tb jump
[qemu.git] / tcg / ppc64 / tcg-target.c
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 static uint8_t *tb_ret_addr;
26
27 #define FAST_PATH
28
29 #if TARGET_PHYS_ADDR_BITS == 32
30 #define LD_ADDEND LWZ
31 #else
32 #define LD_ADDEND LD
33 #endif
34
35 #if TARGET_LONG_BITS == 32
36 #define LD_ADDR LWZU
37 #else
38 #define LD_ADDR LDU
39 #endif
40
41 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
42 "r0",
43 "r1",
44 "rp",
45 "r3",
46 "r4",
47 "r5",
48 "r6",
49 "r7",
50 "r8",
51 "r9",
52 "r10",
53 "r11",
54 "r12",
55 "r13",
56 "r14",
57 "r15",
58 "r16",
59 "r17",
60 "r18",
61 "r19",
62 "r20",
63 "r21",
64 "r22",
65 "r23",
66 "r24",
67 "r25",
68 "r26",
69 "r27",
70 "r28",
71 "r29",
72 "r30",
73 "r31"
74 };
75
76 static const int tcg_target_reg_alloc_order[] = {
77 TCG_REG_R14,
78 TCG_REG_R15,
79 TCG_REG_R16,
80 TCG_REG_R17,
81 TCG_REG_R18,
82 TCG_REG_R19,
83 TCG_REG_R20,
84 TCG_REG_R21,
85 TCG_REG_R22,
86 TCG_REG_R23,
87 TCG_REG_R28,
88 TCG_REG_R29,
89 TCG_REG_R30,
90 TCG_REG_R31,
91 TCG_REG_R3,
92 TCG_REG_R4,
93 TCG_REG_R5,
94 TCG_REG_R6,
95 TCG_REG_R7,
96 TCG_REG_R8,
97 TCG_REG_R9,
98 TCG_REG_R10,
99 TCG_REG_R11,
100 TCG_REG_R12,
101 TCG_REG_R13,
102 TCG_REG_R0,
103 TCG_REG_R1,
104 TCG_REG_R2,
105 TCG_REG_R24,
106 TCG_REG_R25,
107 TCG_REG_R26,
108 TCG_REG_R27
109 };
110
111 static const int tcg_target_call_iarg_regs[] = {
112 TCG_REG_R3,
113 TCG_REG_R4,
114 TCG_REG_R5,
115 TCG_REG_R6,
116 TCG_REG_R7,
117 TCG_REG_R8,
118 TCG_REG_R9,
119 TCG_REG_R10
120 };
121
122 static const int tcg_target_call_oarg_regs[2] = {
123 TCG_REG_R3
124 };
125
126 static const int tcg_target_callee_save_regs[] = {
127 TCG_REG_R14,
128 TCG_REG_R15,
129 TCG_REG_R16,
130 TCG_REG_R17,
131 TCG_REG_R18,
132 TCG_REG_R19,
133 TCG_REG_R20,
134 TCG_REG_R21,
135 TCG_REG_R22,
136 TCG_REG_R23,
137 TCG_REG_R28,
138 TCG_REG_R29,
139 TCG_REG_R30,
140 TCG_REG_R31
141 };
142
143 static uint32_t reloc_pc24_val (void *pc, tcg_target_long target)
144 {
145 tcg_target_long disp;
146
147 disp = target - (tcg_target_long) pc;
148 if ((disp << 38) >> 38 != disp)
149 tcg_abort ();
150
151 return disp & 0x3fffffc;
152 }
153
154 static void reloc_pc24 (void *pc, tcg_target_long target)
155 {
156 *(uint32_t *) pc = (*(uint32_t *) pc & ~0x3fffffc)
157 | reloc_pc24_val (pc, target);
158 }
159
160 static uint16_t reloc_pc14_val (void *pc, tcg_target_long target)
161 {
162 tcg_target_long disp;
163
164 disp = target - (tcg_target_long) pc;
165 if (disp != (int16_t) disp)
166 tcg_abort ();
167
168 return disp & 0xfffc;
169 }
170
171 static void reloc_pc14 (void *pc, tcg_target_long target)
172 {
173 *(uint32_t *) pc = (*(uint32_t *) pc & ~0xfffc)
174 | reloc_pc14_val (pc, target);
175 }
176
177 static void patch_reloc (uint8_t *code_ptr, int type,
178 tcg_target_long value, tcg_target_long addend)
179 {
180 value += addend;
181 switch (type) {
182 case R_PPC_REL14:
183 reloc_pc14 (code_ptr, value);
184 break;
185 case R_PPC_REL24:
186 reloc_pc24 (code_ptr, value);
187 break;
188 default:
189 tcg_abort ();
190 }
191 }
192
193 /* maximum number of register used for input function arguments */
194 static int tcg_target_get_call_iarg_regs_count (int flags)
195 {
196 return sizeof (tcg_target_call_iarg_regs) / sizeof (tcg_target_call_iarg_regs[0]);
197 }
198
199 /* parse target specific constraints */
200 static int target_parse_constraint (TCGArgConstraint *ct, const char **pct_str)
201 {
202 const char *ct_str;
203
204 ct_str = *pct_str;
205 switch (ct_str[0]) {
206 case 'A': case 'B': case 'C': case 'D':
207 ct->ct |= TCG_CT_REG;
208 tcg_regset_set_reg (ct->u.regs, 3 + ct_str[0] - 'A');
209 break;
210 case 'r':
211 ct->ct |= TCG_CT_REG;
212 tcg_regset_set32 (ct->u.regs, 0, 0xffffffff);
213 break;
214 case 'L': /* qemu_ld constraint */
215 ct->ct |= TCG_CT_REG;
216 tcg_regset_set32 (ct->u.regs, 0, 0xffffffff);
217 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3);
218 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4);
219 break;
220 case 'K': /* qemu_st[8..32] constraint */
221 ct->ct |= TCG_CT_REG;
222 tcg_regset_set32 (ct->u.regs, 0, 0xffffffff);
223 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3);
224 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4);
225 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R5);
226 #if TARGET_LONG_BITS == 64
227 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R6);
228 #endif
229 break;
230 case 'M': /* qemu_st64 constraint */
231 ct->ct |= TCG_CT_REG;
232 tcg_regset_set32 (ct->u.regs, 0, 0xffffffff);
233 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3);
234 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4);
235 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R5);
236 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R6);
237 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R7);
238 break;
239 default:
240 return -1;
241 }
242 ct_str++;
243 *pct_str = ct_str;
244 return 0;
245 }
246
247 /* test if a constant matches the constraint */
248 static int tcg_target_const_match (tcg_target_long val,
249 const TCGArgConstraint *arg_ct)
250 {
251 int ct;
252
253 ct = arg_ct->ct;
254 if (ct & TCG_CT_CONST)
255 return 1;
256 return 0;
257 }
258
259 #define OPCD(opc) ((opc)<<26)
260 #define XO19(opc) (OPCD(19)|((opc)<<1))
261 #define XO30(opc) (OPCD(30)|((opc)<<2))
262 #define XO31(opc) (OPCD(31)|((opc)<<1))
263 #define XO58(opc) (OPCD(58)|(opc))
264 #define XO62(opc) (OPCD(62)|(opc))
265
266 #define B OPCD( 18)
267 #define BC OPCD( 16)
268 #define LBZ OPCD( 34)
269 #define LHZ OPCD( 40)
270 #define LHA OPCD( 42)
271 #define LWZ OPCD( 32)
272 #define STB OPCD( 38)
273 #define STH OPCD( 44)
274 #define STW OPCD( 36)
275
276 #define STD XO62( 0)
277 #define STDU XO62( 1)
278 #define STDX XO31(149)
279
280 #define LD XO58( 0)
281 #define LDX XO31( 21)
282 #define LDU XO58( 1)
283 #define LWA XO58( 10)
284 #define LWAX XO31(341)
285
286 #define ADDI OPCD( 14)
287 #define ADDIS OPCD( 15)
288 #define ORI OPCD( 24)
289 #define ORIS OPCD( 25)
290 #define XORI OPCD( 26)
291 #define XORIS OPCD( 27)
292 #define ANDI OPCD( 28)
293 #define ANDIS OPCD( 29)
294 #define MULLI OPCD( 7)
295 #define CMPLI OPCD( 10)
296 #define CMPI OPCD( 11)
297
298 #define LWZU OPCD( 33)
299 #define STWU OPCD( 37)
300
301 #define RLWINM OPCD( 21)
302
303 #define RLDICL XO30( 0)
304 #define RLDICR XO30( 1)
305
306 #define BCLR XO19( 16)
307 #define BCCTR XO19(528)
308 #define CRAND XO19(257)
309 #define CRANDC XO19(129)
310 #define CRNAND XO19(225)
311 #define CROR XO19(449)
312
313 #define EXTSB XO31(954)
314 #define EXTSH XO31(922)
315 #define EXTSW XO31(986)
316 #define ADD XO31(266)
317 #define ADDE XO31(138)
318 #define ADDC XO31( 10)
319 #define AND XO31( 28)
320 #define SUBF XO31( 40)
321 #define SUBFC XO31( 8)
322 #define SUBFE XO31(136)
323 #define OR XO31(444)
324 #define XOR XO31(316)
325 #define MULLW XO31(235)
326 #define MULHWU XO31( 11)
327 #define DIVW XO31(491)
328 #define DIVWU XO31(459)
329 #define CMP XO31( 0)
330 #define CMPL XO31( 32)
331 #define LHBRX XO31(790)
332 #define LWBRX XO31(534)
333 #define STHBRX XO31(918)
334 #define STWBRX XO31(662)
335 #define MFSPR XO31(339)
336 #define MTSPR XO31(467)
337 #define SRAWI XO31(824)
338 #define NEG XO31(104)
339
340 #define MULLD XO31(233)
341 #define MULHD XO31( 73)
342 #define MULHDU XO31( 9)
343 #define DIVD XO31(489)
344 #define DIVDU XO31(457)
345
346 #define LBZX XO31( 87)
347 #define LHZX XO31(276)
348 #define LHAX XO31(343)
349 #define LWZX XO31( 23)
350 #define STBX XO31(215)
351 #define STHX XO31(407)
352 #define STWX XO31(151)
353
354 #define SPR(a,b) ((((a)<<5)|(b))<<11)
355 #define LR SPR(8, 0)
356 #define CTR SPR(9, 0)
357
358 #define SLW XO31( 24)
359 #define SRW XO31(536)
360 #define SRAW XO31(792)
361
362 #define SLD XO31( 27)
363 #define SRD XO31(539)
364 #define SRAD XO31(794)
365
366 #define LMW OPCD( 46)
367 #define STMW OPCD( 47)
368
369 #define TW XO31( 4)
370 #define TRAP (TW | TO (31))
371
372 #define RT(r) ((r)<<21)
373 #define RS(r) ((r)<<21)
374 #define RA(r) ((r)<<16)
375 #define RB(r) ((r)<<11)
376 #define TO(t) ((t)<<21)
377 #define SH(s) ((s)<<11)
378 #define MB(b) ((b)<<6)
379 #define ME(e) ((e)<<1)
380 #define BO(o) ((o)<<21)
381 #define MB64(b) ((b)<<5)
382
383 #define LK 1
384
385 #define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
386 #define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
387
388 #define BF(n) ((n)<<23)
389 #define BI(n, c) (((c)+((n)*4))<<16)
390 #define BT(n, c) (((c)+((n)*4))<<21)
391 #define BA(n, c) (((c)+((n)*4))<<16)
392 #define BB(n, c) (((c)+((n)*4))<<11)
393
394 #define BO_COND_TRUE BO (12)
395 #define BO_COND_FALSE BO ( 4)
396 #define BO_ALWAYS BO (20)
397
398 enum {
399 CR_LT,
400 CR_GT,
401 CR_EQ,
402 CR_SO
403 };
404
405 static const uint32_t tcg_to_bc[10] = {
406 [TCG_COND_EQ] = BC | BI (7, CR_EQ) | BO_COND_TRUE,
407 [TCG_COND_NE] = BC | BI (7, CR_EQ) | BO_COND_FALSE,
408 [TCG_COND_LT] = BC | BI (7, CR_LT) | BO_COND_TRUE,
409 [TCG_COND_GE] = BC | BI (7, CR_LT) | BO_COND_FALSE,
410 [TCG_COND_LE] = BC | BI (7, CR_GT) | BO_COND_FALSE,
411 [TCG_COND_GT] = BC | BI (7, CR_GT) | BO_COND_TRUE,
412 [TCG_COND_LTU] = BC | BI (7, CR_LT) | BO_COND_TRUE,
413 [TCG_COND_GEU] = BC | BI (7, CR_LT) | BO_COND_FALSE,
414 [TCG_COND_LEU] = BC | BI (7, CR_GT) | BO_COND_FALSE,
415 [TCG_COND_GTU] = BC | BI (7, CR_GT) | BO_COND_TRUE,
416 };
417
418 static void tcg_out_mov (TCGContext *s, int ret, int arg)
419 {
420 tcg_out32 (s, OR | SAB (arg, ret, arg));
421 }
422
423 static void tcg_out_rld (TCGContext *s, int op, int ra, int rs, int sh, int mb)
424 {
425 sh = SH (sh & 0x1f) | (((sh >> 5) & 1) << 1);
426 mb = MB64 ((mb >> 5) | ((mb << 1) & 0x3f));
427 tcg_out32 (s, op | RA (ra) | RS (rs) | sh | mb);
428 }
429
430 static void tcg_out_movi32 (TCGContext *s, int ret, int32_t arg)
431 {
432 if (arg == (int16_t) arg)
433 tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff));
434 else {
435 tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff));
436 if (arg & 0xffff)
437 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
438 }
439 }
440
441 static void tcg_out_movi (TCGContext *s, TCGType type,
442 int ret, tcg_target_long arg)
443 {
444 int32_t arg32 = arg;
445
446 if (type == TCG_TYPE_I32 || arg == arg32) {
447 tcg_out_movi32 (s, ret, arg32);
448 }
449 else {
450 if ((uint64_t) arg >> 32) {
451 uint16_t h16 = arg >> 16;
452 uint16_t l16 = arg;
453
454 tcg_out_movi32 (s, ret, (arg >> 32) + (arg32 < 0));
455 tcg_out_rld (s, RLDICR, ret, ret, 32, 31);
456 if (h16) tcg_out32 (s, ORIS | RS (ret) | RA (ret) | h16);
457 if (l16) tcg_out32 (s, ORI | RS (ret) | RA (ret) | l16);
458 }
459 else {
460 tcg_out_movi32 (s, ret, arg32);
461 if (arg32 < 0)
462 tcg_out_rld (s, RLDICL, ret, ret, 0, 32);
463 }
464 }
465 }
466
467 static void tcg_out_call (TCGContext *s, tcg_target_long arg, int const_arg)
468 {
469 int reg;
470
471 if (const_arg) {
472 reg = 2;
473 tcg_out_movi (s, TCG_TYPE_I64, reg, arg);
474 }
475 else reg = arg;
476
477 tcg_out32 (s, LD | RT (0) | RA (reg));
478 tcg_out32 (s, MTSPR | RA (0) | CTR);
479 tcg_out32 (s, LD | RT (11) | RA (reg) | 16);
480 tcg_out32 (s, LD | RT (2) | RA (reg) | 8);
481 tcg_out32 (s, BCCTR | BO_ALWAYS | LK);
482 }
483
484 static void tcg_out_ldst (TCGContext *s, int ret, int addr,
485 int offset, int op1, int op2)
486 {
487 if (offset == (int16_t) offset)
488 tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff));
489 else {
490 tcg_out_movi (s, TCG_TYPE_I64, 0, offset);
491 tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
492 }
493 }
494
495 static void tcg_out_b (TCGContext *s, int mask, tcg_target_long target)
496 {
497 tcg_target_long disp;
498
499 disp = target - (tcg_target_long) s->code_ptr;
500 if ((disp << 38) >> 38 == disp)
501 tcg_out32 (s, B | (disp & 0x3fffffc) | mask);
502 else {
503 tcg_out_movi (s, TCG_TYPE_I64, 0, (tcg_target_long) target);
504 tcg_out32 (s, MTSPR | RS (0) | CTR);
505 tcg_out32 (s, BCCTR | BO_ALWAYS | mask);
506 }
507 }
508
509 #if defined (CONFIG_SOFTMMU)
510 extern void __ldb_mmu(void);
511 extern void __ldw_mmu(void);
512 extern void __ldl_mmu(void);
513 extern void __ldq_mmu(void);
514
515 extern void __stb_mmu(void);
516 extern void __stw_mmu(void);
517 extern void __stl_mmu(void);
518 extern void __stq_mmu(void);
519
520 static void *qemu_ld_helpers[4] = {
521 __ldb_mmu,
522 __ldw_mmu,
523 __ldl_mmu,
524 __ldq_mmu,
525 };
526
527 static void *qemu_st_helpers[4] = {
528 __stb_mmu,
529 __stw_mmu,
530 __stl_mmu,
531 __stq_mmu,
532 };
533 #endif
534
535 static void tcg_out_tlb_read (TCGContext *s, int r0, int r1, int r2,
536 int addr_reg, int s_bits, int offset)
537 {
538 #if TARGET_LONG_BITS == 32
539 tcg_out_rld (s, RLDICL, addr_reg, addr_reg, 0, 32);
540 #endif
541
542 tcg_out_rld (s, RLDICL, r0, addr_reg,
543 64 - TARGET_PAGE_BITS,
544 64 - CPU_TLB_BITS);
545 tcg_out_rld (s, RLDICR, r0, r0,
546 CPU_TLB_ENTRY_BITS,
547 63 - CPU_TLB_ENTRY_BITS);
548
549 tcg_out32 (s, ADD | TAB (r0, r0, TCG_AREG0));
550 tcg_out32 (s, LD_ADDR | RT (r1) | RA (r0) | offset);
551
552 tcg_out_rld (s, RLDICL, r2, addr_reg,
553 64 - TARGET_PAGE_BITS,
554 TARGET_PAGE_BITS - s_bits);
555 tcg_out_rld (s, RLDICL, r2, r2, TARGET_PAGE_BITS, 0);
556 }
557
558 static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
559 {
560 int addr_reg, data_reg, r0, mem_index, s_bits, bswap;
561 #ifdef CONFIG_SOFTMMU
562 int r1, r2;
563 void *label1_ptr, *label2_ptr;
564 #endif
565
566 data_reg = *args++;
567 addr_reg = *args++;
568 mem_index = *args;
569 s_bits = opc & 3;
570
571 #ifdef CONFIG_SOFTMMU
572 r0 = 3;
573 r1 = 4;
574 r2 = 0;
575
576 tcg_out_tlb_read (s, r0, r1, r2, addr_reg, s_bits,
577 offsetof (CPUState, tlb_table[mem_index][0].addr_read));
578
579 tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1));
580
581 label1_ptr = s->code_ptr;
582 #ifdef FAST_PATH
583 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
584 #endif
585
586 /* slow path */
587 tcg_out_mov (s, 3, addr_reg);
588 tcg_out_movi (s, TCG_TYPE_I64, 4, mem_index);
589
590 tcg_out_call (s, (tcg_target_long) qemu_ld_helpers[s_bits], 1);
591
592 switch (opc) {
593 case 0|4:
594 tcg_out32 (s, EXTSB | RA (data_reg) | RS (3));
595 break;
596 case 1|4:
597 tcg_out32 (s, EXTSH | RA (data_reg) | RS (3));
598 break;
599 case 2|4:
600 tcg_out32 (s, EXTSW | RA (data_reg) | RS (3));
601 break;
602 case 0:
603 case 1:
604 case 2:
605 case 3:
606 if (data_reg != 3)
607 tcg_out_mov (s, data_reg, 3);
608 break;
609 }
610 label2_ptr = s->code_ptr;
611 tcg_out32 (s, B);
612
613 /* label1: fast path */
614 #ifdef FAST_PATH
615 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
616 #endif
617
618 /* r0 now contains &env->tlb_table[mem_index][index].addr_read */
619 tcg_out32 (s, (LD_ADDEND
620 | RT (r0)
621 | RA (r0)
622 | (offsetof (CPUTLBEntry, addend)
623 - offsetof (CPUTLBEntry, addr_read))
624 ));
625 /* r0 = env->tlb_table[mem_index][index].addend */
626 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
627 /* r0 = env->tlb_table[mem_index][index].addend + addr */
628
629 #else /* !CONFIG_SOFTMMU */
630 r0 = addr_reg;
631 #endif
632
633 #ifdef TARGET_WORDS_BIGENDIAN
634 bswap = 0;
635 #else
636 bswap = 1;
637 #endif
638 switch (opc) {
639 default:
640 case 0:
641 tcg_out32 (s, LBZ | RT (data_reg) | RA (r0));
642 break;
643 case 0|4:
644 tcg_out32 (s, LBZ | RT (data_reg) | RA (r0));
645 tcg_out32 (s, EXTSB | RA (data_reg) | RS (data_reg));
646 break;
647 case 1:
648 if (bswap) tcg_out32 (s, LHBRX | RT (data_reg) | RB (r0));
649 else tcg_out32 (s, LHZ | RT (data_reg) | RA (r0));
650 break;
651 case 1|4:
652 if (bswap) {
653 tcg_out32 (s, LHBRX | RT (data_reg) | RB (r0));
654 tcg_out32 (s, EXTSH | RA (data_reg) | RS (data_reg));
655 }
656 else tcg_out32 (s, LHA | RT (data_reg) | RA (r0));
657 break;
658 case 2:
659 if (bswap) tcg_out32 (s, LWBRX | RT (data_reg) | RB (r0));
660 else tcg_out32 (s, LWZ | RT (data_reg)| RA (r0));
661 break;
662 case 2|4:
663 if (bswap) {
664 tcg_out32 (s, LWBRX | RT (data_reg) | RB (r0));
665 tcg_out32 (s, EXTSW | RA (data_reg) | RS (data_reg));
666 }
667 else tcg_out32 (s, LWA | RT (data_reg)| RA (r0));
668 break;
669 case 3:
670 if (bswap) {
671 tcg_out32 (s, LWBRX | RT (data_reg) | RB (r0));
672 tcg_out32 (s, ADDI | RT (r0) | RA (r0) | 4);
673 tcg_out32 (s, LWBRX | RT (r0) | RB (r0));
674 tcg_out_rld (s, RLDICR, r0, r0, 32, 31);
675 tcg_out32 (s, OR | SAB (r0, data_reg, data_reg));
676 }
677 else tcg_out32 (s, LD | RT (data_reg) | RA (r0));
678 break;
679 }
680
681 #ifdef CONFIG_SOFTMMU
682 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
683 #endif
684 }
685
686 static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
687 {
688 int addr_reg, r0, r1, data_reg, mem_index, bswap;
689 #ifdef CONFIG_SOFTMMU
690 int r2;
691 void *label1_ptr, *label2_ptr;
692 #endif
693
694 data_reg = *args++;
695 addr_reg = *args++;
696 mem_index = *args;
697
698 #ifdef CONFIG_SOFTMMU
699 r0 = 3;
700 r1 = 4;
701 r2 = 0;
702
703 tcg_out_tlb_read (s, r0, r1, r2, addr_reg, opc,
704 offsetof (CPUState, tlb_table[mem_index][0].addr_write));
705
706 tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1));
707
708 label1_ptr = s->code_ptr;
709 #ifdef FAST_PATH
710 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
711 #endif
712
713 /* slow path */
714 tcg_out_mov (s, 3, addr_reg);
715 tcg_out_rld (s, RLDICL, 4, data_reg, 0, 64 - (1 << (3 + opc)));
716 tcg_out_movi (s, TCG_TYPE_I64, 5, mem_index);
717
718 tcg_out_call (s, (tcg_target_long) qemu_st_helpers[opc], 1);
719
720 label2_ptr = s->code_ptr;
721 tcg_out32 (s, B);
722
723 /* label1: fast path */
724 #ifdef FAST_PATH
725 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
726 #endif
727
728 tcg_out32 (s, (LD_ADDEND
729 | RT (r0)
730 | RA (r0)
731 | (offsetof (CPUTLBEntry, addend)
732 - offsetof (CPUTLBEntry, addr_write))
733 ));
734 /* r0 = env->tlb_table[mem_index][index].addend */
735 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
736 /* r0 = env->tlb_table[mem_index][index].addend + addr */
737
738 #else /* !CONFIG_SOFTMMU */
739 r1 = 4;
740 r0 = addr_reg;
741 #endif
742
743 #ifdef TARGET_WORDS_BIGENDIAN
744 bswap = 0;
745 #else
746 bswap = 1;
747 #endif
748 switch (opc) {
749 case 0:
750 tcg_out32 (s, STB | RS (data_reg) | RA (r0));
751 break;
752 case 1:
753 if (bswap) tcg_out32 (s, STHBRX | RS (data_reg) | RA (0) | RB (r0));
754 else tcg_out32 (s, STH | RS (data_reg) | RA (r0));
755 break;
756 case 2:
757 if (bswap) tcg_out32 (s, STWBRX | RS (data_reg) | RA (0) | RB (r0));
758 else tcg_out32 (s, STW | RS (data_reg) | RA (r0));
759 break;
760 case 3:
761 if (bswap) {
762 tcg_out32 (s, STWBRX | RS (data_reg) | RA (0) | RB (r0));
763 tcg_out32 (s, ADDI | RT (r0) | RA (r0) | 4);
764 tcg_out_rld (s, RLDICL, 0, data_reg, 32, 0);
765 tcg_out32 (s, STWBRX | RS (0) | RA (0) | RB (r0));
766 }
767 else tcg_out32 (s, STD | RS (data_reg) | RA (r0));
768 break;
769 }
770
771 #ifdef CONFIG_SOFTMMU
772 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
773 #endif
774 }
775
776 void tcg_target_qemu_prologue (TCGContext *s)
777 {
778 int i, frame_size;
779 uint64_t addr;
780
781 frame_size = 0
782 + 8 /* back chain */
783 + 8 /* CR */
784 + 8 /* LR */
785 + 8 /* compiler doubleword */
786 + 8 /* link editor doubleword */
787 + 8 /* TOC save area */
788 + TCG_STATIC_CALL_ARGS_SIZE
789 + ARRAY_SIZE (tcg_target_callee_save_regs) * 8
790 ;
791 frame_size = (frame_size + 15) & ~15;
792
793 /* First emit adhoc function descriptor */
794 addr = (uint64_t) s->code_ptr + 24;
795 tcg_out32 (s, addr >> 32); tcg_out32 (s, addr); /* entry point */
796 s->code_ptr += 16; /* skip TOC and environment pointer */
797
798 /* Prologue */
799 tcg_out32 (s, MFSPR | RT (0) | LR);
800 tcg_out32 (s, STDU | RS (1) | RA (1) | (-frame_size & 0xffff));
801 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
802 tcg_out32 (s, (STD
803 | RS (tcg_target_callee_save_regs[i])
804 | RA (1)
805 | (i * 8 + 48 + TCG_STATIC_CALL_ARGS_SIZE)
806 )
807 );
808 tcg_out32 (s, STD | RS (0) | RA (1) | (frame_size + 20));
809
810 tcg_out32 (s, MTSPR | RS (3) | CTR);
811 tcg_out32 (s, BCCTR | BO_ALWAYS);
812
813 /* Epilogue */
814 tb_ret_addr = s->code_ptr;
815
816 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
817 tcg_out32 (s, (LD
818 | RT (tcg_target_callee_save_regs[i])
819 | RA (1)
820 | (i * 8 + 48 + TCG_STATIC_CALL_ARGS_SIZE)
821 )
822 );
823 tcg_out32 (s, LD | RT (0) | RA (1) | (frame_size + 20));
824 tcg_out32 (s, MTSPR | RS (0) | LR);
825 tcg_out32 (s, ADDI | RT (1) | RA (1) | frame_size);
826 tcg_out32 (s, BCLR | BO_ALWAYS);
827 }
828
829 static void tcg_out_ld (TCGContext *s, TCGType type, int ret, int arg1,
830 tcg_target_long arg2)
831 {
832 if (type == TCG_TYPE_I32)
833 tcg_out_ldst (s, ret, arg1, arg2, LWZ, LWZX);
834 else
835 tcg_out_ldst (s, ret, arg1, arg2, LD, LDX);
836 }
837
838 static void tcg_out_st (TCGContext *s, TCGType type, int arg, int arg1,
839 tcg_target_long arg2)
840 {
841 if (type == TCG_TYPE_I32)
842 tcg_out_ldst (s, arg, arg1, arg2, STW, STWX);
843 else
844 tcg_out_ldst (s, arg, arg1, arg2, STD, STDX);
845 }
846
847 static void ppc_addi32 (TCGContext *s, int rt, int ra, tcg_target_long si)
848 {
849 if (!si && rt == ra)
850 return;
851
852 if (si == (int16_t) si)
853 tcg_out32 (s, ADDI | RT (rt) | RA (ra) | (si & 0xffff));
854 else {
855 uint16_t h = ((si >> 16) & 0xffff) + ((uint16_t) si >> 15);
856 tcg_out32 (s, ADDIS | RT (rt) | RA (ra) | h);
857 tcg_out32 (s, ADDI | RT (rt) | RA (rt) | (si & 0xffff));
858 }
859 }
860
861 static void ppc_addi64 (TCGContext *s, int rt, int ra, tcg_target_long si)
862 {
863 tcg_out_movi (s, TCG_TYPE_I64, 0, si);
864 tcg_out32 (s, ADD | RT (rt) | RA (ra));
865 }
866
867 static void tcg_out_addi (TCGContext *s, int reg, tcg_target_long val)
868 {
869 ppc_addi64 (s, reg, reg, val);
870 }
871
872 static void tcg_out_cmp (TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
873 int const_arg2, int cr)
874 {
875 int imm;
876 uint32_t op;
877
878 switch (cond) {
879 case TCG_COND_EQ:
880 case TCG_COND_NE:
881 if (const_arg2) {
882 if ((int16_t) arg2 == arg2) {
883 op = CMPI;
884 imm = 1;
885 break;
886 }
887 else if ((uint16_t) arg2 == arg2) {
888 op = CMPLI;
889 imm = 1;
890 break;
891 }
892 }
893 op = CMPL;
894 imm = 0;
895 break;
896
897 case TCG_COND_LT:
898 case TCG_COND_GE:
899 case TCG_COND_LE:
900 case TCG_COND_GT:
901 if (const_arg2) {
902 if ((int16_t) arg2 == arg2) {
903 op = CMPI;
904 imm = 1;
905 break;
906 }
907 }
908 op = CMP;
909 imm = 0;
910 break;
911
912 case TCG_COND_LTU:
913 case TCG_COND_GEU:
914 case TCG_COND_LEU:
915 case TCG_COND_GTU:
916 if (const_arg2) {
917 if ((uint16_t) arg2 == arg2) {
918 op = CMPLI;
919 imm = 1;
920 break;
921 }
922 }
923 op = CMPL;
924 imm = 0;
925 break;
926
927 default:
928 tcg_abort ();
929 }
930 op |= BF (cr);
931
932 if (imm)
933 tcg_out32 (s, op | RA (arg1) | (arg2 & 0xffff));
934 else {
935 if (const_arg2) {
936 tcg_out_movi (s, TCG_TYPE_I64, 0, arg2);
937 tcg_out32 (s, op | RA (arg1) | RB (0));
938 }
939 else
940 tcg_out32 (s, op | RA (arg1) | RB (arg2));
941 }
942
943 }
944
945 static void tcg_out_bc (TCGContext *s, int bc, int label_index)
946 {
947 TCGLabel *l = &s->labels[label_index];
948
949 if (l->has_value)
950 tcg_out32 (s, bc | reloc_pc14_val (s->code_ptr, l->u.value));
951 else {
952 uint16_t val = *(uint16_t *) &s->code_ptr[2];
953
954 /* Thanks to Andrzej Zaborowski */
955 tcg_out32 (s, bc | (val & 0xfffc));
956 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL14, label_index, 0);
957 }
958 }
959
960 static void tcg_out_brcond (TCGContext *s, int cond,
961 TCGArg arg1, TCGArg arg2, int const_arg2,
962 int label_index)
963 {
964 tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7);
965 tcg_out_bc (s, tcg_to_bc[cond], label_index);
966 }
967
968 void ppc_tb_set_jmp_target (unsigned long jmp_addr, unsigned long addr)
969 {
970 TCGContext s;
971 unsigned long patch_size;
972
973 s.code_ptr = (uint8_t *) jmp_addr;
974 tcg_out_b (&s, 0, addr);
975 patch_size = s.code_ptr - (uint8_t *) jmp_addr;
976 flush_icache_range (jmp_addr, jmp_addr + patch_size);
977 }
978
979 static void tcg_out_op (TCGContext *s, int opc, const TCGArg *args,
980 const int *const_args)
981 {
982 int c;
983
984 switch (opc) {
985 case INDEX_op_exit_tb:
986 tcg_out_movi (s, TCG_TYPE_I64, TCG_REG_R3, args[0]);
987 tcg_out_b (s, 0, (tcg_target_long) tb_ret_addr);
988 break;
989 case INDEX_op_goto_tb:
990 if (s->tb_jmp_offset) {
991 /* direct jump method */
992
993 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
994 s->code_ptr += 28;
995 }
996 else {
997 tcg_abort ();
998 }
999 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1000 break;
1001 case INDEX_op_br:
1002 {
1003 TCGLabel *l = &s->labels[args[0]];
1004
1005 if (l->has_value) {
1006 tcg_out_b (s, 0, l->u.value);
1007 }
1008 else {
1009 uint32_t val = *(uint32_t *) s->code_ptr;
1010
1011 /* Thanks to Andrzej Zaborowski */
1012 tcg_out32 (s, B | (val & 0x3fffffc));
1013 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL24, args[0], 0);
1014 }
1015 }
1016 break;
1017 case INDEX_op_call:
1018 tcg_out_call (s, args[0], const_args[0]);
1019 break;
1020 case INDEX_op_jmp:
1021 if (const_args[0]) {
1022 tcg_out_b (s, 0, args[0]);
1023 }
1024 else {
1025 tcg_out32 (s, MTSPR | RS (args[0]) | CTR);
1026 tcg_out32 (s, BCCTR | BO_ALWAYS);
1027 }
1028 break;
1029 case INDEX_op_movi_i32:
1030 tcg_out_movi (s, TCG_TYPE_I32, args[0], args[1]);
1031 break;
1032 case INDEX_op_movi_i64:
1033 tcg_out_movi (s, TCG_TYPE_I64, args[0], args[1]);
1034 break;
1035 case INDEX_op_ld8u_i32:
1036 case INDEX_op_ld8u_i64:
1037 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1038 break;
1039 case INDEX_op_ld8s_i32:
1040 case INDEX_op_ld8s_i64:
1041 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1042 tcg_out32 (s, EXTSB | RS (args[0]) | RA (args[0]));
1043 break;
1044 case INDEX_op_ld16u_i32:
1045 case INDEX_op_ld16u_i64:
1046 tcg_out_ldst (s, args[0], args[1], args[2], LHZ, LHZX);
1047 break;
1048 case INDEX_op_ld16s_i32:
1049 case INDEX_op_ld16s_i64:
1050 tcg_out_ldst (s, args[0], args[1], args[2], LHA, LHAX);
1051 break;
1052 case INDEX_op_ld_i32:
1053 case INDEX_op_ld32u_i64:
1054 tcg_out_ldst (s, args[0], args[1], args[2], LWZ, LWZX);
1055 break;
1056 case INDEX_op_ld32s_i64:
1057 tcg_out_ldst (s, args[0], args[1], args[2], LWA, LWAX);
1058 break;
1059 case INDEX_op_ld_i64:
1060 tcg_out_ldst (s, args[0], args[1], args[2], LD, LDX);
1061 break;
1062 case INDEX_op_st8_i32:
1063 case INDEX_op_st8_i64:
1064 tcg_out_ldst (s, args[0], args[1], args[2], STB, STBX);
1065 break;
1066 case INDEX_op_st16_i32:
1067 case INDEX_op_st16_i64:
1068 tcg_out_ldst (s, args[0], args[1], args[2], STH, STHX);
1069 break;
1070 case INDEX_op_st_i32:
1071 case INDEX_op_st32_i64:
1072 tcg_out_ldst (s, args[0], args[1], args[2], STW, STWX);
1073 break;
1074 case INDEX_op_st_i64:
1075 tcg_out_ldst (s, args[0], args[1], args[2], STD, STDX);
1076 break;
1077
1078 case INDEX_op_add_i32:
1079 if (const_args[2])
1080 ppc_addi32 (s, args[0], args[1], args[2]);
1081 else
1082 tcg_out32 (s, ADD | TAB (args[0], args[1], args[2]));
1083 break;
1084 case INDEX_op_sub_i32:
1085 if (const_args[2])
1086 ppc_addi32 (s, args[0], args[1], -args[2]);
1087 else
1088 tcg_out32 (s, SUBF | TAB (args[0], args[2], args[1]));
1089 break;
1090
1091 case INDEX_op_and_i32:
1092 if (const_args[2]) {
1093 if (!args[2])
1094 tcg_out_movi (s, TCG_TYPE_I32, args[0], 0);
1095 else {
1096 if ((args[2] & 0xffff) == args[2])
1097 tcg_out32 (s, ANDI | RS (args[1]) | RA (args[0]) | args[2]);
1098 else if ((args[2] & 0xffff0000) == args[2])
1099 tcg_out32 (s, ANDIS | RS (args[1]) | RA (args[0])
1100 | ((args[2] >> 16) & 0xffff));
1101 else if (args[2] == 0xffffffff) {
1102 if (args[0] != args[1])
1103 tcg_out_mov (s, args[0], args[1]);
1104 }
1105 else {
1106 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1107 tcg_out32 (s, AND | SAB (args[1], args[0], 0));
1108 }
1109 }
1110 }
1111 else
1112 tcg_out32 (s, AND | SAB (args[1], args[0], args[2]));
1113 break;
1114 case INDEX_op_or_i32:
1115 if (const_args[2]) {
1116 if (args[2]) {
1117 if (args[2] & 0xffff) {
1118 tcg_out32 (s, ORI | RS (args[1]) | RA (args[0])
1119 | (args[2] & 0xffff));
1120 if (args[2] >> 16)
1121 tcg_out32 (s, ORIS | RS (args[0]) | RA (args[0])
1122 | ((args[2] >> 16) & 0xffff));
1123 }
1124 else {
1125 tcg_out32 (s, ORIS | RS (args[1]) | RA (args[0])
1126 | ((args[2] >> 16) & 0xffff));
1127 }
1128 }
1129 else {
1130 if (args[0] != args[1])
1131 tcg_out_mov (s, args[0], args[1]);
1132 }
1133 }
1134 else
1135 tcg_out32 (s, OR | SAB (args[1], args[0], args[2]));
1136 break;
1137 case INDEX_op_xor_i32:
1138 if (const_args[2]) {
1139 if (args[2]) {
1140 if ((args[2] & 0xffff) == args[2])
1141 tcg_out32 (s, XORI | RS (args[1]) | RA (args[0])
1142 | (args[2] & 0xffff));
1143 else if ((args[2] & 0xffff0000) == args[2])
1144 tcg_out32 (s, XORIS | RS (args[1]) | RA (args[0])
1145 | ((args[2] >> 16) & 0xffff));
1146 else {
1147 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1148 tcg_out32 (s, XOR | SAB (args[1], args[0], 0));
1149 }
1150 }
1151 else {
1152 if (args[0] != args[1])
1153 tcg_out_mov (s, args[0], args[1]);
1154 }
1155 }
1156 else
1157 tcg_out32 (s, XOR | SAB (args[1], args[0], args[2]));
1158 break;
1159
1160 case INDEX_op_mul_i32:
1161 if (const_args[2]) {
1162 if (args[2] == (int16_t) args[2])
1163 tcg_out32 (s, MULLI | RT (args[0]) | RA (args[1])
1164 | (args[2] & 0xffff));
1165 else {
1166 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1167 tcg_out32 (s, MULLW | TAB (args[0], args[1], 0));
1168 }
1169 }
1170 else
1171 tcg_out32 (s, MULLW | TAB (args[0], args[1], args[2]));
1172 break;
1173
1174 case INDEX_op_div_i32:
1175 tcg_out32 (s, DIVW | TAB (args[0], args[1], args[2]));
1176 break;
1177
1178 case INDEX_op_divu_i32:
1179 tcg_out32 (s, DIVWU | TAB (args[0], args[1], args[2]));
1180 break;
1181
1182 case INDEX_op_rem_i32:
1183 tcg_out32 (s, DIVW | TAB (0, args[1], args[2]));
1184 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1185 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1186 break;
1187
1188 case INDEX_op_remu_i32:
1189 tcg_out32 (s, DIVWU | TAB (0, args[1], args[2]));
1190 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1191 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1192 break;
1193
1194 case INDEX_op_shl_i32:
1195 if (const_args[2]) {
1196 if (args[2])
1197 tcg_out32 (s, (RLWINM
1198 | RA (args[0])
1199 | RS (args[1])
1200 | SH (args[2])
1201 | MB (0)
1202 | ME (31 - args[2])
1203 )
1204 );
1205 else
1206 tcg_out_mov (s, args[0], args[1]);
1207 }
1208 else
1209 tcg_out32 (s, SLW | SAB (args[1], args[0], args[2]));
1210 break;
1211 case INDEX_op_shr_i32:
1212 if (const_args[2]) {
1213 if (args[2])
1214 tcg_out32 (s, (RLWINM
1215 | RA (args[0])
1216 | RS (args[1])
1217 | SH (32 - args[2])
1218 | MB (args[2])
1219 | ME (31)
1220 )
1221 );
1222 else
1223 tcg_out_mov (s, args[0], args[1]);
1224 }
1225 else
1226 tcg_out32 (s, SRW | SAB (args[1], args[0], args[2]));
1227 break;
1228 case INDEX_op_sar_i32:
1229 if (const_args[2])
1230 tcg_out32 (s, SRAWI | RS (args[1]) | RA (args[0]) | SH (args[2]));
1231 else
1232 tcg_out32 (s, SRAW | SAB (args[1], args[0], args[2]));
1233 break;
1234
1235 case INDEX_op_brcond_i32:
1236 case INDEX_op_brcond_i64:
1237 tcg_out_brcond (s, args[2], args[0], args[1], const_args[1], args[3]);
1238 break;
1239
1240 case INDEX_op_neg_i32:
1241 case INDEX_op_neg_i64:
1242 tcg_out32 (s, NEG | RT (args[0]) | RA (args[1]));
1243 break;
1244
1245 case INDEX_op_add_i64:
1246 tcg_out32 (s, ADD | TAB (args[0], args[1], args[2]));
1247 break;
1248 case INDEX_op_sub_i64:
1249 tcg_out32 (s, SUBF | TAB (args[0], args[2], args[1]));
1250 break;
1251
1252 case INDEX_op_and_i64:
1253 tcg_out32 (s, AND | SAB (args[1], args[0], args[2]));
1254 break;
1255 case INDEX_op_or_i64:
1256 tcg_out32 (s, OR | SAB (args[1], args[0], args[2]));
1257 break;
1258 case INDEX_op_xor_i64:
1259 tcg_out32 (s, XOR | SAB (args[1], args[0], args[2]));
1260 break;
1261
1262 case INDEX_op_shl_i64:
1263 tcg_out32 (s, SLD | SAB (args[1], args[0], args[2]));
1264 break;
1265 case INDEX_op_shr_i64:
1266 tcg_out32 (s, SRD | SAB (args[1], args[0], args[2]));
1267 break;
1268 case INDEX_op_sar_i64:
1269 tcg_out32 (s, SRAD | SAB (args[1], args[0], args[2]));
1270 break;
1271
1272 case INDEX_op_mul_i64:
1273 tcg_out32 (s, MULLD | TAB (args[0], args[1], args[2]));
1274 break;
1275 case INDEX_op_div_i64:
1276 tcg_out32 (s, DIVD | TAB (args[0], args[1], args[2]));
1277 break;
1278 case INDEX_op_divu_i64:
1279 tcg_out32 (s, DIVDU | TAB (args[0], args[1], args[2]));
1280 break;
1281 case INDEX_op_rem_i64:
1282 tcg_out32 (s, DIVD | TAB (0, args[1], args[2]));
1283 tcg_out32 (s, MULLD | TAB (0, 0, args[2]));
1284 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1285 break;
1286 case INDEX_op_remu_i64:
1287 tcg_out32 (s, DIVDU | TAB (0, args[1], args[2]));
1288 tcg_out32 (s, MULLD | TAB (0, 0, args[2]));
1289 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1290 break;
1291
1292 case INDEX_op_qemu_ld8u:
1293 tcg_out_qemu_ld (s, args, 0);
1294 break;
1295 case INDEX_op_qemu_ld8s:
1296 tcg_out_qemu_ld (s, args, 0 | 4);
1297 break;
1298 case INDEX_op_qemu_ld16u:
1299 tcg_out_qemu_ld (s, args, 1);
1300 break;
1301 case INDEX_op_qemu_ld16s:
1302 tcg_out_qemu_ld (s, args, 1 | 4);
1303 break;
1304 case INDEX_op_qemu_ld32u:
1305 tcg_out_qemu_ld (s, args, 2);
1306 break;
1307 case INDEX_op_qemu_ld32s:
1308 tcg_out_qemu_ld (s, args, 2 | 4);
1309 break;
1310 case INDEX_op_qemu_ld64:
1311 tcg_out_qemu_ld (s, args, 3);
1312 break;
1313 case INDEX_op_qemu_st8:
1314 tcg_out_qemu_st (s, args, 0);
1315 break;
1316 case INDEX_op_qemu_st16:
1317 tcg_out_qemu_st (s, args, 1);
1318 break;
1319 case INDEX_op_qemu_st32:
1320 tcg_out_qemu_st (s, args, 2);
1321 break;
1322 case INDEX_op_qemu_st64:
1323 tcg_out_qemu_st (s, args, 3);
1324 break;
1325
1326 case INDEX_op_ext8s_i32:
1327 case INDEX_op_ext8s_i64:
1328 c = EXTSB;
1329 goto gen_ext;
1330 case INDEX_op_ext16s_i32:
1331 case INDEX_op_ext16s_i64:
1332 c = EXTSH;
1333 goto gen_ext;
1334 case INDEX_op_ext32s_i64:
1335 c = EXTSW;
1336 goto gen_ext;
1337 gen_ext:
1338 tcg_out32 (s, c | RS (args[1]) | RA (args[0]));
1339 break;
1340
1341 default:
1342 tcg_dump_ops (s, stderr);
1343 tcg_abort ();
1344 }
1345 }
1346
1347 static const TCGTargetOpDef ppc_op_defs[] = {
1348 { INDEX_op_exit_tb, { } },
1349 { INDEX_op_goto_tb, { } },
1350 { INDEX_op_call, { "ri" } },
1351 { INDEX_op_jmp, { "ri" } },
1352 { INDEX_op_br, { } },
1353
1354 { INDEX_op_mov_i32, { "r", "r" } },
1355 { INDEX_op_mov_i64, { "r", "r" } },
1356 { INDEX_op_movi_i32, { "r" } },
1357 { INDEX_op_movi_i64, { "r" } },
1358
1359 { INDEX_op_ld8u_i32, { "r", "r" } },
1360 { INDEX_op_ld8s_i32, { "r", "r" } },
1361 { INDEX_op_ld16u_i32, { "r", "r" } },
1362 { INDEX_op_ld16s_i32, { "r", "r" } },
1363 { INDEX_op_ld_i32, { "r", "r" } },
1364 { INDEX_op_ld_i64, { "r", "r" } },
1365 { INDEX_op_st8_i32, { "r", "r" } },
1366 { INDEX_op_st8_i64, { "r", "r" } },
1367 { INDEX_op_st16_i32, { "r", "r" } },
1368 { INDEX_op_st16_i64, { "r", "r" } },
1369 { INDEX_op_st_i32, { "r", "r" } },
1370 { INDEX_op_st_i64, { "r", "r" } },
1371 { INDEX_op_st32_i64, { "r", "r" } },
1372
1373 { INDEX_op_ld8u_i64, { "r", "r" } },
1374 { INDEX_op_ld8s_i64, { "r", "r" } },
1375 { INDEX_op_ld16u_i64, { "r", "r" } },
1376 { INDEX_op_ld16s_i64, { "r", "r" } },
1377 { INDEX_op_ld32u_i64, { "r", "r" } },
1378 { INDEX_op_ld32s_i64, { "r", "r" } },
1379 { INDEX_op_ld_i64, { "r", "r" } },
1380
1381 { INDEX_op_add_i32, { "r", "r", "ri" } },
1382 { INDEX_op_mul_i32, { "r", "r", "ri" } },
1383 { INDEX_op_div_i32, { "r", "r", "r" } },
1384 { INDEX_op_divu_i32, { "r", "r", "r" } },
1385 { INDEX_op_rem_i32, { "r", "r", "r" } },
1386 { INDEX_op_remu_i32, { "r", "r", "r" } },
1387 { INDEX_op_sub_i32, { "r", "r", "ri" } },
1388 { INDEX_op_and_i32, { "r", "r", "ri" } },
1389 { INDEX_op_or_i32, { "r", "r", "ri" } },
1390 { INDEX_op_xor_i32, { "r", "r", "ri" } },
1391
1392 { INDEX_op_shl_i32, { "r", "r", "ri" } },
1393 { INDEX_op_shr_i32, { "r", "r", "ri" } },
1394 { INDEX_op_sar_i32, { "r", "r", "ri" } },
1395
1396 { INDEX_op_brcond_i32, { "r", "ri" } },
1397 { INDEX_op_brcond_i64, { "r", "ri" } },
1398
1399 { INDEX_op_neg_i32, { "r", "r" } },
1400
1401 { INDEX_op_add_i64, { "r", "r", "r" } },
1402 { INDEX_op_sub_i64, { "r", "r", "r" } },
1403 { INDEX_op_and_i64, { "r", "r", "r" } },
1404 { INDEX_op_or_i64, { "r", "r", "r" } },
1405 { INDEX_op_xor_i64, { "r", "r", "r" } },
1406
1407 { INDEX_op_shl_i64, { "r", "r", "r" } },
1408 { INDEX_op_shr_i64, { "r", "r", "r" } },
1409 { INDEX_op_sar_i64, { "r", "r", "r" } },
1410
1411 { INDEX_op_mul_i64, { "r", "r", "r" } },
1412 { INDEX_op_div_i64, { "r", "r", "r" } },
1413 { INDEX_op_divu_i64, { "r", "r", "r" } },
1414 { INDEX_op_rem_i64, { "r", "r", "r" } },
1415 { INDEX_op_remu_i64, { "r", "r", "r" } },
1416
1417 { INDEX_op_neg_i64, { "r", "r" } },
1418
1419 { INDEX_op_qemu_ld8u, { "r", "L" } },
1420 { INDEX_op_qemu_ld8s, { "r", "L" } },
1421 { INDEX_op_qemu_ld16u, { "r", "L" } },
1422 { INDEX_op_qemu_ld16s, { "r", "L" } },
1423 { INDEX_op_qemu_ld32u, { "r", "L" } },
1424 { INDEX_op_qemu_ld32s, { "r", "L" } },
1425 { INDEX_op_qemu_ld64, { "r", "r", "L" } },
1426
1427 { INDEX_op_qemu_st8, { "K", "K" } },
1428 { INDEX_op_qemu_st16, { "K", "K" } },
1429 { INDEX_op_qemu_st32, { "K", "K" } },
1430 { INDEX_op_qemu_st64, { "M", "M", "M" } },
1431
1432 { INDEX_op_ext8s_i32, { "r", "r" } },
1433 { INDEX_op_ext16s_i32, { "r", "r" } },
1434 { INDEX_op_ext8s_i64, { "r", "r" } },
1435 { INDEX_op_ext16s_i64, { "r", "r" } },
1436 { INDEX_op_ext32s_i64, { "r", "r" } },
1437
1438 { -1 },
1439 };
1440
1441 void tcg_target_init (TCGContext *s)
1442 {
1443 tcg_regset_set32 (tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
1444 tcg_regset_set32 (tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
1445 tcg_regset_set32 (tcg_target_call_clobber_regs, 0,
1446 (1 << TCG_REG_R0) |
1447 (1 << TCG_REG_R3) |
1448 (1 << TCG_REG_R4) |
1449 (1 << TCG_REG_R5) |
1450 (1 << TCG_REG_R6) |
1451 (1 << TCG_REG_R7) |
1452 (1 << TCG_REG_R8) |
1453 (1 << TCG_REG_R9) |
1454 (1 << TCG_REG_R10) |
1455 (1 << TCG_REG_R11) |
1456 (1 << TCG_REG_R12)
1457 );
1458
1459 tcg_regset_clear (s->reserved_regs);
1460 tcg_regset_set_reg (s->reserved_regs, TCG_REG_R0);
1461 tcg_regset_set_reg (s->reserved_regs, TCG_REG_R1);
1462 tcg_regset_set_reg (s->reserved_regs, TCG_REG_R2);
1463 tcg_regset_set_reg (s->reserved_regs, TCG_REG_R13);
1464
1465 tcg_add_target_add_op_defs (ppc_op_defs);
1466 }
Qemu copy for testing