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tcg-ppc64: Add _noaddr functions for emitting forward branches
[qemu.git] / tcg / ppc64 / tcg-target.c
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #define TCG_CT_CONST_S16 0x100
26 #define TCG_CT_CONST_U16 0x200
27 #define TCG_CT_CONST_S32 0x400
28 #define TCG_CT_CONST_U32 0x800
29 #define TCG_CT_CONST_ZERO 0x1000
30 #define TCG_CT_CONST_MONE 0x2000
31
32 static uint8_t *tb_ret_addr;
33
34 #if TARGET_LONG_BITS == 32
35 #define LD_ADDR LWZ
36 #define CMP_L 0
37 #else
38 #define LD_ADDR LD
39 #define CMP_L (1<<21)
40 #endif
41
42 #ifndef GUEST_BASE
43 #define GUEST_BASE 0
44 #endif
45
46 #ifdef CONFIG_GETAUXVAL
47 #include <sys/auxv.h>
48 static bool have_isa_2_06;
49 #define HAVE_ISA_2_06 have_isa_2_06
50 #define HAVE_ISEL have_isa_2_06
51 #else
52 #define HAVE_ISA_2_06 0
53 #define HAVE_ISEL 0
54 #endif
55
56 #ifdef CONFIG_USE_GUEST_BASE
57 #define TCG_GUEST_BASE_REG 30
58 #else
59 #define TCG_GUEST_BASE_REG 0
60 #endif
61
62 #ifndef NDEBUG
63 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
64 "r0",
65 "r1",
66 "r2",
67 "r3",
68 "r4",
69 "r5",
70 "r6",
71 "r7",
72 "r8",
73 "r9",
74 "r10",
75 "r11",
76 "r12",
77 "r13",
78 "r14",
79 "r15",
80 "r16",
81 "r17",
82 "r18",
83 "r19",
84 "r20",
85 "r21",
86 "r22",
87 "r23",
88 "r24",
89 "r25",
90 "r26",
91 "r27",
92 "r28",
93 "r29",
94 "r30",
95 "r31"
96 };
97 #endif
98
99 static const int tcg_target_reg_alloc_order[] = {
100 TCG_REG_R14, /* call saved registers */
101 TCG_REG_R15,
102 TCG_REG_R16,
103 TCG_REG_R17,
104 TCG_REG_R18,
105 TCG_REG_R19,
106 TCG_REG_R20,
107 TCG_REG_R21,
108 TCG_REG_R22,
109 TCG_REG_R23,
110 TCG_REG_R24,
111 TCG_REG_R25,
112 TCG_REG_R26,
113 TCG_REG_R27,
114 TCG_REG_R28,
115 TCG_REG_R29,
116 TCG_REG_R30,
117 TCG_REG_R31,
118 TCG_REG_R12, /* call clobbered, non-arguments */
119 TCG_REG_R11,
120 TCG_REG_R10, /* call clobbered, arguments */
121 TCG_REG_R9,
122 TCG_REG_R8,
123 TCG_REG_R7,
124 TCG_REG_R6,
125 TCG_REG_R5,
126 TCG_REG_R4,
127 TCG_REG_R3,
128 };
129
130 static const int tcg_target_call_iarg_regs[] = {
131 TCG_REG_R3,
132 TCG_REG_R4,
133 TCG_REG_R5,
134 TCG_REG_R6,
135 TCG_REG_R7,
136 TCG_REG_R8,
137 TCG_REG_R9,
138 TCG_REG_R10
139 };
140
141 static const int tcg_target_call_oarg_regs[] = {
142 TCG_REG_R3
143 };
144
145 static const int tcg_target_callee_save_regs[] = {
146 #ifdef __APPLE__
147 TCG_REG_R11,
148 #endif
149 TCG_REG_R14,
150 TCG_REG_R15,
151 TCG_REG_R16,
152 TCG_REG_R17,
153 TCG_REG_R18,
154 TCG_REG_R19,
155 TCG_REG_R20,
156 TCG_REG_R21,
157 TCG_REG_R22,
158 TCG_REG_R23,
159 TCG_REG_R24,
160 TCG_REG_R25,
161 TCG_REG_R26,
162 TCG_REG_R27, /* currently used for the global env */
163 TCG_REG_R28,
164 TCG_REG_R29,
165 TCG_REG_R30,
166 TCG_REG_R31
167 };
168
169 static inline bool in_range_b(tcg_target_long target)
170 {
171 return target == sextract64(target, 0, 26);
172 }
173
174 static uint32_t reloc_pc24_val(void *pc, tcg_target_long target)
175 {
176 tcg_target_long disp;
177
178 disp = target - (tcg_target_long)pc;
179 assert(in_range_b(disp));
180
181 return disp & 0x3fffffc;
182 }
183
184 static void reloc_pc24(void *pc, tcg_target_long target)
185 {
186 *(uint32_t *)pc = (*(uint32_t *)pc & ~0x3fffffc)
187 | reloc_pc24_val(pc, target);
188 }
189
190 static uint16_t reloc_pc14_val(void *pc, tcg_target_long target)
191 {
192 tcg_target_long disp;
193
194 disp = target - (tcg_target_long)pc;
195 if (disp != (int16_t) disp) {
196 tcg_abort();
197 }
198
199 return disp & 0xfffc;
200 }
201
202 static void reloc_pc14(void *pc, tcg_target_long target)
203 {
204 *(uint32_t *)pc = (*(uint32_t *)pc & ~0xfffc) | reloc_pc14_val(pc, target);
205 }
206
207 static inline void tcg_out_b_noaddr(TCGContext *s, int insn)
208 {
209 unsigned retrans = *(uint32_t *)s->code_ptr & 0x3fffffc;
210 tcg_out32(s, insn | retrans);
211 }
212
213 static inline void tcg_out_bc_noaddr(TCGContext *s, int insn)
214 {
215 unsigned retrans = *(uint32_t *)s->code_ptr & 0xfffc;
216 tcg_out32(s, insn | retrans);
217 }
218
219 static void patch_reloc(uint8_t *code_ptr, int type,
220 intptr_t value, intptr_t addend)
221 {
222 value += addend;
223 switch (type) {
224 case R_PPC_REL14:
225 reloc_pc14(code_ptr, value);
226 break;
227 case R_PPC_REL24:
228 reloc_pc24(code_ptr, value);
229 break;
230 default:
231 tcg_abort();
232 }
233 }
234
235 /* parse target specific constraints */
236 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
237 {
238 const char *ct_str;
239
240 ct_str = *pct_str;
241 switch (ct_str[0]) {
242 case 'A': case 'B': case 'C': case 'D':
243 ct->ct |= TCG_CT_REG;
244 tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
245 break;
246 case 'r':
247 ct->ct |= TCG_CT_REG;
248 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
249 break;
250 case 'L': /* qemu_ld constraint */
251 ct->ct |= TCG_CT_REG;
252 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
253 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
254 #ifdef CONFIG_SOFTMMU
255 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
256 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
257 #endif
258 break;
259 case 'S': /* qemu_st constraint */
260 ct->ct |= TCG_CT_REG;
261 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
262 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
263 #ifdef CONFIG_SOFTMMU
264 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
265 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
266 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
267 #endif
268 break;
269 case 'I':
270 ct->ct |= TCG_CT_CONST_S16;
271 break;
272 case 'J':
273 ct->ct |= TCG_CT_CONST_U16;
274 break;
275 case 'M':
276 ct->ct |= TCG_CT_CONST_MONE;
277 break;
278 case 'T':
279 ct->ct |= TCG_CT_CONST_S32;
280 break;
281 case 'U':
282 ct->ct |= TCG_CT_CONST_U32;
283 break;
284 case 'Z':
285 ct->ct |= TCG_CT_CONST_ZERO;
286 break;
287 default:
288 return -1;
289 }
290 ct_str++;
291 *pct_str = ct_str;
292 return 0;
293 }
294
295 /* test if a constant matches the constraint */
296 static int tcg_target_const_match(tcg_target_long val,
297 const TCGArgConstraint *arg_ct)
298 {
299 int ct = arg_ct->ct;
300 if (ct & TCG_CT_CONST) {
301 return 1;
302 } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {
303 return 1;
304 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) {
305 return 1;
306 } else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
307 return 1;
308 } else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
309 return 1;
310 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
311 return 1;
312 } else if ((ct & TCG_CT_CONST_MONE) && val == -1) {
313 return 1;
314 }
315 return 0;
316 }
317
318 #define OPCD(opc) ((opc)<<26)
319 #define XO19(opc) (OPCD(19)|((opc)<<1))
320 #define MD30(opc) (OPCD(30)|((opc)<<2))
321 #define MDS30(opc) (OPCD(30)|((opc)<<1))
322 #define XO31(opc) (OPCD(31)|((opc)<<1))
323 #define XO58(opc) (OPCD(58)|(opc))
324 #define XO62(opc) (OPCD(62)|(opc))
325
326 #define B OPCD( 18)
327 #define BC OPCD( 16)
328 #define LBZ OPCD( 34)
329 #define LHZ OPCD( 40)
330 #define LHA OPCD( 42)
331 #define LWZ OPCD( 32)
332 #define STB OPCD( 38)
333 #define STH OPCD( 44)
334 #define STW OPCD( 36)
335
336 #define STD XO62( 0)
337 #define STDU XO62( 1)
338 #define STDX XO31(149)
339
340 #define LD XO58( 0)
341 #define LDX XO31( 21)
342 #define LDU XO58( 1)
343 #define LWA XO58( 2)
344 #define LWAX XO31(341)
345
346 #define ADDIC OPCD( 12)
347 #define ADDI OPCD( 14)
348 #define ADDIS OPCD( 15)
349 #define ORI OPCD( 24)
350 #define ORIS OPCD( 25)
351 #define XORI OPCD( 26)
352 #define XORIS OPCD( 27)
353 #define ANDI OPCD( 28)
354 #define ANDIS OPCD( 29)
355 #define MULLI OPCD( 7)
356 #define CMPLI OPCD( 10)
357 #define CMPI OPCD( 11)
358 #define SUBFIC OPCD( 8)
359
360 #define LWZU OPCD( 33)
361 #define STWU OPCD( 37)
362
363 #define RLWIMI OPCD( 20)
364 #define RLWINM OPCD( 21)
365 #define RLWNM OPCD( 23)
366
367 #define RLDICL MD30( 0)
368 #define RLDICR MD30( 1)
369 #define RLDIMI MD30( 3)
370 #define RLDCL MDS30( 8)
371
372 #define BCLR XO19( 16)
373 #define BCCTR XO19(528)
374 #define CRAND XO19(257)
375 #define CRANDC XO19(129)
376 #define CRNAND XO19(225)
377 #define CROR XO19(449)
378 #define CRNOR XO19( 33)
379
380 #define EXTSB XO31(954)
381 #define EXTSH XO31(922)
382 #define EXTSW XO31(986)
383 #define ADD XO31(266)
384 #define ADDE XO31(138)
385 #define ADDME XO31(234)
386 #define ADDZE XO31(202)
387 #define ADDC XO31( 10)
388 #define AND XO31( 28)
389 #define SUBF XO31( 40)
390 #define SUBFC XO31( 8)
391 #define SUBFE XO31(136)
392 #define SUBFME XO31(232)
393 #define SUBFZE XO31(200)
394 #define OR XO31(444)
395 #define XOR XO31(316)
396 #define MULLW XO31(235)
397 #define MULHWU XO31( 11)
398 #define DIVW XO31(491)
399 #define DIVWU XO31(459)
400 #define CMP XO31( 0)
401 #define CMPL XO31( 32)
402 #define LHBRX XO31(790)
403 #define LWBRX XO31(534)
404 #define LDBRX XO31(532)
405 #define STHBRX XO31(918)
406 #define STWBRX XO31(662)
407 #define STDBRX XO31(660)
408 #define MFSPR XO31(339)
409 #define MTSPR XO31(467)
410 #define SRAWI XO31(824)
411 #define NEG XO31(104)
412 #define MFCR XO31( 19)
413 #define MFOCRF (MFCR | (1u << 20))
414 #define NOR XO31(124)
415 #define CNTLZW XO31( 26)
416 #define CNTLZD XO31( 58)
417 #define ANDC XO31( 60)
418 #define ORC XO31(412)
419 #define EQV XO31(284)
420 #define NAND XO31(476)
421 #define ISEL XO31( 15)
422
423 #define MULLD XO31(233)
424 #define MULHD XO31( 73)
425 #define MULHDU XO31( 9)
426 #define DIVD XO31(489)
427 #define DIVDU XO31(457)
428
429 #define LBZX XO31( 87)
430 #define LHZX XO31(279)
431 #define LHAX XO31(343)
432 #define LWZX XO31( 23)
433 #define STBX XO31(215)
434 #define STHX XO31(407)
435 #define STWX XO31(151)
436
437 #define SPR(a, b) ((((a)<<5)|(b))<<11)
438 #define LR SPR(8, 0)
439 #define CTR SPR(9, 0)
440
441 #define SLW XO31( 24)
442 #define SRW XO31(536)
443 #define SRAW XO31(792)
444
445 #define SLD XO31( 27)
446 #define SRD XO31(539)
447 #define SRAD XO31(794)
448 #define SRADI XO31(413<<1)
449
450 #define TW XO31( 4)
451 #define TRAP (TW | TO(31))
452
453 #define RT(r) ((r)<<21)
454 #define RS(r) ((r)<<21)
455 #define RA(r) ((r)<<16)
456 #define RB(r) ((r)<<11)
457 #define TO(t) ((t)<<21)
458 #define SH(s) ((s)<<11)
459 #define MB(b) ((b)<<6)
460 #define ME(e) ((e)<<1)
461 #define BO(o) ((o)<<21)
462 #define MB64(b) ((b)<<5)
463 #define FXM(b) (1 << (19 - (b)))
464
465 #define LK 1
466
467 #define TAB(t, a, b) (RT(t) | RA(a) | RB(b))
468 #define SAB(s, a, b) (RS(s) | RA(a) | RB(b))
469 #define TAI(s, a, i) (RT(s) | RA(a) | ((i) & 0xffff))
470 #define SAI(s, a, i) (RS(s) | RA(a) | ((i) & 0xffff))
471
472 #define BF(n) ((n)<<23)
473 #define BI(n, c) (((c)+((n)*4))<<16)
474 #define BT(n, c) (((c)+((n)*4))<<21)
475 #define BA(n, c) (((c)+((n)*4))<<16)
476 #define BB(n, c) (((c)+((n)*4))<<11)
477 #define BC_(n, c) (((c)+((n)*4))<<6)
478
479 #define BO_COND_TRUE BO(12)
480 #define BO_COND_FALSE BO( 4)
481 #define BO_ALWAYS BO(20)
482
483 enum {
484 CR_LT,
485 CR_GT,
486 CR_EQ,
487 CR_SO
488 };
489
490 static const uint32_t tcg_to_bc[] = {
491 [TCG_COND_EQ] = BC | BI(7, CR_EQ) | BO_COND_TRUE,
492 [TCG_COND_NE] = BC | BI(7, CR_EQ) | BO_COND_FALSE,
493 [TCG_COND_LT] = BC | BI(7, CR_LT) | BO_COND_TRUE,
494 [TCG_COND_GE] = BC | BI(7, CR_LT) | BO_COND_FALSE,
495 [TCG_COND_LE] = BC | BI(7, CR_GT) | BO_COND_FALSE,
496 [TCG_COND_GT] = BC | BI(7, CR_GT) | BO_COND_TRUE,
497 [TCG_COND_LTU] = BC | BI(7, CR_LT) | BO_COND_TRUE,
498 [TCG_COND_GEU] = BC | BI(7, CR_LT) | BO_COND_FALSE,
499 [TCG_COND_LEU] = BC | BI(7, CR_GT) | BO_COND_FALSE,
500 [TCG_COND_GTU] = BC | BI(7, CR_GT) | BO_COND_TRUE,
501 };
502
503 /* The low bit here is set if the RA and RB fields must be inverted. */
504 static const uint32_t tcg_to_isel[] = {
505 [TCG_COND_EQ] = ISEL | BC_(7, CR_EQ),
506 [TCG_COND_NE] = ISEL | BC_(7, CR_EQ) | 1,
507 [TCG_COND_LT] = ISEL | BC_(7, CR_LT),
508 [TCG_COND_GE] = ISEL | BC_(7, CR_LT) | 1,
509 [TCG_COND_LE] = ISEL | BC_(7, CR_GT) | 1,
510 [TCG_COND_GT] = ISEL | BC_(7, CR_GT),
511 [TCG_COND_LTU] = ISEL | BC_(7, CR_LT),
512 [TCG_COND_GEU] = ISEL | BC_(7, CR_LT) | 1,
513 [TCG_COND_LEU] = ISEL | BC_(7, CR_GT) | 1,
514 [TCG_COND_GTU] = ISEL | BC_(7, CR_GT),
515 };
516
517 static inline void tcg_out_mov(TCGContext *s, TCGType type,
518 TCGReg ret, TCGReg arg)
519 {
520 if (ret != arg) {
521 tcg_out32(s, OR | SAB(arg, ret, arg));
522 }
523 }
524
525 static inline void tcg_out_rld(TCGContext *s, int op, TCGReg ra, TCGReg rs,
526 int sh, int mb)
527 {
528 sh = SH(sh & 0x1f) | (((sh >> 5) & 1) << 1);
529 mb = MB64((mb >> 5) | ((mb << 1) & 0x3f));
530 tcg_out32(s, op | RA(ra) | RS(rs) | sh | mb);
531 }
532
533 static inline void tcg_out_rlw(TCGContext *s, int op, TCGReg ra, TCGReg rs,
534 int sh, int mb, int me)
535 {
536 tcg_out32(s, op | RA(ra) | RS(rs) | SH(sh) | MB(mb) | ME(me));
537 }
538
539 static inline void tcg_out_ext32u(TCGContext *s, TCGReg dst, TCGReg src)
540 {
541 tcg_out_rld(s, RLDICL, dst, src, 0, 32);
542 }
543
544 static inline void tcg_out_shli64(TCGContext *s, TCGReg dst, TCGReg src, int c)
545 {
546 tcg_out_rld(s, RLDICR, dst, src, c, 63 - c);
547 }
548
549 static inline void tcg_out_shri64(TCGContext *s, TCGReg dst, TCGReg src, int c)
550 {
551 tcg_out_rld(s, RLDICL, dst, src, 64 - c, c);
552 }
553
554 static void tcg_out_movi32(TCGContext *s, TCGReg ret, int32_t arg)
555 {
556 if (arg == (int16_t) arg) {
557 tcg_out32(s, ADDI | TAI(ret, 0, arg));
558 } else {
559 tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16));
560 if (arg & 0xffff) {
561 tcg_out32(s, ORI | SAI(ret, ret, arg));
562 }
563 }
564 }
565
566 static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret,
567 tcg_target_long arg)
568 {
569 if (type == TCG_TYPE_I32 || arg == (int32_t)arg) {
570 tcg_out_movi32(s, ret, arg);
571 } else if (arg == (uint32_t)arg && !(arg & 0x8000)) {
572 tcg_out32(s, ADDI | TAI(ret, 0, arg));
573 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
574 } else {
575 int32_t high = arg >> 32;
576 tcg_out_movi32(s, ret, high);
577 if (high) {
578 tcg_out_shli64(s, ret, ret, 32);
579 }
580 if (arg & 0xffff0000) {
581 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
582 }
583 if (arg & 0xffff) {
584 tcg_out32(s, ORI | SAI(ret, ret, arg));
585 }
586 }
587 }
588
589 static bool mask_operand(uint32_t c, int *mb, int *me)
590 {
591 uint32_t lsb, test;
592
593 /* Accept a bit pattern like:
594 0....01....1
595 1....10....0
596 0..01..10..0
597 Keep track of the transitions. */
598 if (c == 0 || c == -1) {
599 return false;
600 }
601 test = c;
602 lsb = test & -test;
603 test += lsb;
604 if (test & (test - 1)) {
605 return false;
606 }
607
608 *me = clz32(lsb);
609 *mb = test ? clz32(test & -test) + 1 : 0;
610 return true;
611 }
612
613 static bool mask64_operand(uint64_t c, int *mb, int *me)
614 {
615 uint64_t lsb;
616
617 if (c == 0) {
618 return false;
619 }
620
621 lsb = c & -c;
622 /* Accept 1..10..0. */
623 if (c == -lsb) {
624 *mb = 0;
625 *me = clz64(lsb);
626 return true;
627 }
628 /* Accept 0..01..1. */
629 if (lsb == 1 && (c & (c + 1)) == 0) {
630 *mb = clz64(c + 1) + 1;
631 *me = 63;
632 return true;
633 }
634 return false;
635 }
636
637 static void tcg_out_andi32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
638 {
639 int mb, me;
640
641 if ((c & 0xffff) == c) {
642 tcg_out32(s, ANDI | SAI(src, dst, c));
643 return;
644 } else if ((c & 0xffff0000) == c) {
645 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
646 return;
647 } else if (mask_operand(c, &mb, &me)) {
648 tcg_out_rlw(s, RLWINM, dst, src, 0, mb, me);
649 } else {
650 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R0, c);
651 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
652 }
653 }
654
655 static void tcg_out_andi64(TCGContext *s, TCGReg dst, TCGReg src, uint64_t c)
656 {
657 int mb, me;
658
659 if ((c & 0xffff) == c) {
660 tcg_out32(s, ANDI | SAI(src, dst, c));
661 return;
662 } else if ((c & 0xffff0000) == c) {
663 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
664 return;
665 } else if (mask64_operand(c, &mb, &me)) {
666 if (mb == 0) {
667 tcg_out_rld(s, RLDICR, dst, src, 0, me);
668 } else {
669 tcg_out_rld(s, RLDICL, dst, src, 0, mb);
670 }
671 } else {
672 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, c);
673 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
674 }
675 }
676
677 static void tcg_out_zori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c,
678 int op_lo, int op_hi)
679 {
680 if (c >> 16) {
681 tcg_out32(s, op_hi | SAI(src, dst, c >> 16));
682 src = dst;
683 }
684 if (c & 0xffff) {
685 tcg_out32(s, op_lo | SAI(src, dst, c));
686 src = dst;
687 }
688 }
689
690 static void tcg_out_ori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
691 {
692 tcg_out_zori32(s, dst, src, c, ORI, ORIS);
693 }
694
695 static void tcg_out_xori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
696 {
697 tcg_out_zori32(s, dst, src, c, XORI, XORIS);
698 }
699
700 static void tcg_out_b(TCGContext *s, int mask, tcg_target_long target)
701 {
702 tcg_target_long disp;
703
704 disp = target - (tcg_target_long)s->code_ptr;
705 if (in_range_b(disp)) {
706 tcg_out32(s, B | (disp & 0x3fffffc) | mask);
707 } else {
708 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, (tcg_target_long)target);
709 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | CTR);
710 tcg_out32(s, BCCTR | BO_ALWAYS | mask);
711 }
712 }
713
714 static void tcg_out_call(TCGContext *s, tcg_target_long arg, int const_arg)
715 {
716 #ifdef __APPLE__
717 if (const_arg) {
718 tcg_out_b(s, LK, arg);
719 } else {
720 tcg_out32(s, MTSPR | RS(arg) | LR);
721 tcg_out32(s, BCLR | BO_ALWAYS | LK);
722 }
723 #else
724 TCGReg reg = arg;
725 int ofs = 0;
726
727 if (const_arg) {
728 /* Look through the descriptor. If the branch is in range, and we
729 don't have to spend too much effort on building the toc. */
730 intptr_t tgt = ((intptr_t *)arg)[0];
731 intptr_t toc = ((intptr_t *)arg)[1];
732 intptr_t diff = tgt - (intptr_t)s->code_ptr;
733
734 if (in_range_b(diff) && toc == (uint32_t)toc) {
735 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R2, toc);
736 tcg_out_b(s, LK, tgt);
737 return;
738 }
739
740 /* Fold the low bits of the constant into the addresses below. */
741 ofs = (int16_t)arg;
742 if (ofs + 8 < 0x8000) {
743 arg -= ofs;
744 } else {
745 ofs = 0;
746 }
747 reg = TCG_REG_R2;
748 tcg_out_movi(s, TCG_TYPE_I64, reg, arg);
749 }
750
751 tcg_out32(s, LD | TAI(TCG_REG_R0, reg, ofs));
752 tcg_out32(s, MTSPR | RA(TCG_REG_R0) | CTR);
753 tcg_out32(s, LD | TAI(TCG_REG_R2, reg, ofs + 8));
754 tcg_out32(s, BCCTR | BO_ALWAYS | LK);
755 #endif
756 }
757
758 static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
759 TCGReg base, tcg_target_long offset)
760 {
761 tcg_target_long orig = offset, l0, l1, extra = 0, align = 0;
762 TCGReg rs = TCG_REG_R2;
763
764 assert(rt != TCG_REG_R2 && base != TCG_REG_R2);
765
766 switch (opi) {
767 case LD: case LWA:
768 align = 3;
769 /* FALLTHRU */
770 default:
771 if (rt != TCG_REG_R0) {
772 rs = rt;
773 }
774 break;
775 case STD:
776 align = 3;
777 break;
778 case STB: case STH: case STW:
779 break;
780 }
781
782 /* For unaligned, or very large offsets, use the indexed form. */
783 if (offset & align || offset != (int32_t)offset) {
784 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R2, orig);
785 tcg_out32(s, opx | TAB(rt, base, TCG_REG_R2));
786 return;
787 }
788
789 l0 = (int16_t)offset;
790 offset = (offset - l0) >> 16;
791 l1 = (int16_t)offset;
792
793 if (l1 < 0 && orig >= 0) {
794 extra = 0x4000;
795 l1 = (int16_t)(offset - 0x4000);
796 }
797 if (l1) {
798 tcg_out32(s, ADDIS | TAI(rs, base, l1));
799 base = rs;
800 }
801 if (extra) {
802 tcg_out32(s, ADDIS | TAI(rs, base, extra));
803 base = rs;
804 }
805 if (opi != ADDI || base != rt || l0 != 0) {
806 tcg_out32(s, opi | TAI(rt, base, l0));
807 }
808 }
809
810 #if defined(CONFIG_SOFTMMU)
811 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
812 int mmu_idx) */
813 static const void * const qemu_ld_helpers[4] = {
814 helper_ldb_mmu,
815 helper_ldw_mmu,
816 helper_ldl_mmu,
817 helper_ldq_mmu,
818 };
819
820 /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
821 uintxx_t val, int mmu_idx) */
822 static const void * const qemu_st_helpers[4] = {
823 helper_stb_mmu,
824 helper_stw_mmu,
825 helper_stl_mmu,
826 helper_stq_mmu,
827 };
828
829 /* Perform the TLB load and compare. Places the result of the comparison
830 in CR7, loads the addend of the TLB into R3, and returns the register
831 containing the guest address (zero-extended into R4). Clobbers R0 and R2. */
832
833 static TCGReg tcg_out_tlb_read(TCGContext *s, int s_bits, TCGReg addr_reg,
834 int mem_index, bool is_read)
835 {
836 int cmp_off
837 = (is_read
838 ? offsetof(CPUArchState, tlb_table[mem_index][0].addr_read)
839 : offsetof(CPUArchState, tlb_table[mem_index][0].addr_write));
840 int add_off = offsetof(CPUArchState, tlb_table[mem_index][0].addend);
841 TCGReg base = TCG_AREG0;
842
843 /* Extract the page index, shifted into place for tlb index. */
844 if (TARGET_LONG_BITS == 32) {
845 /* Zero-extend the address into a place helpful for further use. */
846 tcg_out_ext32u(s, TCG_REG_R4, addr_reg);
847 addr_reg = TCG_REG_R4;
848 } else {
849 tcg_out_rld(s, RLDICL, TCG_REG_R3, addr_reg,
850 64 - TARGET_PAGE_BITS, 64 - CPU_TLB_BITS);
851 }
852
853 /* Compensate for very large offsets. */
854 if (add_off >= 0x8000) {
855 /* Most target env are smaller than 32k; none are larger than 64k.
856 Simplify the logic here merely to offset by 0x7ff0, giving us a
857 range just shy of 64k. Check this assumption. */
858 QEMU_BUILD_BUG_ON(offsetof(CPUArchState,
859 tlb_table[NB_MMU_MODES - 1][1])
860 > 0x7ff0 + 0x7fff);
861 tcg_out32(s, ADDI | TAI(TCG_REG_R2, base, 0x7ff0));
862 base = TCG_REG_R2;
863 cmp_off -= 0x7ff0;
864 add_off -= 0x7ff0;
865 }
866
867 /* Extraction and shifting, part 2. */
868 if (TARGET_LONG_BITS == 32) {
869 tcg_out_rlw(s, RLWINM, TCG_REG_R3, addr_reg,
870 32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
871 32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS),
872 31 - CPU_TLB_ENTRY_BITS);
873 } else {
874 tcg_out_shli64(s, TCG_REG_R3, TCG_REG_R3, CPU_TLB_ENTRY_BITS);
875 }
876
877 tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, base));
878
879 /* Load the tlb comparator. */
880 tcg_out32(s, LD_ADDR | TAI(TCG_REG_R2, TCG_REG_R3, cmp_off));
881
882 /* Load the TLB addend for use on the fast path. Do this asap
883 to minimize any load use delay. */
884 tcg_out32(s, LD | TAI(TCG_REG_R3, TCG_REG_R3, add_off));
885
886 /* Clear the non-page, non-alignment bits from the address. */
887 if (TARGET_LONG_BITS == 32) {
888 tcg_out_rlw(s, RLWINM, TCG_REG_R0, addr_reg, 0,
889 (32 - s_bits) & 31, 31 - TARGET_PAGE_BITS);
890 } else if (!s_bits) {
891 tcg_out_rld(s, RLDICR, TCG_REG_R0, addr_reg, 0, 63 - TARGET_PAGE_BITS);
892 } else {
893 tcg_out_rld(s, RLDICL, TCG_REG_R0, addr_reg,
894 64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - s_bits);
895 tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BITS, 0);
896 }
897
898 tcg_out32(s, CMP | BF(7) | RA(TCG_REG_R0) | RB(TCG_REG_R2) | CMP_L);
899
900 return addr_reg;
901 }
902 #endif
903
904 static const uint32_t qemu_ldx_opc[8] = {
905 #ifdef TARGET_WORDS_BIGENDIAN
906 LBZX, LHZX, LWZX, LDX,
907 0, LHAX, LWAX, LDX
908 #else
909 LBZX, LHBRX, LWBRX, LDBRX,
910 0, 0, 0, LDBRX,
911 #endif
912 };
913
914 static const uint32_t qemu_stx_opc[4] = {
915 #ifdef TARGET_WORDS_BIGENDIAN
916 STBX, STHX, STWX, STDX
917 #else
918 STBX, STHBRX, STWBRX, STDBRX,
919 #endif
920 };
921
922 static const uint32_t qemu_exts_opc[4] = {
923 EXTSB, EXTSH, EXTSW, 0
924 };
925
926 static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
927 {
928 TCGReg addr_reg, data_reg, rbase;
929 uint32_t insn, s_bits;
930 #ifdef CONFIG_SOFTMMU
931 TCGReg ir;
932 int mem_index;
933 void *label1_ptr, *label2_ptr;
934 #endif
935
936 data_reg = *args++;
937 addr_reg = *args++;
938 s_bits = opc & 3;
939
940 #ifdef CONFIG_SOFTMMU
941 mem_index = *args;
942
943 addr_reg = tcg_out_tlb_read(s, s_bits, addr_reg, mem_index, true);
944
945 label1_ptr = s->code_ptr;
946 tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_TRUE);
947
948 /* slow path */
949 ir = TCG_REG_R3;
950 tcg_out_mov(s, TCG_TYPE_I64, ir++, TCG_AREG0);
951 tcg_out_mov(s, TCG_TYPE_I64, ir++, addr_reg);
952 tcg_out_movi(s, TCG_TYPE_I64, ir++, mem_index);
953
954 tcg_out_call(s, (tcg_target_long) qemu_ld_helpers[s_bits], 1);
955
956 if (opc & 4) {
957 insn = qemu_exts_opc[s_bits];
958 tcg_out32(s, insn | RA(data_reg) | RS(TCG_REG_R3));
959 } else if (data_reg != TCG_REG_R3) {
960 tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_R3);
961 }
962
963 label2_ptr = s->code_ptr;
964 tcg_out32(s, B);
965
966 /* label1: fast path */
967 reloc_pc14(label1_ptr, (tcg_target_long)s->code_ptr);
968
969 rbase = TCG_REG_R3;
970 #else /* !CONFIG_SOFTMMU */
971 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
972 if (TARGET_LONG_BITS == 32) {
973 tcg_out_ext32u(s, TCG_REG_R2, addr_reg);
974 addr_reg = TCG_REG_R2;
975 }
976 #endif
977
978 insn = qemu_ldx_opc[opc];
979 if (!HAVE_ISA_2_06 && insn == LDBRX) {
980 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addr_reg, 4));
981 tcg_out32(s, LWBRX | TAB(data_reg, rbase, addr_reg));
982 tcg_out32(s, LWBRX | TAB(TCG_REG_R0, rbase, TCG_REG_R0));
983 tcg_out_rld(s, RLDIMI, data_reg, TCG_REG_R0, 32, 0);
984 } else if (insn) {
985 tcg_out32(s, insn | TAB(data_reg, rbase, addr_reg));
986 } else {
987 insn = qemu_ldx_opc[s_bits];
988 tcg_out32(s, insn | TAB(data_reg, rbase, addr_reg));
989 insn = qemu_exts_opc[s_bits];
990 tcg_out32(s, insn | RA(data_reg) | RS(data_reg));
991 }
992
993 #ifdef CONFIG_SOFTMMU
994 reloc_pc24(label2_ptr, (tcg_target_long)s->code_ptr);
995 #endif
996 }
997
998 static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
999 {
1000 TCGReg addr_reg, rbase, data_reg;
1001 uint32_t insn;
1002 #ifdef CONFIG_SOFTMMU
1003 TCGReg ir;
1004 int mem_index;
1005 void *label1_ptr, *label2_ptr;
1006 #endif
1007
1008 data_reg = *args++;
1009 addr_reg = *args++;
1010
1011 #ifdef CONFIG_SOFTMMU
1012 mem_index = *args;
1013
1014 addr_reg = tcg_out_tlb_read(s, opc, addr_reg, mem_index, false);
1015
1016 label1_ptr = s->code_ptr;
1017 tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_TRUE);
1018
1019 /* slow path */
1020 ir = TCG_REG_R3;
1021 tcg_out_mov(s, TCG_TYPE_I64, ir++, TCG_AREG0);
1022 tcg_out_mov(s, TCG_TYPE_I64, ir++, addr_reg);
1023 tcg_out_rld(s, RLDICL, ir++, data_reg, 0, 64 - (1 << (3 + opc)));
1024 tcg_out_movi(s, TCG_TYPE_I64, ir++, mem_index);
1025
1026 tcg_out_call(s, (tcg_target_long)qemu_st_helpers[opc], 1);
1027
1028 label2_ptr = s->code_ptr;
1029 tcg_out32(s, B);
1030
1031 /* label1: fast path */
1032 reloc_pc14(label1_ptr, (tcg_target_long) s->code_ptr);
1033
1034 rbase = TCG_REG_R3;
1035 #else /* !CONFIG_SOFTMMU */
1036 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
1037 if (TARGET_LONG_BITS == 32) {
1038 tcg_out_ext32u(s, TCG_REG_R2, addr_reg);
1039 addr_reg = TCG_REG_R2;
1040 }
1041 #endif
1042
1043 insn = qemu_stx_opc[opc];
1044 if (!HAVE_ISA_2_06 && insn == STDBRX) {
1045 tcg_out32(s, STWBRX | SAB(data_reg, rbase, addr_reg));
1046 tcg_out32(s, ADDI | TAI(TCG_REG_R2, addr_reg, 4));
1047 tcg_out_shri64(s, TCG_REG_R0, data_reg, 32);
1048 tcg_out32(s, STWBRX | SAB(TCG_REG_R0, rbase, TCG_REG_R2));
1049 } else {
1050 tcg_out32(s, insn | SAB(data_reg, rbase, addr_reg));
1051 }
1052
1053 #ifdef CONFIG_SOFTMMU
1054 reloc_pc24(label2_ptr, (tcg_target_long)s->code_ptr);
1055 #endif
1056 }
1057
1058 #define FRAME_SIZE ((int) \
1059 ((8 /* back chain */ \
1060 + 8 /* CR */ \
1061 + 8 /* LR */ \
1062 + 8 /* compiler doubleword */ \
1063 + 8 /* link editor doubleword */ \
1064 + 8 /* TOC save area */ \
1065 + TCG_STATIC_CALL_ARGS_SIZE \
1066 + CPU_TEMP_BUF_NLONGS * sizeof(long) \
1067 + ARRAY_SIZE(tcg_target_callee_save_regs) * 8 \
1068 + 15) & ~15))
1069
1070 #define REG_SAVE_BOT (FRAME_SIZE - ARRAY_SIZE(tcg_target_callee_save_regs) * 8)
1071
1072 static void tcg_target_qemu_prologue(TCGContext *s)
1073 {
1074 int i;
1075
1076 tcg_set_frame(s, TCG_REG_CALL_STACK,
1077 REG_SAVE_BOT - CPU_TEMP_BUF_NLONGS * sizeof(long),
1078 CPU_TEMP_BUF_NLONGS * sizeof(long));
1079
1080 #ifndef __APPLE__
1081 /* First emit adhoc function descriptor */
1082 tcg_out64(s, (uint64_t)s->code_ptr + 24); /* entry point */
1083 s->code_ptr += 16; /* skip TOC and environment pointer */
1084 #endif
1085
1086 /* Prologue */
1087 tcg_out32(s, MFSPR | RT(TCG_REG_R0) | LR);
1088 tcg_out32(s, STDU | SAI(TCG_REG_R1, TCG_REG_R1, -FRAME_SIZE));
1089 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
1090 tcg_out32(s, STD | SAI(tcg_target_callee_save_regs[i], 1,
1091 REG_SAVE_BOT + i * 8));
1092 }
1093 tcg_out32(s, STD | SAI(TCG_REG_R0, TCG_REG_R1, FRAME_SIZE + 16));
1094
1095 #ifdef CONFIG_USE_GUEST_BASE
1096 if (GUEST_BASE) {
1097 tcg_out_movi(s, TCG_TYPE_I64, TCG_GUEST_BASE_REG, GUEST_BASE);
1098 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
1099 }
1100 #endif
1101
1102 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
1103 tcg_out32(s, MTSPR | RS(tcg_target_call_iarg_regs[1]) | CTR);
1104 tcg_out32(s, BCCTR | BO_ALWAYS);
1105
1106 /* Epilogue */
1107 tb_ret_addr = s->code_ptr;
1108
1109 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
1110 tcg_out32(s, LD | TAI(tcg_target_callee_save_regs[i], TCG_REG_R1,
1111 REG_SAVE_BOT + i * 8));
1112 }
1113 tcg_out32(s, LD | TAI(TCG_REG_R0, TCG_REG_R1, FRAME_SIZE + 16));
1114 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | LR);
1115 tcg_out32(s, ADDI | TAI(TCG_REG_R1, TCG_REG_R1, FRAME_SIZE));
1116 tcg_out32(s, BCLR | BO_ALWAYS);
1117 }
1118
1119 static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
1120 TCGReg arg1, intptr_t arg2)
1121 {
1122 int opi, opx;
1123
1124 if (type == TCG_TYPE_I32) {
1125 opi = LWZ, opx = LWZX;
1126 } else {
1127 opi = LD, opx = LDX;
1128 }
1129 tcg_out_mem_long(s, opi, opx, ret, arg1, arg2);
1130 }
1131
1132 static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
1133 TCGReg arg1, intptr_t arg2)
1134 {
1135 int opi, opx;
1136
1137 if (type == TCG_TYPE_I32) {
1138 opi = STW, opx = STWX;
1139 } else {
1140 opi = STD, opx = STDX;
1141 }
1142 tcg_out_mem_long(s, opi, opx, arg, arg1, arg2);
1143 }
1144
1145 static void tcg_out_cmp(TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
1146 int const_arg2, int cr, TCGType type)
1147 {
1148 int imm;
1149 uint32_t op;
1150
1151 /* Simplify the comparisons below wrt CMPI. */
1152 if (type == TCG_TYPE_I32) {
1153 arg2 = (int32_t)arg2;
1154 }
1155
1156 switch (cond) {
1157 case TCG_COND_EQ:
1158 case TCG_COND_NE:
1159 if (const_arg2) {
1160 if ((int16_t) arg2 == arg2) {
1161 op = CMPI;
1162 imm = 1;
1163 break;
1164 } else if ((uint16_t) arg2 == arg2) {
1165 op = CMPLI;
1166 imm = 1;
1167 break;
1168 }
1169 }
1170 op = CMPL;
1171 imm = 0;
1172 break;
1173
1174 case TCG_COND_LT:
1175 case TCG_COND_GE:
1176 case TCG_COND_LE:
1177 case TCG_COND_GT:
1178 if (const_arg2) {
1179 if ((int16_t) arg2 == arg2) {
1180 op = CMPI;
1181 imm = 1;
1182 break;
1183 }
1184 }
1185 op = CMP;
1186 imm = 0;
1187 break;
1188
1189 case TCG_COND_LTU:
1190 case TCG_COND_GEU:
1191 case TCG_COND_LEU:
1192 case TCG_COND_GTU:
1193 if (const_arg2) {
1194 if ((uint16_t) arg2 == arg2) {
1195 op = CMPLI;
1196 imm = 1;
1197 break;
1198 }
1199 }
1200 op = CMPL;
1201 imm = 0;
1202 break;
1203
1204 default:
1205 tcg_abort();
1206 }
1207 op |= BF(cr) | ((type == TCG_TYPE_I64) << 21);
1208
1209 if (imm) {
1210 tcg_out32(s, op | RA(arg1) | (arg2 & 0xffff));
1211 } else {
1212 if (const_arg2) {
1213 tcg_out_movi(s, type, TCG_REG_R0, arg2);
1214 arg2 = TCG_REG_R0;
1215 }
1216 tcg_out32(s, op | RA(arg1) | RB(arg2));
1217 }
1218 }
1219
1220 static void tcg_out_setcond_eq0(TCGContext *s, TCGType type,
1221 TCGReg dst, TCGReg src)
1222 {
1223 tcg_out32(s, (type == TCG_TYPE_I64 ? CNTLZD : CNTLZW) | RS(src) | RA(dst));
1224 tcg_out_shri64(s, dst, dst, type == TCG_TYPE_I64 ? 6 : 5);
1225 }
1226
1227 static void tcg_out_setcond_ne0(TCGContext *s, TCGReg dst, TCGReg src)
1228 {
1229 /* X != 0 implies X + -1 generates a carry. Extra addition
1230 trickery means: R = X-1 + ~X + C = X-1 + (-X+1) + C = C. */
1231 if (dst != src) {
1232 tcg_out32(s, ADDIC | TAI(dst, src, -1));
1233 tcg_out32(s, SUBFE | TAB(dst, dst, src));
1234 } else {
1235 tcg_out32(s, ADDIC | TAI(TCG_REG_R0, src, -1));
1236 tcg_out32(s, SUBFE | TAB(dst, TCG_REG_R0, src));
1237 }
1238 }
1239
1240 static TCGReg tcg_gen_setcond_xor(TCGContext *s, TCGReg arg1, TCGArg arg2,
1241 bool const_arg2)
1242 {
1243 if (const_arg2) {
1244 if ((uint32_t)arg2 == arg2) {
1245 tcg_out_xori32(s, TCG_REG_R0, arg1, arg2);
1246 } else {
1247 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, arg2);
1248 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, TCG_REG_R0));
1249 }
1250 } else {
1251 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, arg2));
1252 }
1253 return TCG_REG_R0;
1254 }
1255
1256 static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond,
1257 TCGArg arg0, TCGArg arg1, TCGArg arg2,
1258 int const_arg2)
1259 {
1260 int crop, sh;
1261
1262 /* Ignore high bits of a potential constant arg2. */
1263 if (type == TCG_TYPE_I32) {
1264 arg2 = (uint32_t)arg2;
1265 }
1266
1267 /* Handle common and trivial cases before handling anything else. */
1268 if (arg2 == 0) {
1269 switch (cond) {
1270 case TCG_COND_EQ:
1271 tcg_out_setcond_eq0(s, type, arg0, arg1);
1272 return;
1273 case TCG_COND_NE:
1274 if (type == TCG_TYPE_I32) {
1275 tcg_out_ext32u(s, TCG_REG_R0, arg1);
1276 arg1 = TCG_REG_R0;
1277 }
1278 tcg_out_setcond_ne0(s, arg0, arg1);
1279 return;
1280 case TCG_COND_GE:
1281 tcg_out32(s, NOR | SAB(arg1, arg0, arg1));
1282 arg1 = arg0;
1283 /* FALLTHRU */
1284 case TCG_COND_LT:
1285 /* Extract the sign bit. */
1286 tcg_out_rld(s, RLDICL, arg0, arg1,
1287 type == TCG_TYPE_I64 ? 1 : 33, 63);
1288 return;
1289 default:
1290 break;
1291 }
1292 }
1293
1294 /* If we have ISEL, we can implement everything with 3 or 4 insns.
1295 All other cases below are also at least 3 insns, so speed up the
1296 code generator by not considering them and always using ISEL. */
1297 if (HAVE_ISEL) {
1298 int isel, tab;
1299
1300 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1301
1302 isel = tcg_to_isel[cond];
1303
1304 tcg_out_movi(s, type, arg0, 1);
1305 if (isel & 1) {
1306 /* arg0 = (bc ? 0 : 1) */
1307 tab = TAB(arg0, 0, arg0);
1308 isel &= ~1;
1309 } else {
1310 /* arg0 = (bc ? 1 : 0) */
1311 tcg_out_movi(s, type, TCG_REG_R0, 0);
1312 tab = TAB(arg0, arg0, TCG_REG_R0);
1313 }
1314 tcg_out32(s, isel | tab);
1315 return;
1316 }
1317
1318 switch (cond) {
1319 case TCG_COND_EQ:
1320 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
1321 tcg_out_setcond_eq0(s, type, arg0, arg1);
1322 return;
1323
1324 case TCG_COND_NE:
1325 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
1326 /* Discard the high bits only once, rather than both inputs. */
1327 if (type == TCG_TYPE_I32) {
1328 tcg_out_ext32u(s, TCG_REG_R0, arg1);
1329 arg1 = TCG_REG_R0;
1330 }
1331 tcg_out_setcond_ne0(s, arg0, arg1);
1332 return;
1333
1334 case TCG_COND_GT:
1335 case TCG_COND_GTU:
1336 sh = 30;
1337 crop = 0;
1338 goto crtest;
1339
1340 case TCG_COND_LT:
1341 case TCG_COND_LTU:
1342 sh = 29;
1343 crop = 0;
1344 goto crtest;
1345
1346 case TCG_COND_GE:
1347 case TCG_COND_GEU:
1348 sh = 31;
1349 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_LT) | BB(7, CR_LT);
1350 goto crtest;
1351
1352 case TCG_COND_LE:
1353 case TCG_COND_LEU:
1354 sh = 31;
1355 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_GT) | BB(7, CR_GT);
1356 crtest:
1357 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1358 if (crop) {
1359 tcg_out32(s, crop);
1360 }
1361 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7));
1362 tcg_out_rlw(s, RLWINM, arg0, TCG_REG_R0, sh, 31, 31);
1363 break;
1364
1365 default:
1366 tcg_abort();
1367 }
1368 }
1369
1370 static void tcg_out_bc(TCGContext *s, int bc, int label_index)
1371 {
1372 TCGLabel *l = &s->labels[label_index];
1373
1374 if (l->has_value) {
1375 tcg_out32(s, bc | reloc_pc14_val(s->code_ptr, l->u.value));
1376 } else {
1377 tcg_out_reloc(s, s->code_ptr, R_PPC_REL14, label_index, 0);
1378 tcg_out_bc_noaddr(s, bc);
1379 }
1380 }
1381
1382 static void tcg_out_brcond(TCGContext *s, TCGCond cond,
1383 TCGArg arg1, TCGArg arg2, int const_arg2,
1384 int label_index, TCGType type)
1385 {
1386 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1387 tcg_out_bc(s, tcg_to_bc[cond], label_index);
1388 }
1389
1390 static void tcg_out_movcond(TCGContext *s, TCGType type, TCGCond cond,
1391 TCGArg dest, TCGArg c1, TCGArg c2, TCGArg v1,
1392 TCGArg v2, bool const_c2)
1393 {
1394 /* If for some reason both inputs are zero, don't produce bad code. */
1395 if (v1 == 0 && v2 == 0) {
1396 tcg_out_movi(s, type, dest, 0);
1397 return;
1398 }
1399
1400 tcg_out_cmp(s, cond, c1, c2, const_c2, 7, type);
1401
1402 if (HAVE_ISEL) {
1403 int isel = tcg_to_isel[cond];
1404
1405 /* Swap the V operands if the operation indicates inversion. */
1406 if (isel & 1) {
1407 int t = v1;
1408 v1 = v2;
1409 v2 = t;
1410 isel &= ~1;
1411 }
1412 /* V1 == 0 is handled by isel; V2 == 0 must be handled by hand. */
1413 if (v2 == 0) {
1414 tcg_out_movi(s, type, TCG_REG_R0, 0);
1415 }
1416 tcg_out32(s, isel | TAB(dest, v1, v2));
1417 } else {
1418 if (dest == v2) {
1419 cond = tcg_invert_cond(cond);
1420 v2 = v1;
1421 } else if (dest != v1) {
1422 if (v1 == 0) {
1423 tcg_out_movi(s, type, dest, 0);
1424 } else {
1425 tcg_out_mov(s, type, dest, v1);
1426 }
1427 }
1428 /* Branch forward over one insn */
1429 tcg_out32(s, tcg_to_bc[cond] | 8);
1430 if (v2 == 0) {
1431 tcg_out_movi(s, type, dest, 0);
1432 } else {
1433 tcg_out_mov(s, type, dest, v2);
1434 }
1435 }
1436 }
1437
1438 void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr)
1439 {
1440 TCGContext s;
1441 unsigned long patch_size;
1442
1443 s.code_ptr = (uint8_t *) jmp_addr;
1444 tcg_out_b(&s, 0, addr);
1445 patch_size = s.code_ptr - (uint8_t *) jmp_addr;
1446 flush_icache_range(jmp_addr, jmp_addr + patch_size);
1447 }
1448
1449 static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
1450 const int *const_args)
1451 {
1452 TCGArg a0, a1, a2;
1453 int c;
1454
1455 switch (opc) {
1456 case INDEX_op_exit_tb:
1457 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R3, args[0]);
1458 tcg_out_b(s, 0, (tcg_target_long)tb_ret_addr);
1459 break;
1460 case INDEX_op_goto_tb:
1461 if (s->tb_jmp_offset) {
1462 /* Direct jump method. */
1463 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1464 s->code_ptr += 28;
1465 } else {
1466 /* Indirect jump method. */
1467 tcg_abort();
1468 }
1469 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1470 break;
1471 case INDEX_op_br:
1472 {
1473 TCGLabel *l = &s->labels[args[0]];
1474
1475 if (l->has_value) {
1476 tcg_out_b(s, 0, l->u.value);
1477 } else {
1478 tcg_out_reloc(s, s->code_ptr, R_PPC_REL24, args[0], 0);
1479 tcg_out_b_noaddr(s, B);
1480 }
1481 }
1482 break;
1483 case INDEX_op_call:
1484 tcg_out_call(s, args[0], const_args[0]);
1485 break;
1486 case INDEX_op_movi_i32:
1487 tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
1488 break;
1489 case INDEX_op_movi_i64:
1490 tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
1491 break;
1492 case INDEX_op_ld8u_i32:
1493 case INDEX_op_ld8u_i64:
1494 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
1495 break;
1496 case INDEX_op_ld8s_i32:
1497 case INDEX_op_ld8s_i64:
1498 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
1499 tcg_out32(s, EXTSB | RS(args[0]) | RA(args[0]));
1500 break;
1501 case INDEX_op_ld16u_i32:
1502 case INDEX_op_ld16u_i64:
1503 tcg_out_mem_long(s, LHZ, LHZX, args[0], args[1], args[2]);
1504 break;
1505 case INDEX_op_ld16s_i32:
1506 case INDEX_op_ld16s_i64:
1507 tcg_out_mem_long(s, LHA, LHAX, args[0], args[1], args[2]);
1508 break;
1509 case INDEX_op_ld_i32:
1510 case INDEX_op_ld32u_i64:
1511 tcg_out_mem_long(s, LWZ, LWZX, args[0], args[1], args[2]);
1512 break;
1513 case INDEX_op_ld32s_i64:
1514 tcg_out_mem_long(s, LWA, LWAX, args[0], args[1], args[2]);
1515 break;
1516 case INDEX_op_ld_i64:
1517 tcg_out_mem_long(s, LD, LDX, args[0], args[1], args[2]);
1518 break;
1519 case INDEX_op_st8_i32:
1520 case INDEX_op_st8_i64:
1521 tcg_out_mem_long(s, STB, STBX, args[0], args[1], args[2]);
1522 break;
1523 case INDEX_op_st16_i32:
1524 case INDEX_op_st16_i64:
1525 tcg_out_mem_long(s, STH, STHX, args[0], args[1], args[2]);
1526 break;
1527 case INDEX_op_st_i32:
1528 case INDEX_op_st32_i64:
1529 tcg_out_mem_long(s, STW, STWX, args[0], args[1], args[2]);
1530 break;
1531 case INDEX_op_st_i64:
1532 tcg_out_mem_long(s, STD, STDX, args[0], args[1], args[2]);
1533 break;
1534
1535 case INDEX_op_add_i32:
1536 a0 = args[0], a1 = args[1], a2 = args[2];
1537 if (const_args[2]) {
1538 do_addi_32:
1539 tcg_out_mem_long(s, ADDI, ADD, a0, a1, (int32_t)a2);
1540 } else {
1541 tcg_out32(s, ADD | TAB(a0, a1, a2));
1542 }
1543 break;
1544 case INDEX_op_sub_i32:
1545 a0 = args[0], a1 = args[1], a2 = args[2];
1546 if (const_args[1]) {
1547 if (const_args[2]) {
1548 tcg_out_movi(s, TCG_TYPE_I32, a0, a1 - a2);
1549 } else {
1550 tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
1551 }
1552 } else if (const_args[2]) {
1553 a2 = -a2;
1554 goto do_addi_32;
1555 } else {
1556 tcg_out32(s, SUBF | TAB(a0, a2, a1));
1557 }
1558 break;
1559
1560 case INDEX_op_and_i32:
1561 a0 = args[0], a1 = args[1], a2 = args[2];
1562 if (const_args[2]) {
1563 tcg_out_andi32(s, a0, a1, a2);
1564 } else {
1565 tcg_out32(s, AND | SAB(a1, a0, a2));
1566 }
1567 break;
1568 case INDEX_op_and_i64:
1569 a0 = args[0], a1 = args[1], a2 = args[2];
1570 if (const_args[2]) {
1571 tcg_out_andi64(s, a0, a1, a2);
1572 } else {
1573 tcg_out32(s, AND | SAB(a1, a0, a2));
1574 }
1575 break;
1576 case INDEX_op_or_i64:
1577 case INDEX_op_or_i32:
1578 a0 = args[0], a1 = args[1], a2 = args[2];
1579 if (const_args[2]) {
1580 tcg_out_ori32(s, a0, a1, a2);
1581 } else {
1582 tcg_out32(s, OR | SAB(a1, a0, a2));
1583 }
1584 break;
1585 case INDEX_op_xor_i64:
1586 case INDEX_op_xor_i32:
1587 a0 = args[0], a1 = args[1], a2 = args[2];
1588 if (const_args[2]) {
1589 tcg_out_xori32(s, a0, a1, a2);
1590 } else {
1591 tcg_out32(s, XOR | SAB(a1, a0, a2));
1592 }
1593 break;
1594 case INDEX_op_andc_i32:
1595 a0 = args[0], a1 = args[1], a2 = args[2];
1596 if (const_args[2]) {
1597 tcg_out_andi32(s, a0, a1, ~a2);
1598 } else {
1599 tcg_out32(s, ANDC | SAB(a1, a0, a2));
1600 }
1601 break;
1602 case INDEX_op_andc_i64:
1603 a0 = args[0], a1 = args[1], a2 = args[2];
1604 if (const_args[2]) {
1605 tcg_out_andi64(s, a0, a1, ~a2);
1606 } else {
1607 tcg_out32(s, ANDC | SAB(a1, a0, a2));
1608 }
1609 break;
1610 case INDEX_op_orc_i32:
1611 if (const_args[2]) {
1612 tcg_out_ori32(s, args[0], args[1], ~args[2]);
1613 break;
1614 }
1615 /* FALLTHRU */
1616 case INDEX_op_orc_i64:
1617 tcg_out32(s, ORC | SAB(args[1], args[0], args[2]));
1618 break;
1619 case INDEX_op_eqv_i32:
1620 if (const_args[2]) {
1621 tcg_out_xori32(s, args[0], args[1], ~args[2]);
1622 break;
1623 }
1624 /* FALLTHRU */
1625 case INDEX_op_eqv_i64:
1626 tcg_out32(s, EQV | SAB(args[1], args[0], args[2]));
1627 break;
1628 case INDEX_op_nand_i32:
1629 case INDEX_op_nand_i64:
1630 tcg_out32(s, NAND | SAB(args[1], args[0], args[2]));
1631 break;
1632 case INDEX_op_nor_i32:
1633 case INDEX_op_nor_i64:
1634 tcg_out32(s, NOR | SAB(args[1], args[0], args[2]));
1635 break;
1636
1637 case INDEX_op_mul_i32:
1638 a0 = args[0], a1 = args[1], a2 = args[2];
1639 if (const_args[2]) {
1640 tcg_out32(s, MULLI | TAI(a0, a1, a2));
1641 } else {
1642 tcg_out32(s, MULLW | TAB(a0, a1, a2));
1643 }
1644 break;
1645
1646 case INDEX_op_div_i32:
1647 tcg_out32(s, DIVW | TAB(args[0], args[1], args[2]));
1648 break;
1649
1650 case INDEX_op_divu_i32:
1651 tcg_out32(s, DIVWU | TAB(args[0], args[1], args[2]));
1652 break;
1653
1654 case INDEX_op_shl_i32:
1655 if (const_args[2]) {
1656 tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31 - args[2]);
1657 } else {
1658 tcg_out32(s, SLW | SAB(args[1], args[0], args[2]));
1659 }
1660 break;
1661 case INDEX_op_shr_i32:
1662 if (const_args[2]) {
1663 tcg_out_rlw(s, RLWINM, args[0], args[1], 32 - args[2], args[2], 31);
1664 } else {
1665 tcg_out32(s, SRW | SAB(args[1], args[0], args[2]));
1666 }
1667 break;
1668 case INDEX_op_sar_i32:
1669 if (const_args[2]) {
1670 tcg_out32(s, SRAWI | RS(args[1]) | RA(args[0]) | SH(args[2]));
1671 } else {
1672 tcg_out32(s, SRAW | SAB(args[1], args[0], args[2]));
1673 }
1674 break;
1675 case INDEX_op_rotl_i32:
1676 if (const_args[2]) {
1677 tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31);
1678 } else {
1679 tcg_out32(s, RLWNM | SAB(args[1], args[0], args[2])
1680 | MB(0) | ME(31));
1681 }
1682 break;
1683 case INDEX_op_rotr_i32:
1684 if (const_args[2]) {
1685 tcg_out_rlw(s, RLWINM, args[0], args[1], 32 - args[2], 0, 31);
1686 } else {
1687 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 32));
1688 tcg_out32(s, RLWNM | SAB(args[1], args[0], TCG_REG_R0)
1689 | MB(0) | ME(31));
1690 }
1691 break;
1692
1693 case INDEX_op_brcond_i32:
1694 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
1695 args[3], TCG_TYPE_I32);
1696 break;
1697
1698 case INDEX_op_brcond_i64:
1699 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
1700 args[3], TCG_TYPE_I64);
1701 break;
1702
1703 case INDEX_op_neg_i32:
1704 case INDEX_op_neg_i64:
1705 tcg_out32(s, NEG | RT(args[0]) | RA(args[1]));
1706 break;
1707
1708 case INDEX_op_not_i32:
1709 case INDEX_op_not_i64:
1710 tcg_out32(s, NOR | SAB(args[1], args[0], args[1]));
1711 break;
1712
1713 case INDEX_op_add_i64:
1714 a0 = args[0], a1 = args[1], a2 = args[2];
1715 if (const_args[2]) {
1716 do_addi_64:
1717 tcg_out_mem_long(s, ADDI, ADD, a0, a1, a2);
1718 } else {
1719 tcg_out32(s, ADD | TAB(a0, a1, a2));
1720 }
1721 break;
1722 case INDEX_op_sub_i64:
1723 a0 = args[0], a1 = args[1], a2 = args[2];
1724 if (const_args[1]) {
1725 if (const_args[2]) {
1726 tcg_out_movi(s, TCG_TYPE_I64, a0, a1 - a2);
1727 } else {
1728 tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
1729 }
1730 } else if (const_args[2]) {
1731 a2 = -a2;
1732 goto do_addi_64;
1733 } else {
1734 tcg_out32(s, SUBF | TAB(a0, a2, a1));
1735 }
1736 break;
1737
1738 case INDEX_op_shl_i64:
1739 if (const_args[2]) {
1740 tcg_out_shli64(s, args[0], args[1], args[2]);
1741 } else {
1742 tcg_out32(s, SLD | SAB(args[1], args[0], args[2]));
1743 }
1744 break;
1745 case INDEX_op_shr_i64:
1746 if (const_args[2]) {
1747 tcg_out_shri64(s, args[0], args[1], args[2]);
1748 } else {
1749 tcg_out32(s, SRD | SAB(args[1], args[0], args[2]));
1750 }
1751 break;
1752 case INDEX_op_sar_i64:
1753 if (const_args[2]) {
1754 int sh = SH(args[2] & 0x1f) | (((args[2] >> 5) & 1) << 1);
1755 tcg_out32(s, SRADI | RA(args[0]) | RS(args[1]) | sh);
1756 } else {
1757 tcg_out32(s, SRAD | SAB(args[1], args[0], args[2]));
1758 }
1759 break;
1760 case INDEX_op_rotl_i64:
1761 if (const_args[2]) {
1762 tcg_out_rld(s, RLDICL, args[0], args[1], args[2], 0);
1763 } else {
1764 tcg_out32(s, RLDCL | SAB(args[1], args[0], args[2]) | MB64(0));
1765 }
1766 break;
1767 case INDEX_op_rotr_i64:
1768 if (const_args[2]) {
1769 tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 0);
1770 } else {
1771 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 64));
1772 tcg_out32(s, RLDCL | SAB(args[1], args[0], TCG_REG_R0) | MB64(0));
1773 }
1774 break;
1775
1776 case INDEX_op_mul_i64:
1777 a0 = args[0], a1 = args[1], a2 = args[2];
1778 if (const_args[2]) {
1779 tcg_out32(s, MULLI | TAI(a0, a1, a2));
1780 } else {
1781 tcg_out32(s, MULLD | TAB(a0, a1, a2));
1782 }
1783 break;
1784 case INDEX_op_div_i64:
1785 tcg_out32(s, DIVD | TAB(args[0], args[1], args[2]));
1786 break;
1787 case INDEX_op_divu_i64:
1788 tcg_out32(s, DIVDU | TAB(args[0], args[1], args[2]));
1789 break;
1790
1791 case INDEX_op_qemu_ld8u:
1792 tcg_out_qemu_ld(s, args, 0);
1793 break;
1794 case INDEX_op_qemu_ld8s:
1795 tcg_out_qemu_ld(s, args, 0 | 4);
1796 break;
1797 case INDEX_op_qemu_ld16u:
1798 tcg_out_qemu_ld(s, args, 1);
1799 break;
1800 case INDEX_op_qemu_ld16s:
1801 tcg_out_qemu_ld(s, args, 1 | 4);
1802 break;
1803 case INDEX_op_qemu_ld32:
1804 case INDEX_op_qemu_ld32u:
1805 tcg_out_qemu_ld(s, args, 2);
1806 break;
1807 case INDEX_op_qemu_ld32s:
1808 tcg_out_qemu_ld(s, args, 2 | 4);
1809 break;
1810 case INDEX_op_qemu_ld64:
1811 tcg_out_qemu_ld(s, args, 3);
1812 break;
1813 case INDEX_op_qemu_st8:
1814 tcg_out_qemu_st(s, args, 0);
1815 break;
1816 case INDEX_op_qemu_st16:
1817 tcg_out_qemu_st(s, args, 1);
1818 break;
1819 case INDEX_op_qemu_st32:
1820 tcg_out_qemu_st(s, args, 2);
1821 break;
1822 case INDEX_op_qemu_st64:
1823 tcg_out_qemu_st(s, args, 3);
1824 break;
1825
1826 case INDEX_op_ext8s_i32:
1827 case INDEX_op_ext8s_i64:
1828 c = EXTSB;
1829 goto gen_ext;
1830 case INDEX_op_ext16s_i32:
1831 case INDEX_op_ext16s_i64:
1832 c = EXTSH;
1833 goto gen_ext;
1834 case INDEX_op_ext32s_i64:
1835 c = EXTSW;
1836 goto gen_ext;
1837 gen_ext:
1838 tcg_out32(s, c | RS(args[1]) | RA(args[0]));
1839 break;
1840
1841 case INDEX_op_setcond_i32:
1842 tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2],
1843 const_args[2]);
1844 break;
1845 case INDEX_op_setcond_i64:
1846 tcg_out_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], args[2],
1847 const_args[2]);
1848 break;
1849
1850 case INDEX_op_bswap16_i32:
1851 case INDEX_op_bswap16_i64:
1852 a0 = args[0], a1 = args[1];
1853 /* a1 = abcd */
1854 if (a0 != a1) {
1855 /* a0 = (a1 r<< 24) & 0xff # 000c */
1856 tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
1857 /* a0 = (a0 & ~0xff00) | (a1 r<< 8) & 0xff00 # 00dc */
1858 tcg_out_rlw(s, RLWIMI, a0, a1, 8, 16, 23);
1859 } else {
1860 /* r0 = (a1 r<< 8) & 0xff00 # 00d0 */
1861 tcg_out_rlw(s, RLWINM, TCG_REG_R0, a1, 8, 16, 23);
1862 /* a0 = (a1 r<< 24) & 0xff # 000c */
1863 tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
1864 /* a0 = a0 | r0 # 00dc */
1865 tcg_out32(s, OR | SAB(TCG_REG_R0, a0, a0));
1866 }
1867 break;
1868
1869 case INDEX_op_bswap32_i32:
1870 case INDEX_op_bswap32_i64:
1871 /* Stolen from gcc's builtin_bswap32 */
1872 a1 = args[1];
1873 a0 = args[0] == a1 ? TCG_REG_R0 : args[0];
1874
1875 /* a1 = args[1] # abcd */
1876 /* a0 = rotate_left (a1, 8) # bcda */
1877 tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
1878 /* a0 = (a0 & ~0xff000000) | ((a1 r<< 24) & 0xff000000) # dcda */
1879 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
1880 /* a0 = (a0 & ~0x0000ff00) | ((a1 r<< 24) & 0x0000ff00) # dcba */
1881 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
1882
1883 if (a0 == TCG_REG_R0) {
1884 tcg_out_mov(s, TCG_TYPE_I64, args[0], a0);
1885 }
1886 break;
1887
1888 case INDEX_op_bswap64_i64:
1889 a0 = args[0], a1 = args[1], a2 = TCG_REG_R0;
1890 if (a0 == a1) {
1891 a0 = TCG_REG_R0;
1892 a2 = a1;
1893 }
1894
1895 /* a1 = # abcd efgh */
1896 /* a0 = rl32(a1, 8) # 0000 fghe */
1897 tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
1898 /* a0 = dep(a0, rl32(a1, 24), 0xff000000) # 0000 hghe */
1899 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
1900 /* a0 = dep(a0, rl32(a1, 24), 0x0000ff00) # 0000 hgfe */
1901 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
1902
1903 /* a0 = rl64(a0, 32) # hgfe 0000 */
1904 /* a2 = rl64(a1, 32) # efgh abcd */
1905 tcg_out_rld(s, RLDICL, a0, a0, 32, 0);
1906 tcg_out_rld(s, RLDICL, a2, a1, 32, 0);
1907
1908 /* a0 = dep(a0, rl32(a2, 8), 0xffffffff) # hgfe bcda */
1909 tcg_out_rlw(s, RLWIMI, a0, a2, 8, 0, 31);
1910 /* a0 = dep(a0, rl32(a2, 24), 0xff000000) # hgfe dcda */
1911 tcg_out_rlw(s, RLWIMI, a0, a2, 24, 0, 7);
1912 /* a0 = dep(a0, rl32(a2, 24), 0x0000ff00) # hgfe dcba */
1913 tcg_out_rlw(s, RLWIMI, a0, a2, 24, 16, 23);
1914
1915 if (a0 == 0) {
1916 tcg_out_mov(s, TCG_TYPE_I64, args[0], a0);
1917 }
1918 break;
1919
1920 case INDEX_op_deposit_i32:
1921 if (const_args[2]) {
1922 uint32_t mask = ((2u << (args[4] - 1)) - 1) << args[3];
1923 tcg_out_andi32(s, args[0], args[0], ~mask);
1924 } else {
1925 tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3],
1926 32 - args[3] - args[4], 31 - args[3]);
1927 }
1928 break;
1929 case INDEX_op_deposit_i64:
1930 if (const_args[2]) {
1931 uint64_t mask = ((2ull << (args[4] - 1)) - 1) << args[3];
1932 tcg_out_andi64(s, args[0], args[0], ~mask);
1933 } else {
1934 tcg_out_rld(s, RLDIMI, args[0], args[2], args[3],
1935 64 - args[3] - args[4]);
1936 }
1937 break;
1938
1939 case INDEX_op_movcond_i32:
1940 tcg_out_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], args[2],
1941 args[3], args[4], const_args[2]);
1942 break;
1943 case INDEX_op_movcond_i64:
1944 tcg_out_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], args[2],
1945 args[3], args[4], const_args[2]);
1946 break;
1947
1948 case INDEX_op_add2_i64:
1949 /* Note that the CA bit is defined based on the word size of the
1950 environment. So in 64-bit mode it's always carry-out of bit 63.
1951 The fallback code using deposit works just as well for 32-bit. */
1952 a0 = args[0], a1 = args[1];
1953 if (a0 == args[3] || (!const_args[5] && a0 == args[5])) {
1954 a0 = TCG_REG_R0;
1955 }
1956 if (const_args[4]) {
1957 tcg_out32(s, ADDIC | TAI(a0, args[2], args[4]));
1958 } else {
1959 tcg_out32(s, ADDC | TAB(a0, args[2], args[4]));
1960 }
1961 if (const_args[5]) {
1962 tcg_out32(s, (args[5] ? ADDME : ADDZE) | RT(a1) | RA(args[3]));
1963 } else {
1964 tcg_out32(s, ADDE | TAB(a1, args[3], args[5]));
1965 }
1966 if (a0 != args[0]) {
1967 tcg_out_mov(s, TCG_TYPE_I64, args[0], a0);
1968 }
1969 break;
1970
1971 case INDEX_op_sub2_i64:
1972 a0 = args[0], a1 = args[1];
1973 if (a0 == args[5] || (!const_args[4] && a0 == args[4])) {
1974 a0 = TCG_REG_R0;
1975 }
1976 if (const_args[2]) {
1977 tcg_out32(s, SUBFIC | TAI(a0, args[3], args[2]));
1978 } else {
1979 tcg_out32(s, SUBFC | TAB(a0, args[3], args[2]));
1980 }
1981 if (const_args[4]) {
1982 tcg_out32(s, (args[4] ? SUBFME : SUBFZE) | RT(a1) | RA(args[5]));
1983 } else {
1984 tcg_out32(s, SUBFE | TAB(a1, args[5], args[4]));
1985 }
1986 if (a0 != args[0]) {
1987 tcg_out_mov(s, TCG_TYPE_I64, args[0], a0);
1988 }
1989 break;
1990
1991 case INDEX_op_muluh_i64:
1992 tcg_out32(s, MULHDU | TAB(args[0], args[1], args[2]));
1993 break;
1994 case INDEX_op_mulsh_i64:
1995 tcg_out32(s, MULHD | TAB(args[0], args[1], args[2]));
1996 break;
1997
1998 default:
1999 tcg_dump_ops(s);
2000 tcg_abort();
2001 }
2002 }
2003
2004 static const TCGTargetOpDef ppc_op_defs[] = {
2005 { INDEX_op_exit_tb, { } },
2006 { INDEX_op_goto_tb, { } },
2007 { INDEX_op_call, { "ri" } },
2008 { INDEX_op_br, { } },
2009
2010 { INDEX_op_mov_i32, { "r", "r" } },
2011 { INDEX_op_mov_i64, { "r", "r" } },
2012 { INDEX_op_movi_i32, { "r" } },
2013 { INDEX_op_movi_i64, { "r" } },
2014
2015 { INDEX_op_ld8u_i32, { "r", "r" } },
2016 { INDEX_op_ld8s_i32, { "r", "r" } },
2017 { INDEX_op_ld16u_i32, { "r", "r" } },
2018 { INDEX_op_ld16s_i32, { "r", "r" } },
2019 { INDEX_op_ld_i32, { "r", "r" } },
2020 { INDEX_op_ld_i64, { "r", "r" } },
2021 { INDEX_op_st8_i32, { "r", "r" } },
2022 { INDEX_op_st8_i64, { "r", "r" } },
2023 { INDEX_op_st16_i32, { "r", "r" } },
2024 { INDEX_op_st16_i64, { "r", "r" } },
2025 { INDEX_op_st_i32, { "r", "r" } },
2026 { INDEX_op_st_i64, { "r", "r" } },
2027 { INDEX_op_st32_i64, { "r", "r" } },
2028
2029 { INDEX_op_ld8u_i64, { "r", "r" } },
2030 { INDEX_op_ld8s_i64, { "r", "r" } },
2031 { INDEX_op_ld16u_i64, { "r", "r" } },
2032 { INDEX_op_ld16s_i64, { "r", "r" } },
2033 { INDEX_op_ld32u_i64, { "r", "r" } },
2034 { INDEX_op_ld32s_i64, { "r", "r" } },
2035
2036 { INDEX_op_add_i32, { "r", "r", "ri" } },
2037 { INDEX_op_mul_i32, { "r", "r", "rI" } },
2038 { INDEX_op_div_i32, { "r", "r", "r" } },
2039 { INDEX_op_divu_i32, { "r", "r", "r" } },
2040 { INDEX_op_sub_i32, { "r", "rI", "ri" } },
2041 { INDEX_op_and_i32, { "r", "r", "ri" } },
2042 { INDEX_op_or_i32, { "r", "r", "ri" } },
2043 { INDEX_op_xor_i32, { "r", "r", "ri" } },
2044 { INDEX_op_andc_i32, { "r", "r", "ri" } },
2045 { INDEX_op_orc_i32, { "r", "r", "ri" } },
2046 { INDEX_op_eqv_i32, { "r", "r", "ri" } },
2047 { INDEX_op_nand_i32, { "r", "r", "r" } },
2048 { INDEX_op_nor_i32, { "r", "r", "r" } },
2049
2050 { INDEX_op_shl_i32, { "r", "r", "ri" } },
2051 { INDEX_op_shr_i32, { "r", "r", "ri" } },
2052 { INDEX_op_sar_i32, { "r", "r", "ri" } },
2053 { INDEX_op_rotl_i32, { "r", "r", "ri" } },
2054 { INDEX_op_rotr_i32, { "r", "r", "ri" } },
2055
2056 { INDEX_op_brcond_i32, { "r", "ri" } },
2057 { INDEX_op_brcond_i64, { "r", "ri" } },
2058
2059 { INDEX_op_neg_i32, { "r", "r" } },
2060 { INDEX_op_not_i32, { "r", "r" } },
2061
2062 { INDEX_op_add_i64, { "r", "r", "rT" } },
2063 { INDEX_op_sub_i64, { "r", "rI", "rT" } },
2064 { INDEX_op_and_i64, { "r", "r", "ri" } },
2065 { INDEX_op_or_i64, { "r", "r", "rU" } },
2066 { INDEX_op_xor_i64, { "r", "r", "rU" } },
2067 { INDEX_op_andc_i64, { "r", "r", "ri" } },
2068 { INDEX_op_orc_i64, { "r", "r", "r" } },
2069 { INDEX_op_eqv_i64, { "r", "r", "r" } },
2070 { INDEX_op_nand_i64, { "r", "r", "r" } },
2071 { INDEX_op_nor_i64, { "r", "r", "r" } },
2072
2073 { INDEX_op_shl_i64, { "r", "r", "ri" } },
2074 { INDEX_op_shr_i64, { "r", "r", "ri" } },
2075 { INDEX_op_sar_i64, { "r", "r", "ri" } },
2076 { INDEX_op_rotl_i64, { "r", "r", "ri" } },
2077 { INDEX_op_rotr_i64, { "r", "r", "ri" } },
2078
2079 { INDEX_op_mul_i64, { "r", "r", "rI" } },
2080 { INDEX_op_div_i64, { "r", "r", "r" } },
2081 { INDEX_op_divu_i64, { "r", "r", "r" } },
2082
2083 { INDEX_op_neg_i64, { "r", "r" } },
2084 { INDEX_op_not_i64, { "r", "r" } },
2085
2086 { INDEX_op_qemu_ld8u, { "r", "L" } },
2087 { INDEX_op_qemu_ld8s, { "r", "L" } },
2088 { INDEX_op_qemu_ld16u, { "r", "L" } },
2089 { INDEX_op_qemu_ld16s, { "r", "L" } },
2090 { INDEX_op_qemu_ld32, { "r", "L" } },
2091 { INDEX_op_qemu_ld32u, { "r", "L" } },
2092 { INDEX_op_qemu_ld32s, { "r", "L" } },
2093 { INDEX_op_qemu_ld64, { "r", "L" } },
2094
2095 { INDEX_op_qemu_st8, { "S", "S" } },
2096 { INDEX_op_qemu_st16, { "S", "S" } },
2097 { INDEX_op_qemu_st32, { "S", "S" } },
2098 { INDEX_op_qemu_st64, { "S", "S" } },
2099
2100 { INDEX_op_ext8s_i32, { "r", "r" } },
2101 { INDEX_op_ext16s_i32, { "r", "r" } },
2102 { INDEX_op_ext8s_i64, { "r", "r" } },
2103 { INDEX_op_ext16s_i64, { "r", "r" } },
2104 { INDEX_op_ext32s_i64, { "r", "r" } },
2105
2106 { INDEX_op_setcond_i32, { "r", "r", "ri" } },
2107 { INDEX_op_setcond_i64, { "r", "r", "ri" } },
2108 { INDEX_op_movcond_i32, { "r", "r", "ri", "rZ", "rZ" } },
2109 { INDEX_op_movcond_i64, { "r", "r", "ri", "rZ", "rZ" } },
2110
2111 { INDEX_op_bswap16_i32, { "r", "r" } },
2112 { INDEX_op_bswap16_i64, { "r", "r" } },
2113 { INDEX_op_bswap32_i32, { "r", "r" } },
2114 { INDEX_op_bswap32_i64, { "r", "r" } },
2115 { INDEX_op_bswap64_i64, { "r", "r" } },
2116
2117 { INDEX_op_deposit_i32, { "r", "0", "rZ" } },
2118 { INDEX_op_deposit_i64, { "r", "0", "rZ" } },
2119
2120 { INDEX_op_add2_i64, { "r", "r", "r", "r", "rI", "rZM" } },
2121 { INDEX_op_sub2_i64, { "r", "r", "rI", "r", "rZM", "r" } },
2122 { INDEX_op_mulsh_i64, { "r", "r", "r" } },
2123 { INDEX_op_muluh_i64, { "r", "r", "r" } },
2124
2125 { -1 },
2126 };
2127
2128 static void tcg_target_init(TCGContext *s)
2129 {
2130 #ifdef CONFIG_GETAUXVAL
2131 unsigned long hwcap = getauxval(AT_HWCAP);
2132 if (hwcap & PPC_FEATURE_ARCH_2_06) {
2133 have_isa_2_06 = true;
2134 }
2135 #endif
2136
2137 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
2138 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
2139 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
2140 (1 << TCG_REG_R0) |
2141 (1 << TCG_REG_R2) |
2142 (1 << TCG_REG_R3) |
2143 (1 << TCG_REG_R4) |
2144 (1 << TCG_REG_R5) |
2145 (1 << TCG_REG_R6) |
2146 (1 << TCG_REG_R7) |
2147 (1 << TCG_REG_R8) |
2148 (1 << TCG_REG_R9) |
2149 (1 << TCG_REG_R10) |
2150 (1 << TCG_REG_R11) |
2151 (1 << TCG_REG_R12));
2152
2153 tcg_regset_clear(s->reserved_regs);
2154 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */
2155 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */
2156 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* mem temp */
2157 #ifdef __APPLE__
2158 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R11); /* ??? */
2159 #endif
2160 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */
2161
2162 tcg_add_target_add_op_defs(ppc_op_defs);
2163 }
2164
2165 typedef struct {
2166 DebugFrameCIE cie;
2167 DebugFrameFDEHeader fde;
2168 uint8_t fde_def_cfa[4];
2169 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2 + 3];
2170 } DebugFrame;
2171
2172 /* We're expecting a 2 byte uleb128 encoded value. */
2173 QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14));
2174
2175 #define ELF_HOST_MACHINE EM_PPC64
2176
2177 static DebugFrame debug_frame = {
2178 .cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
2179 .cie.id = -1,
2180 .cie.version = 1,
2181 .cie.code_align = 1,
2182 .cie.data_align = 0x78, /* sleb128 -8 */
2183 .cie.return_column = 65,
2184
2185 /* Total FDE size does not include the "len" member. */
2186 .fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, fde.cie_offset),
2187
2188 .fde_def_cfa = {
2189 12, 1, /* DW_CFA_def_cfa r1, ... */
2190 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2191 (FRAME_SIZE >> 7)
2192 },
2193 .fde_reg_ofs = {
2194 0x11, 65, 0x7e, /* DW_CFA_offset_extended_sf, lr, 16 */
2195 }
2196 };
2197
2198 void tcg_register_jit(void *buf, size_t buf_size)
2199 {
2200 uint8_t *p = &debug_frame.fde_reg_ofs[3];
2201 int i;
2202
2203 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i, p += 2) {
2204 p[0] = 0x80 + tcg_target_callee_save_regs[i];
2205 p[1] = (FRAME_SIZE - (REG_SAVE_BOT + i * 8)) / 8;
2206 }
2207
2208 debug_frame.fde.func_start = (tcg_target_long) buf;
2209 debug_frame.fde.func_len = buf_size;
2210
2211 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
2212 }
Qemu copy for testing