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Merge remote branch 'qemu-kvm/uq/master' into staging-tmp
[qemu.git] / tcg / ppc64 / tcg-target.c
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #define TCG_CT_CONST_U32 0x100
26
27 static uint8_t *tb_ret_addr;
28
29 #define FAST_PATH
30
31 #if TARGET_PHYS_ADDR_BITS == 32
32 #define LD_ADDEND LWZ
33 #else
34 #define LD_ADDEND LD
35 #endif
36
37 #if TARGET_LONG_BITS == 32
38 #define LD_ADDR LWZU
39 #define CMP_L 0
40 #else
41 #define LD_ADDR LDU
42 #define CMP_L (1<<21)
43 #endif
44
45 #ifndef GUEST_BASE
46 #define GUEST_BASE 0
47 #endif
48
49 #ifdef CONFIG_USE_GUEST_BASE
50 #define TCG_GUEST_BASE_REG 30
51 #else
52 #define TCG_GUEST_BASE_REG 0
53 #endif
54
55 #ifndef NDEBUG
56 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
57 "r0",
58 "r1",
59 "rp",
60 "r3",
61 "r4",
62 "r5",
63 "r6",
64 "r7",
65 "r8",
66 "r9",
67 "r10",
68 "r11",
69 "r12",
70 "r13",
71 "r14",
72 "r15",
73 "r16",
74 "r17",
75 "r18",
76 "r19",
77 "r20",
78 "r21",
79 "r22",
80 "r23",
81 "r24",
82 "r25",
83 "r26",
84 "r27",
85 "r28",
86 "r29",
87 "r30",
88 "r31"
89 };
90 #endif
91
92 static const int tcg_target_reg_alloc_order[] = {
93 TCG_REG_R14,
94 TCG_REG_R15,
95 TCG_REG_R16,
96 TCG_REG_R17,
97 TCG_REG_R18,
98 TCG_REG_R19,
99 TCG_REG_R20,
100 TCG_REG_R21,
101 TCG_REG_R22,
102 TCG_REG_R23,
103 TCG_REG_R28,
104 TCG_REG_R29,
105 TCG_REG_R30,
106 TCG_REG_R31,
107 #ifdef __APPLE__
108 TCG_REG_R2,
109 #endif
110 TCG_REG_R3,
111 TCG_REG_R4,
112 TCG_REG_R5,
113 TCG_REG_R6,
114 TCG_REG_R7,
115 TCG_REG_R8,
116 TCG_REG_R9,
117 TCG_REG_R10,
118 #ifndef __APPLE__
119 TCG_REG_R11,
120 #endif
121 TCG_REG_R12,
122 TCG_REG_R24,
123 TCG_REG_R25,
124 TCG_REG_R26,
125 TCG_REG_R27
126 };
127
128 static const int tcg_target_call_iarg_regs[] = {
129 TCG_REG_R3,
130 TCG_REG_R4,
131 TCG_REG_R5,
132 TCG_REG_R6,
133 TCG_REG_R7,
134 TCG_REG_R8,
135 TCG_REG_R9,
136 TCG_REG_R10
137 };
138
139 static const int tcg_target_call_oarg_regs[2] = {
140 TCG_REG_R3
141 };
142
143 static const int tcg_target_callee_save_regs[] = {
144 #ifdef __APPLE__
145 TCG_REG_R11,
146 #endif
147 TCG_REG_R14,
148 TCG_REG_R15,
149 TCG_REG_R16,
150 TCG_REG_R17,
151 TCG_REG_R18,
152 TCG_REG_R19,
153 TCG_REG_R20,
154 TCG_REG_R21,
155 TCG_REG_R22,
156 TCG_REG_R23,
157 TCG_REG_R24,
158 TCG_REG_R25,
159 TCG_REG_R26,
160 /* TCG_REG_R27, */ /* currently used for the global env, so no
161 need to save */
162 TCG_REG_R28,
163 TCG_REG_R29,
164 TCG_REG_R30,
165 TCG_REG_R31
166 };
167
168 static uint32_t reloc_pc24_val (void *pc, tcg_target_long target)
169 {
170 tcg_target_long disp;
171
172 disp = target - (tcg_target_long) pc;
173 if ((disp << 38) >> 38 != disp)
174 tcg_abort ();
175
176 return disp & 0x3fffffc;
177 }
178
179 static void reloc_pc24 (void *pc, tcg_target_long target)
180 {
181 *(uint32_t *) pc = (*(uint32_t *) pc & ~0x3fffffc)
182 | reloc_pc24_val (pc, target);
183 }
184
185 static uint16_t reloc_pc14_val (void *pc, tcg_target_long target)
186 {
187 tcg_target_long disp;
188
189 disp = target - (tcg_target_long) pc;
190 if (disp != (int16_t) disp)
191 tcg_abort ();
192
193 return disp & 0xfffc;
194 }
195
196 static void reloc_pc14 (void *pc, tcg_target_long target)
197 {
198 *(uint32_t *) pc = (*(uint32_t *) pc & ~0xfffc)
199 | reloc_pc14_val (pc, target);
200 }
201
202 static void patch_reloc (uint8_t *code_ptr, int type,
203 tcg_target_long value, tcg_target_long addend)
204 {
205 value += addend;
206 switch (type) {
207 case R_PPC_REL14:
208 reloc_pc14 (code_ptr, value);
209 break;
210 case R_PPC_REL24:
211 reloc_pc24 (code_ptr, value);
212 break;
213 default:
214 tcg_abort ();
215 }
216 }
217
218 /* maximum number of register used for input function arguments */
219 static int tcg_target_get_call_iarg_regs_count (int flags)
220 {
221 return ARRAY_SIZE (tcg_target_call_iarg_regs);
222 }
223
224 /* parse target specific constraints */
225 static int target_parse_constraint (TCGArgConstraint *ct, const char **pct_str)
226 {
227 const char *ct_str;
228
229 ct_str = *pct_str;
230 switch (ct_str[0]) {
231 case 'A': case 'B': case 'C': case 'D':
232 ct->ct |= TCG_CT_REG;
233 tcg_regset_set_reg (ct->u.regs, 3 + ct_str[0] - 'A');
234 break;
235 case 'r':
236 ct->ct |= TCG_CT_REG;
237 tcg_regset_set32 (ct->u.regs, 0, 0xffffffff);
238 break;
239 case 'L': /* qemu_ld constraint */
240 ct->ct |= TCG_CT_REG;
241 tcg_regset_set32 (ct->u.regs, 0, 0xffffffff);
242 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3);
243 #ifdef CONFIG_SOFTMMU
244 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4);
245 #endif
246 break;
247 case 'S': /* qemu_st constraint */
248 ct->ct |= TCG_CT_REG;
249 tcg_regset_set32 (ct->u.regs, 0, 0xffffffff);
250 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3);
251 #ifdef CONFIG_SOFTMMU
252 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4);
253 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R5);
254 #endif
255 break;
256 case 'Z':
257 ct->ct |= TCG_CT_CONST_U32;
258 break;
259 default:
260 return -1;
261 }
262 ct_str++;
263 *pct_str = ct_str;
264 return 0;
265 }
266
267 /* test if a constant matches the constraint */
268 static int tcg_target_const_match (tcg_target_long val,
269 const TCGArgConstraint *arg_ct)
270 {
271 int ct;
272
273 ct = arg_ct->ct;
274 if (ct & TCG_CT_CONST)
275 return 1;
276 else if ((ct & TCG_CT_CONST_U32) && (val == (uint32_t) val))
277 return 1;
278 return 0;
279 }
280
281 #define OPCD(opc) ((opc)<<26)
282 #define XO19(opc) (OPCD(19)|((opc)<<1))
283 #define XO30(opc) (OPCD(30)|((opc)<<2))
284 #define XO31(opc) (OPCD(31)|((opc)<<1))
285 #define XO58(opc) (OPCD(58)|(opc))
286 #define XO62(opc) (OPCD(62)|(opc))
287
288 #define B OPCD( 18)
289 #define BC OPCD( 16)
290 #define LBZ OPCD( 34)
291 #define LHZ OPCD( 40)
292 #define LHA OPCD( 42)
293 #define LWZ OPCD( 32)
294 #define STB OPCD( 38)
295 #define STH OPCD( 44)
296 #define STW OPCD( 36)
297
298 #define STD XO62( 0)
299 #define STDU XO62( 1)
300 #define STDX XO31(149)
301
302 #define LD XO58( 0)
303 #define LDX XO31( 21)
304 #define LDU XO58( 1)
305 #define LWA XO58( 2)
306 #define LWAX XO31(341)
307
308 #define ADDIC OPCD( 12)
309 #define ADDI OPCD( 14)
310 #define ADDIS OPCD( 15)
311 #define ORI OPCD( 24)
312 #define ORIS OPCD( 25)
313 #define XORI OPCD( 26)
314 #define XORIS OPCD( 27)
315 #define ANDI OPCD( 28)
316 #define ANDIS OPCD( 29)
317 #define MULLI OPCD( 7)
318 #define CMPLI OPCD( 10)
319 #define CMPI OPCD( 11)
320
321 #define LWZU OPCD( 33)
322 #define STWU OPCD( 37)
323
324 #define RLWINM OPCD( 21)
325
326 #define RLDICL XO30( 0)
327 #define RLDICR XO30( 1)
328 #define RLDIMI XO30( 3)
329
330 #define BCLR XO19( 16)
331 #define BCCTR XO19(528)
332 #define CRAND XO19(257)
333 #define CRANDC XO19(129)
334 #define CRNAND XO19(225)
335 #define CROR XO19(449)
336 #define CRNOR XO19( 33)
337
338 #define EXTSB XO31(954)
339 #define EXTSH XO31(922)
340 #define EXTSW XO31(986)
341 #define ADD XO31(266)
342 #define ADDE XO31(138)
343 #define ADDC XO31( 10)
344 #define AND XO31( 28)
345 #define SUBF XO31( 40)
346 #define SUBFC XO31( 8)
347 #define SUBFE XO31(136)
348 #define OR XO31(444)
349 #define XOR XO31(316)
350 #define MULLW XO31(235)
351 #define MULHWU XO31( 11)
352 #define DIVW XO31(491)
353 #define DIVWU XO31(459)
354 #define CMP XO31( 0)
355 #define CMPL XO31( 32)
356 #define LHBRX XO31(790)
357 #define LWBRX XO31(534)
358 #define STHBRX XO31(918)
359 #define STWBRX XO31(662)
360 #define MFSPR XO31(339)
361 #define MTSPR XO31(467)
362 #define SRAWI XO31(824)
363 #define NEG XO31(104)
364 #define MFCR XO31( 19)
365 #define CNTLZW XO31( 26)
366 #define CNTLZD XO31( 58)
367
368 #define MULLD XO31(233)
369 #define MULHD XO31( 73)
370 #define MULHDU XO31( 9)
371 #define DIVD XO31(489)
372 #define DIVDU XO31(457)
373
374 #define LBZX XO31( 87)
375 #define LHZX XO31(279)
376 #define LHAX XO31(343)
377 #define LWZX XO31( 23)
378 #define STBX XO31(215)
379 #define STHX XO31(407)
380 #define STWX XO31(151)
381
382 #define SPR(a,b) ((((a)<<5)|(b))<<11)
383 #define LR SPR(8, 0)
384 #define CTR SPR(9, 0)
385
386 #define SLW XO31( 24)
387 #define SRW XO31(536)
388 #define SRAW XO31(792)
389
390 #define SLD XO31( 27)
391 #define SRD XO31(539)
392 #define SRAD XO31(794)
393 #define SRADI XO31(413<<1)
394
395 #define TW XO31( 4)
396 #define TRAP (TW | TO (31))
397
398 #define RT(r) ((r)<<21)
399 #define RS(r) ((r)<<21)
400 #define RA(r) ((r)<<16)
401 #define RB(r) ((r)<<11)
402 #define TO(t) ((t)<<21)
403 #define SH(s) ((s)<<11)
404 #define MB(b) ((b)<<6)
405 #define ME(e) ((e)<<1)
406 #define BO(o) ((o)<<21)
407 #define MB64(b) ((b)<<5)
408
409 #define LK 1
410
411 #define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
412 #define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
413
414 #define BF(n) ((n)<<23)
415 #define BI(n, c) (((c)+((n)*4))<<16)
416 #define BT(n, c) (((c)+((n)*4))<<21)
417 #define BA(n, c) (((c)+((n)*4))<<16)
418 #define BB(n, c) (((c)+((n)*4))<<11)
419
420 #define BO_COND_TRUE BO (12)
421 #define BO_COND_FALSE BO ( 4)
422 #define BO_ALWAYS BO (20)
423
424 enum {
425 CR_LT,
426 CR_GT,
427 CR_EQ,
428 CR_SO
429 };
430
431 static const uint32_t tcg_to_bc[10] = {
432 [TCG_COND_EQ] = BC | BI (7, CR_EQ) | BO_COND_TRUE,
433 [TCG_COND_NE] = BC | BI (7, CR_EQ) | BO_COND_FALSE,
434 [TCG_COND_LT] = BC | BI (7, CR_LT) | BO_COND_TRUE,
435 [TCG_COND_GE] = BC | BI (7, CR_LT) | BO_COND_FALSE,
436 [TCG_COND_LE] = BC | BI (7, CR_GT) | BO_COND_FALSE,
437 [TCG_COND_GT] = BC | BI (7, CR_GT) | BO_COND_TRUE,
438 [TCG_COND_LTU] = BC | BI (7, CR_LT) | BO_COND_TRUE,
439 [TCG_COND_GEU] = BC | BI (7, CR_LT) | BO_COND_FALSE,
440 [TCG_COND_LEU] = BC | BI (7, CR_GT) | BO_COND_FALSE,
441 [TCG_COND_GTU] = BC | BI (7, CR_GT) | BO_COND_TRUE,
442 };
443
444 static void tcg_out_mov (TCGContext *s, int ret, int arg)
445 {
446 tcg_out32 (s, OR | SAB (arg, ret, arg));
447 }
448
449 static void tcg_out_rld (TCGContext *s, int op, int ra, int rs, int sh, int mb)
450 {
451 sh = SH (sh & 0x1f) | (((sh >> 5) & 1) << 1);
452 mb = MB64 ((mb >> 5) | ((mb << 1) & 0x3f));
453 tcg_out32 (s, op | RA (ra) | RS (rs) | sh | mb);
454 }
455
456 static void tcg_out_movi32 (TCGContext *s, int ret, int32_t arg)
457 {
458 if (arg == (int16_t) arg)
459 tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff));
460 else {
461 tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff));
462 if (arg & 0xffff)
463 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
464 }
465 }
466
467 static void tcg_out_movi (TCGContext *s, TCGType type,
468 int ret, tcg_target_long arg)
469 {
470 int32_t arg32 = arg;
471 arg = type == TCG_TYPE_I32 ? arg & 0xffffffff : arg;
472
473 if (arg == arg32) {
474 tcg_out_movi32 (s, ret, arg32);
475 }
476 else {
477 if ((uint64_t) arg >> 32) {
478 uint16_t h16 = arg >> 16;
479 uint16_t l16 = arg;
480
481 tcg_out_movi32 (s, ret, arg >> 32);
482 tcg_out_rld (s, RLDICR, ret, ret, 32, 31);
483 if (h16) tcg_out32 (s, ORIS | RS (ret) | RA (ret) | h16);
484 if (l16) tcg_out32 (s, ORI | RS (ret) | RA (ret) | l16);
485 }
486 else {
487 tcg_out_movi32 (s, ret, arg32);
488 if (arg32 < 0)
489 tcg_out_rld (s, RLDICL, ret, ret, 0, 32);
490 }
491 }
492 }
493
494 static void tcg_out_b (TCGContext *s, int mask, tcg_target_long target)
495 {
496 tcg_target_long disp;
497
498 disp = target - (tcg_target_long) s->code_ptr;
499 if ((disp << 38) >> 38 == disp)
500 tcg_out32 (s, B | (disp & 0x3fffffc) | mask);
501 else {
502 tcg_out_movi (s, TCG_TYPE_I64, 0, (tcg_target_long) target);
503 tcg_out32 (s, MTSPR | RS (0) | CTR);
504 tcg_out32 (s, BCCTR | BO_ALWAYS | mask);
505 }
506 }
507
508 static void tcg_out_call (TCGContext *s, tcg_target_long arg, int const_arg)
509 {
510 #ifdef __APPLE__
511 if (const_arg) {
512 tcg_out_b (s, LK, arg);
513 }
514 else {
515 tcg_out32 (s, MTSPR | RS (arg) | LR);
516 tcg_out32 (s, BCLR | BO_ALWAYS | LK);
517 }
518 #else
519 int reg;
520
521 if (const_arg) {
522 reg = 2;
523 tcg_out_movi (s, TCG_TYPE_I64, reg, arg);
524 }
525 else reg = arg;
526
527 tcg_out32 (s, LD | RT (0) | RA (reg));
528 tcg_out32 (s, MTSPR | RA (0) | CTR);
529 tcg_out32 (s, LD | RT (11) | RA (reg) | 16);
530 tcg_out32 (s, LD | RT (2) | RA (reg) | 8);
531 tcg_out32 (s, BCCTR | BO_ALWAYS | LK);
532 #endif
533 }
534
535 static void tcg_out_ldst (TCGContext *s, int ret, int addr,
536 int offset, int op1, int op2)
537 {
538 if (offset == (int16_t) offset)
539 tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff));
540 else {
541 tcg_out_movi (s, TCG_TYPE_I64, 0, offset);
542 tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
543 }
544 }
545
546 static void tcg_out_ldsta (TCGContext *s, int ret, int addr,
547 int offset, int op1, int op2)
548 {
549 if (offset == (int16_t) (offset & ~3))
550 tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff));
551 else {
552 tcg_out_movi (s, TCG_TYPE_I64, 0, offset);
553 tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
554 }
555 }
556
557 #if defined (CONFIG_SOFTMMU)
558
559 #include "../../softmmu_defs.h"
560
561 static void *qemu_ld_helpers[4] = {
562 __ldb_mmu,
563 __ldw_mmu,
564 __ldl_mmu,
565 __ldq_mmu,
566 };
567
568 static void *qemu_st_helpers[4] = {
569 __stb_mmu,
570 __stw_mmu,
571 __stl_mmu,
572 __stq_mmu,
573 };
574
575 static void tcg_out_tlb_read (TCGContext *s, int r0, int r1, int r2,
576 int addr_reg, int s_bits, int offset)
577 {
578 #if TARGET_LONG_BITS == 32
579 tcg_out_rld (s, RLDICL, addr_reg, addr_reg, 0, 32);
580
581 tcg_out32 (s, (RLWINM
582 | RA (r0)
583 | RS (addr_reg)
584 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
585 | MB (32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS))
586 | ME (31 - CPU_TLB_ENTRY_BITS)
587 )
588 );
589 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
590 tcg_out32 (s, (LWZU | RT (r1) | RA (r0) | offset));
591 tcg_out32 (s, (RLWINM
592 | RA (r2)
593 | RS (addr_reg)
594 | SH (0)
595 | MB ((32 - s_bits) & 31)
596 | ME (31 - TARGET_PAGE_BITS)
597 )
598 );
599 #else
600 tcg_out_rld (s, RLDICL, r0, addr_reg,
601 64 - TARGET_PAGE_BITS,
602 64 - CPU_TLB_BITS);
603 tcg_out_rld (s, RLDICR, r0, r0,
604 CPU_TLB_ENTRY_BITS,
605 63 - CPU_TLB_ENTRY_BITS);
606
607 tcg_out32 (s, ADD | TAB (r0, r0, TCG_AREG0));
608 tcg_out32 (s, LD_ADDR | RT (r1) | RA (r0) | offset);
609
610 if (!s_bits) {
611 tcg_out_rld (s, RLDICR, r2, addr_reg, 0, 63 - TARGET_PAGE_BITS);
612 }
613 else {
614 tcg_out_rld (s, RLDICL, r2, addr_reg,
615 64 - TARGET_PAGE_BITS,
616 TARGET_PAGE_BITS - s_bits);
617 tcg_out_rld (s, RLDICL, r2, r2, TARGET_PAGE_BITS, 0);
618 }
619 #endif
620 }
621 #endif
622
623 static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
624 {
625 int addr_reg, data_reg, r0, r1, rbase, mem_index, s_bits, bswap;
626 #ifdef CONFIG_SOFTMMU
627 int r2;
628 void *label1_ptr, *label2_ptr;
629 #endif
630
631 data_reg = *args++;
632 addr_reg = *args++;
633 mem_index = *args;
634 s_bits = opc & 3;
635
636 #ifdef CONFIG_SOFTMMU
637 r0 = 3;
638 r1 = 4;
639 r2 = 0;
640 rbase = 0;
641
642 tcg_out_tlb_read (s, r0, r1, r2, addr_reg, s_bits,
643 offsetof (CPUState, tlb_table[mem_index][0].addr_read));
644
645 tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1) | CMP_L);
646
647 label1_ptr = s->code_ptr;
648 #ifdef FAST_PATH
649 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
650 #endif
651
652 /* slow path */
653 tcg_out_mov (s, 3, addr_reg);
654 tcg_out_movi (s, TCG_TYPE_I64, 4, mem_index);
655
656 tcg_out_call (s, (tcg_target_long) qemu_ld_helpers[s_bits], 1);
657
658 switch (opc) {
659 case 0|4:
660 tcg_out32 (s, EXTSB | RA (data_reg) | RS (3));
661 break;
662 case 1|4:
663 tcg_out32 (s, EXTSH | RA (data_reg) | RS (3));
664 break;
665 case 2|4:
666 tcg_out32 (s, EXTSW | RA (data_reg) | RS (3));
667 break;
668 case 0:
669 case 1:
670 case 2:
671 case 3:
672 if (data_reg != 3)
673 tcg_out_mov (s, data_reg, 3);
674 break;
675 }
676 label2_ptr = s->code_ptr;
677 tcg_out32 (s, B);
678
679 /* label1: fast path */
680 #ifdef FAST_PATH
681 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
682 #endif
683
684 /* r0 now contains &env->tlb_table[mem_index][index].addr_read */
685 tcg_out32 (s, (LD_ADDEND
686 | RT (r0)
687 | RA (r0)
688 | (offsetof (CPUTLBEntry, addend)
689 - offsetof (CPUTLBEntry, addr_read))
690 ));
691 /* r0 = env->tlb_table[mem_index][index].addend */
692 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
693 /* r0 = env->tlb_table[mem_index][index].addend + addr */
694
695 #else /* !CONFIG_SOFTMMU */
696 #if TARGET_LONG_BITS == 32
697 tcg_out_rld (s, RLDICL, addr_reg, addr_reg, 0, 32);
698 #endif
699 r0 = addr_reg;
700 r1 = 3;
701 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
702 #endif
703
704 #ifdef TARGET_WORDS_BIGENDIAN
705 bswap = 0;
706 #else
707 bswap = 1;
708 #endif
709 switch (opc) {
710 default:
711 case 0:
712 tcg_out32 (s, LBZX | TAB (data_reg, rbase, r0));
713 break;
714 case 0|4:
715 tcg_out32 (s, LBZX | TAB (data_reg, rbase, r0));
716 tcg_out32 (s, EXTSB | RA (data_reg) | RS (data_reg));
717 break;
718 case 1:
719 if (bswap)
720 tcg_out32 (s, LHBRX | TAB (data_reg, rbase, r0));
721 else
722 tcg_out32 (s, LHZX | TAB (data_reg, rbase, r0));
723 break;
724 case 1|4:
725 if (bswap) {
726 tcg_out32 (s, LHBRX | TAB (data_reg, rbase, r0));
727 tcg_out32 (s, EXTSH | RA (data_reg) | RS (data_reg));
728 }
729 else tcg_out32 (s, LHAX | TAB (data_reg, rbase, r0));
730 break;
731 case 2:
732 if (bswap)
733 tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
734 else
735 tcg_out32 (s, LWZX | TAB (data_reg, rbase, r0));
736 break;
737 case 2|4:
738 if (bswap) {
739 tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
740 tcg_out32 (s, EXTSW | RA (data_reg) | RS (data_reg));
741 }
742 else tcg_out32 (s, LWAX | TAB (data_reg, rbase, r0));
743 break;
744 case 3:
745 #ifdef CONFIG_USE_GUEST_BASE
746 if (bswap) {
747 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
748 tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
749 tcg_out32 (s, LWBRX | TAB ( r1, rbase, r1));
750 tcg_out_rld (s, RLDIMI, data_reg, r1, 32, 0);
751 }
752 else tcg_out32 (s, LDX | TAB (data_reg, rbase, r0));
753 #else
754 if (bswap) {
755 tcg_out_movi32 (s, 0, 4);
756 tcg_out32 (s, LWBRX | RT (data_reg) | RB (r0));
757 tcg_out32 (s, LWBRX | RT ( r1) | RA (r0));
758 tcg_out_rld (s, RLDIMI, data_reg, r1, 32, 0);
759 }
760 else tcg_out32 (s, LD | RT (data_reg) | RA (r0));
761 #endif
762 break;
763 }
764
765 #ifdef CONFIG_SOFTMMU
766 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
767 #endif
768 }
769
770 static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
771 {
772 int addr_reg, r0, r1, rbase, data_reg, mem_index, bswap;
773 #ifdef CONFIG_SOFTMMU
774 int r2;
775 void *label1_ptr, *label2_ptr;
776 #endif
777
778 data_reg = *args++;
779 addr_reg = *args++;
780 mem_index = *args;
781
782 #ifdef CONFIG_SOFTMMU
783 r0 = 3;
784 r1 = 4;
785 r2 = 0;
786 rbase = 0;
787
788 tcg_out_tlb_read (s, r0, r1, r2, addr_reg, opc,
789 offsetof (CPUState, tlb_table[mem_index][0].addr_write));
790
791 tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1) | CMP_L);
792
793 label1_ptr = s->code_ptr;
794 #ifdef FAST_PATH
795 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
796 #endif
797
798 /* slow path */
799 tcg_out_mov (s, 3, addr_reg);
800 tcg_out_rld (s, RLDICL, 4, data_reg, 0, 64 - (1 << (3 + opc)));
801 tcg_out_movi (s, TCG_TYPE_I64, 5, mem_index);
802
803 tcg_out_call (s, (tcg_target_long) qemu_st_helpers[opc], 1);
804
805 label2_ptr = s->code_ptr;
806 tcg_out32 (s, B);
807
808 /* label1: fast path */
809 #ifdef FAST_PATH
810 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
811 #endif
812
813 tcg_out32 (s, (LD_ADDEND
814 | RT (r0)
815 | RA (r0)
816 | (offsetof (CPUTLBEntry, addend)
817 - offsetof (CPUTLBEntry, addr_write))
818 ));
819 /* r0 = env->tlb_table[mem_index][index].addend */
820 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
821 /* r0 = env->tlb_table[mem_index][index].addend + addr */
822
823 #else /* !CONFIG_SOFTMMU */
824 #if TARGET_LONG_BITS == 32
825 tcg_out_rld (s, RLDICL, addr_reg, addr_reg, 0, 32);
826 #endif
827 r1 = 3;
828 r0 = addr_reg;
829 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
830 #endif
831
832 #ifdef TARGET_WORDS_BIGENDIAN
833 bswap = 0;
834 #else
835 bswap = 1;
836 #endif
837 switch (opc) {
838 case 0:
839 tcg_out32 (s, STBX | SAB (data_reg, rbase, r0));
840 break;
841 case 1:
842 if (bswap)
843 tcg_out32 (s, STHBRX | SAB (data_reg, rbase, r0));
844 else
845 tcg_out32 (s, STHX | SAB (data_reg, rbase, r0));
846 break;
847 case 2:
848 if (bswap)
849 tcg_out32 (s, STWBRX | SAB (data_reg, rbase, r0));
850 else
851 tcg_out32 (s, STWX | SAB (data_reg, rbase, r0));
852 break;
853 case 3:
854 if (bswap) {
855 tcg_out32 (s, STWBRX | SAB (data_reg, rbase, r0));
856 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
857 tcg_out_rld (s, RLDICL, 0, data_reg, 32, 0);
858 tcg_out32 (s, STWBRX | SAB (0, rbase, r1));
859 }
860 else tcg_out32 (s, STDX | SAB (data_reg, rbase, r0));
861 break;
862 }
863
864 #ifdef CONFIG_SOFTMMU
865 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
866 #endif
867 }
868
869 void tcg_target_qemu_prologue (TCGContext *s)
870 {
871 int i, frame_size;
872 #ifndef __APPLE__
873 uint64_t addr;
874 #endif
875
876 frame_size = 0
877 + 8 /* back chain */
878 + 8 /* CR */
879 + 8 /* LR */
880 + 8 /* compiler doubleword */
881 + 8 /* link editor doubleword */
882 + 8 /* TOC save area */
883 + TCG_STATIC_CALL_ARGS_SIZE
884 + ARRAY_SIZE (tcg_target_callee_save_regs) * 8
885 ;
886 frame_size = (frame_size + 15) & ~15;
887
888 #ifndef __APPLE__
889 /* First emit adhoc function descriptor */
890 addr = (uint64_t) s->code_ptr + 24;
891 tcg_out32 (s, addr >> 32); tcg_out32 (s, addr); /* entry point */
892 s->code_ptr += 16; /* skip TOC and environment pointer */
893 #endif
894
895 /* Prologue */
896 tcg_out32 (s, MFSPR | RT (0) | LR);
897 tcg_out32 (s, STDU | RS (1) | RA (1) | (-frame_size & 0xffff));
898 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
899 tcg_out32 (s, (STD
900 | RS (tcg_target_callee_save_regs[i])
901 | RA (1)
902 | (i * 8 + 48 + TCG_STATIC_CALL_ARGS_SIZE)
903 )
904 );
905 tcg_out32 (s, STD | RS (0) | RA (1) | (frame_size + 16));
906
907 #ifdef CONFIG_USE_GUEST_BASE
908 tcg_out_movi (s, TCG_TYPE_I64, TCG_GUEST_BASE_REG, GUEST_BASE);
909 #endif
910
911 tcg_out32 (s, MTSPR | RS (3) | CTR);
912 tcg_out32 (s, BCCTR | BO_ALWAYS);
913
914 /* Epilogue */
915 tb_ret_addr = s->code_ptr;
916
917 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
918 tcg_out32 (s, (LD
919 | RT (tcg_target_callee_save_regs[i])
920 | RA (1)
921 | (i * 8 + 48 + TCG_STATIC_CALL_ARGS_SIZE)
922 )
923 );
924 tcg_out32 (s, LD | RT (0) | RA (1) | (frame_size + 16));
925 tcg_out32 (s, MTSPR | RS (0) | LR);
926 tcg_out32 (s, ADDI | RT (1) | RA (1) | frame_size);
927 tcg_out32 (s, BCLR | BO_ALWAYS);
928 }
929
930 static void tcg_out_ld (TCGContext *s, TCGType type, int ret, int arg1,
931 tcg_target_long arg2)
932 {
933 if (type == TCG_TYPE_I32)
934 tcg_out_ldst (s, ret, arg1, arg2, LWZ, LWZX);
935 else
936 tcg_out_ldsta (s, ret, arg1, arg2, LD, LDX);
937 }
938
939 static void tcg_out_st (TCGContext *s, TCGType type, int arg, int arg1,
940 tcg_target_long arg2)
941 {
942 if (type == TCG_TYPE_I32)
943 tcg_out_ldst (s, arg, arg1, arg2, STW, STWX);
944 else
945 tcg_out_ldsta (s, arg, arg1, arg2, STD, STDX);
946 }
947
948 static void ppc_addi32 (TCGContext *s, int rt, int ra, tcg_target_long si)
949 {
950 if (!si && rt == ra)
951 return;
952
953 if (si == (int16_t) si)
954 tcg_out32 (s, ADDI | RT (rt) | RA (ra) | (si & 0xffff));
955 else {
956 uint16_t h = ((si >> 16) & 0xffff) + ((uint16_t) si >> 15);
957 tcg_out32 (s, ADDIS | RT (rt) | RA (ra) | h);
958 tcg_out32 (s, ADDI | RT (rt) | RA (rt) | (si & 0xffff));
959 }
960 }
961
962 static void ppc_addi64 (TCGContext *s, int rt, int ra, tcg_target_long si)
963 {
964 /* XXX: suboptimal */
965 if (si == (int16_t) si
966 || ((((uint64_t) si >> 31) == 0) && (si & 0x8000) == 0))
967 ppc_addi32 (s, rt, ra, si);
968 else {
969 tcg_out_movi (s, TCG_TYPE_I64, 0, si);
970 tcg_out32 (s, ADD | RT (rt) | RA (ra));
971 }
972 }
973
974 static void tcg_out_addi (TCGContext *s, int reg, tcg_target_long val)
975 {
976 ppc_addi64 (s, reg, reg, val);
977 }
978
979 static void tcg_out_cmp (TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
980 int const_arg2, int cr, int arch64)
981 {
982 int imm;
983 uint32_t op;
984
985 switch (cond) {
986 case TCG_COND_EQ:
987 case TCG_COND_NE:
988 if (const_arg2) {
989 if ((int16_t) arg2 == arg2) {
990 op = CMPI;
991 imm = 1;
992 break;
993 }
994 else if ((uint16_t) arg2 == arg2) {
995 op = CMPLI;
996 imm = 1;
997 break;
998 }
999 }
1000 op = CMPL;
1001 imm = 0;
1002 break;
1003
1004 case TCG_COND_LT:
1005 case TCG_COND_GE:
1006 case TCG_COND_LE:
1007 case TCG_COND_GT:
1008 if (const_arg2) {
1009 if ((int16_t) arg2 == arg2) {
1010 op = CMPI;
1011 imm = 1;
1012 break;
1013 }
1014 }
1015 op = CMP;
1016 imm = 0;
1017 break;
1018
1019 case TCG_COND_LTU:
1020 case TCG_COND_GEU:
1021 case TCG_COND_LEU:
1022 case TCG_COND_GTU:
1023 if (const_arg2) {
1024 if ((uint16_t) arg2 == arg2) {
1025 op = CMPLI;
1026 imm = 1;
1027 break;
1028 }
1029 }
1030 op = CMPL;
1031 imm = 0;
1032 break;
1033
1034 default:
1035 tcg_abort ();
1036 }
1037 op |= BF (cr) | (arch64 << 21);
1038
1039 if (imm)
1040 tcg_out32 (s, op | RA (arg1) | (arg2 & 0xffff));
1041 else {
1042 if (const_arg2) {
1043 tcg_out_movi (s, TCG_TYPE_I64, 0, arg2);
1044 tcg_out32 (s, op | RA (arg1) | RB (0));
1045 }
1046 else
1047 tcg_out32 (s, op | RA (arg1) | RB (arg2));
1048 }
1049
1050 }
1051
1052 static void tcg_out_setcond (TCGContext *s, TCGType type, int cond, TCGArg arg0,
1053 TCGArg arg1, TCGArg arg2, int const_arg2)
1054 {
1055 int crop, sh, arg;
1056
1057 switch (cond) {
1058 case TCG_COND_EQ:
1059 if (const_arg2) {
1060 if (!arg2) {
1061 arg = arg1;
1062 }
1063 else {
1064 arg = 0;
1065 if ((uint16_t) arg2 == arg2) {
1066 tcg_out32 (s, XORI | RS (arg1) | RA (0) | arg2);
1067 }
1068 else {
1069 tcg_out_movi (s, type, 0, arg2);
1070 tcg_out32 (s, XOR | SAB (arg1, 0, 0));
1071 }
1072 }
1073 }
1074 else {
1075 arg = 0;
1076 tcg_out32 (s, XOR | SAB (arg1, 0, arg2));
1077 }
1078
1079 if (type == TCG_TYPE_I64) {
1080 tcg_out32 (s, CNTLZD | RS (arg) | RA (0));
1081 tcg_out_rld (s, RLDICL, arg0, 0, 58, 6);
1082 }
1083 else {
1084 tcg_out32 (s, CNTLZW | RS (arg) | RA (0));
1085 tcg_out32 (s, (RLWINM
1086 | RA (arg0)
1087 | RS (0)
1088 | SH (27)
1089 | MB (5)
1090 | ME (31)
1091 )
1092 );
1093 }
1094 break;
1095
1096 case TCG_COND_NE:
1097 if (const_arg2) {
1098 if (!arg2) {
1099 arg = arg1;
1100 }
1101 else {
1102 arg = 0;
1103 if ((uint16_t) arg2 == arg2) {
1104 tcg_out32 (s, XORI | RS (arg1) | RA (0) | arg2);
1105 }
1106 else {
1107 tcg_out_movi (s, type, 0, arg2);
1108 tcg_out32 (s, XOR | SAB (arg1, 0, 0));
1109 }
1110 }
1111 }
1112 else {
1113 arg = 0;
1114 tcg_out32 (s, XOR | SAB (arg1, 0, arg2));
1115 }
1116
1117 if (arg == arg1 && arg1 == arg0) {
1118 tcg_out32 (s, ADDIC | RT (0) | RA (arg) | 0xffff);
1119 tcg_out32 (s, SUBFE | TAB (arg0, 0, arg));
1120 }
1121 else {
1122 tcg_out32 (s, ADDIC | RT (arg0) | RA (arg) | 0xffff);
1123 tcg_out32 (s, SUBFE | TAB (arg0, arg0, arg));
1124 }
1125 break;
1126
1127 case TCG_COND_GT:
1128 case TCG_COND_GTU:
1129 sh = 30;
1130 crop = 0;
1131 goto crtest;
1132
1133 case TCG_COND_LT:
1134 case TCG_COND_LTU:
1135 sh = 29;
1136 crop = 0;
1137 goto crtest;
1138
1139 case TCG_COND_GE:
1140 case TCG_COND_GEU:
1141 sh = 31;
1142 crop = CRNOR | BT (7, CR_EQ) | BA (7, CR_LT) | BB (7, CR_LT);
1143 goto crtest;
1144
1145 case TCG_COND_LE:
1146 case TCG_COND_LEU:
1147 sh = 31;
1148 crop = CRNOR | BT (7, CR_EQ) | BA (7, CR_GT) | BB (7, CR_GT);
1149 crtest:
1150 tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7, type == TCG_TYPE_I64);
1151 if (crop) tcg_out32 (s, crop);
1152 tcg_out32 (s, MFCR | RT (0));
1153 tcg_out32 (s, (RLWINM
1154 | RA (arg0)
1155 | RS (0)
1156 | SH (sh)
1157 | MB (31)
1158 | ME (31)
1159 )
1160 );
1161 break;
1162
1163 default:
1164 tcg_abort ();
1165 }
1166 }
1167
1168 static void tcg_out_bc (TCGContext *s, int bc, int label_index)
1169 {
1170 TCGLabel *l = &s->labels[label_index];
1171
1172 if (l->has_value)
1173 tcg_out32 (s, bc | reloc_pc14_val (s->code_ptr, l->u.value));
1174 else {
1175 uint16_t val = *(uint16_t *) &s->code_ptr[2];
1176
1177 /* Thanks to Andrzej Zaborowski */
1178 tcg_out32 (s, bc | (val & 0xfffc));
1179 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL14, label_index, 0);
1180 }
1181 }
1182
1183 static void tcg_out_brcond (TCGContext *s, int cond,
1184 TCGArg arg1, TCGArg arg2, int const_arg2,
1185 int label_index, int arch64)
1186 {
1187 tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7, arch64);
1188 tcg_out_bc (s, tcg_to_bc[cond], label_index);
1189 }
1190
1191 void ppc_tb_set_jmp_target (unsigned long jmp_addr, unsigned long addr)
1192 {
1193 TCGContext s;
1194 unsigned long patch_size;
1195
1196 s.code_ptr = (uint8_t *) jmp_addr;
1197 tcg_out_b (&s, 0, addr);
1198 patch_size = s.code_ptr - (uint8_t *) jmp_addr;
1199 flush_icache_range (jmp_addr, jmp_addr + patch_size);
1200 }
1201
1202 static void tcg_out_op (TCGContext *s, int opc, const TCGArg *args,
1203 const int *const_args)
1204 {
1205 int c;
1206
1207 switch (opc) {
1208 case INDEX_op_exit_tb:
1209 tcg_out_movi (s, TCG_TYPE_I64, TCG_REG_R3, args[0]);
1210 tcg_out_b (s, 0, (tcg_target_long) tb_ret_addr);
1211 break;
1212 case INDEX_op_goto_tb:
1213 if (s->tb_jmp_offset) {
1214 /* direct jump method */
1215
1216 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1217 s->code_ptr += 28;
1218 }
1219 else {
1220 tcg_abort ();
1221 }
1222 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1223 break;
1224 case INDEX_op_br:
1225 {
1226 TCGLabel *l = &s->labels[args[0]];
1227
1228 if (l->has_value) {
1229 tcg_out_b (s, 0, l->u.value);
1230 }
1231 else {
1232 uint32_t val = *(uint32_t *) s->code_ptr;
1233
1234 /* Thanks to Andrzej Zaborowski */
1235 tcg_out32 (s, B | (val & 0x3fffffc));
1236 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL24, args[0], 0);
1237 }
1238 }
1239 break;
1240 case INDEX_op_call:
1241 tcg_out_call (s, args[0], const_args[0]);
1242 break;
1243 case INDEX_op_jmp:
1244 if (const_args[0]) {
1245 tcg_out_b (s, 0, args[0]);
1246 }
1247 else {
1248 tcg_out32 (s, MTSPR | RS (args[0]) | CTR);
1249 tcg_out32 (s, BCCTR | BO_ALWAYS);
1250 }
1251 break;
1252 case INDEX_op_movi_i32:
1253 tcg_out_movi (s, TCG_TYPE_I32, args[0], args[1]);
1254 break;
1255 case INDEX_op_movi_i64:
1256 tcg_out_movi (s, TCG_TYPE_I64, args[0], args[1]);
1257 break;
1258 case INDEX_op_ld8u_i32:
1259 case INDEX_op_ld8u_i64:
1260 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1261 break;
1262 case INDEX_op_ld8s_i32:
1263 case INDEX_op_ld8s_i64:
1264 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1265 tcg_out32 (s, EXTSB | RS (args[0]) | RA (args[0]));
1266 break;
1267 case INDEX_op_ld16u_i32:
1268 case INDEX_op_ld16u_i64:
1269 tcg_out_ldst (s, args[0], args[1], args[2], LHZ, LHZX);
1270 break;
1271 case INDEX_op_ld16s_i32:
1272 case INDEX_op_ld16s_i64:
1273 tcg_out_ldst (s, args[0], args[1], args[2], LHA, LHAX);
1274 break;
1275 case INDEX_op_ld_i32:
1276 case INDEX_op_ld32u_i64:
1277 tcg_out_ldst (s, args[0], args[1], args[2], LWZ, LWZX);
1278 break;
1279 case INDEX_op_ld32s_i64:
1280 tcg_out_ldsta (s, args[0], args[1], args[2], LWA, LWAX);
1281 break;
1282 case INDEX_op_ld_i64:
1283 tcg_out_ldsta (s, args[0], args[1], args[2], LD, LDX);
1284 break;
1285 case INDEX_op_st8_i32:
1286 case INDEX_op_st8_i64:
1287 tcg_out_ldst (s, args[0], args[1], args[2], STB, STBX);
1288 break;
1289 case INDEX_op_st16_i32:
1290 case INDEX_op_st16_i64:
1291 tcg_out_ldst (s, args[0], args[1], args[2], STH, STHX);
1292 break;
1293 case INDEX_op_st_i32:
1294 case INDEX_op_st32_i64:
1295 tcg_out_ldst (s, args[0], args[1], args[2], STW, STWX);
1296 break;
1297 case INDEX_op_st_i64:
1298 tcg_out_ldsta (s, args[0], args[1], args[2], STD, STDX);
1299 break;
1300
1301 case INDEX_op_add_i32:
1302 if (const_args[2])
1303 ppc_addi32 (s, args[0], args[1], args[2]);
1304 else
1305 tcg_out32 (s, ADD | TAB (args[0], args[1], args[2]));
1306 break;
1307 case INDEX_op_sub_i32:
1308 if (const_args[2])
1309 ppc_addi32 (s, args[0], args[1], -args[2]);
1310 else
1311 tcg_out32 (s, SUBF | TAB (args[0], args[2], args[1]));
1312 break;
1313
1314 case INDEX_op_and_i64:
1315 case INDEX_op_and_i32:
1316 if (const_args[2]) {
1317 if ((args[2] & 0xffff) == args[2])
1318 tcg_out32 (s, ANDI | RS (args[1]) | RA (args[0]) | args[2]);
1319 else if ((args[2] & 0xffff0000) == args[2])
1320 tcg_out32 (s, ANDIS | RS (args[1]) | RA (args[0])
1321 | ((args[2] >> 16) & 0xffff));
1322 else {
1323 tcg_out_movi (s, (opc == INDEX_op_and_i32
1324 ? TCG_TYPE_I32
1325 : TCG_TYPE_I64),
1326 0, args[2]);
1327 tcg_out32 (s, AND | SAB (args[1], args[0], 0));
1328 }
1329 }
1330 else
1331 tcg_out32 (s, AND | SAB (args[1], args[0], args[2]));
1332 break;
1333 case INDEX_op_or_i64:
1334 case INDEX_op_or_i32:
1335 if (const_args[2]) {
1336 if (args[2] & 0xffff) {
1337 tcg_out32 (s, ORI | RS (args[1]) | RA (args[0])
1338 | (args[2] & 0xffff));
1339 if (args[2] >> 16)
1340 tcg_out32 (s, ORIS | RS (args[0]) | RA (args[0])
1341 | ((args[2] >> 16) & 0xffff));
1342 }
1343 else {
1344 tcg_out32 (s, ORIS | RS (args[1]) | RA (args[0])
1345 | ((args[2] >> 16) & 0xffff));
1346 }
1347 }
1348 else
1349 tcg_out32 (s, OR | SAB (args[1], args[0], args[2]));
1350 break;
1351 case INDEX_op_xor_i64:
1352 case INDEX_op_xor_i32:
1353 if (const_args[2]) {
1354 if ((args[2] & 0xffff) == args[2])
1355 tcg_out32 (s, XORI | RS (args[1]) | RA (args[0])
1356 | (args[2] & 0xffff));
1357 else if ((args[2] & 0xffff0000) == args[2])
1358 tcg_out32 (s, XORIS | RS (args[1]) | RA (args[0])
1359 | ((args[2] >> 16) & 0xffff));
1360 else {
1361 tcg_out_movi (s, (opc == INDEX_op_and_i32
1362 ? TCG_TYPE_I32
1363 : TCG_TYPE_I64),
1364 0, args[2]);
1365 tcg_out32 (s, XOR | SAB (args[1], args[0], 0));
1366 }
1367 }
1368 else
1369 tcg_out32 (s, XOR | SAB (args[1], args[0], args[2]));
1370 break;
1371
1372 case INDEX_op_mul_i32:
1373 if (const_args[2]) {
1374 if (args[2] == (int16_t) args[2])
1375 tcg_out32 (s, MULLI | RT (args[0]) | RA (args[1])
1376 | (args[2] & 0xffff));
1377 else {
1378 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1379 tcg_out32 (s, MULLW | TAB (args[0], args[1], 0));
1380 }
1381 }
1382 else
1383 tcg_out32 (s, MULLW | TAB (args[0], args[1], args[2]));
1384 break;
1385
1386 case INDEX_op_div_i32:
1387 tcg_out32 (s, DIVW | TAB (args[0], args[1], args[2]));
1388 break;
1389
1390 case INDEX_op_divu_i32:
1391 tcg_out32 (s, DIVWU | TAB (args[0], args[1], args[2]));
1392 break;
1393
1394 case INDEX_op_rem_i32:
1395 tcg_out32 (s, DIVW | TAB (0, args[1], args[2]));
1396 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1397 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1398 break;
1399
1400 case INDEX_op_remu_i32:
1401 tcg_out32 (s, DIVWU | TAB (0, args[1], args[2]));
1402 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1403 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1404 break;
1405
1406 case INDEX_op_shl_i32:
1407 if (const_args[2]) {
1408 tcg_out32 (s, (RLWINM
1409 | RA (args[0])
1410 | RS (args[1])
1411 | SH (args[2])
1412 | MB (0)
1413 | ME (31 - args[2])
1414 )
1415 );
1416 }
1417 else
1418 tcg_out32 (s, SLW | SAB (args[1], args[0], args[2]));
1419 break;
1420 case INDEX_op_shr_i32:
1421 if (const_args[2]) {
1422 tcg_out32 (s, (RLWINM
1423 | RA (args[0])
1424 | RS (args[1])
1425 | SH (32 - args[2])
1426 | MB (args[2])
1427 | ME (31)
1428 )
1429 );
1430 }
1431 else
1432 tcg_out32 (s, SRW | SAB (args[1], args[0], args[2]));
1433 break;
1434 case INDEX_op_sar_i32:
1435 if (const_args[2])
1436 tcg_out32 (s, SRAWI | RS (args[1]) | RA (args[0]) | SH (args[2]));
1437 else
1438 tcg_out32 (s, SRAW | SAB (args[1], args[0], args[2]));
1439 break;
1440
1441 case INDEX_op_brcond_i32:
1442 tcg_out_brcond (s, args[2], args[0], args[1], const_args[1], args[3], 0);
1443 break;
1444
1445 case INDEX_op_brcond_i64:
1446 tcg_out_brcond (s, args[2], args[0], args[1], const_args[1], args[3], 1);
1447 break;
1448
1449 case INDEX_op_neg_i32:
1450 case INDEX_op_neg_i64:
1451 tcg_out32 (s, NEG | RT (args[0]) | RA (args[1]));
1452 break;
1453
1454 case INDEX_op_add_i64:
1455 if (const_args[2])
1456 ppc_addi64 (s, args[0], args[1], args[2]);
1457 else
1458 tcg_out32 (s, ADD | TAB (args[0], args[1], args[2]));
1459 break;
1460 case INDEX_op_sub_i64:
1461 if (const_args[2])
1462 ppc_addi64 (s, args[0], args[1], -args[2]);
1463 else
1464 tcg_out32 (s, SUBF | TAB (args[0], args[2], args[1]));
1465 break;
1466
1467 case INDEX_op_shl_i64:
1468 if (const_args[2])
1469 tcg_out_rld (s, RLDICR, args[0], args[1], args[2], 63 - args[2]);
1470 else
1471 tcg_out32 (s, SLD | SAB (args[1], args[0], args[2]));
1472 break;
1473 case INDEX_op_shr_i64:
1474 if (const_args[2])
1475 tcg_out_rld (s, RLDICL, args[0], args[1], 64 - args[2], args[2]);
1476 else
1477 tcg_out32 (s, SRD | SAB (args[1], args[0], args[2]));
1478 break;
1479 case INDEX_op_sar_i64:
1480 if (const_args[2]) {
1481 int sh = SH (args[2] & 0x1f) | (((args[2] >> 5) & 1) << 1);
1482 tcg_out32 (s, SRADI | RA (args[0]) | RS (args[1]) | sh);
1483 }
1484 else
1485 tcg_out32 (s, SRAD | SAB (args[1], args[0], args[2]));
1486 break;
1487
1488 case INDEX_op_mul_i64:
1489 tcg_out32 (s, MULLD | TAB (args[0], args[1], args[2]));
1490 break;
1491 case INDEX_op_div_i64:
1492 tcg_out32 (s, DIVD | TAB (args[0], args[1], args[2]));
1493 break;
1494 case INDEX_op_divu_i64:
1495 tcg_out32 (s, DIVDU | TAB (args[0], args[1], args[2]));
1496 break;
1497 case INDEX_op_rem_i64:
1498 tcg_out32 (s, DIVD | TAB (0, args[1], args[2]));
1499 tcg_out32 (s, MULLD | TAB (0, 0, args[2]));
1500 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1501 break;
1502 case INDEX_op_remu_i64:
1503 tcg_out32 (s, DIVDU | TAB (0, args[1], args[2]));
1504 tcg_out32 (s, MULLD | TAB (0, 0, args[2]));
1505 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1506 break;
1507
1508 case INDEX_op_qemu_ld8u:
1509 tcg_out_qemu_ld (s, args, 0);
1510 break;
1511 case INDEX_op_qemu_ld8s:
1512 tcg_out_qemu_ld (s, args, 0 | 4);
1513 break;
1514 case INDEX_op_qemu_ld16u:
1515 tcg_out_qemu_ld (s, args, 1);
1516 break;
1517 case INDEX_op_qemu_ld16s:
1518 tcg_out_qemu_ld (s, args, 1 | 4);
1519 break;
1520 case INDEX_op_qemu_ld32u:
1521 tcg_out_qemu_ld (s, args, 2);
1522 break;
1523 case INDEX_op_qemu_ld32s:
1524 tcg_out_qemu_ld (s, args, 2 | 4);
1525 break;
1526 case INDEX_op_qemu_ld64:
1527 tcg_out_qemu_ld (s, args, 3);
1528 break;
1529 case INDEX_op_qemu_st8:
1530 tcg_out_qemu_st (s, args, 0);
1531 break;
1532 case INDEX_op_qemu_st16:
1533 tcg_out_qemu_st (s, args, 1);
1534 break;
1535 case INDEX_op_qemu_st32:
1536 tcg_out_qemu_st (s, args, 2);
1537 break;
1538 case INDEX_op_qemu_st64:
1539 tcg_out_qemu_st (s, args, 3);
1540 break;
1541
1542 case INDEX_op_ext8s_i32:
1543 case INDEX_op_ext8s_i64:
1544 c = EXTSB;
1545 goto gen_ext;
1546 case INDEX_op_ext16s_i32:
1547 case INDEX_op_ext16s_i64:
1548 c = EXTSH;
1549 goto gen_ext;
1550 case INDEX_op_ext32s_i64:
1551 c = EXTSW;
1552 goto gen_ext;
1553 gen_ext:
1554 tcg_out32 (s, c | RS (args[1]) | RA (args[0]));
1555 break;
1556
1557 case INDEX_op_setcond_i32:
1558 tcg_out_setcond (s, TCG_TYPE_I32, args[3], args[0], args[1], args[2],
1559 const_args[2]);
1560 break;
1561 case INDEX_op_setcond_i64:
1562 tcg_out_setcond (s, TCG_TYPE_I64, args[3], args[0], args[1], args[2],
1563 const_args[2]);
1564 break;
1565
1566 default:
1567 tcg_dump_ops (s, stderr);
1568 tcg_abort ();
1569 }
1570 }
1571
1572 static const TCGTargetOpDef ppc_op_defs[] = {
1573 { INDEX_op_exit_tb, { } },
1574 { INDEX_op_goto_tb, { } },
1575 { INDEX_op_call, { "ri" } },
1576 { INDEX_op_jmp, { "ri" } },
1577 { INDEX_op_br, { } },
1578
1579 { INDEX_op_mov_i32, { "r", "r" } },
1580 { INDEX_op_mov_i64, { "r", "r" } },
1581 { INDEX_op_movi_i32, { "r" } },
1582 { INDEX_op_movi_i64, { "r" } },
1583
1584 { INDEX_op_ld8u_i32, { "r", "r" } },
1585 { INDEX_op_ld8s_i32, { "r", "r" } },
1586 { INDEX_op_ld16u_i32, { "r", "r" } },
1587 { INDEX_op_ld16s_i32, { "r", "r" } },
1588 { INDEX_op_ld_i32, { "r", "r" } },
1589 { INDEX_op_ld_i64, { "r", "r" } },
1590 { INDEX_op_st8_i32, { "r", "r" } },
1591 { INDEX_op_st8_i64, { "r", "r" } },
1592 { INDEX_op_st16_i32, { "r", "r" } },
1593 { INDEX_op_st16_i64, { "r", "r" } },
1594 { INDEX_op_st_i32, { "r", "r" } },
1595 { INDEX_op_st_i64, { "r", "r" } },
1596 { INDEX_op_st32_i64, { "r", "r" } },
1597
1598 { INDEX_op_ld8u_i64, { "r", "r" } },
1599 { INDEX_op_ld8s_i64, { "r", "r" } },
1600 { INDEX_op_ld16u_i64, { "r", "r" } },
1601 { INDEX_op_ld16s_i64, { "r", "r" } },
1602 { INDEX_op_ld32u_i64, { "r", "r" } },
1603 { INDEX_op_ld32s_i64, { "r", "r" } },
1604 { INDEX_op_ld_i64, { "r", "r" } },
1605
1606 { INDEX_op_add_i32, { "r", "r", "ri" } },
1607 { INDEX_op_mul_i32, { "r", "r", "ri" } },
1608 { INDEX_op_div_i32, { "r", "r", "r" } },
1609 { INDEX_op_divu_i32, { "r", "r", "r" } },
1610 { INDEX_op_rem_i32, { "r", "r", "r" } },
1611 { INDEX_op_remu_i32, { "r", "r", "r" } },
1612 { INDEX_op_sub_i32, { "r", "r", "ri" } },
1613 { INDEX_op_and_i32, { "r", "r", "ri" } },
1614 { INDEX_op_or_i32, { "r", "r", "ri" } },
1615 { INDEX_op_xor_i32, { "r", "r", "ri" } },
1616
1617 { INDEX_op_shl_i32, { "r", "r", "ri" } },
1618 { INDEX_op_shr_i32, { "r", "r", "ri" } },
1619 { INDEX_op_sar_i32, { "r", "r", "ri" } },
1620
1621 { INDEX_op_brcond_i32, { "r", "ri" } },
1622 { INDEX_op_brcond_i64, { "r", "ri" } },
1623
1624 { INDEX_op_neg_i32, { "r", "r" } },
1625
1626 { INDEX_op_add_i64, { "r", "r", "ri" } },
1627 { INDEX_op_sub_i64, { "r", "r", "ri" } },
1628 { INDEX_op_and_i64, { "r", "r", "rZ" } },
1629 { INDEX_op_or_i64, { "r", "r", "rZ" } },
1630 { INDEX_op_xor_i64, { "r", "r", "rZ" } },
1631
1632 { INDEX_op_shl_i64, { "r", "r", "ri" } },
1633 { INDEX_op_shr_i64, { "r", "r", "ri" } },
1634 { INDEX_op_sar_i64, { "r", "r", "ri" } },
1635
1636 { INDEX_op_mul_i64, { "r", "r", "r" } },
1637 { INDEX_op_div_i64, { "r", "r", "r" } },
1638 { INDEX_op_divu_i64, { "r", "r", "r" } },
1639 { INDEX_op_rem_i64, { "r", "r", "r" } },
1640 { INDEX_op_remu_i64, { "r", "r", "r" } },
1641
1642 { INDEX_op_neg_i64, { "r", "r" } },
1643
1644 { INDEX_op_qemu_ld8u, { "r", "L" } },
1645 { INDEX_op_qemu_ld8s, { "r", "L" } },
1646 { INDEX_op_qemu_ld16u, { "r", "L" } },
1647 { INDEX_op_qemu_ld16s, { "r", "L" } },
1648 { INDEX_op_qemu_ld32u, { "r", "L" } },
1649 { INDEX_op_qemu_ld32s, { "r", "L" } },
1650 { INDEX_op_qemu_ld64, { "r", "L" } },
1651
1652 { INDEX_op_qemu_st8, { "S", "S" } },
1653 { INDEX_op_qemu_st16, { "S", "S" } },
1654 { INDEX_op_qemu_st32, { "S", "S" } },
1655 { INDEX_op_qemu_st64, { "S", "S" } },
1656
1657 { INDEX_op_ext8s_i32, { "r", "r" } },
1658 { INDEX_op_ext16s_i32, { "r", "r" } },
1659 { INDEX_op_ext8s_i64, { "r", "r" } },
1660 { INDEX_op_ext16s_i64, { "r", "r" } },
1661 { INDEX_op_ext32s_i64, { "r", "r" } },
1662
1663 { INDEX_op_setcond_i32, { "r", "r", "ri" } },
1664 { INDEX_op_setcond_i64, { "r", "r", "ri" } },
1665
1666 { -1 },
1667 };
1668
1669 void tcg_target_init (TCGContext *s)
1670 {
1671 tcg_regset_set32 (tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
1672 tcg_regset_set32 (tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
1673 tcg_regset_set32 (tcg_target_call_clobber_regs, 0,
1674 (1 << TCG_REG_R0) |
1675 #ifdef __APPLE__
1676 (1 << TCG_REG_R2) |
1677 #endif
1678 (1 << TCG_REG_R3) |
1679 (1 << TCG_REG_R4) |
1680 (1 << TCG_REG_R5) |
1681 (1 << TCG_REG_R6) |
1682 (1 << TCG_REG_R7) |
1683 (1 << TCG_REG_R8) |
1684 (1 << TCG_REG_R9) |
1685 (1 << TCG_REG_R10) |
1686 (1 << TCG_REG_R11) |
1687 (1 << TCG_REG_R12)
1688 );
1689
1690 tcg_regset_clear (s->reserved_regs);
1691 tcg_regset_set_reg (s->reserved_regs, TCG_REG_R0);
1692 tcg_regset_set_reg (s->reserved_regs, TCG_REG_R1);
1693 #ifndef __APPLE__
1694 tcg_regset_set_reg (s->reserved_regs, TCG_REG_R2);
1695 #endif
1696 tcg_regset_set_reg (s->reserved_regs, TCG_REG_R13);
1697
1698 #ifdef CONFIG_USE_GUEST_BASE
1699 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
1700 #endif
1701
1702 tcg_add_target_add_op_defs (ppc_op_defs);
1703 }
Qemu copy for testing