2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #define TCG_CT_CONST_U32 0x100
27 static uint8_t *tb_ret_addr
;
31 #if TARGET_LONG_BITS == 32
43 #ifdef CONFIG_USE_GUEST_BASE
44 #define TCG_GUEST_BASE_REG 30
46 #define TCG_GUEST_BASE_REG 0
50 static const char * const tcg_target_reg_names
[TCG_TARGET_NB_REGS
] = {
86 static const int tcg_target_reg_alloc_order
[] = {
122 static const int tcg_target_call_iarg_regs
[] = {
133 static const int tcg_target_call_oarg_regs
[] = {
137 static const int tcg_target_callee_save_regs
[] = {
154 TCG_REG_R27
, /* currently used for the global env */
161 static uint32_t reloc_pc24_val (void *pc
, tcg_target_long target
)
163 tcg_target_long disp
;
165 disp
= target
- (tcg_target_long
) pc
;
166 if ((disp
<< 38) >> 38 != disp
)
169 return disp
& 0x3fffffc;
172 static void reloc_pc24 (void *pc
, tcg_target_long target
)
174 *(uint32_t *) pc
= (*(uint32_t *) pc
& ~0x3fffffc)
175 | reloc_pc24_val (pc
, target
);
178 static uint16_t reloc_pc14_val (void *pc
, tcg_target_long target
)
180 tcg_target_long disp
;
182 disp
= target
- (tcg_target_long
) pc
;
183 if (disp
!= (int16_t) disp
)
186 return disp
& 0xfffc;
189 static void reloc_pc14 (void *pc
, tcg_target_long target
)
191 *(uint32_t *) pc
= (*(uint32_t *) pc
& ~0xfffc)
192 | reloc_pc14_val (pc
, target
);
195 static void patch_reloc (uint8_t *code_ptr
, int type
,
196 tcg_target_long value
, tcg_target_long addend
)
201 reloc_pc14 (code_ptr
, value
);
204 reloc_pc24 (code_ptr
, value
);
211 /* maximum number of register used for input function arguments */
212 static int tcg_target_get_call_iarg_regs_count (int flags
)
214 return ARRAY_SIZE (tcg_target_call_iarg_regs
);
217 /* parse target specific constraints */
218 static int target_parse_constraint (TCGArgConstraint
*ct
, const char **pct_str
)
224 case 'A': case 'B': case 'C': case 'D':
225 ct
->ct
|= TCG_CT_REG
;
226 tcg_regset_set_reg (ct
->u
.regs
, 3 + ct_str
[0] - 'A');
229 ct
->ct
|= TCG_CT_REG
;
230 tcg_regset_set32 (ct
->u
.regs
, 0, 0xffffffff);
232 case 'L': /* qemu_ld constraint */
233 ct
->ct
|= TCG_CT_REG
;
234 tcg_regset_set32 (ct
->u
.regs
, 0, 0xffffffff);
235 tcg_regset_reset_reg (ct
->u
.regs
, TCG_REG_R3
);
236 #ifdef CONFIG_SOFTMMU
237 tcg_regset_reset_reg (ct
->u
.regs
, TCG_REG_R4
);
240 case 'S': /* qemu_st constraint */
241 ct
->ct
|= TCG_CT_REG
;
242 tcg_regset_set32 (ct
->u
.regs
, 0, 0xffffffff);
243 tcg_regset_reset_reg (ct
->u
.regs
, TCG_REG_R3
);
244 #ifdef CONFIG_SOFTMMU
245 tcg_regset_reset_reg (ct
->u
.regs
, TCG_REG_R4
);
246 tcg_regset_reset_reg (ct
->u
.regs
, TCG_REG_R5
);
250 ct
->ct
|= TCG_CT_CONST_U32
;
260 /* test if a constant matches the constraint */
261 static int tcg_target_const_match (tcg_target_long val
,
262 const TCGArgConstraint
*arg_ct
)
267 if (ct
& TCG_CT_CONST
)
269 else if ((ct
& TCG_CT_CONST_U32
) && (val
== (uint32_t) val
))
274 #define OPCD(opc) ((opc)<<26)
275 #define XO19(opc) (OPCD(19)|((opc)<<1))
276 #define XO30(opc) (OPCD(30)|((opc)<<2))
277 #define XO31(opc) (OPCD(31)|((opc)<<1))
278 #define XO58(opc) (OPCD(58)|(opc))
279 #define XO62(opc) (OPCD(62)|(opc))
283 #define LBZ OPCD( 34)
284 #define LHZ OPCD( 40)
285 #define LHA OPCD( 42)
286 #define LWZ OPCD( 32)
287 #define STB OPCD( 38)
288 #define STH OPCD( 44)
289 #define STW OPCD( 36)
292 #define STDU XO62( 1)
293 #define STDX XO31(149)
296 #define LDX XO31( 21)
299 #define LWAX XO31(341)
301 #define ADDIC OPCD( 12)
302 #define ADDI OPCD( 14)
303 #define ADDIS OPCD( 15)
304 #define ORI OPCD( 24)
305 #define ORIS OPCD( 25)
306 #define XORI OPCD( 26)
307 #define XORIS OPCD( 27)
308 #define ANDI OPCD( 28)
309 #define ANDIS OPCD( 29)
310 #define MULLI OPCD( 7)
311 #define CMPLI OPCD( 10)
312 #define CMPI OPCD( 11)
314 #define LWZU OPCD( 33)
315 #define STWU OPCD( 37)
317 #define RLWINM OPCD( 21)
319 #define RLDICL XO30( 0)
320 #define RLDICR XO30( 1)
321 #define RLDIMI XO30( 3)
323 #define BCLR XO19( 16)
324 #define BCCTR XO19(528)
325 #define CRAND XO19(257)
326 #define CRANDC XO19(129)
327 #define CRNAND XO19(225)
328 #define CROR XO19(449)
329 #define CRNOR XO19( 33)
331 #define EXTSB XO31(954)
332 #define EXTSH XO31(922)
333 #define EXTSW XO31(986)
334 #define ADD XO31(266)
335 #define ADDE XO31(138)
336 #define ADDC XO31( 10)
337 #define AND XO31( 28)
338 #define SUBF XO31( 40)
339 #define SUBFC XO31( 8)
340 #define SUBFE XO31(136)
342 #define XOR XO31(316)
343 #define MULLW XO31(235)
344 #define MULHWU XO31( 11)
345 #define DIVW XO31(491)
346 #define DIVWU XO31(459)
348 #define CMPL XO31( 32)
349 #define LHBRX XO31(790)
350 #define LWBRX XO31(534)
351 #define STHBRX XO31(918)
352 #define STWBRX XO31(662)
353 #define MFSPR XO31(339)
354 #define MTSPR XO31(467)
355 #define SRAWI XO31(824)
356 #define NEG XO31(104)
357 #define MFCR XO31( 19)
358 #define NOR XO31(124)
359 #define CNTLZW XO31( 26)
360 #define CNTLZD XO31( 58)
362 #define MULLD XO31(233)
363 #define MULHD XO31( 73)
364 #define MULHDU XO31( 9)
365 #define DIVD XO31(489)
366 #define DIVDU XO31(457)
368 #define LBZX XO31( 87)
369 #define LHZX XO31(279)
370 #define LHAX XO31(343)
371 #define LWZX XO31( 23)
372 #define STBX XO31(215)
373 #define STHX XO31(407)
374 #define STWX XO31(151)
376 #define SPR(a,b) ((((a)<<5)|(b))<<11)
378 #define CTR SPR(9, 0)
380 #define SLW XO31( 24)
381 #define SRW XO31(536)
382 #define SRAW XO31(792)
384 #define SLD XO31( 27)
385 #define SRD XO31(539)
386 #define SRAD XO31(794)
387 #define SRADI XO31(413<<1)
390 #define TRAP (TW | TO (31))
392 #define RT(r) ((r)<<21)
393 #define RS(r) ((r)<<21)
394 #define RA(r) ((r)<<16)
395 #define RB(r) ((r)<<11)
396 #define TO(t) ((t)<<21)
397 #define SH(s) ((s)<<11)
398 #define MB(b) ((b)<<6)
399 #define ME(e) ((e)<<1)
400 #define BO(o) ((o)<<21)
401 #define MB64(b) ((b)<<5)
405 #define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
406 #define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
408 #define BF(n) ((n)<<23)
409 #define BI(n, c) (((c)+((n)*4))<<16)
410 #define BT(n, c) (((c)+((n)*4))<<21)
411 #define BA(n, c) (((c)+((n)*4))<<16)
412 #define BB(n, c) (((c)+((n)*4))<<11)
414 #define BO_COND_TRUE BO (12)
415 #define BO_COND_FALSE BO ( 4)
416 #define BO_ALWAYS BO (20)
425 static const uint32_t tcg_to_bc
[10] = {
426 [TCG_COND_EQ
] = BC
| BI (7, CR_EQ
) | BO_COND_TRUE
,
427 [TCG_COND_NE
] = BC
| BI (7, CR_EQ
) | BO_COND_FALSE
,
428 [TCG_COND_LT
] = BC
| BI (7, CR_LT
) | BO_COND_TRUE
,
429 [TCG_COND_GE
] = BC
| BI (7, CR_LT
) | BO_COND_FALSE
,
430 [TCG_COND_LE
] = BC
| BI (7, CR_GT
) | BO_COND_FALSE
,
431 [TCG_COND_GT
] = BC
| BI (7, CR_GT
) | BO_COND_TRUE
,
432 [TCG_COND_LTU
] = BC
| BI (7, CR_LT
) | BO_COND_TRUE
,
433 [TCG_COND_GEU
] = BC
| BI (7, CR_LT
) | BO_COND_FALSE
,
434 [TCG_COND_LEU
] = BC
| BI (7, CR_GT
) | BO_COND_FALSE
,
435 [TCG_COND_GTU
] = BC
| BI (7, CR_GT
) | BO_COND_TRUE
,
438 static void tcg_out_mov (TCGContext
*s
, TCGType type
, TCGReg ret
, TCGReg arg
)
440 tcg_out32 (s
, OR
| SAB (arg
, ret
, arg
));
443 static void tcg_out_rld (TCGContext
*s
, int op
, int ra
, int rs
, int sh
, int mb
)
445 sh
= SH (sh
& 0x1f) | (((sh
>> 5) & 1) << 1);
446 mb
= MB64 ((mb
>> 5) | ((mb
<< 1) & 0x3f));
447 tcg_out32 (s
, op
| RA (ra
) | RS (rs
) | sh
| mb
);
450 static void tcg_out_movi32 (TCGContext
*s
, int ret
, int32_t arg
)
452 if (arg
== (int16_t) arg
)
453 tcg_out32 (s
, ADDI
| RT (ret
) | RA (0) | (arg
& 0xffff));
455 tcg_out32 (s
, ADDIS
| RT (ret
) | RA (0) | ((arg
>> 16) & 0xffff));
457 tcg_out32 (s
, ORI
| RS (ret
) | RA (ret
) | (arg
& 0xffff));
461 static void tcg_out_movi (TCGContext
*s
, TCGType type
,
462 TCGReg ret
, tcg_target_long arg
)
465 arg
= type
== TCG_TYPE_I32
? arg
& 0xffffffff : arg
;
468 tcg_out_movi32 (s
, ret
, arg32
);
471 if ((uint64_t) arg
>> 32) {
472 uint16_t h16
= arg
>> 16;
475 tcg_out_movi32 (s
, ret
, arg
>> 32);
476 tcg_out_rld (s
, RLDICR
, ret
, ret
, 32, 31);
477 if (h16
) tcg_out32 (s
, ORIS
| RS (ret
) | RA (ret
) | h16
);
478 if (l16
) tcg_out32 (s
, ORI
| RS (ret
) | RA (ret
) | l16
);
481 tcg_out_movi32 (s
, ret
, arg32
);
483 tcg_out_rld (s
, RLDICL
, ret
, ret
, 0, 32);
488 static void tcg_out_b (TCGContext
*s
, int mask
, tcg_target_long target
)
490 tcg_target_long disp
;
492 disp
= target
- (tcg_target_long
) s
->code_ptr
;
493 if ((disp
<< 38) >> 38 == disp
)
494 tcg_out32 (s
, B
| (disp
& 0x3fffffc) | mask
);
496 tcg_out_movi (s
, TCG_TYPE_I64
, 0, (tcg_target_long
) target
);
497 tcg_out32 (s
, MTSPR
| RS (0) | CTR
);
498 tcg_out32 (s
, BCCTR
| BO_ALWAYS
| mask
);
502 static void tcg_out_call (TCGContext
*s
, tcg_target_long arg
, int const_arg
)
506 tcg_out_b (s
, LK
, arg
);
509 tcg_out32 (s
, MTSPR
| RS (arg
) | LR
);
510 tcg_out32 (s
, BCLR
| BO_ALWAYS
| LK
);
517 tcg_out_movi (s
, TCG_TYPE_I64
, reg
, arg
);
521 tcg_out32 (s
, LD
| RT (0) | RA (reg
));
522 tcg_out32 (s
, MTSPR
| RA (0) | CTR
);
523 tcg_out32 (s
, LD
| RT (11) | RA (reg
) | 16);
524 tcg_out32 (s
, LD
| RT (2) | RA (reg
) | 8);
525 tcg_out32 (s
, BCCTR
| BO_ALWAYS
| LK
);
529 static void tcg_out_ldst (TCGContext
*s
, int ret
, int addr
,
530 int offset
, int op1
, int op2
)
532 if (offset
== (int16_t) offset
)
533 tcg_out32 (s
, op1
| RT (ret
) | RA (addr
) | (offset
& 0xffff));
535 tcg_out_movi (s
, TCG_TYPE_I64
, 0, offset
);
536 tcg_out32 (s
, op2
| RT (ret
) | RA (addr
) | RB (0));
540 static void tcg_out_ldsta (TCGContext
*s
, int ret
, int addr
,
541 int offset
, int op1
, int op2
)
543 if (offset
== (int16_t) (offset
& ~3))
544 tcg_out32 (s
, op1
| RT (ret
) | RA (addr
) | (offset
& 0xffff));
546 tcg_out_movi (s
, TCG_TYPE_I64
, 0, offset
);
547 tcg_out32 (s
, op2
| RT (ret
) | RA (addr
) | RB (0));
551 #if defined (CONFIG_SOFTMMU)
553 #include "../../softmmu_defs.h"
555 #ifdef CONFIG_TCG_PASS_AREG0
556 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
558 static const void * const qemu_ld_helpers
[4] = {
565 /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
566 uintxx_t val, int mmu_idx) */
567 static const void * const qemu_st_helpers
[4] = {
574 /* legacy helper signature: __ld_mmu(target_ulong addr, int
576 static void *qemu_ld_helpers
[4] = {
583 /* legacy helper signature: __st_mmu(target_ulong addr, uintxx_t val,
585 static void *qemu_st_helpers
[4] = {
593 static void tcg_out_tlb_read (TCGContext
*s
, int r0
, int r1
, int r2
,
594 int addr_reg
, int s_bits
, int offset
)
596 #if TARGET_LONG_BITS == 32
597 tcg_out_rld (s
, RLDICL
, addr_reg
, addr_reg
, 0, 32);
599 tcg_out32 (s
, (RLWINM
602 | SH (32 - (TARGET_PAGE_BITS
- CPU_TLB_ENTRY_BITS
))
603 | MB (32 - (CPU_TLB_BITS
+ CPU_TLB_ENTRY_BITS
))
604 | ME (31 - CPU_TLB_ENTRY_BITS
)
607 tcg_out32 (s
, ADD
| RT (r0
) | RA (r0
) | RB (TCG_AREG0
));
608 tcg_out32 (s
, (LWZU
| RT (r1
) | RA (r0
) | offset
));
609 tcg_out32 (s
, (RLWINM
613 | MB ((32 - s_bits
) & 31)
614 | ME (31 - TARGET_PAGE_BITS
)
618 tcg_out_rld (s
, RLDICL
, r0
, addr_reg
,
619 64 - TARGET_PAGE_BITS
,
621 tcg_out_rld (s
, RLDICR
, r0
, r0
,
623 63 - CPU_TLB_ENTRY_BITS
);
625 tcg_out32 (s
, ADD
| TAB (r0
, r0
, TCG_AREG0
));
626 tcg_out32 (s
, LD_ADDR
| RT (r1
) | RA (r0
) | offset
);
629 tcg_out_rld (s
, RLDICR
, r2
, addr_reg
, 0, 63 - TARGET_PAGE_BITS
);
632 tcg_out_rld (s
, RLDICL
, r2
, addr_reg
,
633 64 - TARGET_PAGE_BITS
,
634 TARGET_PAGE_BITS
- s_bits
);
635 tcg_out_rld (s
, RLDICL
, r2
, r2
, TARGET_PAGE_BITS
, 0);
641 static void tcg_out_qemu_ld (TCGContext
*s
, const TCGArg
*args
, int opc
)
643 int addr_reg
, data_reg
, r0
, r1
, rbase
, bswap
;
644 #ifdef CONFIG_SOFTMMU
645 int r2
, mem_index
, s_bits
;
646 void *label1_ptr
, *label2_ptr
;
652 #ifdef CONFIG_SOFTMMU
661 tcg_out_tlb_read (s
, r0
, r1
, r2
, addr_reg
, s_bits
,
662 offsetof (CPUArchState
, tlb_table
[mem_index
][0].addr_read
));
664 tcg_out32 (s
, CMP
| BF (7) | RA (r2
) | RB (r1
) | CMP_L
);
666 label1_ptr
= s
->code_ptr
;
668 tcg_out32 (s
, BC
| BI (7, CR_EQ
) | BO_COND_TRUE
);
672 tcg_out_mov (s
, TCG_TYPE_I64
, 3, addr_reg
);
673 tcg_out_movi (s
, TCG_TYPE_I64
, 4, mem_index
);
675 #ifdef CONFIG_TCG_PASS_AREG0
676 /* XXX/FIXME: suboptimal */
677 tcg_out_mov(s
, TCG_TYPE_I32
, tcg_target_call_iarg_regs
[2],
678 tcg_target_call_iarg_regs
[1]);
679 tcg_out_mov(s
, TCG_TYPE_TL
, tcg_target_call_iarg_regs
[1],
680 tcg_target_call_iarg_regs
[0]);
681 tcg_out_mov(s
, TCG_TYPE_PTR
, tcg_target_call_iarg_regs
[0],
684 tcg_out_call (s
, (tcg_target_long
) qemu_ld_helpers
[s_bits
], 1);
688 tcg_out32 (s
, EXTSB
| RA (data_reg
) | RS (3));
691 tcg_out32 (s
, EXTSH
| RA (data_reg
) | RS (3));
694 tcg_out32 (s
, EXTSW
| RA (data_reg
) | RS (3));
701 tcg_out_mov (s
, TCG_TYPE_I64
, data_reg
, 3);
704 label2_ptr
= s
->code_ptr
;
707 /* label1: fast path */
709 reloc_pc14 (label1_ptr
, (tcg_target_long
) s
->code_ptr
);
712 /* r0 now contains &env->tlb_table[mem_index][index].addr_read */
716 | (offsetof (CPUTLBEntry
, addend
)
717 - offsetof (CPUTLBEntry
, addr_read
))
719 /* r0 = env->tlb_table[mem_index][index].addend */
720 tcg_out32 (s
, ADD
| RT (r0
) | RA (r0
) | RB (addr_reg
));
721 /* r0 = env->tlb_table[mem_index][index].addend + addr */
723 #else /* !CONFIG_SOFTMMU */
724 #if TARGET_LONG_BITS == 32
725 tcg_out_rld (s
, RLDICL
, addr_reg
, addr_reg
, 0, 32);
729 rbase
= GUEST_BASE
? TCG_GUEST_BASE_REG
: 0;
732 #ifdef TARGET_WORDS_BIGENDIAN
740 tcg_out32 (s
, LBZX
| TAB (data_reg
, rbase
, r0
));
743 tcg_out32 (s
, LBZX
| TAB (data_reg
, rbase
, r0
));
744 tcg_out32 (s
, EXTSB
| RA (data_reg
) | RS (data_reg
));
748 tcg_out32 (s
, LHBRX
| TAB (data_reg
, rbase
, r0
));
750 tcg_out32 (s
, LHZX
| TAB (data_reg
, rbase
, r0
));
754 tcg_out32 (s
, LHBRX
| TAB (data_reg
, rbase
, r0
));
755 tcg_out32 (s
, EXTSH
| RA (data_reg
) | RS (data_reg
));
757 else tcg_out32 (s
, LHAX
| TAB (data_reg
, rbase
, r0
));
761 tcg_out32 (s
, LWBRX
| TAB (data_reg
, rbase
, r0
));
763 tcg_out32 (s
, LWZX
| TAB (data_reg
, rbase
, r0
));
767 tcg_out32 (s
, LWBRX
| TAB (data_reg
, rbase
, r0
));
768 tcg_out32 (s
, EXTSW
| RA (data_reg
) | RS (data_reg
));
770 else tcg_out32 (s
, LWAX
| TAB (data_reg
, rbase
, r0
));
773 #ifdef CONFIG_USE_GUEST_BASE
775 tcg_out32 (s
, ADDI
| RT (r1
) | RA (r0
) | 4);
776 tcg_out32 (s
, LWBRX
| TAB (data_reg
, rbase
, r0
));
777 tcg_out32 (s
, LWBRX
| TAB ( r1
, rbase
, r1
));
778 tcg_out_rld (s
, RLDIMI
, data_reg
, r1
, 32, 0);
780 else tcg_out32 (s
, LDX
| TAB (data_reg
, rbase
, r0
));
783 tcg_out_movi32 (s
, 0, 4);
784 tcg_out32 (s
, LWBRX
| RT (data_reg
) | RB (r0
));
785 tcg_out32 (s
, LWBRX
| RT ( r1
) | RA (r0
));
786 tcg_out_rld (s
, RLDIMI
, data_reg
, r1
, 32, 0);
788 else tcg_out32 (s
, LD
| RT (data_reg
) | RA (r0
));
793 #ifdef CONFIG_SOFTMMU
794 reloc_pc24 (label2_ptr
, (tcg_target_long
) s
->code_ptr
);
798 static void tcg_out_qemu_st (TCGContext
*s
, const TCGArg
*args
, int opc
)
800 int addr_reg
, r0
, r1
, rbase
, data_reg
, bswap
;
801 #ifdef CONFIG_SOFTMMU
803 void *label1_ptr
, *label2_ptr
;
809 #ifdef CONFIG_SOFTMMU
817 tcg_out_tlb_read (s
, r0
, r1
, r2
, addr_reg
, opc
,
818 offsetof (CPUArchState
, tlb_table
[mem_index
][0].addr_write
));
820 tcg_out32 (s
, CMP
| BF (7) | RA (r2
) | RB (r1
) | CMP_L
);
822 label1_ptr
= s
->code_ptr
;
824 tcg_out32 (s
, BC
| BI (7, CR_EQ
) | BO_COND_TRUE
);
828 tcg_out_mov (s
, TCG_TYPE_I64
, 3, addr_reg
);
829 tcg_out_rld (s
, RLDICL
, 4, data_reg
, 0, 64 - (1 << (3 + opc
)));
830 tcg_out_movi (s
, TCG_TYPE_I64
, 5, mem_index
);
832 #ifdef CONFIG_TCG_PASS_AREG0
833 /* XXX/FIXME: suboptimal */
834 tcg_out_mov(s
, TCG_TYPE_I32
, tcg_target_call_iarg_regs
[3],
835 tcg_target_call_iarg_regs
[2]);
836 tcg_out_mov(s
, TCG_TYPE_I64
, tcg_target_call_iarg_regs
[2],
837 tcg_target_call_iarg_regs
[1]);
838 tcg_out_mov(s
, TCG_TYPE_TL
, tcg_target_call_iarg_regs
[1],
839 tcg_target_call_iarg_regs
[0]);
840 tcg_out_mov(s
, TCG_TYPE_PTR
, tcg_target_call_iarg_regs
[0],
843 tcg_out_call (s
, (tcg_target_long
) qemu_st_helpers
[opc
], 1);
845 label2_ptr
= s
->code_ptr
;
848 /* label1: fast path */
850 reloc_pc14 (label1_ptr
, (tcg_target_long
) s
->code_ptr
);
856 | (offsetof (CPUTLBEntry
, addend
)
857 - offsetof (CPUTLBEntry
, addr_write
))
859 /* r0 = env->tlb_table[mem_index][index].addend */
860 tcg_out32 (s
, ADD
| RT (r0
) | RA (r0
) | RB (addr_reg
));
861 /* r0 = env->tlb_table[mem_index][index].addend + addr */
863 #else /* !CONFIG_SOFTMMU */
864 #if TARGET_LONG_BITS == 32
865 tcg_out_rld (s
, RLDICL
, addr_reg
, addr_reg
, 0, 32);
869 rbase
= GUEST_BASE
? TCG_GUEST_BASE_REG
: 0;
872 #ifdef TARGET_WORDS_BIGENDIAN
879 tcg_out32 (s
, STBX
| SAB (data_reg
, rbase
, r0
));
883 tcg_out32 (s
, STHBRX
| SAB (data_reg
, rbase
, r0
));
885 tcg_out32 (s
, STHX
| SAB (data_reg
, rbase
, r0
));
889 tcg_out32 (s
, STWBRX
| SAB (data_reg
, rbase
, r0
));
891 tcg_out32 (s
, STWX
| SAB (data_reg
, rbase
, r0
));
895 tcg_out32 (s
, STWBRX
| SAB (data_reg
, rbase
, r0
));
896 tcg_out32 (s
, ADDI
| RT (r1
) | RA (r0
) | 4);
897 tcg_out_rld (s
, RLDICL
, 0, data_reg
, 32, 0);
898 tcg_out32 (s
, STWBRX
| SAB (0, rbase
, r1
));
900 else tcg_out32 (s
, STDX
| SAB (data_reg
, rbase
, r0
));
904 #ifdef CONFIG_SOFTMMU
905 reloc_pc24 (label2_ptr
, (tcg_target_long
) s
->code_ptr
);
909 static void tcg_target_qemu_prologue (TCGContext
*s
)
920 + 8 /* compiler doubleword */
921 + 8 /* link editor doubleword */
922 + 8 /* TOC save area */
923 + TCG_STATIC_CALL_ARGS_SIZE
924 + ARRAY_SIZE (tcg_target_callee_save_regs
) * 8
925 + CPU_TEMP_BUF_NLONGS
* sizeof(long)
927 frame_size
= (frame_size
+ 15) & ~15;
929 tcg_set_frame(s
, TCG_REG_CALL_STACK
, frame_size
930 - CPU_TEMP_BUF_NLONGS
* sizeof(long),
931 CPU_TEMP_BUF_NLONGS
* sizeof(long));
934 /* First emit adhoc function descriptor */
935 addr
= (uint64_t) s
->code_ptr
+ 24;
936 tcg_out32 (s
, addr
>> 32); tcg_out32 (s
, addr
); /* entry point */
937 s
->code_ptr
+= 16; /* skip TOC and environment pointer */
941 tcg_out32 (s
, MFSPR
| RT (0) | LR
);
942 tcg_out32 (s
, STDU
| RS (1) | RA (1) | (-frame_size
& 0xffff));
943 for (i
= 0; i
< ARRAY_SIZE (tcg_target_callee_save_regs
); ++i
)
945 | RS (tcg_target_callee_save_regs
[i
])
947 | (i
* 8 + 48 + TCG_STATIC_CALL_ARGS_SIZE
)
950 tcg_out32 (s
, STD
| RS (0) | RA (1) | (frame_size
+ 16));
952 #ifdef CONFIG_USE_GUEST_BASE
954 tcg_out_movi (s
, TCG_TYPE_I64
, TCG_GUEST_BASE_REG
, GUEST_BASE
);
955 tcg_regset_set_reg(s
->reserved_regs
, TCG_GUEST_BASE_REG
);
959 tcg_out_mov (s
, TCG_TYPE_PTR
, TCG_AREG0
, tcg_target_call_iarg_regs
[0]);
960 tcg_out32 (s
, MTSPR
| RS (tcg_target_call_iarg_regs
[1]) | CTR
);
961 tcg_out32 (s
, BCCTR
| BO_ALWAYS
);
964 tb_ret_addr
= s
->code_ptr
;
966 for (i
= 0; i
< ARRAY_SIZE (tcg_target_callee_save_regs
); ++i
)
968 | RT (tcg_target_callee_save_regs
[i
])
970 | (i
* 8 + 48 + TCG_STATIC_CALL_ARGS_SIZE
)
973 tcg_out32 (s
, LD
| RT (0) | RA (1) | (frame_size
+ 16));
974 tcg_out32 (s
, MTSPR
| RS (0) | LR
);
975 tcg_out32 (s
, ADDI
| RT (1) | RA (1) | frame_size
);
976 tcg_out32 (s
, BCLR
| BO_ALWAYS
);
979 static void tcg_out_ld (TCGContext
*s
, TCGType type
, TCGReg ret
, TCGReg arg1
,
980 tcg_target_long arg2
)
982 if (type
== TCG_TYPE_I32
)
983 tcg_out_ldst (s
, ret
, arg1
, arg2
, LWZ
, LWZX
);
985 tcg_out_ldsta (s
, ret
, arg1
, arg2
, LD
, LDX
);
988 static void tcg_out_st (TCGContext
*s
, TCGType type
, TCGReg arg
, TCGReg arg1
,
989 tcg_target_long arg2
)
991 if (type
== TCG_TYPE_I32
)
992 tcg_out_ldst (s
, arg
, arg1
, arg2
, STW
, STWX
);
994 tcg_out_ldsta (s
, arg
, arg1
, arg2
, STD
, STDX
);
997 static void ppc_addi32 (TCGContext
*s
, int rt
, int ra
, tcg_target_long si
)
1002 if (si
== (int16_t) si
)
1003 tcg_out32 (s
, ADDI
| RT (rt
) | RA (ra
) | (si
& 0xffff));
1005 uint16_t h
= ((si
>> 16) & 0xffff) + ((uint16_t) si
>> 15);
1006 tcg_out32 (s
, ADDIS
| RT (rt
) | RA (ra
) | h
);
1007 tcg_out32 (s
, ADDI
| RT (rt
) | RA (rt
) | (si
& 0xffff));
1011 static void ppc_addi64 (TCGContext
*s
, int rt
, int ra
, tcg_target_long si
)
1013 /* XXX: suboptimal */
1014 if (si
== (int16_t) si
1015 || ((((uint64_t) si
>> 31) == 0) && (si
& 0x8000) == 0))
1016 ppc_addi32 (s
, rt
, ra
, si
);
1018 tcg_out_movi (s
, TCG_TYPE_I64
, 0, si
);
1019 tcg_out32 (s
, ADD
| RT (rt
) | RA (ra
));
1023 static void tcg_out_cmp (TCGContext
*s
, int cond
, TCGArg arg1
, TCGArg arg2
,
1024 int const_arg2
, int cr
, int arch64
)
1033 if ((int16_t) arg2
== arg2
) {
1038 else if ((uint16_t) arg2
== arg2
) {
1053 if ((int16_t) arg2
== arg2
) {
1068 if ((uint16_t) arg2
== arg2
) {
1081 op
|= BF (cr
) | (arch64
<< 21);
1084 tcg_out32 (s
, op
| RA (arg1
) | (arg2
& 0xffff));
1087 tcg_out_movi (s
, TCG_TYPE_I64
, 0, arg2
);
1088 tcg_out32 (s
, op
| RA (arg1
) | RB (0));
1091 tcg_out32 (s
, op
| RA (arg1
) | RB (arg2
));
1096 static void tcg_out_setcond (TCGContext
*s
, TCGType type
, TCGCond cond
,
1097 TCGArg arg0
, TCGArg arg1
, TCGArg arg2
,
1110 if ((uint16_t) arg2
== arg2
) {
1111 tcg_out32 (s
, XORI
| RS (arg1
) | RA (0) | arg2
);
1114 tcg_out_movi (s
, type
, 0, arg2
);
1115 tcg_out32 (s
, XOR
| SAB (arg1
, 0, 0));
1121 tcg_out32 (s
, XOR
| SAB (arg1
, 0, arg2
));
1124 if (type
== TCG_TYPE_I64
) {
1125 tcg_out32 (s
, CNTLZD
| RS (arg
) | RA (0));
1126 tcg_out_rld (s
, RLDICL
, arg0
, 0, 58, 6);
1129 tcg_out32 (s
, CNTLZW
| RS (arg
) | RA (0));
1130 tcg_out32 (s
, (RLWINM
1148 if ((uint16_t) arg2
== arg2
) {
1149 tcg_out32 (s
, XORI
| RS (arg1
) | RA (0) | arg2
);
1152 tcg_out_movi (s
, type
, 0, arg2
);
1153 tcg_out32 (s
, XOR
| SAB (arg1
, 0, 0));
1159 tcg_out32 (s
, XOR
| SAB (arg1
, 0, arg2
));
1162 if (arg
== arg1
&& arg1
== arg0
) {
1163 tcg_out32 (s
, ADDIC
| RT (0) | RA (arg
) | 0xffff);
1164 tcg_out32 (s
, SUBFE
| TAB (arg0
, 0, arg
));
1167 tcg_out32 (s
, ADDIC
| RT (arg0
) | RA (arg
) | 0xffff);
1168 tcg_out32 (s
, SUBFE
| TAB (arg0
, arg0
, arg
));
1187 crop
= CRNOR
| BT (7, CR_EQ
) | BA (7, CR_LT
) | BB (7, CR_LT
);
1193 crop
= CRNOR
| BT (7, CR_EQ
) | BA (7, CR_GT
) | BB (7, CR_GT
);
1195 tcg_out_cmp (s
, cond
, arg1
, arg2
, const_arg2
, 7, type
== TCG_TYPE_I64
);
1196 if (crop
) tcg_out32 (s
, crop
);
1197 tcg_out32 (s
, MFCR
| RT (0));
1198 tcg_out32 (s
, (RLWINM
1213 static void tcg_out_bc (TCGContext
*s
, int bc
, int label_index
)
1215 TCGLabel
*l
= &s
->labels
[label_index
];
1218 tcg_out32 (s
, bc
| reloc_pc14_val (s
->code_ptr
, l
->u
.value
));
1220 uint16_t val
= *(uint16_t *) &s
->code_ptr
[2];
1222 /* Thanks to Andrzej Zaborowski */
1223 tcg_out32 (s
, bc
| (val
& 0xfffc));
1224 tcg_out_reloc (s
, s
->code_ptr
- 4, R_PPC_REL14
, label_index
, 0);
1228 static void tcg_out_brcond (TCGContext
*s
, TCGCond cond
,
1229 TCGArg arg1
, TCGArg arg2
, int const_arg2
,
1230 int label_index
, int arch64
)
1232 tcg_out_cmp (s
, cond
, arg1
, arg2
, const_arg2
, 7, arch64
);
1233 tcg_out_bc (s
, tcg_to_bc
[cond
], label_index
);
1236 void ppc_tb_set_jmp_target (unsigned long jmp_addr
, unsigned long addr
)
1239 unsigned long patch_size
;
1241 s
.code_ptr
= (uint8_t *) jmp_addr
;
1242 tcg_out_b (&s
, 0, addr
);
1243 patch_size
= s
.code_ptr
- (uint8_t *) jmp_addr
;
1244 flush_icache_range (jmp_addr
, jmp_addr
+ patch_size
);
1247 static void tcg_out_op (TCGContext
*s
, TCGOpcode opc
, const TCGArg
*args
,
1248 const int *const_args
)
1253 case INDEX_op_exit_tb
:
1254 tcg_out_movi (s
, TCG_TYPE_I64
, TCG_REG_R3
, args
[0]);
1255 tcg_out_b (s
, 0, (tcg_target_long
) tb_ret_addr
);
1257 case INDEX_op_goto_tb
:
1258 if (s
->tb_jmp_offset
) {
1259 /* direct jump method */
1261 s
->tb_jmp_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
1267 s
->tb_next_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
1271 TCGLabel
*l
= &s
->labels
[args
[0]];
1274 tcg_out_b (s
, 0, l
->u
.value
);
1277 uint32_t val
= *(uint32_t *) s
->code_ptr
;
1279 /* Thanks to Andrzej Zaborowski */
1280 tcg_out32 (s
, B
| (val
& 0x3fffffc));
1281 tcg_out_reloc (s
, s
->code_ptr
- 4, R_PPC_REL24
, args
[0], 0);
1286 tcg_out_call (s
, args
[0], const_args
[0]);
1289 if (const_args
[0]) {
1290 tcg_out_b (s
, 0, args
[0]);
1293 tcg_out32 (s
, MTSPR
| RS (args
[0]) | CTR
);
1294 tcg_out32 (s
, BCCTR
| BO_ALWAYS
);
1297 case INDEX_op_movi_i32
:
1298 tcg_out_movi (s
, TCG_TYPE_I32
, args
[0], args
[1]);
1300 case INDEX_op_movi_i64
:
1301 tcg_out_movi (s
, TCG_TYPE_I64
, args
[0], args
[1]);
1303 case INDEX_op_ld8u_i32
:
1304 case INDEX_op_ld8u_i64
:
1305 tcg_out_ldst (s
, args
[0], args
[1], args
[2], LBZ
, LBZX
);
1307 case INDEX_op_ld8s_i32
:
1308 case INDEX_op_ld8s_i64
:
1309 tcg_out_ldst (s
, args
[0], args
[1], args
[2], LBZ
, LBZX
);
1310 tcg_out32 (s
, EXTSB
| RS (args
[0]) | RA (args
[0]));
1312 case INDEX_op_ld16u_i32
:
1313 case INDEX_op_ld16u_i64
:
1314 tcg_out_ldst (s
, args
[0], args
[1], args
[2], LHZ
, LHZX
);
1316 case INDEX_op_ld16s_i32
:
1317 case INDEX_op_ld16s_i64
:
1318 tcg_out_ldst (s
, args
[0], args
[1], args
[2], LHA
, LHAX
);
1320 case INDEX_op_ld_i32
:
1321 case INDEX_op_ld32u_i64
:
1322 tcg_out_ldst (s
, args
[0], args
[1], args
[2], LWZ
, LWZX
);
1324 case INDEX_op_ld32s_i64
:
1325 tcg_out_ldsta (s
, args
[0], args
[1], args
[2], LWA
, LWAX
);
1327 case INDEX_op_ld_i64
:
1328 tcg_out_ldsta (s
, args
[0], args
[1], args
[2], LD
, LDX
);
1330 case INDEX_op_st8_i32
:
1331 case INDEX_op_st8_i64
:
1332 tcg_out_ldst (s
, args
[0], args
[1], args
[2], STB
, STBX
);
1334 case INDEX_op_st16_i32
:
1335 case INDEX_op_st16_i64
:
1336 tcg_out_ldst (s
, args
[0], args
[1], args
[2], STH
, STHX
);
1338 case INDEX_op_st_i32
:
1339 case INDEX_op_st32_i64
:
1340 tcg_out_ldst (s
, args
[0], args
[1], args
[2], STW
, STWX
);
1342 case INDEX_op_st_i64
:
1343 tcg_out_ldsta (s
, args
[0], args
[1], args
[2], STD
, STDX
);
1346 case INDEX_op_add_i32
:
1348 ppc_addi32 (s
, args
[0], args
[1], args
[2]);
1350 tcg_out32 (s
, ADD
| TAB (args
[0], args
[1], args
[2]));
1352 case INDEX_op_sub_i32
:
1354 ppc_addi32 (s
, args
[0], args
[1], -args
[2]);
1356 tcg_out32 (s
, SUBF
| TAB (args
[0], args
[2], args
[1]));
1359 case INDEX_op_and_i64
:
1360 case INDEX_op_and_i32
:
1361 if (const_args
[2]) {
1362 if ((args
[2] & 0xffff) == args
[2])
1363 tcg_out32 (s
, ANDI
| RS (args
[1]) | RA (args
[0]) | args
[2]);
1364 else if ((args
[2] & 0xffff0000) == args
[2])
1365 tcg_out32 (s
, ANDIS
| RS (args
[1]) | RA (args
[0])
1366 | ((args
[2] >> 16) & 0xffff));
1368 tcg_out_movi (s
, (opc
== INDEX_op_and_i32
1372 tcg_out32 (s
, AND
| SAB (args
[1], args
[0], 0));
1376 tcg_out32 (s
, AND
| SAB (args
[1], args
[0], args
[2]));
1378 case INDEX_op_or_i64
:
1379 case INDEX_op_or_i32
:
1380 if (const_args
[2]) {
1381 if (args
[2] & 0xffff) {
1382 tcg_out32 (s
, ORI
| RS (args
[1]) | RA (args
[0])
1383 | (args
[2] & 0xffff));
1385 tcg_out32 (s
, ORIS
| RS (args
[0]) | RA (args
[0])
1386 | ((args
[2] >> 16) & 0xffff));
1389 tcg_out32 (s
, ORIS
| RS (args
[1]) | RA (args
[0])
1390 | ((args
[2] >> 16) & 0xffff));
1394 tcg_out32 (s
, OR
| SAB (args
[1], args
[0], args
[2]));
1396 case INDEX_op_xor_i64
:
1397 case INDEX_op_xor_i32
:
1398 if (const_args
[2]) {
1399 if ((args
[2] & 0xffff) == args
[2])
1400 tcg_out32 (s
, XORI
| RS (args
[1]) | RA (args
[0])
1401 | (args
[2] & 0xffff));
1402 else if ((args
[2] & 0xffff0000) == args
[2])
1403 tcg_out32 (s
, XORIS
| RS (args
[1]) | RA (args
[0])
1404 | ((args
[2] >> 16) & 0xffff));
1406 tcg_out_movi (s
, (opc
== INDEX_op_and_i32
1410 tcg_out32 (s
, XOR
| SAB (args
[1], args
[0], 0));
1414 tcg_out32 (s
, XOR
| SAB (args
[1], args
[0], args
[2]));
1417 case INDEX_op_mul_i32
:
1418 if (const_args
[2]) {
1419 if (args
[2] == (int16_t) args
[2])
1420 tcg_out32 (s
, MULLI
| RT (args
[0]) | RA (args
[1])
1421 | (args
[2] & 0xffff));
1423 tcg_out_movi (s
, TCG_TYPE_I32
, 0, args
[2]);
1424 tcg_out32 (s
, MULLW
| TAB (args
[0], args
[1], 0));
1428 tcg_out32 (s
, MULLW
| TAB (args
[0], args
[1], args
[2]));
1431 case INDEX_op_div_i32
:
1432 tcg_out32 (s
, DIVW
| TAB (args
[0], args
[1], args
[2]));
1435 case INDEX_op_divu_i32
:
1436 tcg_out32 (s
, DIVWU
| TAB (args
[0], args
[1], args
[2]));
1439 case INDEX_op_rem_i32
:
1440 tcg_out32 (s
, DIVW
| TAB (0, args
[1], args
[2]));
1441 tcg_out32 (s
, MULLW
| TAB (0, 0, args
[2]));
1442 tcg_out32 (s
, SUBF
| TAB (args
[0], 0, args
[1]));
1445 case INDEX_op_remu_i32
:
1446 tcg_out32 (s
, DIVWU
| TAB (0, args
[1], args
[2]));
1447 tcg_out32 (s
, MULLW
| TAB (0, 0, args
[2]));
1448 tcg_out32 (s
, SUBF
| TAB (args
[0], 0, args
[1]));
1451 case INDEX_op_shl_i32
:
1452 if (const_args
[2]) {
1453 tcg_out32 (s
, (RLWINM
1463 tcg_out32 (s
, SLW
| SAB (args
[1], args
[0], args
[2]));
1465 case INDEX_op_shr_i32
:
1466 if (const_args
[2]) {
1467 tcg_out32 (s
, (RLWINM
1477 tcg_out32 (s
, SRW
| SAB (args
[1], args
[0], args
[2]));
1479 case INDEX_op_sar_i32
:
1481 tcg_out32 (s
, SRAWI
| RS (args
[1]) | RA (args
[0]) | SH (args
[2]));
1483 tcg_out32 (s
, SRAW
| SAB (args
[1], args
[0], args
[2]));
1486 case INDEX_op_brcond_i32
:
1487 tcg_out_brcond (s
, args
[2], args
[0], args
[1], const_args
[1], args
[3], 0);
1490 case INDEX_op_brcond_i64
:
1491 tcg_out_brcond (s
, args
[2], args
[0], args
[1], const_args
[1], args
[3], 1);
1494 case INDEX_op_neg_i32
:
1495 case INDEX_op_neg_i64
:
1496 tcg_out32 (s
, NEG
| RT (args
[0]) | RA (args
[1]));
1499 case INDEX_op_not_i32
:
1500 case INDEX_op_not_i64
:
1501 tcg_out32 (s
, NOR
| SAB (args
[1], args
[0], args
[1]));
1504 case INDEX_op_add_i64
:
1506 ppc_addi64 (s
, args
[0], args
[1], args
[2]);
1508 tcg_out32 (s
, ADD
| TAB (args
[0], args
[1], args
[2]));
1510 case INDEX_op_sub_i64
:
1512 ppc_addi64 (s
, args
[0], args
[1], -args
[2]);
1514 tcg_out32 (s
, SUBF
| TAB (args
[0], args
[2], args
[1]));
1517 case INDEX_op_shl_i64
:
1519 tcg_out_rld (s
, RLDICR
, args
[0], args
[1], args
[2], 63 - args
[2]);
1521 tcg_out32 (s
, SLD
| SAB (args
[1], args
[0], args
[2]));
1523 case INDEX_op_shr_i64
:
1525 tcg_out_rld (s
, RLDICL
, args
[0], args
[1], 64 - args
[2], args
[2]);
1527 tcg_out32 (s
, SRD
| SAB (args
[1], args
[0], args
[2]));
1529 case INDEX_op_sar_i64
:
1530 if (const_args
[2]) {
1531 int sh
= SH (args
[2] & 0x1f) | (((args
[2] >> 5) & 1) << 1);
1532 tcg_out32 (s
, SRADI
| RA (args
[0]) | RS (args
[1]) | sh
);
1535 tcg_out32 (s
, SRAD
| SAB (args
[1], args
[0], args
[2]));
1538 case INDEX_op_mul_i64
:
1539 tcg_out32 (s
, MULLD
| TAB (args
[0], args
[1], args
[2]));
1541 case INDEX_op_div_i64
:
1542 tcg_out32 (s
, DIVD
| TAB (args
[0], args
[1], args
[2]));
1544 case INDEX_op_divu_i64
:
1545 tcg_out32 (s
, DIVDU
| TAB (args
[0], args
[1], args
[2]));
1547 case INDEX_op_rem_i64
:
1548 tcg_out32 (s
, DIVD
| TAB (0, args
[1], args
[2]));
1549 tcg_out32 (s
, MULLD
| TAB (0, 0, args
[2]));
1550 tcg_out32 (s
, SUBF
| TAB (args
[0], 0, args
[1]));
1552 case INDEX_op_remu_i64
:
1553 tcg_out32 (s
, DIVDU
| TAB (0, args
[1], args
[2]));
1554 tcg_out32 (s
, MULLD
| TAB (0, 0, args
[2]));
1555 tcg_out32 (s
, SUBF
| TAB (args
[0], 0, args
[1]));
1558 case INDEX_op_qemu_ld8u
:
1559 tcg_out_qemu_ld (s
, args
, 0);
1561 case INDEX_op_qemu_ld8s
:
1562 tcg_out_qemu_ld (s
, args
, 0 | 4);
1564 case INDEX_op_qemu_ld16u
:
1565 tcg_out_qemu_ld (s
, args
, 1);
1567 case INDEX_op_qemu_ld16s
:
1568 tcg_out_qemu_ld (s
, args
, 1 | 4);
1570 case INDEX_op_qemu_ld32
:
1571 case INDEX_op_qemu_ld32u
:
1572 tcg_out_qemu_ld (s
, args
, 2);
1574 case INDEX_op_qemu_ld32s
:
1575 tcg_out_qemu_ld (s
, args
, 2 | 4);
1577 case INDEX_op_qemu_ld64
:
1578 tcg_out_qemu_ld (s
, args
, 3);
1580 case INDEX_op_qemu_st8
:
1581 tcg_out_qemu_st (s
, args
, 0);
1583 case INDEX_op_qemu_st16
:
1584 tcg_out_qemu_st (s
, args
, 1);
1586 case INDEX_op_qemu_st32
:
1587 tcg_out_qemu_st (s
, args
, 2);
1589 case INDEX_op_qemu_st64
:
1590 tcg_out_qemu_st (s
, args
, 3);
1593 case INDEX_op_ext8s_i32
:
1594 case INDEX_op_ext8s_i64
:
1597 case INDEX_op_ext16s_i32
:
1598 case INDEX_op_ext16s_i64
:
1601 case INDEX_op_ext32s_i64
:
1605 tcg_out32 (s
, c
| RS (args
[1]) | RA (args
[0]));
1608 case INDEX_op_ext32u_i64
:
1609 tcg_out_rld (s
, RLDICL
, args
[0], args
[1], 0, 32);
1612 case INDEX_op_setcond_i32
:
1613 tcg_out_setcond (s
, TCG_TYPE_I32
, args
[3], args
[0], args
[1], args
[2],
1616 case INDEX_op_setcond_i64
:
1617 tcg_out_setcond (s
, TCG_TYPE_I64
, args
[3], args
[0], args
[1], args
[2],
1622 tcg_dump_ops (s
, stderr
);
1627 static const TCGTargetOpDef ppc_op_defs
[] = {
1628 { INDEX_op_exit_tb
, { } },
1629 { INDEX_op_goto_tb
, { } },
1630 { INDEX_op_call
, { "ri" } },
1631 { INDEX_op_jmp
, { "ri" } },
1632 { INDEX_op_br
, { } },
1634 { INDEX_op_mov_i32
, { "r", "r" } },
1635 { INDEX_op_mov_i64
, { "r", "r" } },
1636 { INDEX_op_movi_i32
, { "r" } },
1637 { INDEX_op_movi_i64
, { "r" } },
1639 { INDEX_op_ld8u_i32
, { "r", "r" } },
1640 { INDEX_op_ld8s_i32
, { "r", "r" } },
1641 { INDEX_op_ld16u_i32
, { "r", "r" } },
1642 { INDEX_op_ld16s_i32
, { "r", "r" } },
1643 { INDEX_op_ld_i32
, { "r", "r" } },
1644 { INDEX_op_ld_i64
, { "r", "r" } },
1645 { INDEX_op_st8_i32
, { "r", "r" } },
1646 { INDEX_op_st8_i64
, { "r", "r" } },
1647 { INDEX_op_st16_i32
, { "r", "r" } },
1648 { INDEX_op_st16_i64
, { "r", "r" } },
1649 { INDEX_op_st_i32
, { "r", "r" } },
1650 { INDEX_op_st_i64
, { "r", "r" } },
1651 { INDEX_op_st32_i64
, { "r", "r" } },
1653 { INDEX_op_ld8u_i64
, { "r", "r" } },
1654 { INDEX_op_ld8s_i64
, { "r", "r" } },
1655 { INDEX_op_ld16u_i64
, { "r", "r" } },
1656 { INDEX_op_ld16s_i64
, { "r", "r" } },
1657 { INDEX_op_ld32u_i64
, { "r", "r" } },
1658 { INDEX_op_ld32s_i64
, { "r", "r" } },
1659 { INDEX_op_ld_i64
, { "r", "r" } },
1661 { INDEX_op_add_i32
, { "r", "r", "ri" } },
1662 { INDEX_op_mul_i32
, { "r", "r", "ri" } },
1663 { INDEX_op_div_i32
, { "r", "r", "r" } },
1664 { INDEX_op_divu_i32
, { "r", "r", "r" } },
1665 { INDEX_op_rem_i32
, { "r", "r", "r" } },
1666 { INDEX_op_remu_i32
, { "r", "r", "r" } },
1667 { INDEX_op_sub_i32
, { "r", "r", "ri" } },
1668 { INDEX_op_and_i32
, { "r", "r", "ri" } },
1669 { INDEX_op_or_i32
, { "r", "r", "ri" } },
1670 { INDEX_op_xor_i32
, { "r", "r", "ri" } },
1672 { INDEX_op_shl_i32
, { "r", "r", "ri" } },
1673 { INDEX_op_shr_i32
, { "r", "r", "ri" } },
1674 { INDEX_op_sar_i32
, { "r", "r", "ri" } },
1676 { INDEX_op_brcond_i32
, { "r", "ri" } },
1677 { INDEX_op_brcond_i64
, { "r", "ri" } },
1679 { INDEX_op_neg_i32
, { "r", "r" } },
1680 { INDEX_op_not_i32
, { "r", "r" } },
1682 { INDEX_op_add_i64
, { "r", "r", "ri" } },
1683 { INDEX_op_sub_i64
, { "r", "r", "ri" } },
1684 { INDEX_op_and_i64
, { "r", "r", "rZ" } },
1685 { INDEX_op_or_i64
, { "r", "r", "rZ" } },
1686 { INDEX_op_xor_i64
, { "r", "r", "rZ" } },
1688 { INDEX_op_shl_i64
, { "r", "r", "ri" } },
1689 { INDEX_op_shr_i64
, { "r", "r", "ri" } },
1690 { INDEX_op_sar_i64
, { "r", "r", "ri" } },
1692 { INDEX_op_mul_i64
, { "r", "r", "r" } },
1693 { INDEX_op_div_i64
, { "r", "r", "r" } },
1694 { INDEX_op_divu_i64
, { "r", "r", "r" } },
1695 { INDEX_op_rem_i64
, { "r", "r", "r" } },
1696 { INDEX_op_remu_i64
, { "r", "r", "r" } },
1698 { INDEX_op_neg_i64
, { "r", "r" } },
1699 { INDEX_op_not_i64
, { "r", "r" } },
1701 { INDEX_op_qemu_ld8u
, { "r", "L" } },
1702 { INDEX_op_qemu_ld8s
, { "r", "L" } },
1703 { INDEX_op_qemu_ld16u
, { "r", "L" } },
1704 { INDEX_op_qemu_ld16s
, { "r", "L" } },
1705 { INDEX_op_qemu_ld32
, { "r", "L" } },
1706 { INDEX_op_qemu_ld32u
, { "r", "L" } },
1707 { INDEX_op_qemu_ld32s
, { "r", "L" } },
1708 { INDEX_op_qemu_ld64
, { "r", "L" } },
1710 { INDEX_op_qemu_st8
, { "S", "S" } },
1711 { INDEX_op_qemu_st16
, { "S", "S" } },
1712 { INDEX_op_qemu_st32
, { "S", "S" } },
1713 { INDEX_op_qemu_st64
, { "S", "S" } },
1715 { INDEX_op_ext8s_i32
, { "r", "r" } },
1716 { INDEX_op_ext16s_i32
, { "r", "r" } },
1717 { INDEX_op_ext8s_i64
, { "r", "r" } },
1718 { INDEX_op_ext16s_i64
, { "r", "r" } },
1719 { INDEX_op_ext32s_i64
, { "r", "r" } },
1720 { INDEX_op_ext32u_i64
, { "r", "r" } },
1722 { INDEX_op_setcond_i32
, { "r", "r", "ri" } },
1723 { INDEX_op_setcond_i64
, { "r", "r", "ri" } },
1728 static void tcg_target_init (TCGContext
*s
)
1730 tcg_regset_set32 (tcg_target_available_regs
[TCG_TYPE_I32
], 0, 0xffffffff);
1731 tcg_regset_set32 (tcg_target_available_regs
[TCG_TYPE_I64
], 0, 0xffffffff);
1732 tcg_regset_set32 (tcg_target_call_clobber_regs
, 0,
1744 (1 << TCG_REG_R10
) |
1745 (1 << TCG_REG_R11
) |
1749 tcg_regset_clear (s
->reserved_regs
);
1750 tcg_regset_set_reg (s
->reserved_regs
, TCG_REG_R0
);
1751 tcg_regset_set_reg (s
->reserved_regs
, TCG_REG_R1
);
1753 tcg_regset_set_reg (s
->reserved_regs
, TCG_REG_R2
);
1755 tcg_regset_set_reg (s
->reserved_regs
, TCG_REG_R13
);
1757 tcg_add_target_add_op_defs (ppc_op_defs
);