2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 static const char * const tcg_target_reg_names
[TCG_TARGET_NB_REGS
] = {
60 static const int tcg_target_reg_alloc_order
[] = {
76 static const int tcg_target_call_iarg_regs
[6] = {
85 static const int tcg_target_call_oarg_regs
[2] = {
90 static void patch_reloc(uint8_t *code_ptr
, int type
,
91 tcg_target_long value
)
95 if (value
!= (uint32_t)value
)
97 *(uint32_t *)code_ptr
= value
;
104 /* maximum number of register used for input function arguments */
105 static inline int tcg_target_get_call_iarg_regs_count(int flags
)
110 /* parse target specific constraints */
111 static int target_parse_constraint(TCGArgConstraint
*ct
, const char **pct_str
)
118 case 'L': /* qemu_ld/st constraint */
119 ct
->ct
|= TCG_CT_REG
;
120 tcg_regset_set32(ct
->u
.regs
, 0, 0xffffffff);
123 ct
->ct
|= TCG_CT_CONST_S11
;
126 ct
->ct
|= TCG_CT_CONST_S13
;
136 #define ABS(x) ((x) < 0? -(x) : (x))
137 /* test if a constant matches the constraint */
138 static inline int tcg_target_const_match(tcg_target_long val
,
139 const TCGArgConstraint
*arg_ct
)
144 if (ct
& TCG_CT_CONST
)
146 else if ((ct
& TCG_CT_CONST_S11
) && ABS(val
) == (ABS(val
) & 0x3ff))
148 else if ((ct
& TCG_CT_CONST_S13
) && ABS(val
) == (ABS(val
) & 0xfff))
154 #define INSN_OP(x) ((x) << 30)
155 #define INSN_OP2(x) ((x) << 22)
156 #define INSN_OP3(x) ((x) << 19)
157 #define INSN_OPF(x) ((x) << 5)
158 #define INSN_RD(x) ((x) << 25)
159 #define INSN_RS1(x) ((x) << 14)
160 #define INSN_RS2(x) (x)
162 #define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff))
163 #define INSN_OFF22(x) (((x) >> 2) & 0x3fffff)
165 #define INSN_COND(x, a) (((x) << 25) | ((a) << 29))
167 #define BA (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2))
169 #define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00))
170 #define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01))
171 #define ARITH_OR (INSN_OP(2) | INSN_OP3(0x02))
172 #define ARITH_XOR (INSN_OP(2) | INSN_OP3(0x03))
173 #define ARITH_SUB (INSN_OP(2) | INSN_OP3(0x08))
174 #define ARITH_ADDX (INSN_OP(2) | INSN_OP3(0x10))
175 #define ARITH_SUBX (INSN_OP(2) | INSN_OP3(0x0c))
176 #define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a))
177 #define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e))
178 #define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f))
179 #define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09))
180 #define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d))
181 #define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d))
183 #define SHIFT_SLL (INSN_OP(2) | INSN_OP3(0x25))
184 #define SHIFT_SRL (INSN_OP(2) | INSN_OP3(0x26))
185 #define SHIFT_SRA (INSN_OP(2) | INSN_OP3(0x27))
187 #define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12))
188 #define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12))
189 #define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12))
191 #define WRY (INSN_OP(2) | INSN_OP3(0x30))
192 #define JMPL (INSN_OP(2) | INSN_OP3(0x38))
193 #define SAVE (INSN_OP(2) | INSN_OP3(0x3c))
194 #define RESTORE (INSN_OP(2) | INSN_OP3(0x3d))
195 #define SETHI (INSN_OP(0) | INSN_OP2(0x4))
196 #define CALL INSN_OP(1)
197 #define LDUB (INSN_OP(3) | INSN_OP3(0x01))
198 #define LDSB (INSN_OP(3) | INSN_OP3(0x09))
199 #define LDUH (INSN_OP(3) | INSN_OP3(0x02))
200 #define LDSH (INSN_OP(3) | INSN_OP3(0x0a))
201 #define LDUW (INSN_OP(3) | INSN_OP3(0x00))
202 #define LDSW (INSN_OP(3) | INSN_OP3(0x08))
203 #define LDX (INSN_OP(3) | INSN_OP3(0x0b))
204 #define STB (INSN_OP(3) | INSN_OP3(0x05))
205 #define STH (INSN_OP(3) | INSN_OP3(0x06))
206 #define STW (INSN_OP(3) | INSN_OP3(0x04))
207 #define STX (INSN_OP(3) | INSN_OP3(0x0e))
209 static inline void tcg_out_mov(TCGContext
*s
, int ret
, int arg
)
211 tcg_out32(s
, ARITH_OR
| INSN_RD(ret
) | INSN_RS1(arg
) |
212 INSN_RS2(TCG_REG_G0
));
215 static inline void tcg_out_movi(TCGContext
*s
, TCGType type
,
216 int ret
, tcg_target_long arg
)
218 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
219 if (arg
!= (arg
& 0xffffffff))
220 fprintf(stderr
, "unimplemented %s with constant %ld\n", __func__
, arg
);
222 if (arg
== (arg
& 0xfff))
223 tcg_out32(s
, ARITH_OR
| INSN_RD(ret
) | INSN_RS1(TCG_REG_G0
) |
226 tcg_out32(s
, SETHI
| INSN_RD(ret
) | ((arg
& 0xfffffc00) >> 10));
228 tcg_out32(s
, ARITH_OR
| INSN_RD(ret
) | INSN_RS1(ret
) |
229 INSN_IMM13(arg
& 0x3ff));
233 static inline void tcg_out_ld_raw(TCGContext
*s
, int ret
,
236 tcg_out32(s
, SETHI
| INSN_RD(ret
) | (((uint32_t)arg
& 0xfffffc00) >> 10));
237 tcg_out32(s
, LDUW
| INSN_RD(ret
) | INSN_RS1(ret
) |
238 INSN_IMM13(arg
& 0x3ff));
241 static inline void tcg_out_ld_ptr(TCGContext
*s
, int ret
,
244 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
245 if (arg
!= (arg
& 0xffffffff))
246 fprintf(stderr
, "unimplemented %s with offset %ld\n", __func__
, arg
);
247 if (arg
!= (arg
& 0xfff))
248 tcg_out32(s
, SETHI
| INSN_RD(ret
) | (((uint32_t)arg
& 0xfffffc00) >> 10));
249 tcg_out32(s
, LDX
| INSN_RD(ret
) | INSN_RS1(ret
) |
250 INSN_IMM13(arg
& 0x3ff));
252 tcg_out_ld_raw(s
, ret
, arg
);
256 static inline void tcg_out_ldst(TCGContext
*s
, int ret
, int addr
, int offset
, int op
)
258 if (offset
== (offset
& 0xfff))
259 tcg_out32(s
, op
| INSN_RD(ret
) | INSN_RS1(addr
) |
262 fprintf(stderr
, "unimplemented %s with offset %d\n", __func__
, offset
);
265 static inline void tcg_out_ld(TCGContext
*s
, int ret
,
266 int arg1
, tcg_target_long arg2
)
268 fprintf(stderr
, "unimplemented %s\n", __func__
);
271 static inline void tcg_out_st(TCGContext
*s
, int arg
,
272 int arg1
, tcg_target_long arg2
)
274 fprintf(stderr
, "unimplemented %s\n", __func__
);
277 static inline void tcg_out_arith(TCGContext
*s
, int rd
, int rs1
, int rs2
,
280 tcg_out32(s
, op
| INSN_RD(rd
) | INSN_RS1(rs1
) |
284 static inline void tcg_out_arithi(TCGContext
*s
, int rd
, int rs1
, int offset
,
287 tcg_out32(s
, op
| INSN_RD(rd
) | INSN_RS1(rs1
) |
291 static inline void tcg_out_sety(TCGContext
*s
, tcg_target_long val
)
293 if (val
== 0 || val
== -1)
294 tcg_out32(s
, WRY
| INSN_IMM13(val
));
296 fprintf(stderr
, "unimplemented sety %ld\n", (long)val
);
299 static inline void tcg_out_addi(TCGContext
*s
, int reg
, tcg_target_long val
)
302 if (val
== (val
& 0xfff))
303 tcg_out_arithi(s
, reg
, reg
, val
, ARITH_ADD
);
305 fprintf(stderr
, "unimplemented addi %ld\n", (long)val
);
309 static inline void tcg_out_nop(TCGContext
*s
)
311 tcg_out32(s
, SETHI
| INSN_RD(TCG_REG_G0
) | 0);
314 static inline void tcg_target_prologue(TCGContext
*s
)
316 tcg_out32(s
, SAVE
| INSN_RD(TCG_REG_O6
) | INSN_RS1(TCG_REG_O6
) |
317 INSN_IMM13(-TCG_TARGET_STACK_MINFRAME
));
320 static inline void tcg_out_op(TCGContext
*s
, int opc
, const TCGArg
*args
,
321 const int *const_args
)
326 case INDEX_op_exit_tb
:
327 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_I0
, args
[0]);
328 tcg_out32(s
, JMPL
| INSN_RD(TCG_REG_G0
) | INSN_RS1(TCG_REG_I7
) |
330 tcg_out32(s
, RESTORE
| INSN_RD(TCG_REG_G0
) | INSN_RS1(TCG_REG_G0
) |
331 INSN_RS2(TCG_REG_G0
));
333 case INDEX_op_goto_tb
:
334 if (s
->tb_jmp_offset
) {
335 /* direct jump method */
336 if (ABS(args
[0] - (unsigned long)s
->code_ptr
) ==
337 (ABS(args
[0] - (unsigned long)s
->code_ptr
) & 0x1fffff)) {
339 INSN_OFF22(args
[0] - (unsigned long)s
->code_ptr
));
341 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_I5
, args
[0]);
342 tcg_out32(s
, JMPL
| INSN_RD(TCG_REG_G0
) | INSN_RS1(TCG_REG_I5
) |
343 INSN_RS2(TCG_REG_G0
));
345 s
->tb_jmp_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
347 /* indirect jump method */
348 tcg_out_ld_ptr(s
, TCG_REG_I5
, (tcg_target_long
)(s
->tb_next
+ args
[0]));
349 tcg_out32(s
, JMPL
| INSN_RD(TCG_REG_G0
) | INSN_RS1(TCG_REG_I5
) |
350 INSN_RS2(TCG_REG_G0
));
353 s
->tb_next_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
357 tcg_out32(s
, CALL
| ((((tcg_target_ulong
)args
[0]
358 - (tcg_target_ulong
)s
->code_ptr
) >> 2)
362 tcg_out_ld_ptr(s
, TCG_REG_O7
, (tcg_target_long
)(s
->tb_next
+ args
[0]));
363 tcg_out32(s
, JMPL
| INSN_RD(TCG_REG_O7
) | INSN_RS1(TCG_REG_O7
) |
364 INSN_RS2(TCG_REG_G0
));
369 fprintf(stderr
, "unimplemented jmp\n");
372 fprintf(stderr
, "unimplemented br\n");
374 case INDEX_op_movi_i32
:
375 tcg_out_movi(s
, TCG_TYPE_I32
, args
[0], (uint32_t)args
[1]);
378 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
379 #define OP_32_64(x) \
380 glue(glue(case INDEX_op_, x), _i32:) \
381 glue(glue(case INDEX_op_, x), _i64:)
383 #define OP_32_64(x) \
384 glue(glue(case INDEX_op_, x), _i32:)
387 tcg_out_ldst(s
, args
[0], args
[1], args
[2], LDUB
);
390 tcg_out_ldst(s
, args
[0], args
[1], args
[2], LDSB
);
393 tcg_out_ldst(s
, args
[0], args
[1], args
[2], LDUH
);
396 tcg_out_ldst(s
, args
[0], args
[1], args
[2], LDSH
);
398 case INDEX_op_ld_i32
:
399 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
400 case INDEX_op_ld32u_i64
:
402 tcg_out_ldst(s
, args
[0], args
[1], args
[2], LDUW
);
405 tcg_out_ldst(s
, args
[0], args
[1], args
[2], STB
);
408 tcg_out_ldst(s
, args
[0], args
[1], args
[2], STH
);
410 case INDEX_op_st_i32
:
411 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
412 case INDEX_op_st32_i64
:
414 tcg_out_ldst(s
, args
[0], args
[1], args
[2], STW
);
431 case INDEX_op_shl_i32
:
434 case INDEX_op_shr_i32
:
437 case INDEX_op_sar_i32
:
440 case INDEX_op_mul_i32
:
443 case INDEX_op_div2_i32
:
444 #if defined(__sparc_v9__) || defined(__sparc_v8plus__)
452 case INDEX_op_divu2_i32
:
453 #if defined(__sparc_v9__) || defined(__sparc_v8plus__)
462 case INDEX_op_brcond_i32
:
463 fprintf(stderr
, "unimplemented brcond\n");
466 case INDEX_op_qemu_ld8u
:
467 fprintf(stderr
, "unimplemented qld\n");
469 case INDEX_op_qemu_ld8s
:
470 fprintf(stderr
, "unimplemented qld\n");
472 case INDEX_op_qemu_ld16u
:
473 fprintf(stderr
, "unimplemented qld\n");
475 case INDEX_op_qemu_ld16s
:
476 fprintf(stderr
, "unimplemented qld\n");
478 case INDEX_op_qemu_ld32u
:
479 fprintf(stderr
, "unimplemented qld\n");
481 case INDEX_op_qemu_ld32s
:
482 fprintf(stderr
, "unimplemented qld\n");
484 case INDEX_op_qemu_st8
:
485 fprintf(stderr
, "unimplemented qst\n");
487 case INDEX_op_qemu_st16
:
488 fprintf(stderr
, "unimplemented qst\n");
490 case INDEX_op_qemu_st32
:
491 fprintf(stderr
, "unimplemented qst\n");
494 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
495 case INDEX_op_movi_i64
:
496 tcg_out_movi(s
, TCG_TYPE_I64
, args
[0], args
[1]);
498 case INDEX_op_ld32s_i64
:
499 tcg_out_ldst(s
, args
[0], args
[1], args
[2], LDSW
);
501 case INDEX_op_ld_i64
:
502 tcg_out_ldst(s
, args
[0], args
[1], args
[2], LDX
);
504 case INDEX_op_st_i64
:
505 tcg_out_ldst(s
, args
[0], args
[1], args
[2], STX
);
507 case INDEX_op_shl_i64
:
510 case INDEX_op_shr_i64
:
513 case INDEX_op_sar_i64
:
516 case INDEX_op_mul_i64
:
519 case INDEX_op_div2_i64
:
522 case INDEX_op_divu2_i64
:
526 case INDEX_op_brcond_i64
:
527 fprintf(stderr
, "unimplemented brcond\n");
529 case INDEX_op_qemu_ld64
:
530 fprintf(stderr
, "unimplemented qld\n");
532 case INDEX_op_qemu_st64
:
533 fprintf(stderr
, "unimplemented qst\n");
539 tcg_out_arithi(s
, args
[0], args
[1], args
[2], c
);
541 tcg_out_arith(s
, args
[0], args
[1], args
[2], c
);
546 fprintf(stderr
, "unknown opcode 0x%x\n", opc
);
551 static const TCGTargetOpDef sparc_op_defs
[] = {
552 { INDEX_op_exit_tb
, { } },
553 { INDEX_op_goto_tb
, { } },
554 { INDEX_op_call
, { "ri" } },
555 { INDEX_op_jmp
, { "ri" } },
556 { INDEX_op_br
, { } },
558 { INDEX_op_mov_i32
, { "r", "r" } },
559 { INDEX_op_movi_i32
, { "r" } },
560 { INDEX_op_ld8u_i32
, { "r", "r" } },
561 { INDEX_op_ld8s_i32
, { "r", "r" } },
562 { INDEX_op_ld16u_i32
, { "r", "r" } },
563 { INDEX_op_ld16s_i32
, { "r", "r" } },
564 { INDEX_op_ld_i32
, { "r", "r" } },
565 { INDEX_op_st8_i32
, { "r", "r" } },
566 { INDEX_op_st16_i32
, { "r", "r" } },
567 { INDEX_op_st_i32
, { "r", "r" } },
569 { INDEX_op_add_i32
, { "r", "r", "rJ" } },
570 { INDEX_op_mul_i32
, { "r", "r", "rJ" } },
571 { INDEX_op_div2_i32
, { "r", "r", "0", "1", "r" } },
572 { INDEX_op_divu2_i32
, { "r", "r", "0", "1", "r" } },
573 { INDEX_op_sub_i32
, { "r", "r", "rJ" } },
574 { INDEX_op_and_i32
, { "r", "r", "rJ" } },
575 { INDEX_op_or_i32
, { "r", "r", "rJ" } },
576 { INDEX_op_xor_i32
, { "r", "r", "rJ" } },
578 { INDEX_op_shl_i32
, { "r", "r", "rJ" } },
579 { INDEX_op_shr_i32
, { "r", "r", "rJ" } },
580 { INDEX_op_sar_i32
, { "r", "r", "rJ" } },
582 { INDEX_op_brcond_i32
, { "r", "ri" } },
584 { INDEX_op_qemu_ld8u
, { "r", "L" } },
585 { INDEX_op_qemu_ld8s
, { "r", "L" } },
586 { INDEX_op_qemu_ld16u
, { "r", "L" } },
587 { INDEX_op_qemu_ld16s
, { "r", "L" } },
588 { INDEX_op_qemu_ld32u
, { "r", "L" } },
589 { INDEX_op_qemu_ld32s
, { "r", "L" } },
591 { INDEX_op_qemu_st8
, { "L", "L" } },
592 { INDEX_op_qemu_st16
, { "L", "L" } },
593 { INDEX_op_qemu_st32
, { "L", "L" } },
595 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
596 { INDEX_op_mov_i64
, { "r", "r" } },
597 { INDEX_op_movi_i64
, { "r" } },
598 { INDEX_op_ld8u_i64
, { "r", "r" } },
599 { INDEX_op_ld8s_i64
, { "r", "r" } },
600 { INDEX_op_ld16u_i64
, { "r", "r" } },
601 { INDEX_op_ld16s_i64
, { "r", "r" } },
602 { INDEX_op_ld32u_i64
, { "r", "r" } },
603 { INDEX_op_ld32s_i64
, { "r", "r" } },
604 { INDEX_op_ld_i64
, { "r", "r" } },
605 { INDEX_op_st8_i64
, { "r", "r" } },
606 { INDEX_op_st16_i64
, { "r", "r" } },
607 { INDEX_op_st32_i64
, { "r", "r" } },
608 { INDEX_op_st_i64
, { "r", "r" } },
610 { INDEX_op_add_i64
, { "r", "r", "rJ" } },
611 { INDEX_op_mul_i64
, { "r", "r", "rJ" } },
612 { INDEX_op_div2_i64
, { "r", "r", "0", "1", "r" } },
613 { INDEX_op_divu2_i64
, { "r", "r", "0", "1", "r" } },
614 { INDEX_op_sub_i64
, { "r", "r", "rJ" } },
615 { INDEX_op_and_i64
, { "r", "r", "rJ" } },
616 { INDEX_op_or_i64
, { "r", "r", "rJ" } },
617 { INDEX_op_xor_i64
, { "r", "r", "rJ" } },
619 { INDEX_op_shl_i64
, { "r", "r", "rJ" } },
620 { INDEX_op_shr_i64
, { "r", "r", "rJ" } },
621 { INDEX_op_sar_i64
, { "r", "r", "rJ" } },
623 { INDEX_op_brcond_i64
, { "r", "ri" } },
628 void tcg_target_init(TCGContext
*s
)
630 tcg_regset_set32(tcg_target_available_regs
[TCG_TYPE_I32
], 0, 0xffffffff);
631 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
632 tcg_regset_set32(tcg_target_available_regs
[TCG_TYPE_I64
], 0, 0xffffffff);
634 tcg_regset_set32(tcg_target_call_clobber_regs
, 0,
650 tcg_regset_clear(s
->reserved_regs
);
651 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_G0
);
652 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_I5
); // for internal use
653 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_I6
);
654 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_I7
);
655 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_O6
);
656 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_O7
);
657 tcg_add_target_add_op_defs(sparc_op_defs
);