2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 static const char * const tcg_target_reg_names
[TCG_TARGET_NB_REGS
] = {
60 static const int tcg_target_reg_alloc_order
[] = {
76 static const int tcg_target_call_iarg_regs
[6] = {
85 static const int tcg_target_call_oarg_regs
[2] = {
90 static void patch_reloc(uint8_t *code_ptr
, int type
,
91 tcg_target_long value
, tcg_target_long addend
)
96 if (value
!= (uint32_t)value
)
98 *(uint32_t *)code_ptr
= value
;
105 /* maximum number of register used for input function arguments */
106 static inline int tcg_target_get_call_iarg_regs_count(int flags
)
111 /* parse target specific constraints */
112 static int target_parse_constraint(TCGArgConstraint
*ct
, const char **pct_str
)
119 case 'L': /* qemu_ld/st constraint */
120 ct
->ct
|= TCG_CT_REG
;
121 tcg_regset_set32(ct
->u
.regs
, 0, 0xffffffff);
124 ct
->ct
|= TCG_CT_CONST_S11
;
127 ct
->ct
|= TCG_CT_CONST_S13
;
137 #define ABS(x) ((x) < 0? -(x) : (x))
138 /* test if a constant matches the constraint */
139 static inline int tcg_target_const_match(tcg_target_long val
,
140 const TCGArgConstraint
*arg_ct
)
145 if (ct
& TCG_CT_CONST
)
147 else if ((ct
& TCG_CT_CONST_S11
) && ABS(val
) == (ABS(val
) & 0x3ff))
149 else if ((ct
& TCG_CT_CONST_S13
) && ABS(val
) == (ABS(val
) & 0xfff))
155 #define INSN_OP(x) ((x) << 30)
156 #define INSN_OP2(x) ((x) << 22)
157 #define INSN_OP3(x) ((x) << 19)
158 #define INSN_OPF(x) ((x) << 5)
159 #define INSN_RD(x) ((x) << 25)
160 #define INSN_RS1(x) ((x) << 14)
161 #define INSN_RS2(x) (x)
163 #define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff))
164 #define INSN_OFF22(x) (((x) >> 2) & 0x3fffff)
166 #define INSN_COND(x, a) (((x) << 25) | ((a) << 29))
168 #define BA (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2))
170 #define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00))
171 #define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01))
172 #define ARITH_OR (INSN_OP(2) | INSN_OP3(0x02))
173 #define ARITH_XOR (INSN_OP(2) | INSN_OP3(0x03))
174 #define ARITH_SUB (INSN_OP(2) | INSN_OP3(0x08))
175 #define ARITH_ADDX (INSN_OP(2) | INSN_OP3(0x10))
176 #define ARITH_SUBX (INSN_OP(2) | INSN_OP3(0x0c))
177 #define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a))
178 #define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e))
179 #define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f))
180 #define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09))
181 #define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d))
182 #define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d))
184 #define SHIFT_SLL (INSN_OP(2) | INSN_OP3(0x25))
185 #define SHIFT_SRL (INSN_OP(2) | INSN_OP3(0x26))
186 #define SHIFT_SRA (INSN_OP(2) | INSN_OP3(0x27))
188 #define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12))
189 #define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12))
190 #define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12))
192 #define WRY (INSN_OP(2) | INSN_OP3(0x30))
193 #define JMPL (INSN_OP(2) | INSN_OP3(0x38))
194 #define SAVE (INSN_OP(2) | INSN_OP3(0x3c))
195 #define RESTORE (INSN_OP(2) | INSN_OP3(0x3d))
196 #define SETHI (INSN_OP(0) | INSN_OP2(0x4))
197 #define CALL INSN_OP(1)
198 #define LDUB (INSN_OP(3) | INSN_OP3(0x01))
199 #define LDSB (INSN_OP(3) | INSN_OP3(0x09))
200 #define LDUH (INSN_OP(3) | INSN_OP3(0x02))
201 #define LDSH (INSN_OP(3) | INSN_OP3(0x0a))
202 #define LDUW (INSN_OP(3) | INSN_OP3(0x00))
203 #define LDSW (INSN_OP(3) | INSN_OP3(0x08))
204 #define LDX (INSN_OP(3) | INSN_OP3(0x0b))
205 #define STB (INSN_OP(3) | INSN_OP3(0x05))
206 #define STH (INSN_OP(3) | INSN_OP3(0x06))
207 #define STW (INSN_OP(3) | INSN_OP3(0x04))
208 #define STX (INSN_OP(3) | INSN_OP3(0x0e))
210 static inline void tcg_out_mov(TCGContext
*s
, int ret
, int arg
)
212 tcg_out32(s
, ARITH_OR
| INSN_RD(ret
) | INSN_RS1(arg
) |
213 INSN_RS2(TCG_REG_G0
));
216 static inline void tcg_out_movi(TCGContext
*s
, TCGType type
,
217 int ret
, tcg_target_long arg
)
219 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
220 if (arg
!= (arg
& 0xffffffff))
221 fprintf(stderr
, "unimplemented %s with constant %ld\n", __func__
, arg
);
223 if (arg
== (arg
& 0xfff))
224 tcg_out32(s
, ARITH_OR
| INSN_RD(ret
) | INSN_RS1(TCG_REG_G0
) |
227 tcg_out32(s
, SETHI
| INSN_RD(ret
) | ((arg
& 0xfffffc00) >> 10));
229 tcg_out32(s
, ARITH_OR
| INSN_RD(ret
) | INSN_RS1(ret
) |
230 INSN_IMM13(arg
& 0x3ff));
234 static inline void tcg_out_ld_raw(TCGContext
*s
, int ret
,
237 tcg_out32(s
, SETHI
| INSN_RD(ret
) | (((uint32_t)arg
& 0xfffffc00) >> 10));
238 tcg_out32(s
, LDUW
| INSN_RD(ret
) | INSN_RS1(ret
) |
239 INSN_IMM13(arg
& 0x3ff));
242 static inline void tcg_out_ld_ptr(TCGContext
*s
, int ret
,
245 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
246 if (arg
!= (arg
& 0xffffffff))
247 fprintf(stderr
, "unimplemented %s with offset %ld\n", __func__
, arg
);
248 if (arg
!= (arg
& 0xfff))
249 tcg_out32(s
, SETHI
| INSN_RD(ret
) | (((uint32_t)arg
& 0xfffffc00) >> 10));
250 tcg_out32(s
, LDX
| INSN_RD(ret
) | INSN_RS1(ret
) |
251 INSN_IMM13(arg
& 0x3ff));
253 tcg_out_ld_raw(s
, ret
, arg
);
257 static inline void tcg_out_ldst(TCGContext
*s
, int ret
, int addr
, int offset
, int op
)
259 if (offset
== (offset
& 0xfff))
260 tcg_out32(s
, op
| INSN_RD(ret
) | INSN_RS1(addr
) |
263 fprintf(stderr
, "unimplemented %s with offset %d\n", __func__
, offset
);
266 static inline void tcg_out_ld(TCGContext
*s
, TCGType type
, int ret
,
267 int arg1
, tcg_target_long arg2
)
269 fprintf(stderr
, "unimplemented %s\n", __func__
);
272 static inline void tcg_out_st(TCGContext
*s
, TCGType type
, int arg
,
273 int arg1
, tcg_target_long arg2
)
275 fprintf(stderr
, "unimplemented %s\n", __func__
);
278 static inline void tcg_out_arith(TCGContext
*s
, int rd
, int rs1
, int rs2
,
281 tcg_out32(s
, op
| INSN_RD(rd
) | INSN_RS1(rs1
) |
285 static inline void tcg_out_arithi(TCGContext
*s
, int rd
, int rs1
, int offset
,
288 tcg_out32(s
, op
| INSN_RD(rd
) | INSN_RS1(rs1
) |
292 static inline void tcg_out_sety(TCGContext
*s
, tcg_target_long val
)
294 if (val
== 0 || val
== -1)
295 tcg_out32(s
, WRY
| INSN_IMM13(val
));
297 fprintf(stderr
, "unimplemented sety %ld\n", (long)val
);
300 static inline void tcg_out_addi(TCGContext
*s
, int reg
, tcg_target_long val
)
303 if (val
== (val
& 0xfff))
304 tcg_out_arithi(s
, reg
, reg
, val
, ARITH_ADD
);
306 fprintf(stderr
, "unimplemented addi %ld\n", (long)val
);
310 static inline void tcg_out_nop(TCGContext
*s
)
312 tcg_out32(s
, SETHI
| INSN_RD(TCG_REG_G0
) | 0);
315 static inline void tcg_target_prologue(TCGContext
*s
)
317 tcg_out32(s
, SAVE
| INSN_RD(TCG_REG_O6
) | INSN_RS1(TCG_REG_O6
) |
318 INSN_IMM13(-TCG_TARGET_STACK_MINFRAME
));
321 static inline void tcg_out_op(TCGContext
*s
, int opc
, const TCGArg
*args
,
322 const int *const_args
)
327 case INDEX_op_exit_tb
:
328 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_I0
, args
[0]);
329 tcg_out32(s
, JMPL
| INSN_RD(TCG_REG_G0
) | INSN_RS1(TCG_REG_I7
) |
331 tcg_out32(s
, RESTORE
| INSN_RD(TCG_REG_G0
) | INSN_RS1(TCG_REG_G0
) |
332 INSN_RS2(TCG_REG_G0
));
334 case INDEX_op_goto_tb
:
335 if (s
->tb_jmp_offset
) {
336 /* direct jump method */
337 if (ABS(args
[0] - (unsigned long)s
->code_ptr
) ==
338 (ABS(args
[0] - (unsigned long)s
->code_ptr
) & 0x1fffff)) {
340 INSN_OFF22(args
[0] - (unsigned long)s
->code_ptr
));
342 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_I5
, args
[0]);
343 tcg_out32(s
, JMPL
| INSN_RD(TCG_REG_G0
) | INSN_RS1(TCG_REG_I5
) |
344 INSN_RS2(TCG_REG_G0
));
346 s
->tb_jmp_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
348 /* indirect jump method */
349 tcg_out_ld_ptr(s
, TCG_REG_I5
, (tcg_target_long
)(s
->tb_next
+ args
[0]));
350 tcg_out32(s
, JMPL
| INSN_RD(TCG_REG_G0
) | INSN_RS1(TCG_REG_I5
) |
351 INSN_RS2(TCG_REG_G0
));
354 s
->tb_next_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
358 tcg_out32(s
, CALL
| ((((tcg_target_ulong
)args
[0]
359 - (tcg_target_ulong
)s
->code_ptr
) >> 2)
363 tcg_out_ld_ptr(s
, TCG_REG_O7
, (tcg_target_long
)(s
->tb_next
+ args
[0]));
364 tcg_out32(s
, JMPL
| INSN_RD(TCG_REG_O7
) | INSN_RS1(TCG_REG_O7
) |
365 INSN_RS2(TCG_REG_G0
));
370 fprintf(stderr
, "unimplemented jmp\n");
373 fprintf(stderr
, "unimplemented br\n");
375 case INDEX_op_movi_i32
:
376 tcg_out_movi(s
, TCG_TYPE_I32
, args
[0], (uint32_t)args
[1]);
379 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
380 #define OP_32_64(x) \
381 glue(glue(case INDEX_op_, x), _i32:) \
382 glue(glue(case INDEX_op_, x), _i64:)
384 #define OP_32_64(x) \
385 glue(glue(case INDEX_op_, x), _i32:)
388 tcg_out_ldst(s
, args
[0], args
[1], args
[2], LDUB
);
391 tcg_out_ldst(s
, args
[0], args
[1], args
[2], LDSB
);
394 tcg_out_ldst(s
, args
[0], args
[1], args
[2], LDUH
);
397 tcg_out_ldst(s
, args
[0], args
[1], args
[2], LDSH
);
399 case INDEX_op_ld_i32
:
400 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
401 case INDEX_op_ld32u_i64
:
403 tcg_out_ldst(s
, args
[0], args
[1], args
[2], LDUW
);
406 tcg_out_ldst(s
, args
[0], args
[1], args
[2], STB
);
409 tcg_out_ldst(s
, args
[0], args
[1], args
[2], STH
);
411 case INDEX_op_st_i32
:
412 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
413 case INDEX_op_st32_i64
:
415 tcg_out_ldst(s
, args
[0], args
[1], args
[2], STW
);
432 case INDEX_op_shl_i32
:
435 case INDEX_op_shr_i32
:
438 case INDEX_op_sar_i32
:
441 case INDEX_op_mul_i32
:
444 case INDEX_op_div2_i32
:
445 #if defined(__sparc_v9__) || defined(__sparc_v8plus__)
453 case INDEX_op_divu2_i32
:
454 #if defined(__sparc_v9__) || defined(__sparc_v8plus__)
463 case INDEX_op_brcond_i32
:
464 fprintf(stderr
, "unimplemented brcond\n");
467 case INDEX_op_qemu_ld8u
:
468 fprintf(stderr
, "unimplemented qld\n");
470 case INDEX_op_qemu_ld8s
:
471 fprintf(stderr
, "unimplemented qld\n");
473 case INDEX_op_qemu_ld16u
:
474 fprintf(stderr
, "unimplemented qld\n");
476 case INDEX_op_qemu_ld16s
:
477 fprintf(stderr
, "unimplemented qld\n");
479 case INDEX_op_qemu_ld32u
:
480 fprintf(stderr
, "unimplemented qld\n");
482 case INDEX_op_qemu_ld32s
:
483 fprintf(stderr
, "unimplemented qld\n");
485 case INDEX_op_qemu_st8
:
486 fprintf(stderr
, "unimplemented qst\n");
488 case INDEX_op_qemu_st16
:
489 fprintf(stderr
, "unimplemented qst\n");
491 case INDEX_op_qemu_st32
:
492 fprintf(stderr
, "unimplemented qst\n");
495 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
496 case INDEX_op_movi_i64
:
497 tcg_out_movi(s
, TCG_TYPE_I64
, args
[0], args
[1]);
499 case INDEX_op_ld32s_i64
:
500 tcg_out_ldst(s
, args
[0], args
[1], args
[2], LDSW
);
502 case INDEX_op_ld_i64
:
503 tcg_out_ldst(s
, args
[0], args
[1], args
[2], LDX
);
505 case INDEX_op_st_i64
:
506 tcg_out_ldst(s
, args
[0], args
[1], args
[2], STX
);
508 case INDEX_op_shl_i64
:
511 case INDEX_op_shr_i64
:
514 case INDEX_op_sar_i64
:
517 case INDEX_op_mul_i64
:
520 case INDEX_op_div2_i64
:
523 case INDEX_op_divu2_i64
:
527 case INDEX_op_brcond_i64
:
528 fprintf(stderr
, "unimplemented brcond\n");
530 case INDEX_op_qemu_ld64
:
531 fprintf(stderr
, "unimplemented qld\n");
533 case INDEX_op_qemu_st64
:
534 fprintf(stderr
, "unimplemented qst\n");
540 tcg_out_arithi(s
, args
[0], args
[1], args
[2], c
);
542 tcg_out_arith(s
, args
[0], args
[1], args
[2], c
);
547 fprintf(stderr
, "unknown opcode 0x%x\n", opc
);
552 static const TCGTargetOpDef sparc_op_defs
[] = {
553 { INDEX_op_exit_tb
, { } },
554 { INDEX_op_goto_tb
, { } },
555 { INDEX_op_call
, { "ri" } },
556 { INDEX_op_jmp
, { "ri" } },
557 { INDEX_op_br
, { } },
559 { INDEX_op_mov_i32
, { "r", "r" } },
560 { INDEX_op_movi_i32
, { "r" } },
561 { INDEX_op_ld8u_i32
, { "r", "r" } },
562 { INDEX_op_ld8s_i32
, { "r", "r" } },
563 { INDEX_op_ld16u_i32
, { "r", "r" } },
564 { INDEX_op_ld16s_i32
, { "r", "r" } },
565 { INDEX_op_ld_i32
, { "r", "r" } },
566 { INDEX_op_st8_i32
, { "r", "r" } },
567 { INDEX_op_st16_i32
, { "r", "r" } },
568 { INDEX_op_st_i32
, { "r", "r" } },
570 { INDEX_op_add_i32
, { "r", "r", "rJ" } },
571 { INDEX_op_mul_i32
, { "r", "r", "rJ" } },
572 { INDEX_op_div2_i32
, { "r", "r", "0", "1", "r" } },
573 { INDEX_op_divu2_i32
, { "r", "r", "0", "1", "r" } },
574 { INDEX_op_sub_i32
, { "r", "r", "rJ" } },
575 { INDEX_op_and_i32
, { "r", "r", "rJ" } },
576 { INDEX_op_or_i32
, { "r", "r", "rJ" } },
577 { INDEX_op_xor_i32
, { "r", "r", "rJ" } },
579 { INDEX_op_shl_i32
, { "r", "r", "rJ" } },
580 { INDEX_op_shr_i32
, { "r", "r", "rJ" } },
581 { INDEX_op_sar_i32
, { "r", "r", "rJ" } },
583 { INDEX_op_brcond_i32
, { "r", "ri" } },
585 { INDEX_op_qemu_ld8u
, { "r", "L" } },
586 { INDEX_op_qemu_ld8s
, { "r", "L" } },
587 { INDEX_op_qemu_ld16u
, { "r", "L" } },
588 { INDEX_op_qemu_ld16s
, { "r", "L" } },
589 { INDEX_op_qemu_ld32u
, { "r", "L" } },
590 { INDEX_op_qemu_ld32s
, { "r", "L" } },
592 { INDEX_op_qemu_st8
, { "L", "L" } },
593 { INDEX_op_qemu_st16
, { "L", "L" } },
594 { INDEX_op_qemu_st32
, { "L", "L" } },
596 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
597 { INDEX_op_mov_i64
, { "r", "r" } },
598 { INDEX_op_movi_i64
, { "r" } },
599 { INDEX_op_ld8u_i64
, { "r", "r" } },
600 { INDEX_op_ld8s_i64
, { "r", "r" } },
601 { INDEX_op_ld16u_i64
, { "r", "r" } },
602 { INDEX_op_ld16s_i64
, { "r", "r" } },
603 { INDEX_op_ld32u_i64
, { "r", "r" } },
604 { INDEX_op_ld32s_i64
, { "r", "r" } },
605 { INDEX_op_ld_i64
, { "r", "r" } },
606 { INDEX_op_st8_i64
, { "r", "r" } },
607 { INDEX_op_st16_i64
, { "r", "r" } },
608 { INDEX_op_st32_i64
, { "r", "r" } },
609 { INDEX_op_st_i64
, { "r", "r" } },
611 { INDEX_op_add_i64
, { "r", "r", "rJ" } },
612 { INDEX_op_mul_i64
, { "r", "r", "rJ" } },
613 { INDEX_op_div2_i64
, { "r", "r", "0", "1", "r" } },
614 { INDEX_op_divu2_i64
, { "r", "r", "0", "1", "r" } },
615 { INDEX_op_sub_i64
, { "r", "r", "rJ" } },
616 { INDEX_op_and_i64
, { "r", "r", "rJ" } },
617 { INDEX_op_or_i64
, { "r", "r", "rJ" } },
618 { INDEX_op_xor_i64
, { "r", "r", "rJ" } },
620 { INDEX_op_shl_i64
, { "r", "r", "rJ" } },
621 { INDEX_op_shr_i64
, { "r", "r", "rJ" } },
622 { INDEX_op_sar_i64
, { "r", "r", "rJ" } },
624 { INDEX_op_brcond_i64
, { "r", "ri" } },
629 void tcg_target_init(TCGContext
*s
)
631 tcg_regset_set32(tcg_target_available_regs
[TCG_TYPE_I32
], 0, 0xffffffff);
632 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
633 tcg_regset_set32(tcg_target_available_regs
[TCG_TYPE_I64
], 0, 0xffffffff);
635 tcg_regset_set32(tcg_target_call_clobber_regs
, 0,
651 tcg_regset_clear(s
->reserved_regs
);
652 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_G0
);
653 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_I5
); // for internal use
654 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_I6
);
655 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_I7
);
656 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_O6
);
657 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_O7
);
658 tcg_add_target_add_op_defs(sparc_op_defs
);