tcg/tcg-op.h

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2008 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "tcg.h"
  25
  26 int gen_new_label(void);
  27
  28 static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 arg1)
  29 {
  30     *gen_opc_ptr++ = opc;
  31     *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
  32 }
  33
  34 static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 arg1)
  35 {
  36     *gen_opc_ptr++ = opc;
  37     *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
  38 }
  39
  40 static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg arg1)
  41 {
  42     *gen_opc_ptr++ = opc;
  43     *gen_opparam_ptr++ = arg1;
  44 }
  45
  46 static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2)
  47 {
  48     *gen_opc_ptr++ = opc;
  49     *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
  50     *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
  51 }
  52
  53 static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2)
  54 {
  55     *gen_opc_ptr++ = opc;
  56     *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
  57     *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
  58 }
  59
  60 static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGArg arg2)
  61 {
  62     *gen_opc_ptr++ = opc;
  63     *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
  64     *gen_opparam_ptr++ = arg2;
  65 }
  66
  67 static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGArg arg2)
  68 {
  69     *gen_opc_ptr++ = opc;
  70     *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
  71     *gen_opparam_ptr++ = arg2;
  72 }
  73
  74 static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg arg1, TCGArg arg2)
  75 {
  76     *gen_opc_ptr++ = opc;
  77     *gen_opparam_ptr++ = arg1;
  78     *gen_opparam_ptr++ = arg2;
  79 }
  80
  81 static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
  82                                    TCGv_i32 arg3)
  83 {
  84     *gen_opc_ptr++ = opc;
  85     *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
  86     *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
  87     *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
  88 }
  89
  90 static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
  91                                    TCGv_i64 arg3)
  92 {
  93     *gen_opc_ptr++ = opc;
  94     *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
  95     *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
  96     *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
  97 }
  98
  99 static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 arg1,
 100                                     TCGv_i32 arg2, TCGArg arg3)
 101 {
 102     *gen_opc_ptr++ = opc;
 103     *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
 104     *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
 105     *gen_opparam_ptr++ = arg3;
 106 }
 107
 108 static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 arg1,
 109                                     TCGv_i64 arg2, TCGArg arg3)
 110 {
 111     *gen_opc_ptr++ = opc;
 112     *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
 113     *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
 114     *gen_opparam_ptr++ = arg3;
 115 }
 116
 117 static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val,
 118                                        TCGv_ptr base, TCGArg offset)
 119 {
 120     *gen_opc_ptr++ = opc;
 121     *gen_opparam_ptr++ = GET_TCGV_I32(val);
 122     *gen_opparam_ptr++ = GET_TCGV_PTR(base);
 123     *gen_opparam_ptr++ = offset;
 124 }
 125
 126 static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val,
 127                                        TCGv_ptr base, TCGArg offset)
 128 {
 129     *gen_opc_ptr++ = opc;
 130     *gen_opparam_ptr++ = GET_TCGV_I64(val);
 131     *gen_opparam_ptr++ = GET_TCGV_PTR(base);
 132     *gen_opparam_ptr++ = offset;
 133 }
 134
 135 static inline void tcg_gen_qemu_ldst_op_i64_i32(TCGOpcode opc, TCGv_i64 val,
 136                                                 TCGv_i32 addr, TCGArg mem_index)
 137 {
 138     *gen_opc_ptr++ = opc;
 139     *gen_opparam_ptr++ = GET_TCGV_I64(val);
 140     *gen_opparam_ptr++ = GET_TCGV_I32(addr);
 141     *gen_opparam_ptr++ = mem_index;
 142 }
 143
 144 static inline void tcg_gen_qemu_ldst_op_i64_i64(TCGOpcode opc, TCGv_i64 val,
 145                                                 TCGv_i64 addr, TCGArg mem_index)
 146 {
 147     *gen_opc_ptr++ = opc;
 148     *gen_opparam_ptr++ = GET_TCGV_I64(val);
 149     *gen_opparam_ptr++ = GET_TCGV_I64(addr);
 150     *gen_opparam_ptr++ = mem_index;
 151 }
 152
 153 static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
 154                                    TCGv_i32 arg3, TCGv_i32 arg4)
 155 {
 156     *gen_opc_ptr++ = opc;
 157     *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
 158     *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
 159     *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
 160     *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
 161 }
 162
 163 static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
 164                                    TCGv_i64 arg3, TCGv_i64 arg4)
 165 {
 166     *gen_opc_ptr++ = opc;
 167     *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
 168     *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
 169     *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
 170     *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
 171 }
 172
 173 static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
 174                                     TCGv_i32 arg3, TCGArg arg4)
 175 {
 176     *gen_opc_ptr++ = opc;
 177     *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
 178     *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
 179     *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
 180     *gen_opparam_ptr++ = arg4;
 181 }
 182
 183 static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
 184                                     TCGv_i64 arg3, TCGArg arg4)
 185 {
 186     *gen_opc_ptr++ = opc;
 187     *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
 188     *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
 189     *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
 190     *gen_opparam_ptr++ = arg4;
 191 }
 192
 193 static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
 194                                      TCGArg arg3, TCGArg arg4)
 195 {
 196     *gen_opc_ptr++ = opc;
 197     *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
 198     *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
 199     *gen_opparam_ptr++ = arg3;
 200     *gen_opparam_ptr++ = arg4;
 201 }
 202
 203 static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
 204                                      TCGArg arg3, TCGArg arg4)
 205 {
 206     *gen_opc_ptr++ = opc;
 207     *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
 208     *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
 209     *gen_opparam_ptr++ = arg3;
 210     *gen_opparam_ptr++ = arg4;
 211 }
 212
 213 static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
 214                                    TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5)
 215 {
 216     *gen_opc_ptr++ = opc;
 217     *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
 218     *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
 219     *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
 220     *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
 221     *gen_opparam_ptr++ = GET_TCGV_I32(arg5);
 222 }
 223
 224 static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
 225                                    TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5)
 226 {
 227     *gen_opc_ptr++ = opc;
 228     *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
 229     *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
 230     *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
 231     *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
 232     *gen_opparam_ptr++ = GET_TCGV_I64(arg5);
 233 }
 234
 235 static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
 236                                     TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5)
 237 {
 238     *gen_opc_ptr++ = opc;
 239     *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
 240     *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
 241     *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
 242     *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
 243     *gen_opparam_ptr++ = arg5;
 244 }
 245
 246 static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
 247                                     TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5)
 248 {
 249     *gen_opc_ptr++ = opc;
 250     *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
 251     *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
 252     *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
 253     *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
 254     *gen_opparam_ptr++ = arg5;
 255 }
 256
 257 static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 arg1,
 258                                      TCGv_i32 arg2, TCGv_i32 arg3,
 259                                      TCGArg arg4, TCGArg arg5)
 260 {
 261     *gen_opc_ptr++ = opc;
 262     *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
 263     *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
 264     *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
 265     *gen_opparam_ptr++ = arg4;
 266     *gen_opparam_ptr++ = arg5;
 267 }
 268
 269 static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 arg1,
 270                                      TCGv_i64 arg2, TCGv_i64 arg3,
 271                                      TCGArg arg4, TCGArg arg5)
 272 {
 273     *gen_opc_ptr++ = opc;
 274     *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
 275     *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
 276     *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
 277     *gen_opparam_ptr++ = arg4;
 278     *gen_opparam_ptr++ = arg5;
 279 }
 280
 281 static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
 282                                    TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5,
 283                                    TCGv_i32 arg6)
 284 {
 285     *gen_opc_ptr++ = opc;
 286     *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
 287     *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
 288     *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
 289     *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
 290     *gen_opparam_ptr++ = GET_TCGV_I32(arg5);
 291     *gen_opparam_ptr++ = GET_TCGV_I32(arg6);
 292 }
 293
 294 static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
 295                                    TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5,
 296                                    TCGv_i64 arg6)
 297 {
 298     *gen_opc_ptr++ = opc;
 299     *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
 300     *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
 301     *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
 302     *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
 303     *gen_opparam_ptr++ = GET_TCGV_I64(arg5);
 304     *gen_opparam_ptr++ = GET_TCGV_I64(arg6);
 305 }
 306
 307 static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
 308                                     TCGv_i32 arg3, TCGv_i32 arg4,
 309                                     TCGv_i32 arg5, TCGArg arg6)
 310 {
 311     *gen_opc_ptr++ = opc;
 312     *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
 313     *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
 314     *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
 315     *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
 316     *gen_opparam_ptr++ = GET_TCGV_I32(arg5);
 317     *gen_opparam_ptr++ = arg6;
 318 }
 319
 320 static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
 321                                     TCGv_i64 arg3, TCGv_i64 arg4,
 322                                     TCGv_i64 arg5, TCGArg arg6)
 323 {
 324     *gen_opc_ptr++ = opc;
 325     *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
 326     *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
 327     *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
 328     *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
 329     *gen_opparam_ptr++ = GET_TCGV_I64(arg5);
 330     *gen_opparam_ptr++ = arg6;
 331 }
 332
 333 static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 arg1,
 334                                      TCGv_i32 arg2, TCGv_i32 arg3,
 335                                      TCGv_i32 arg4, TCGArg arg5, TCGArg arg6)
 336 {
 337     *gen_opc_ptr++ = opc;
 338     *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
 339     *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
 340     *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
 341     *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
 342     *gen_opparam_ptr++ = arg5;
 343     *gen_opparam_ptr++ = arg6;
 344 }
 345
 346 static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 arg1,
 347                                      TCGv_i64 arg2, TCGv_i64 arg3,
 348                                      TCGv_i64 arg4, TCGArg arg5, TCGArg arg6)
 349 {
 350     *gen_opc_ptr++ = opc;
 351     *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
 352     *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
 353     *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
 354     *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
 355     *gen_opparam_ptr++ = arg5;
 356     *gen_opparam_ptr++ = arg6;
 357 }
 358
 359 static inline void gen_set_label(int n)
 360 {
 361     tcg_gen_op1i(INDEX_op_set_label, n);
 362 }
 363
 364 static inline void tcg_gen_br(int label)
 365 {
 366     tcg_gen_op1i(INDEX_op_br, label);
 367 }
 368
 369 static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg)
 370 {
 371     if (!TCGV_EQUAL_I32(ret, arg))
 372         tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg);
 373 }
 374
 375 static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg)
 376 {
 377     tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg);
 378 }
 379
 380 /* A version of dh_sizemask from def-helper.h that doesn't rely on
 381    preprocessor magic.  */
 382 static inline int tcg_gen_sizemask(int n, int is_64bit, int is_signed)
 383 {
 384     return (is_64bit << n*2) | (is_signed << (n*2 + 1));
 385 }
 386
 387 /* helper calls */
 388 static inline void tcg_gen_helperN(void *func, int flags, int sizemask,
 389                                    TCGArg ret, int nargs, TCGArg *args)
 390 {
 391     TCGv_ptr fn;
 392     fn = tcg_const_ptr(func);
 393     tcg_gen_callN(&tcg_ctx, fn, flags, sizemask, ret,
 394                   nargs, args);
 395     tcg_temp_free_ptr(fn);
 396 }
 397
 398 /* Note: Both tcg_gen_helper32() and tcg_gen_helper64() are currently
 399    reserved for helpers in tcg-runtime.c. These helpers are all const
 400    and pure, hence the call to tcg_gen_callN() with TCG_CALL_CONST |
 401    TCG_CALL_PURE. This may need to be adjusted if these functions
 402    start to be used with other helpers. */
 403 static inline void tcg_gen_helper32(void *func, int sizemask, TCGv_i32 ret,
 404                                     TCGv_i32 a, TCGv_i32 b)
 405 {
 406     TCGv_ptr fn;
 407     TCGArg args[2];
 408     fn = tcg_const_ptr(func);
 409     args[0] = GET_TCGV_I32(a);
 410     args[1] = GET_TCGV_I32(b);
 411     tcg_gen_callN(&tcg_ctx, fn, TCG_CALL_CONST | TCG_CALL_PURE, sizemask,
 412                   GET_TCGV_I32(ret), 2, args);
 413     tcg_temp_free_ptr(fn);
 414 }
 415
 416 static inline void tcg_gen_helper64(void *func, int sizemask, TCGv_i64 ret,
 417                                     TCGv_i64 a, TCGv_i64 b)
 418 {
 419     TCGv_ptr fn;
 420     TCGArg args[2];
 421     fn = tcg_const_ptr(func);
 422     args[0] = GET_TCGV_I64(a);
 423     args[1] = GET_TCGV_I64(b);
 424     tcg_gen_callN(&tcg_ctx, fn, TCG_CALL_CONST | TCG_CALL_PURE, sizemask,
 425                   GET_TCGV_I64(ret), 2, args);
 426     tcg_temp_free_ptr(fn);
 427 }
 428
 429 /* 32 bit ops */
 430
 431 static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
 432 {
 433     tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset);
 434 }
 435
 436 static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
 437 {
 438     tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset);
 439 }
 440
 441 static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
 442 {
 443     tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset);
 444 }
 445
 446 static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
 447 {
 448     tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset);
 449 }
 450
 451 static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
 452 {
 453     tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset);
 454 }
 455
 456 static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
 457 {
 458     tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset);
 459 }
 460
 461 static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
 462 {
 463     tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset);
 464 }
 465
 466 static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
 467 {
 468     tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset);
 469 }
 470
 471 static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 472 {
 473     tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2);
 474 }
 475
 476 static inline void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
 477 {
 478     /* some cases can be optimized here */
 479     if (arg2 == 0) {
 480         tcg_gen_mov_i32(ret, arg1);
 481     } else {
 482         TCGv_i32 t0 = tcg_const_i32(arg2);
 483         tcg_gen_add_i32(ret, arg1, t0);
 484         tcg_temp_free_i32(t0);
 485     }
 486 }
 487
 488 static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 489 {
 490     tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2);
 491 }
 492
 493 static inline void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2)
 494 {
 495     TCGv_i32 t0 = tcg_const_i32(arg1);
 496     tcg_gen_sub_i32(ret, t0, arg2);
 497     tcg_temp_free_i32(t0);
 498 }
 499
 500 static inline void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
 501 {
 502     /* some cases can be optimized here */
 503     if (arg2 == 0) {
 504         tcg_gen_mov_i32(ret, arg1);
 505     } else {
 506         TCGv_i32 t0 = tcg_const_i32(arg2);
 507         tcg_gen_sub_i32(ret, arg1, t0);
 508         tcg_temp_free_i32(t0);
 509     }
 510 }
 511
 512 static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 513 {
 514     if (TCGV_EQUAL_I32(arg1, arg2)) {
 515         tcg_gen_mov_i32(ret, arg1);
 516     } else {
 517         tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2);
 518     }
 519 }
 520
 521 static inline void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2)
 522 {
 523     TCGv_i32 t0;
 524     /* Some cases can be optimized here.  */
 525     switch (arg2) {
 526     case 0:
 527         tcg_gen_movi_i32(ret, 0);
 528         return;
 529     case 0xffffffffu:
 530         tcg_gen_mov_i32(ret, arg1);
 531         return;
 532     case 0xffu:
 533         /* Don't recurse with tcg_gen_ext8u_i32.  */
 534         if (TCG_TARGET_HAS_ext8u_i32) {
 535             tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg1);
 536             return;
 537         }
 538         break;
 539     case 0xffffu:
 540         if (TCG_TARGET_HAS_ext16u_i32) {
 541             tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg1);
 542             return;
 543         }
 544         break;
 545     }
 546     t0 = tcg_const_i32(arg2);
 547     tcg_gen_and_i32(ret, arg1, t0);
 548     tcg_temp_free_i32(t0);
 549 }
 550
 551 static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 552 {
 553     if (TCGV_EQUAL_I32(arg1, arg2)) {
 554         tcg_gen_mov_i32(ret, arg1);
 555     } else {
 556         tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2);
 557     }
 558 }
 559
 560 static inline void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
 561 {
 562     /* Some cases can be optimized here.  */
 563     if (arg2 == -1) {
 564         tcg_gen_movi_i32(ret, -1);
 565     } else if (arg2 == 0) {
 566         tcg_gen_mov_i32(ret, arg1);
 567     } else {
 568         TCGv_i32 t0 = tcg_const_i32(arg2);
 569         tcg_gen_or_i32(ret, arg1, t0);
 570         tcg_temp_free_i32(t0);
 571     }
 572 }
 573
 574 static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 575 {
 576     if (TCGV_EQUAL_I32(arg1, arg2)) {
 577         tcg_gen_movi_i32(ret, 0);
 578     } else {
 579         tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2);
 580     }
 581 }
 582
 583 static inline void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
 584 {
 585     /* Some cases can be optimized here.  */
 586     if (arg2 == 0) {
 587         tcg_gen_mov_i32(ret, arg1);
 588     } else if (arg2 == -1 && TCG_TARGET_HAS_not_i32) {
 589         /* Don't recurse with tcg_gen_not_i32.  */
 590         tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg1);
 591     } else {
 592         TCGv_i32 t0 = tcg_const_i32(arg2);
 593         tcg_gen_xor_i32(ret, arg1, t0);
 594         tcg_temp_free_i32(t0);
 595     }
 596 }
 597
 598 static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 599 {
 600     tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2);
 601 }
 602
 603 static inline void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
 604 {
 605     if (arg2 == 0) {
 606         tcg_gen_mov_i32(ret, arg1);
 607     } else {
 608         TCGv_i32 t0 = tcg_const_i32(arg2);
 609         tcg_gen_shl_i32(ret, arg1, t0);
 610         tcg_temp_free_i32(t0);
 611     }
 612 }
 613
 614 static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 615 {
 616     tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2);
 617 }
 618
 619 static inline void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
 620 {
 621     if (arg2 == 0) {
 622         tcg_gen_mov_i32(ret, arg1);
 623     } else {
 624         TCGv_i32 t0 = tcg_const_i32(arg2);
 625         tcg_gen_shr_i32(ret, arg1, t0);
 626         tcg_temp_free_i32(t0);
 627     }
 628 }
 629
 630 static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 631 {
 632     tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2);
 633 }
 634
 635 static inline void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
 636 {
 637     if (arg2 == 0) {
 638         tcg_gen_mov_i32(ret, arg1);
 639     } else {
 640         TCGv_i32 t0 = tcg_const_i32(arg2);
 641         tcg_gen_sar_i32(ret, arg1, t0);
 642         tcg_temp_free_i32(t0);
 643     }
 644 }
 645
 646 static inline void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1,
 647                                       TCGv_i32 arg2, int label_index)
 648 {
 649     if (cond == TCG_COND_ALWAYS) {
 650         tcg_gen_br(label_index);
 651     } else if (cond != TCG_COND_NEVER) {
 652         tcg_gen_op4ii_i32(INDEX_op_brcond_i32, arg1, arg2, cond, label_index);
 653     }
 654 }
 655
 656 static inline void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1,
 657                                        int32_t arg2, int label_index)
 658 {
 659     if (cond == TCG_COND_ALWAYS) {
 660         tcg_gen_br(label_index);
 661     } else if (cond != TCG_COND_NEVER) {
 662         TCGv_i32 t0 = tcg_const_i32(arg2);
 663         tcg_gen_brcond_i32(cond, arg1, t0, label_index);
 664         tcg_temp_free_i32(t0);
 665     }
 666 }
 667
 668 static inline void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret,
 669                                        TCGv_i32 arg1, TCGv_i32 arg2)
 670 {
 671     if (cond == TCG_COND_ALWAYS) {
 672         tcg_gen_movi_i32(ret, 1);
 673     } else if (cond == TCG_COND_NEVER) {
 674         tcg_gen_movi_i32(ret, 0);
 675     } else {
 676         tcg_gen_op4i_i32(INDEX_op_setcond_i32, ret, arg1, arg2, cond);
 677     }
 678 }
 679
 680 static inline void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret,
 681                                         TCGv_i32 arg1, int32_t arg2)
 682 {
 683     if (cond == TCG_COND_ALWAYS) {
 684         tcg_gen_movi_i32(ret, 1);
 685     } else if (cond == TCG_COND_NEVER) {
 686         tcg_gen_movi_i32(ret, 0);
 687     } else {
 688         TCGv_i32 t0 = tcg_const_i32(arg2);
 689         tcg_gen_setcond_i32(cond, ret, arg1, t0);
 690         tcg_temp_free_i32(t0);
 691     }
 692 }
 693
 694 static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 695 {
 696     tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2);
 697 }
 698
 699 static inline void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
 700 {
 701     TCGv_i32 t0 = tcg_const_i32(arg2);
 702     tcg_gen_mul_i32(ret, arg1, t0);
 703     tcg_temp_free_i32(t0);
 704 }
 705
 706 static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 707 {
 708     if (TCG_TARGET_HAS_div_i32) {
 709         tcg_gen_op3_i32(INDEX_op_div_i32, ret, arg1, arg2);
 710     } else if (TCG_TARGET_HAS_div2_i32) {
 711         TCGv_i32 t0 = tcg_temp_new_i32();
 712         tcg_gen_sari_i32(t0, arg1, 31);
 713         tcg_gen_op5_i32(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2);
 714         tcg_temp_free_i32(t0);
 715     } else {
 716         int sizemask = 0;
 717         /* Return value and both arguments are 32-bit and signed.  */
 718         sizemask |= tcg_gen_sizemask(0, 0, 1);
 719         sizemask |= tcg_gen_sizemask(1, 0, 1);
 720         sizemask |= tcg_gen_sizemask(2, 0, 1);
 721         tcg_gen_helper32(tcg_helper_div_i32, sizemask, ret, arg1, arg2);
 722     }
 723 }
 724
 725 static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 726 {
 727     if (TCG_TARGET_HAS_div_i32) {
 728         tcg_gen_op3_i32(INDEX_op_rem_i32, ret, arg1, arg2);
 729     } else if (TCG_TARGET_HAS_div2_i32) {
 730         TCGv_i32 t0 = tcg_temp_new_i32();
 731         tcg_gen_sari_i32(t0, arg1, 31);
 732         tcg_gen_op5_i32(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2);
 733         tcg_temp_free_i32(t0);
 734     } else {
 735         int sizemask = 0;
 736         /* Return value and both arguments are 32-bit and signed.  */
 737         sizemask |= tcg_gen_sizemask(0, 0, 1);
 738         sizemask |= tcg_gen_sizemask(1, 0, 1);
 739         sizemask |= tcg_gen_sizemask(2, 0, 1);
 740         tcg_gen_helper32(tcg_helper_rem_i32, sizemask, ret, arg1, arg2);
 741     }
 742 }
 743
 744 static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 745 {
 746     if (TCG_TARGET_HAS_div_i32) {
 747         tcg_gen_op3_i32(INDEX_op_divu_i32, ret, arg1, arg2);
 748     } else if (TCG_TARGET_HAS_div2_i32) {
 749         TCGv_i32 t0 = tcg_temp_new_i32();
 750         tcg_gen_movi_i32(t0, 0);
 751         tcg_gen_op5_i32(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2);
 752         tcg_temp_free_i32(t0);
 753     } else {
 754         int sizemask = 0;
 755         /* Return value and both arguments are 32-bit and unsigned.  */
 756         sizemask |= tcg_gen_sizemask(0, 0, 0);
 757         sizemask |= tcg_gen_sizemask(1, 0, 0);
 758         sizemask |= tcg_gen_sizemask(2, 0, 0);
 759         tcg_gen_helper32(tcg_helper_divu_i32, sizemask, ret, arg1, arg2);
 760     }
 761 }
 762
 763 static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 764 {
 765     if (TCG_TARGET_HAS_div_i32) {
 766         tcg_gen_op3_i32(INDEX_op_remu_i32, ret, arg1, arg2);
 767     } else if (TCG_TARGET_HAS_div2_i32) {
 768         TCGv_i32 t0 = tcg_temp_new_i32();
 769         tcg_gen_movi_i32(t0, 0);
 770         tcg_gen_op5_i32(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2);
 771         tcg_temp_free_i32(t0);
 772     } else {
 773         int sizemask = 0;
 774         /* Return value and both arguments are 32-bit and unsigned.  */
 775         sizemask |= tcg_gen_sizemask(0, 0, 0);
 776         sizemask |= tcg_gen_sizemask(1, 0, 0);
 777         sizemask |= tcg_gen_sizemask(2, 0, 0);
 778         tcg_gen_helper32(tcg_helper_remu_i32, sizemask, ret, arg1, arg2);
 779     }
 780 }
 781
 782 #if TCG_TARGET_REG_BITS == 32
 783
 784 static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
 785 {
 786     if (!TCGV_EQUAL_I64(ret, arg)) {
 787         tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
 788         tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
 789     }
 790 }
 791
 792 static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
 793 {
 794     tcg_gen_movi_i32(TCGV_LOW(ret), arg);
 795     tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32);
 796 }
 797
 798 static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2,
 799                                     tcg_target_long offset)
 800 {
 801     tcg_gen_ld8u_i32(TCGV_LOW(ret), arg2, offset);
 802     tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
 803 }
 804
 805 static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2,
 806                                     tcg_target_long offset)
 807 {
 808     tcg_gen_ld8s_i32(TCGV_LOW(ret), arg2, offset);
 809     tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), 31);
 810 }
 811
 812 static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2,
 813                                      tcg_target_long offset)
 814 {
 815     tcg_gen_ld16u_i32(TCGV_LOW(ret), arg2, offset);
 816     tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
 817 }
 818
 819 static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2,
 820                                      tcg_target_long offset)
 821 {
 822     tcg_gen_ld16s_i32(TCGV_LOW(ret), arg2, offset);
 823     tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
 824 }
 825
 826 static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2,
 827                                      tcg_target_long offset)
 828 {
 829     tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
 830     tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
 831 }
 832
 833 static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2,
 834                                      tcg_target_long offset)
 835 {
 836     tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
 837     tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
 838 }
 839
 840 static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2,
 841                                   tcg_target_long offset)
 842 {
 843     /* since arg2 and ret have different types, they cannot be the
 844        same temporary */
 845 #ifdef TCG_TARGET_WORDS_BIGENDIAN
 846     tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset);
 847     tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset + 4);
 848 #else
 849     tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
 850     tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4);
 851 #endif
 852 }
 853
 854 static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
 855                                    tcg_target_long offset)
 856 {
 857     tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset);
 858 }
 859
 860 static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
 861                                     tcg_target_long offset)
 862 {
 863     tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset);
 864 }
 865
 866 static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
 867                                     tcg_target_long offset)
 868 {
 869     tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
 870 }
 871
 872 static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2,
 873                                   tcg_target_long offset)
 874 {
 875 #ifdef TCG_TARGET_WORDS_BIGENDIAN
 876     tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset);
 877     tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset + 4);
 878 #else
 879     tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
 880     tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4);
 881 #endif
 882 }
 883
 884 static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 885 {
 886     tcg_gen_op6_i32(INDEX_op_add2_i32, TCGV_LOW(ret), TCGV_HIGH(ret),
 887                     TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
 888                     TCGV_HIGH(arg2));
 889 }
 890
 891 static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 892 {
 893     tcg_gen_op6_i32(INDEX_op_sub2_i32, TCGV_LOW(ret), TCGV_HIGH(ret),
 894                     TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
 895                     TCGV_HIGH(arg2));
 896 }
 897
 898 static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 899 {
 900     tcg_gen_and_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
 901     tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
 902 }
 903
 904 static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
 905 {
 906     tcg_gen_andi_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
 907     tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
 908 }
 909
 910 static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 911 {
 912     tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
 913     tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
 914 }
 915
 916 static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
 917 {
 918     tcg_gen_ori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
 919     tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
 920 }
 921
 922 static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 923 {
 924     tcg_gen_xor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
 925     tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
 926 }
 927
 928 static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
 929 {
 930     tcg_gen_xori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
 931     tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
 932 }
 933
 934 /* XXX: use generic code when basic block handling is OK or CPU
 935    specific code (x86) */
 936 static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 937 {
 938     int sizemask = 0;
 939     /* Return value and both arguments are 64-bit and signed.  */
 940     sizemask |= tcg_gen_sizemask(0, 1, 1);
 941     sizemask |= tcg_gen_sizemask(1, 1, 1);
 942     sizemask |= tcg_gen_sizemask(2, 1, 1);
 943
 944     tcg_gen_helper64(tcg_helper_shl_i64, sizemask, ret, arg1, arg2);
 945 }
 946
 947 static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
 948 {
 949     tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0);
 950 }
 951
 952 static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 953 {
 954     int sizemask = 0;
 955     /* Return value and both arguments are 64-bit and signed.  */
 956     sizemask |= tcg_gen_sizemask(0, 1, 1);
 957     sizemask |= tcg_gen_sizemask(1, 1, 1);
 958     sizemask |= tcg_gen_sizemask(2, 1, 1);
 959
 960     tcg_gen_helper64(tcg_helper_shr_i64, sizemask, ret, arg1, arg2);
 961 }
 962
 963 static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
 964 {
 965     tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0);
 966 }
 967
 968 static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 969 {
 970     int sizemask = 0;
 971     /* Return value and both arguments are 64-bit and signed.  */
 972     sizemask |= tcg_gen_sizemask(0, 1, 1);
 973     sizemask |= tcg_gen_sizemask(1, 1, 1);
 974     sizemask |= tcg_gen_sizemask(2, 1, 1);
 975
 976     tcg_gen_helper64(tcg_helper_sar_i64, sizemask, ret, arg1, arg2);
 977 }
 978
 979 static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
 980 {
 981     tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1);
 982 }
 983
 984 static inline void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1,
 985                                       TCGv_i64 arg2, int label_index)
 986 {
 987     if (cond == TCG_COND_ALWAYS) {
 988         tcg_gen_br(label_index);
 989     } else if (cond != TCG_COND_NEVER) {
 990         tcg_gen_op6ii_i32(INDEX_op_brcond2_i32,
 991                           TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
 992                           TCGV_HIGH(arg2), cond, label_index);
 993     }
 994 }
 995
 996 static inline void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
 997                                        TCGv_i64 arg1, TCGv_i64 arg2)
 998 {
 999     if (cond == TCG_COND_ALWAYS) {
1000         tcg_gen_movi_i32(TCGV_LOW(ret), 1);
1001     } else if (cond == TCG_COND_NEVER) {
1002         tcg_gen_movi_i32(TCGV_LOW(ret), 0);
1003     } else {
1004         tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret),
1005                          TCGV_LOW(arg1), TCGV_HIGH(arg1),
1006                          TCGV_LOW(arg2), TCGV_HIGH(arg2), cond);
1007     }
1008     tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1009 }
1010
1011 static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1012 {
1013     TCGv_i64 t0;
1014     TCGv_i32 t1;
1015
1016     t0 = tcg_temp_new_i64();
1017     t1 = tcg_temp_new_i32();
1018
1019     tcg_gen_op4_i32(INDEX_op_mulu2_i32, TCGV_LOW(t0), TCGV_HIGH(t0),
1020                     TCGV_LOW(arg1), TCGV_LOW(arg2));
1021
1022     tcg_gen_mul_i32(t1, TCGV_LOW(arg1), TCGV_HIGH(arg2));
1023     tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
1024     tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), TCGV_LOW(arg2));
1025     tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
1026
1027     tcg_gen_mov_i64(ret, t0);
1028     tcg_temp_free_i64(t0);
1029     tcg_temp_free_i32(t1);
1030 }
1031
1032 static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1033 {
1034     int sizemask = 0;
1035     /* Return value and both arguments are 64-bit and signed.  */
1036     sizemask |= tcg_gen_sizemask(0, 1, 1);
1037     sizemask |= tcg_gen_sizemask(1, 1, 1);
1038     sizemask |= tcg_gen_sizemask(2, 1, 1);
1039
1040     tcg_gen_helper64(tcg_helper_div_i64, sizemask, ret, arg1, arg2);
1041 }
1042
1043 static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1044 {
1045     int sizemask = 0;
1046     /* Return value and both arguments are 64-bit and signed.  */
1047     sizemask |= tcg_gen_sizemask(0, 1, 1);
1048     sizemask |= tcg_gen_sizemask(1, 1, 1);
1049     sizemask |= tcg_gen_sizemask(2, 1, 1);
1050
1051     tcg_gen_helper64(tcg_helper_rem_i64, sizemask, ret, arg1, arg2);
1052 }
1053
1054 static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1055 {
1056     int sizemask = 0;
1057     /* Return value and both arguments are 64-bit and unsigned.  */
1058     sizemask |= tcg_gen_sizemask(0, 1, 0);
1059     sizemask |= tcg_gen_sizemask(1, 1, 0);
1060     sizemask |= tcg_gen_sizemask(2, 1, 0);
1061
1062     tcg_gen_helper64(tcg_helper_divu_i64, sizemask, ret, arg1, arg2);
1063 }
1064
1065 static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1066 {
1067     int sizemask = 0;
1068     /* Return value and both arguments are 64-bit and unsigned.  */
1069     sizemask |= tcg_gen_sizemask(0, 1, 0);
1070     sizemask |= tcg_gen_sizemask(1, 1, 0);
1071     sizemask |= tcg_gen_sizemask(2, 1, 0);
1072
1073     tcg_gen_helper64(tcg_helper_remu_i64, sizemask, ret, arg1, arg2);
1074 }
1075
1076 #else
1077
1078 static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
1079 {
1080     if (!TCGV_EQUAL_I64(ret, arg))
1081         tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg);
1082 }
1083
1084 static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
1085 {
1086     tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg);
1087 }
1088
1089 static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2,
1090                                     tcg_target_long offset)
1091 {
1092     tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset);
1093 }
1094
1095 static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2,
1096                                     tcg_target_long offset)
1097 {
1098     tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset);
1099 }
1100
1101 static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2,
1102                                      tcg_target_long offset)
1103 {
1104     tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset);
1105 }
1106
1107 static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2,
1108                                      tcg_target_long offset)
1109 {
1110     tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset);
1111 }
1112
1113 static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2,
1114                                      tcg_target_long offset)
1115 {
1116     tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset);
1117 }
1118
1119 static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2,
1120                                      tcg_target_long offset)
1121 {
1122     tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset);
1123 }
1124
1125 static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset)
1126 {
1127     tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset);
1128 }
1129
1130 static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
1131                                    tcg_target_long offset)
1132 {
1133     tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset);
1134 }
1135
1136 static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
1137                                     tcg_target_long offset)
1138 {
1139     tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset);
1140 }
1141
1142 static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
1143                                     tcg_target_long offset)
1144 {
1145     tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset);
1146 }
1147
1148 static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset)
1149 {
1150     tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset);
1151 }
1152
1153 static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1154 {
1155     tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2);
1156 }
1157
1158 static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1159 {
1160     tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2);
1161 }
1162
1163 static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1164 {
1165     if (TCGV_EQUAL_I64(arg1, arg2)) {
1166         tcg_gen_mov_i64(ret, arg1);
1167     } else {
1168         tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2);
1169     }
1170 }
1171
1172 static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2)
1173 {
1174     TCGv_i64 t0;
1175     /* Some cases can be optimized here.  */
1176     switch (arg2) {
1177     case 0:
1178         tcg_gen_movi_i64(ret, 0);
1179         return;
1180     case 0xffffffffffffffffull:
1181         tcg_gen_mov_i64(ret, arg1);
1182         return;
1183     case 0xffull:
1184         /* Don't recurse with tcg_gen_ext8u_i32.  */
1185         if (TCG_TARGET_HAS_ext8u_i64) {
1186             tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg1);
1187             return;
1188         }
1189         break;
1190     case 0xffffu:
1191         if (TCG_TARGET_HAS_ext16u_i64) {
1192             tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg1);
1193             return;
1194         }
1195         break;
1196     case 0xffffffffull:
1197         if (TCG_TARGET_HAS_ext32u_i64) {
1198             tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg1);
1199             return;
1200         }
1201         break;
1202     }
1203     t0 = tcg_const_i64(arg2);
1204     tcg_gen_and_i64(ret, arg1, t0);
1205     tcg_temp_free_i64(t0);
1206 }
1207
1208 static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1209 {
1210     if (TCGV_EQUAL_I64(arg1, arg2)) {
1211         tcg_gen_mov_i64(ret, arg1);
1212     } else {
1213         tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2);
1214     }
1215 }
1216
1217 static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1218 {
1219     /* Some cases can be optimized here.  */
1220     if (arg2 == -1) {
1221         tcg_gen_movi_i64(ret, -1);
1222     } else if (arg2 == 0) {
1223         tcg_gen_mov_i64(ret, arg1);
1224     } else {
1225         TCGv_i64 t0 = tcg_const_i64(arg2);
1226         tcg_gen_or_i64(ret, arg1, t0);
1227         tcg_temp_free_i64(t0);
1228     }
1229 }
1230
1231 static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1232 {
1233     if (TCGV_EQUAL_I64(arg1, arg2)) {
1234         tcg_gen_movi_i64(ret, 0);
1235     } else {
1236         tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2);
1237     }
1238 }
1239
1240 static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1241 {
1242     /* Some cases can be optimized here.  */
1243     if (arg2 == 0) {
1244         tcg_gen_mov_i64(ret, arg1);
1245     } else if (arg2 == -1 && TCG_TARGET_HAS_not_i64) {
1246         /* Don't recurse with tcg_gen_not_i64.  */
1247         tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg1);
1248     } else {
1249         TCGv_i64 t0 = tcg_const_i64(arg2);
1250         tcg_gen_xor_i64(ret, arg1, t0);
1251         tcg_temp_free_i64(t0);
1252     }
1253 }
1254
1255 static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1256 {
1257     tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2);
1258 }
1259
1260 static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1261 {
1262     if (arg2 == 0) {
1263         tcg_gen_mov_i64(ret, arg1);
1264     } else {
1265         TCGv_i64 t0 = tcg_const_i64(arg2);
1266         tcg_gen_shl_i64(ret, arg1, t0);
1267         tcg_temp_free_i64(t0);
1268     }
1269 }
1270
1271 static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1272 {
1273     tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2);
1274 }
1275
1276 static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1277 {
1278     if (arg2 == 0) {
1279         tcg_gen_mov_i64(ret, arg1);
1280     } else {
1281         TCGv_i64 t0 = tcg_const_i64(arg2);
1282         tcg_gen_shr_i64(ret, arg1, t0);
1283         tcg_temp_free_i64(t0);
1284     }
1285 }
1286
1287 static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1288 {
1289     tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2);
1290 }
1291
1292 static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1293 {
1294     if (arg2 == 0) {
1295         tcg_gen_mov_i64(ret, arg1);
1296     } else {
1297         TCGv_i64 t0 = tcg_const_i64(arg2);
1298         tcg_gen_sar_i64(ret, arg1, t0);
1299         tcg_temp_free_i64(t0);
1300     }
1301 }
1302
1303 static inline void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1,
1304                                       TCGv_i64 arg2, int label_index)
1305 {
1306     if (cond == TCG_COND_ALWAYS) {
1307         tcg_gen_br(label_index);
1308     } else if (cond != TCG_COND_NEVER) {
1309         tcg_gen_op4ii_i64(INDEX_op_brcond_i64, arg1, arg2, cond, label_index);
1310     }
1311 }
1312
1313 static inline void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
1314                                        TCGv_i64 arg1, TCGv_i64 arg2)
1315 {
1316     if (cond == TCG_COND_ALWAYS) {
1317         tcg_gen_movi_i64(ret, 1);
1318     } else if (cond == TCG_COND_NEVER) {
1319         tcg_gen_movi_i64(ret, 0);
1320     } else {
1321         tcg_gen_op4i_i64(INDEX_op_setcond_i64, ret, arg1, arg2, cond);
1322     }
1323 }
1324
1325 static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1326 {
1327     tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2);
1328 }
1329
1330 static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1331 {
1332     if (TCG_TARGET_HAS_div_i64) {
1333         tcg_gen_op3_i64(INDEX_op_div_i64, ret, arg1, arg2);
1334     } else if (TCG_TARGET_HAS_div2_i64) {
1335         TCGv_i64 t0 = tcg_temp_new_i64();
1336         tcg_gen_sari_i64(t0, arg1, 63);
1337         tcg_gen_op5_i64(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2);
1338         tcg_temp_free_i64(t0);
1339     } else {
1340         int sizemask = 0;
1341         /* Return value and both arguments are 64-bit and signed.  */
1342         sizemask |= tcg_gen_sizemask(0, 1, 1);
1343         sizemask |= tcg_gen_sizemask(1, 1, 1);
1344         sizemask |= tcg_gen_sizemask(2, 1, 1);
1345         tcg_gen_helper64(tcg_helper_div_i64, sizemask, ret, arg1, arg2);
1346     }
1347 }
1348
1349 static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1350 {
1351     if (TCG_TARGET_HAS_div_i64) {
1352         tcg_gen_op3_i64(INDEX_op_rem_i64, ret, arg1, arg2);
1353     } else if (TCG_TARGET_HAS_div2_i64) {
1354         TCGv_i64 t0 = tcg_temp_new_i64();
1355         tcg_gen_sari_i64(t0, arg1, 63);
1356         tcg_gen_op5_i64(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2);
1357         tcg_temp_free_i64(t0);
1358     } else {
1359         int sizemask = 0;
1360         /* Return value and both arguments are 64-bit and signed.  */
1361         sizemask |= tcg_gen_sizemask(0, 1, 1);
1362         sizemask |= tcg_gen_sizemask(1, 1, 1);
1363         sizemask |= tcg_gen_sizemask(2, 1, 1);
1364         tcg_gen_helper64(tcg_helper_rem_i64, sizemask, ret, arg1, arg2);
1365     }
1366 }
1367
1368 static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1369 {
1370     if (TCG_TARGET_HAS_div_i64) {
1371         tcg_gen_op3_i64(INDEX_op_divu_i64, ret, arg1, arg2);
1372     } else if (TCG_TARGET_HAS_div2_i64) {
1373         TCGv_i64 t0 = tcg_temp_new_i64();
1374         tcg_gen_movi_i64(t0, 0);
1375         tcg_gen_op5_i64(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2);
1376         tcg_temp_free_i64(t0);
1377     } else {
1378         int sizemask = 0;
1379         /* Return value and both arguments are 64-bit and unsigned.  */
1380         sizemask |= tcg_gen_sizemask(0, 1, 0);
1381         sizemask |= tcg_gen_sizemask(1, 1, 0);
1382         sizemask |= tcg_gen_sizemask(2, 1, 0);
1383         tcg_gen_helper64(tcg_helper_divu_i64, sizemask, ret, arg1, arg2);
1384     }
1385 }
1386
1387 static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1388 {
1389     if (TCG_TARGET_HAS_div_i64) {
1390         tcg_gen_op3_i64(INDEX_op_remu_i64, ret, arg1, arg2);
1391     } else if (TCG_TARGET_HAS_div2_i64) {
1392         TCGv_i64 t0 = tcg_temp_new_i64();
1393         tcg_gen_movi_i64(t0, 0);
1394         tcg_gen_op5_i64(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2);
1395         tcg_temp_free_i64(t0);
1396     } else {
1397         int sizemask = 0;
1398         /* Return value and both arguments are 64-bit and unsigned.  */
1399         sizemask |= tcg_gen_sizemask(0, 1, 0);
1400         sizemask |= tcg_gen_sizemask(1, 1, 0);
1401         sizemask |= tcg_gen_sizemask(2, 1, 0);
1402         tcg_gen_helper64(tcg_helper_remu_i64, sizemask, ret, arg1, arg2);
1403     }
1404 }
1405 #endif /* TCG_TARGET_REG_BITS == 32 */
1406
1407 static inline void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1408 {
1409     /* some cases can be optimized here */
1410     if (arg2 == 0) {
1411         tcg_gen_mov_i64(ret, arg1);
1412     } else {
1413         TCGv_i64 t0 = tcg_const_i64(arg2);
1414         tcg_gen_add_i64(ret, arg1, t0);
1415         tcg_temp_free_i64(t0);
1416     }
1417 }
1418
1419 static inline void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2)
1420 {
1421     TCGv_i64 t0 = tcg_const_i64(arg1);
1422     tcg_gen_sub_i64(ret, t0, arg2);
1423     tcg_temp_free_i64(t0);
1424 }
1425
1426 static inline void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1427 {
1428     /* some cases can be optimized here */
1429     if (arg2 == 0) {
1430         tcg_gen_mov_i64(ret, arg1);
1431     } else {
1432         TCGv_i64 t0 = tcg_const_i64(arg2);
1433         tcg_gen_sub_i64(ret, arg1, t0);
1434         tcg_temp_free_i64(t0);
1435     }
1436 }
1437 static inline void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1,
1438                                        int64_t arg2, int label_index)
1439 {
1440     if (cond == TCG_COND_ALWAYS) {
1441         tcg_gen_br(label_index);
1442     } else if (cond != TCG_COND_NEVER) {
1443         TCGv_i64 t0 = tcg_const_i64(arg2);
1444         tcg_gen_brcond_i64(cond, arg1, t0, label_index);
1445         tcg_temp_free_i64(t0);
1446     }
1447 }
1448
1449 static inline void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret,
1450                                         TCGv_i64 arg1, int64_t arg2)
1451 {
1452     TCGv_i64 t0 = tcg_const_i64(arg2);
1453     tcg_gen_setcond_i64(cond, ret, arg1, t0);
1454     tcg_temp_free_i64(t0);
1455 }
1456
1457 static inline void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1458 {
1459     TCGv_i64 t0 = tcg_const_i64(arg2);
1460     tcg_gen_mul_i64(ret, arg1, t0);
1461     tcg_temp_free_i64(t0);
1462 }
1463
1464
1465 /***************************************/
1466 /* optional operations */
1467
1468 static inline void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg)
1469 {
1470     if (TCG_TARGET_HAS_ext8s_i32) {
1471         tcg_gen_op2_i32(INDEX_op_ext8s_i32, ret, arg);
1472     } else {
1473         tcg_gen_shli_i32(ret, arg, 24);
1474         tcg_gen_sari_i32(ret, ret, 24);
1475     }
1476 }
1477
1478 static inline void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg)
1479 {
1480     if (TCG_TARGET_HAS_ext16s_i32) {
1481         tcg_gen_op2_i32(INDEX_op_ext16s_i32, ret, arg);
1482     } else {
1483         tcg_gen_shli_i32(ret, arg, 16);
1484         tcg_gen_sari_i32(ret, ret, 16);
1485     }
1486 }
1487
1488 static inline void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg)
1489 {
1490     if (TCG_TARGET_HAS_ext8u_i32) {
1491         tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg);
1492     } else {
1493         tcg_gen_andi_i32(ret, arg, 0xffu);
1494     }
1495 }
1496
1497 static inline void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg)
1498 {
1499     if (TCG_TARGET_HAS_ext16u_i32) {
1500         tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg);
1501     } else {
1502         tcg_gen_andi_i32(ret, arg, 0xffffu);
1503     }
1504 }
1505
1506 /* Note: we assume the two high bytes are set to zero */
1507 static inline void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg)
1508 {
1509     if (TCG_TARGET_HAS_bswap16_i32) {
1510         tcg_gen_op2_i32(INDEX_op_bswap16_i32, ret, arg);
1511     } else {
1512         TCGv_i32 t0 = tcg_temp_new_i32();
1513
1514         tcg_gen_ext8u_i32(t0, arg);
1515         tcg_gen_shli_i32(t0, t0, 8);
1516         tcg_gen_shri_i32(ret, arg, 8);
1517         tcg_gen_or_i32(ret, ret, t0);
1518         tcg_temp_free_i32(t0);
1519     }
1520 }
1521
1522 static inline void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg)
1523 {
1524     if (TCG_TARGET_HAS_bswap32_i32) {
1525         tcg_gen_op2_i32(INDEX_op_bswap32_i32, ret, arg);
1526     } else {
1527         TCGv_i32 t0, t1;
1528         t0 = tcg_temp_new_i32();
1529         t1 = tcg_temp_new_i32();
1530
1531         tcg_gen_shli_i32(t0, arg, 24);
1532
1533         tcg_gen_andi_i32(t1, arg, 0x0000ff00);
1534         tcg_gen_shli_i32(t1, t1, 8);
1535         tcg_gen_or_i32(t0, t0, t1);
1536
1537         tcg_gen_shri_i32(t1, arg, 8);
1538         tcg_gen_andi_i32(t1, t1, 0x0000ff00);
1539         tcg_gen_or_i32(t0, t0, t1);
1540
1541         tcg_gen_shri_i32(t1, arg, 24);
1542         tcg_gen_or_i32(ret, t0, t1);
1543         tcg_temp_free_i32(t0);
1544         tcg_temp_free_i32(t1);
1545     }
1546 }
1547
1548 #if TCG_TARGET_REG_BITS == 32
1549 static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg)
1550 {
1551     tcg_gen_ext8s_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1552     tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1553 }
1554
1555 static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg)
1556 {
1557     tcg_gen_ext16s_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1558     tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1559 }
1560
1561 static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg)
1562 {
1563     tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1564     tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1565 }
1566
1567 static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg)
1568 {
1569     tcg_gen_ext8u_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1570     tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1571 }
1572
1573 static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg)
1574 {
1575     tcg_gen_ext16u_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1576     tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1577 }
1578
1579 static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg)
1580 {
1581     tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1582     tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1583 }
1584
1585 static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
1586 {
1587     tcg_gen_mov_i32(ret, TCGV_LOW(arg));
1588 }
1589
1590 static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1591 {
1592     tcg_gen_mov_i32(TCGV_LOW(ret), arg);
1593     tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1594 }
1595
1596 static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1597 {
1598     tcg_gen_mov_i32(TCGV_LOW(ret), arg);
1599     tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1600 }
1601
1602 /* Note: we assume the six high bytes are set to zero */
1603 static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg)
1604 {
1605     tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
1606     tcg_gen_bswap16_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1607 }
1608
1609 /* Note: we assume the four high bytes are set to zero */
1610 static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg)
1611 {
1612     tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
1613     tcg_gen_bswap32_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1614 }
1615
1616 static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg)
1617 {
1618     TCGv_i32 t0, t1;
1619     t0 = tcg_temp_new_i32();
1620     t1 = tcg_temp_new_i32();
1621
1622     tcg_gen_bswap32_i32(t0, TCGV_LOW(arg));
1623     tcg_gen_bswap32_i32(t1, TCGV_HIGH(arg));
1624     tcg_gen_mov_i32(TCGV_LOW(ret), t1);
1625     tcg_gen_mov_i32(TCGV_HIGH(ret), t0);
1626     tcg_temp_free_i32(t0);
1627     tcg_temp_free_i32(t1);
1628 }
1629 #else
1630
1631 static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg)
1632 {
1633     if (TCG_TARGET_HAS_ext8s_i64) {
1634         tcg_gen_op2_i64(INDEX_op_ext8s_i64, ret, arg);
1635     } else {
1636         tcg_gen_shli_i64(ret, arg, 56);
1637         tcg_gen_sari_i64(ret, ret, 56);
1638     }
1639 }
1640
1641 static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg)
1642 {
1643     if (TCG_TARGET_HAS_ext16s_i64) {
1644         tcg_gen_op2_i64(INDEX_op_ext16s_i64, ret, arg);
1645     } else {
1646         tcg_gen_shli_i64(ret, arg, 48);
1647         tcg_gen_sari_i64(ret, ret, 48);
1648     }
1649 }
1650
1651 static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg)
1652 {
1653     if (TCG_TARGET_HAS_ext32s_i64) {
1654         tcg_gen_op2_i64(INDEX_op_ext32s_i64, ret, arg);
1655     } else {
1656         tcg_gen_shli_i64(ret, arg, 32);
1657         tcg_gen_sari_i64(ret, ret, 32);
1658     }
1659 }
1660
1661 static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg)
1662 {
1663     if (TCG_TARGET_HAS_ext8u_i64) {
1664         tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg);
1665     } else {
1666         tcg_gen_andi_i64(ret, arg, 0xffu);
1667     }
1668 }
1669
1670 static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg)
1671 {
1672     if (TCG_TARGET_HAS_ext16u_i64) {
1673         tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg);
1674     } else {
1675         tcg_gen_andi_i64(ret, arg, 0xffffu);
1676     }
1677 }
1678
1679 static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg)
1680 {
1681     if (TCG_TARGET_HAS_ext32u_i64) {
1682         tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg);
1683     } else {
1684         tcg_gen_andi_i64(ret, arg, 0xffffffffu);
1685     }
1686 }
1687
1688 /* Note: we assume the target supports move between 32 and 64 bit
1689    registers.  This will probably break MIPS64 targets.  */
1690 static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
1691 {
1692     tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg)));
1693 }
1694
1695 /* Note: we assume the target supports move between 32 and 64 bit
1696    registers */
1697 static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1698 {
1699     tcg_gen_ext32u_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg)));
1700 }
1701
1702 /* Note: we assume the target supports move between 32 and 64 bit
1703    registers */
1704 static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1705 {
1706     tcg_gen_ext32s_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg)));
1707 }
1708
1709 /* Note: we assume the six high bytes are set to zero */
1710 static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg)
1711 {
1712     if (TCG_TARGET_HAS_bswap16_i64) {
1713         tcg_gen_op2_i64(INDEX_op_bswap16_i64, ret, arg);
1714     } else {
1715         TCGv_i64 t0 = tcg_temp_new_i64();
1716
1717         tcg_gen_ext8u_i64(t0, arg);
1718         tcg_gen_shli_i64(t0, t0, 8);
1719         tcg_gen_shri_i64(ret, arg, 8);
1720         tcg_gen_or_i64(ret, ret, t0);
1721         tcg_temp_free_i64(t0);
1722     }
1723 }
1724
1725 /* Note: we assume the four high bytes are set to zero */
1726 static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg)
1727 {
1728     if (TCG_TARGET_HAS_bswap32_i64) {
1729         tcg_gen_op2_i64(INDEX_op_bswap32_i64, ret, arg);
1730     } else {
1731         TCGv_i64 t0, t1;
1732         t0 = tcg_temp_new_i64();
1733         t1 = tcg_temp_new_i64();
1734
1735         tcg_gen_shli_i64(t0, arg, 24);
1736         tcg_gen_ext32u_i64(t0, t0);
1737
1738         tcg_gen_andi_i64(t1, arg, 0x0000ff00);
1739         tcg_gen_shli_i64(t1, t1, 8);
1740         tcg_gen_or_i64(t0, t0, t1);
1741
1742         tcg_gen_shri_i64(t1, arg, 8);
1743         tcg_gen_andi_i64(t1, t1, 0x0000ff00);
1744         tcg_gen_or_i64(t0, t0, t1);
1745
1746         tcg_gen_shri_i64(t1, arg, 24);
1747         tcg_gen_or_i64(ret, t0, t1);
1748         tcg_temp_free_i64(t0);
1749         tcg_temp_free_i64(t1);
1750     }
1751 }
1752
1753 static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg)
1754 {
1755     if (TCG_TARGET_HAS_bswap64_i64) {
1756         tcg_gen_op2_i64(INDEX_op_bswap64_i64, ret, arg);
1757     } else {
1758         TCGv_i64 t0 = tcg_temp_new_i64();
1759         TCGv_i64 t1 = tcg_temp_new_i64();
1760
1761         tcg_gen_shli_i64(t0, arg, 56);
1762
1763         tcg_gen_andi_i64(t1, arg, 0x0000ff00);
1764         tcg_gen_shli_i64(t1, t1, 40);
1765         tcg_gen_or_i64(t0, t0, t1);
1766
1767         tcg_gen_andi_i64(t1, arg, 0x00ff0000);
1768         tcg_gen_shli_i64(t1, t1, 24);
1769         tcg_gen_or_i64(t0, t0, t1);
1770
1771         tcg_gen_andi_i64(t1, arg, 0xff000000);
1772         tcg_gen_shli_i64(t1, t1, 8);
1773         tcg_gen_or_i64(t0, t0, t1);
1774
1775         tcg_gen_shri_i64(t1, arg, 8);
1776         tcg_gen_andi_i64(t1, t1, 0xff000000);
1777         tcg_gen_or_i64(t0, t0, t1);
1778
1779         tcg_gen_shri_i64(t1, arg, 24);
1780         tcg_gen_andi_i64(t1, t1, 0x00ff0000);
1781         tcg_gen_or_i64(t0, t0, t1);
1782
1783         tcg_gen_shri_i64(t1, arg, 40);
1784         tcg_gen_andi_i64(t1, t1, 0x0000ff00);
1785         tcg_gen_or_i64(t0, t0, t1);
1786
1787         tcg_gen_shri_i64(t1, arg, 56);
1788         tcg_gen_or_i64(ret, t0, t1);
1789         tcg_temp_free_i64(t0);
1790         tcg_temp_free_i64(t1);
1791     }
1792 }
1793
1794 #endif
1795
1796 static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg)
1797 {
1798     if (TCG_TARGET_HAS_neg_i32) {
1799         tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg);
1800     } else {
1801         TCGv_i32 t0 = tcg_const_i32(0);
1802         tcg_gen_sub_i32(ret, t0, arg);
1803         tcg_temp_free_i32(t0);
1804     }
1805 }
1806
1807 static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg)
1808 {
1809     if (TCG_TARGET_HAS_neg_i64) {
1810         tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg);
1811     } else {
1812         TCGv_i64 t0 = tcg_const_i64(0);
1813         tcg_gen_sub_i64(ret, t0, arg);
1814         tcg_temp_free_i64(t0);
1815     }
1816 }
1817
1818 static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg)
1819 {
1820     if (TCG_TARGET_HAS_not_i32) {
1821         tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg);
1822     } else {
1823         tcg_gen_xori_i32(ret, arg, -1);
1824     }
1825 }
1826
1827 static inline void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg)
1828 {
1829 #if TCG_TARGET_REG_BITS == 64
1830     if (TCG_TARGET_HAS_not_i64) {
1831         tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg);
1832     } else {
1833         tcg_gen_xori_i64(ret, arg, -1);
1834     }
1835 #else
1836     tcg_gen_not_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1837     tcg_gen_not_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
1838 #endif
1839 }
1840
1841 static inline void tcg_gen_discard_i32(TCGv_i32 arg)
1842 {
1843     tcg_gen_op1_i32(INDEX_op_discard, arg);
1844 }
1845
1846 static inline void tcg_gen_discard_i64(TCGv_i64 arg)
1847 {
1848 #if TCG_TARGET_REG_BITS == 32
1849     tcg_gen_discard_i32(TCGV_LOW(arg));
1850     tcg_gen_discard_i32(TCGV_HIGH(arg));
1851 #else
1852     tcg_gen_op1_i64(INDEX_op_discard, arg);
1853 #endif
1854 }
1855
1856 static inline void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1857 {
1858     if (TCG_TARGET_HAS_andc_i32) {
1859         tcg_gen_op3_i32(INDEX_op_andc_i32, ret, arg1, arg2);
1860     } else {
1861         TCGv_i32 t0 = tcg_temp_new_i32();
1862         tcg_gen_not_i32(t0, arg2);
1863         tcg_gen_and_i32(ret, arg1, t0);
1864         tcg_temp_free_i32(t0);
1865     }
1866 }
1867
1868 static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1869 {
1870 #if TCG_TARGET_REG_BITS == 64
1871     if (TCG_TARGET_HAS_andc_i64) {
1872         tcg_gen_op3_i64(INDEX_op_andc_i64, ret, arg1, arg2);
1873     } else {
1874         TCGv_i64 t0 = tcg_temp_new_i64();
1875         tcg_gen_not_i64(t0, arg2);
1876         tcg_gen_and_i64(ret, arg1, t0);
1877         tcg_temp_free_i64(t0);
1878     }
1879 #else
1880     tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1881     tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1882 #endif
1883 }
1884
1885 static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1886 {
1887     if (TCG_TARGET_HAS_eqv_i32) {
1888         tcg_gen_op3_i32(INDEX_op_eqv_i32, ret, arg1, arg2);
1889     } else {
1890         tcg_gen_xor_i32(ret, arg1, arg2);
1891         tcg_gen_not_i32(ret, ret);
1892     }
1893 }
1894
1895 static inline void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1896 {
1897 #if TCG_TARGET_REG_BITS == 64
1898     if (TCG_TARGET_HAS_eqv_i64) {
1899         tcg_gen_op3_i64(INDEX_op_eqv_i64, ret, arg1, arg2);
1900     } else {
1901         tcg_gen_xor_i64(ret, arg1, arg2);
1902         tcg_gen_not_i64(ret, ret);
1903     }
1904 #else
1905     tcg_gen_eqv_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1906     tcg_gen_eqv_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1907 #endif
1908 }
1909
1910 static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1911 {
1912     if (TCG_TARGET_HAS_nand_i32) {
1913         tcg_gen_op3_i32(INDEX_op_nand_i32, ret, arg1, arg2);
1914     } else {
1915         tcg_gen_and_i32(ret, arg1, arg2);
1916         tcg_gen_not_i32(ret, ret);
1917     }
1918 }
1919
1920 static inline void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1921 {
1922 #if TCG_TARGET_REG_BITS == 64
1923     if (TCG_TARGET_HAS_nand_i64) {
1924         tcg_gen_op3_i64(INDEX_op_nand_i64, ret, arg1, arg2);
1925     } else {
1926         tcg_gen_and_i64(ret, arg1, arg2);
1927         tcg_gen_not_i64(ret, ret);
1928     }
1929 #else
1930     tcg_gen_nand_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1931     tcg_gen_nand_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1932 #endif
1933 }
1934
1935 static inline void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1936 {
1937     if (TCG_TARGET_HAS_nor_i32) {
1938         tcg_gen_op3_i32(INDEX_op_nor_i32, ret, arg1, arg2);
1939     } else {
1940         tcg_gen_or_i32(ret, arg1, arg2);
1941         tcg_gen_not_i32(ret, ret);
1942     }
1943 }
1944
1945 static inline void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1946 {
1947 #if TCG_TARGET_REG_BITS == 64
1948     if (TCG_TARGET_HAS_nor_i64) {
1949         tcg_gen_op3_i64(INDEX_op_nor_i64, ret, arg1, arg2);
1950     } else {
1951         tcg_gen_or_i64(ret, arg1, arg2);
1952         tcg_gen_not_i64(ret, ret);
1953     }
1954 #else
1955     tcg_gen_nor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1956     tcg_gen_nor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1957 #endif
1958 }
1959
1960 static inline void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1961 {
1962     if (TCG_TARGET_HAS_orc_i32) {
1963         tcg_gen_op3_i32(INDEX_op_orc_i32, ret, arg1, arg2);
1964     } else {
1965         TCGv_i32 t0 = tcg_temp_new_i32();
1966         tcg_gen_not_i32(t0, arg2);
1967         tcg_gen_or_i32(ret, arg1, t0);
1968         tcg_temp_free_i32(t0);
1969     }
1970 }
1971
1972 static inline void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1973 {
1974 #if TCG_TARGET_REG_BITS == 64
1975     if (TCG_TARGET_HAS_orc_i64) {
1976         tcg_gen_op3_i64(INDEX_op_orc_i64, ret, arg1, arg2);
1977     } else {
1978         TCGv_i64 t0 = tcg_temp_new_i64();
1979         tcg_gen_not_i64(t0, arg2);
1980         tcg_gen_or_i64(ret, arg1, t0);
1981         tcg_temp_free_i64(t0);
1982     }
1983 #else
1984     tcg_gen_orc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1985     tcg_gen_orc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1986 #endif
1987 }
1988
1989 static inline void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1990 {
1991     if (TCG_TARGET_HAS_rot_i32) {
1992         tcg_gen_op3_i32(INDEX_op_rotl_i32, ret, arg1, arg2);
1993     } else {
1994         TCGv_i32 t0, t1;
1995
1996         t0 = tcg_temp_new_i32();
1997         t1 = tcg_temp_new_i32();
1998         tcg_gen_shl_i32(t0, arg1, arg2);
1999         tcg_gen_subfi_i32(t1, 32, arg2);
2000         tcg_gen_shr_i32(t1, arg1, t1);
2001         tcg_gen_or_i32(ret, t0, t1);
2002         tcg_temp_free_i32(t0);
2003         tcg_temp_free_i32(t1);
2004     }
2005 }
2006
2007 static inline void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
2008 {
2009     if (TCG_TARGET_HAS_rot_i64) {
2010         tcg_gen_op3_i64(INDEX_op_rotl_i64, ret, arg1, arg2);
2011     } else {
2012         TCGv_i64 t0, t1;
2013         t0 = tcg_temp_new_i64();
2014         t1 = tcg_temp_new_i64();
2015         tcg_gen_shl_i64(t0, arg1, arg2);
2016         tcg_gen_subfi_i64(t1, 64, arg2);
2017         tcg_gen_shr_i64(t1, arg1, t1);
2018         tcg_gen_or_i64(ret, t0, t1);
2019         tcg_temp_free_i64(t0);
2020         tcg_temp_free_i64(t1);
2021     }
2022 }
2023
2024 static inline void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
2025 {
2026     /* some cases can be optimized here */
2027     if (arg2 == 0) {
2028         tcg_gen_mov_i32(ret, arg1);
2029     } else if (TCG_TARGET_HAS_rot_i32) {
2030         TCGv_i32 t0 = tcg_const_i32(arg2);
2031         tcg_gen_rotl_i32(ret, arg1, t0);
2032         tcg_temp_free_i32(t0);
2033     } else {
2034         TCGv_i32 t0, t1;
2035         t0 = tcg_temp_new_i32();
2036         t1 = tcg_temp_new_i32();
2037         tcg_gen_shli_i32(t0, arg1, arg2);
2038         tcg_gen_shri_i32(t1, arg1, 32 - arg2);
2039         tcg_gen_or_i32(ret, t0, t1);
2040         tcg_temp_free_i32(t0);
2041         tcg_temp_free_i32(t1);
2042     }
2043 }
2044
2045 static inline void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
2046 {
2047     /* some cases can be optimized here */
2048     if (arg2 == 0) {
2049         tcg_gen_mov_i64(ret, arg1);
2050     } else if (TCG_TARGET_HAS_rot_i64) {
2051         TCGv_i64 t0 = tcg_const_i64(arg2);
2052         tcg_gen_rotl_i64(ret, arg1, t0);
2053         tcg_temp_free_i64(t0);
2054     } else {
2055         TCGv_i64 t0, t1;
2056         t0 = tcg_temp_new_i64();
2057         t1 = tcg_temp_new_i64();
2058         tcg_gen_shli_i64(t0, arg1, arg2);
2059         tcg_gen_shri_i64(t1, arg1, 64 - arg2);
2060         tcg_gen_or_i64(ret, t0, t1);
2061         tcg_temp_free_i64(t0);
2062         tcg_temp_free_i64(t1);
2063     }
2064 }
2065
2066 static inline void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
2067 {
2068     if (TCG_TARGET_HAS_rot_i32) {
2069         tcg_gen_op3_i32(INDEX_op_rotr_i32, ret, arg1, arg2);
2070     } else {
2071         TCGv_i32 t0, t1;
2072
2073         t0 = tcg_temp_new_i32();
2074         t1 = tcg_temp_new_i32();
2075         tcg_gen_shr_i32(t0, arg1, arg2);
2076         tcg_gen_subfi_i32(t1, 32, arg2);
2077         tcg_gen_shl_i32(t1, arg1, t1);
2078         tcg_gen_or_i32(ret, t0, t1);
2079         tcg_temp_free_i32(t0);
2080         tcg_temp_free_i32(t1);
2081     }
2082 }
2083
2084 static inline void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
2085 {
2086     if (TCG_TARGET_HAS_rot_i64) {
2087         tcg_gen_op3_i64(INDEX_op_rotr_i64, ret, arg1, arg2);
2088     } else {
2089         TCGv_i64 t0, t1;
2090         t0 = tcg_temp_new_i64();
2091         t1 = tcg_temp_new_i64();
2092         tcg_gen_shr_i64(t0, arg1, arg2);
2093         tcg_gen_subfi_i64(t1, 64, arg2);
2094         tcg_gen_shl_i64(t1, arg1, t1);
2095         tcg_gen_or_i64(ret, t0, t1);
2096         tcg_temp_free_i64(t0);
2097         tcg_temp_free_i64(t1);
2098     }
2099 }
2100
2101 static inline void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
2102 {
2103     /* some cases can be optimized here */
2104     if (arg2 == 0) {
2105         tcg_gen_mov_i32(ret, arg1);
2106     } else {
2107         tcg_gen_rotli_i32(ret, arg1, 32 - arg2);
2108     }
2109 }
2110
2111 static inline void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
2112 {
2113     /* some cases can be optimized here */
2114     if (arg2 == 0) {
2115         tcg_gen_mov_i64(ret, arg1);
2116     } else {
2117         tcg_gen_rotli_i64(ret, arg1, 64 - arg2);
2118     }
2119 }
2120
2121 static inline void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1,
2122                                        TCGv_i32 arg2, unsigned int ofs,
2123                                        unsigned int len)
2124 {
2125     uint32_t mask;
2126     TCGv_i32 t1;
2127
2128     tcg_debug_assert(ofs < 32);
2129     tcg_debug_assert(len <= 32);
2130     tcg_debug_assert(ofs + len <= 32);
2131
2132     if (ofs == 0 && len == 32) {
2133         tcg_gen_mov_i32(ret, arg2);
2134         return;
2135     }
2136     if (TCG_TARGET_HAS_deposit_i32 && TCG_TARGET_deposit_i32_valid(ofs, len)) {
2137         tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, arg1, arg2, ofs, len);
2138         return;
2139     }
2140
2141     mask = (1u << len) - 1;
2142     t1 = tcg_temp_new_i32();
2143
2144     if (ofs + len < 32) {
2145         tcg_gen_andi_i32(t1, arg2, mask);
2146         tcg_gen_shli_i32(t1, t1, ofs);
2147     } else {
2148         tcg_gen_shli_i32(t1, arg2, ofs);
2149     }
2150     tcg_gen_andi_i32(ret, arg1, ~(mask << ofs));
2151     tcg_gen_or_i32(ret, ret, t1);
2152
2153     tcg_temp_free_i32(t1);
2154 }
2155
2156 static inline void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1,
2157                                        TCGv_i64 arg2, unsigned int ofs,
2158                                        unsigned int len)
2159 {
2160     uint64_t mask;
2161     TCGv_i64 t1;
2162
2163     tcg_debug_assert(ofs < 64);
2164     tcg_debug_assert(len <= 64);
2165     tcg_debug_assert(ofs + len <= 64);
2166
2167     if (ofs == 0 && len == 64) {
2168         tcg_gen_mov_i64(ret, arg2);
2169         return;
2170     }
2171     if (TCG_TARGET_HAS_deposit_i64 && TCG_TARGET_deposit_i64_valid(ofs, len)) {
2172         tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret, arg1, arg2, ofs, len);
2173         return;
2174     }
2175
2176 #if TCG_TARGET_REG_BITS == 32
2177     if (ofs >= 32) {
2178         tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg1));
2179         tcg_gen_deposit_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1),
2180                             TCGV_LOW(arg2), ofs - 32, len);
2181         return;
2182     }
2183     if (ofs + len <= 32) {
2184         tcg_gen_deposit_i32(TCGV_LOW(ret), TCGV_LOW(arg1),
2185                             TCGV_LOW(arg2), ofs, len);
2186         tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1));
2187         return;
2188     }
2189 #endif
2190
2191     mask = (1ull << len) - 1;
2192     t1 = tcg_temp_new_i64();
2193
2194     if (ofs + len < 64) {
2195         tcg_gen_andi_i64(t1, arg2, mask);
2196         tcg_gen_shli_i64(t1, t1, ofs);
2197     } else {
2198         tcg_gen_shli_i64(t1, arg2, ofs);
2199     }
2200     tcg_gen_andi_i64(ret, arg1, ~(mask << ofs));
2201     tcg_gen_or_i64(ret, ret, t1);
2202
2203     tcg_temp_free_i64(t1);
2204 }
2205
2206 static inline void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low,
2207                                           TCGv_i32 high)
2208 {
2209 #if TCG_TARGET_REG_BITS == 32
2210     tcg_gen_mov_i32(TCGV_LOW(dest), low);
2211     tcg_gen_mov_i32(TCGV_HIGH(dest), high);
2212 #else
2213     TCGv_i64 tmp = tcg_temp_new_i64();
2214     /* These extensions are only needed for type correctness.
2215        We may be able to do better given target specific information.  */
2216     tcg_gen_extu_i32_i64(tmp, high);
2217     tcg_gen_extu_i32_i64(dest, low);
2218     /* If deposit is available, use it.  Otherwise use the extra
2219        knowledge that we have of the zero-extensions above.  */
2220     if (TCG_TARGET_HAS_deposit_i64 && TCG_TARGET_deposit_i64_valid(32, 32)) {
2221         tcg_gen_deposit_i64(dest, dest, tmp, 32, 32);
2222     } else {
2223         tcg_gen_shli_i64(tmp, tmp, 32);
2224         tcg_gen_or_i64(dest, dest, tmp);
2225     }
2226     tcg_temp_free_i64(tmp);
2227 #endif
2228 }
2229
2230 static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low,
2231                                         TCGv_i64 high)
2232 {
2233     tcg_gen_deposit_i64(dest, low, high, 32, 32);
2234 }
2235
2236 static inline void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret,
2237                                        TCGv_i32 c1, TCGv_i32 c2,
2238                                        TCGv_i32 v1, TCGv_i32 v2)
2239 {
2240     if (TCG_TARGET_HAS_movcond_i32) {
2241         tcg_gen_op6i_i32(INDEX_op_movcond_i32, ret, c1, c2, v1, v2, cond);
2242     } else {
2243         TCGv_i32 t0 = tcg_temp_new_i32();
2244         TCGv_i32 t1 = tcg_temp_new_i32();
2245         tcg_gen_setcond_i32(cond, t0, c1, c2);
2246         tcg_gen_neg_i32(t0, t0);
2247         tcg_gen_and_i32(t1, v1, t0);
2248         tcg_gen_andc_i32(ret, v2, t0);
2249         tcg_gen_or_i32(ret, ret, t1);
2250         tcg_temp_free_i32(t0);
2251         tcg_temp_free_i32(t1);
2252     }
2253 }
2254
2255 static inline void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret,
2256                                        TCGv_i64 c1, TCGv_i64 c2,
2257                                        TCGv_i64 v1, TCGv_i64 v2)
2258 {
2259 #if TCG_TARGET_REG_BITS == 32
2260     TCGv_i32 t0 = tcg_temp_new_i32();
2261     TCGv_i32 t1 = tcg_temp_new_i32();
2262     tcg_gen_op6i_i32(INDEX_op_setcond2_i32, t0,
2263                      TCGV_LOW(c1), TCGV_HIGH(c1),
2264                      TCGV_LOW(c2), TCGV_HIGH(c2), cond);
2265
2266     if (TCG_TARGET_HAS_movcond_i32) {
2267         tcg_gen_movi_i32(t1, 0);
2268         tcg_gen_movcond_i32(TCG_COND_NE, TCGV_LOW(ret), t0, t1,
2269                             TCGV_LOW(v1), TCGV_LOW(v2));
2270         tcg_gen_movcond_i32(TCG_COND_NE, TCGV_HIGH(ret), t0, t1,
2271                             TCGV_HIGH(v1), TCGV_HIGH(v2));
2272     } else {
2273         tcg_gen_neg_i32(t0, t0);
2274
2275         tcg_gen_and_i32(t1, TCGV_LOW(v1), t0);
2276         tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(v2), t0);
2277         tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(ret), t1);
2278
2279         tcg_gen_and_i32(t1, TCGV_HIGH(v1), t0);
2280         tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(v2), t0);
2281         tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), t1);
2282     }
2283     tcg_temp_free_i32(t0);
2284     tcg_temp_free_i32(t1);
2285 #else
2286     if (TCG_TARGET_HAS_movcond_i64) {
2287         tcg_gen_op6i_i64(INDEX_op_movcond_i64, ret, c1, c2, v1, v2, cond);
2288     } else {
2289         TCGv_i64 t0 = tcg_temp_new_i64();
2290         TCGv_i64 t1 = tcg_temp_new_i64();
2291         tcg_gen_setcond_i64(cond, t0, c1, c2);
2292         tcg_gen_neg_i64(t0, t0);
2293         tcg_gen_and_i64(t1, v1, t0);
2294         tcg_gen_andc_i64(ret, v2, t0);
2295         tcg_gen_or_i64(ret, ret, t1);
2296         tcg_temp_free_i64(t0);
2297         tcg_temp_free_i64(t1);
2298     }
2299 #endif
2300 }
2301
2302 /***************************************/
2303 /* QEMU specific operations. Their type depend on the QEMU CPU
2304    type. */
2305 #ifndef TARGET_LONG_BITS
2306 #error must include QEMU headers
2307 #endif
2308
2309 #if TARGET_LONG_BITS == 32
2310 #define TCGv TCGv_i32
2311 #define tcg_temp_new() tcg_temp_new_i32()
2312 #define tcg_global_reg_new tcg_global_reg_new_i32
2313 #define tcg_global_mem_new tcg_global_mem_new_i32
2314 #define tcg_temp_local_new() tcg_temp_local_new_i32()
2315 #define tcg_temp_free tcg_temp_free_i32
2316 #define tcg_gen_qemu_ldst_op tcg_gen_op3i_i32
2317 #define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i32
2318 #define TCGV_UNUSED(x) TCGV_UNUSED_I32(x)
2319 #define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b)
2320 #else
2321 #define TCGv TCGv_i64
2322 #define tcg_temp_new() tcg_temp_new_i64()
2323 #define tcg_global_reg_new tcg_global_reg_new_i64
2324 #define tcg_global_mem_new tcg_global_mem_new_i64
2325 #define tcg_temp_local_new() tcg_temp_local_new_i64()
2326 #define tcg_temp_free tcg_temp_free_i64
2327 #define tcg_gen_qemu_ldst_op tcg_gen_op3i_i64
2328 #define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i64
2329 #define TCGV_UNUSED(x) TCGV_UNUSED_I64(x)
2330 #define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b)
2331 #endif
2332
2333 /* debug info: write the PC of the corresponding QEMU CPU instruction */
2334 static inline void tcg_gen_debug_insn_start(uint64_t pc)
2335 {
2336     /* XXX: must really use a 32 bit size for TCGArg in all cases */
2337 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
2338     tcg_gen_op2ii(INDEX_op_debug_insn_start,
2339                   (uint32_t)(pc), (uint32_t)(pc >> 32));
2340 #else
2341     tcg_gen_op1i(INDEX_op_debug_insn_start, pc);
2342 #endif
2343 }
2344
2345 static inline void tcg_gen_exit_tb(tcg_target_long val)
2346 {
2347     tcg_gen_op1i(INDEX_op_exit_tb, val);
2348 }
2349
2350 static inline void tcg_gen_goto_tb(unsigned idx)
2351 {
2352     /* We only support two chained exits.  */
2353     tcg_debug_assert(idx <= 1);
2354 #ifdef CONFIG_DEBUG_TCG
2355     /* Verify that we havn't seen this numbered exit before.  */
2356     tcg_debug_assert((tcg_ctx.goto_tb_issue_mask & (1 << idx)) == 0);
2357     tcg_ctx.goto_tb_issue_mask |= 1 << idx;
2358 #endif
2359     tcg_gen_op1i(INDEX_op_goto_tb, idx);
2360 }
2361
2362 #if TCG_TARGET_REG_BITS == 32
2363 static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
2364 {
2365 #if TARGET_LONG_BITS == 32
2366     tcg_gen_op3i_i32(INDEX_op_qemu_ld8u, ret, addr, mem_index);
2367 #else
2368     tcg_gen_op4i_i32(INDEX_op_qemu_ld8u, TCGV_LOW(ret), TCGV_LOW(addr),
2369                      TCGV_HIGH(addr), mem_index);
2370     tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
2371 #endif
2372 }
2373
2374 static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
2375 {
2376 #if TARGET_LONG_BITS == 32
2377     tcg_gen_op3i_i32(INDEX_op_qemu_ld8s, ret, addr, mem_index);
2378 #else
2379     tcg_gen_op4i_i32(INDEX_op_qemu_ld8s, TCGV_LOW(ret), TCGV_LOW(addr),
2380                      TCGV_HIGH(addr), mem_index);
2381     tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
2382 #endif
2383 }
2384
2385 static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
2386 {
2387 #if TARGET_LONG_BITS == 32
2388     tcg_gen_op3i_i32(INDEX_op_qemu_ld16u, ret, addr, mem_index);
2389 #else
2390     tcg_gen_op4i_i32(INDEX_op_qemu_ld16u, TCGV_LOW(ret), TCGV_LOW(addr),
2391                      TCGV_HIGH(addr), mem_index);
2392     tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
2393 #endif
2394 }
2395
2396 static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
2397 {
2398 #if TARGET_LONG_BITS == 32
2399     tcg_gen_op3i_i32(INDEX_op_qemu_ld16s, ret, addr, mem_index);
2400 #else
2401     tcg_gen_op4i_i32(INDEX_op_qemu_ld16s, TCGV_LOW(ret), TCGV_LOW(addr),
2402                      TCGV_HIGH(addr), mem_index);
2403     tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
2404 #endif
2405 }
2406
2407 static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
2408 {
2409 #if TARGET_LONG_BITS == 32
2410     tcg_gen_op3i_i32(INDEX_op_qemu_ld32, ret, addr, mem_index);
2411 #else
2412     tcg_gen_op4i_i32(INDEX_op_qemu_ld32, TCGV_LOW(ret), TCGV_LOW(addr),
2413                      TCGV_HIGH(addr), mem_index);
2414     tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
2415 #endif
2416 }
2417
2418 static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
2419 {
2420 #if TARGET_LONG_BITS == 32
2421     tcg_gen_op3i_i32(INDEX_op_qemu_ld32, ret, addr, mem_index);
2422 #else
2423     tcg_gen_op4i_i32(INDEX_op_qemu_ld32, TCGV_LOW(ret), TCGV_LOW(addr),
2424                      TCGV_HIGH(addr), mem_index);
2425     tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
2426 #endif
2427 }
2428
2429 static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
2430 {
2431 #if TARGET_LONG_BITS == 32
2432     tcg_gen_op4i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), addr, mem_index);
2433 #else
2434     tcg_gen_op5i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret),
2435                      TCGV_LOW(addr), TCGV_HIGH(addr), mem_index);
2436 #endif
2437 }
2438
2439 static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
2440 {
2441 #if TARGET_LONG_BITS == 32
2442     tcg_gen_op3i_i32(INDEX_op_qemu_st8, arg, addr, mem_index);
2443 #else
2444     tcg_gen_op4i_i32(INDEX_op_qemu_st8, TCGV_LOW(arg), TCGV_LOW(addr),
2445                      TCGV_HIGH(addr), mem_index);
2446 #endif
2447 }
2448
2449 static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
2450 {
2451 #if TARGET_LONG_BITS == 32
2452     tcg_gen_op3i_i32(INDEX_op_qemu_st16, arg, addr, mem_index);
2453 #else
2454     tcg_gen_op4i_i32(INDEX_op_qemu_st16, TCGV_LOW(arg), TCGV_LOW(addr),
2455                      TCGV_HIGH(addr), mem_index);
2456 #endif
2457 }
2458
2459 static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
2460 {
2461 #if TARGET_LONG_BITS == 32
2462     tcg_gen_op3i_i32(INDEX_op_qemu_st32, arg, addr, mem_index);
2463 #else
2464     tcg_gen_op4i_i32(INDEX_op_qemu_st32, TCGV_LOW(arg), TCGV_LOW(addr),
2465                      TCGV_HIGH(addr), mem_index);
2466 #endif
2467 }
2468
2469 static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
2470 {
2471 #if TARGET_LONG_BITS == 32
2472     tcg_gen_op4i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), addr,
2473                      mem_index);
2474 #else
2475     tcg_gen_op5i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg),
2476                      TCGV_LOW(addr), TCGV_HIGH(addr), mem_index);
2477 #endif
2478 }
2479
2480 #define tcg_gen_ld_ptr(R, A, O) tcg_gen_ld_i32(TCGV_PTR_TO_NAT(R), (A), (O))
2481 #define tcg_gen_discard_ptr(A) tcg_gen_discard_i32(TCGV_PTR_TO_NAT(A))
2482
2483 #else /* TCG_TARGET_REG_BITS == 32 */
2484
2485 static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
2486 {
2487     tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8u, ret, addr, mem_index);
2488 }
2489
2490 static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
2491 {
2492     tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8s, ret, addr, mem_index);
2493 }
2494
2495 static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
2496 {
2497     tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16u, ret, addr, mem_index);
2498 }
2499
2500 static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
2501 {
2502     tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16s, ret, addr, mem_index);
2503 }
2504
2505 static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
2506 {
2507 #if TARGET_LONG_BITS == 32
2508     tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32, ret, addr, mem_index);
2509 #else
2510     tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32u, ret, addr, mem_index);
2511 #endif
2512 }
2513
2514 static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
2515 {
2516 #if TARGET_LONG_BITS == 32
2517     tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32, ret, addr, mem_index);
2518 #else
2519     tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32s, ret, addr, mem_index);
2520 #endif
2521 }
2522
2523 static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
2524 {
2525     tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_ld64, ret, addr, mem_index);
2526 }
2527
2528 static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
2529 {
2530     tcg_gen_qemu_ldst_op(INDEX_op_qemu_st8, arg, addr, mem_index);
2531 }
2532
2533 static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
2534 {
2535     tcg_gen_qemu_ldst_op(INDEX_op_qemu_st16, arg, addr, mem_index);
2536 }
2537
2538 static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
2539 {
2540     tcg_gen_qemu_ldst_op(INDEX_op_qemu_st32, arg, addr, mem_index);
2541 }
2542
2543 static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
2544 {
2545     tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_st64, arg, addr, mem_index);
2546 }
2547
2548 #define tcg_gen_ld_ptr(R, A, O) tcg_gen_ld_i64(TCGV_PTR_TO_NAT(R), (A), (O))
2549 #define tcg_gen_discard_ptr(A) tcg_gen_discard_i64(TCGV_PTR_TO_NAT(A))
2550
2551 #endif /* TCG_TARGET_REG_BITS != 32 */
2552
2553 #if TARGET_LONG_BITS == 64
2554 #define tcg_gen_movi_tl tcg_gen_movi_i64
2555 #define tcg_gen_mov_tl tcg_gen_mov_i64
2556 #define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
2557 #define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
2558 #define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
2559 #define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
2560 #define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
2561 #define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
2562 #define tcg_gen_ld_tl tcg_gen_ld_i64
2563 #define tcg_gen_st8_tl tcg_gen_st8_i64
2564 #define tcg_gen_st16_tl tcg_gen_st16_i64
2565 #define tcg_gen_st32_tl tcg_gen_st32_i64
2566 #define tcg_gen_st_tl tcg_gen_st_i64
2567 #define tcg_gen_add_tl tcg_gen_add_i64
2568 #define tcg_gen_addi_tl tcg_gen_addi_i64
2569 #define tcg_gen_sub_tl tcg_gen_sub_i64
2570 #define tcg_gen_neg_tl tcg_gen_neg_i64
2571 #define tcg_gen_subfi_tl tcg_gen_subfi_i64
2572 #define tcg_gen_subi_tl tcg_gen_subi_i64
2573 #define tcg_gen_and_tl tcg_gen_and_i64
2574 #define tcg_gen_andi_tl tcg_gen_andi_i64
2575 #define tcg_gen_or_tl tcg_gen_or_i64
2576 #define tcg_gen_ori_tl tcg_gen_ori_i64
2577 #define tcg_gen_xor_tl tcg_gen_xor_i64
2578 #define tcg_gen_xori_tl tcg_gen_xori_i64
2579 #define tcg_gen_not_tl tcg_gen_not_i64
2580 #define tcg_gen_shl_tl tcg_gen_shl_i64
2581 #define tcg_gen_shli_tl tcg_gen_shli_i64
2582 #define tcg_gen_shr_tl tcg_gen_shr_i64
2583 #define tcg_gen_shri_tl tcg_gen_shri_i64
2584 #define tcg_gen_sar_tl tcg_gen_sar_i64
2585 #define tcg_gen_sari_tl tcg_gen_sari_i64
2586 #define tcg_gen_brcond_tl tcg_gen_brcond_i64
2587 #define tcg_gen_brcondi_tl tcg_gen_brcondi_i64
2588 #define tcg_gen_setcond_tl tcg_gen_setcond_i64
2589 #define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
2590 #define tcg_gen_mul_tl tcg_gen_mul_i64
2591 #define tcg_gen_muli_tl tcg_gen_muli_i64
2592 #define tcg_gen_div_tl tcg_gen_div_i64
2593 #define tcg_gen_rem_tl tcg_gen_rem_i64
2594 #define tcg_gen_divu_tl tcg_gen_divu_i64
2595 #define tcg_gen_remu_tl tcg_gen_remu_i64
2596 #define tcg_gen_discard_tl tcg_gen_discard_i64
2597 #define tcg_gen_trunc_tl_i32 tcg_gen_trunc_i64_i32
2598 #define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
2599 #define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
2600 #define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
2601 #define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
2602 #define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
2603 #define tcg_gen_ext8u_tl tcg_gen_ext8u_i64
2604 #define tcg_gen_ext8s_tl tcg_gen_ext8s_i64
2605 #define tcg_gen_ext16u_tl tcg_gen_ext16u_i64
2606 #define tcg_gen_ext16s_tl tcg_gen_ext16s_i64
2607 #define tcg_gen_ext32u_tl tcg_gen_ext32u_i64
2608 #define tcg_gen_ext32s_tl tcg_gen_ext32s_i64
2609 #define tcg_gen_bswap16_tl tcg_gen_bswap16_i64
2610 #define tcg_gen_bswap32_tl tcg_gen_bswap32_i64
2611 #define tcg_gen_bswap64_tl tcg_gen_bswap64_i64
2612 #define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
2613 #define tcg_gen_andc_tl tcg_gen_andc_i64
2614 #define tcg_gen_eqv_tl tcg_gen_eqv_i64
2615 #define tcg_gen_nand_tl tcg_gen_nand_i64
2616 #define tcg_gen_nor_tl tcg_gen_nor_i64
2617 #define tcg_gen_orc_tl tcg_gen_orc_i64
2618 #define tcg_gen_rotl_tl tcg_gen_rotl_i64
2619 #define tcg_gen_rotli_tl tcg_gen_rotli_i64
2620 #define tcg_gen_rotr_tl tcg_gen_rotr_i64
2621 #define tcg_gen_rotri_tl tcg_gen_rotri_i64
2622 #define tcg_gen_deposit_tl tcg_gen_deposit_i64
2623 #define tcg_const_tl tcg_const_i64
2624 #define tcg_const_local_tl tcg_const_local_i64
2625 #define tcg_gen_movcond_tl tcg_gen_movcond_i64
2626 #else
2627 #define tcg_gen_movi_tl tcg_gen_movi_i32
2628 #define tcg_gen_mov_tl tcg_gen_mov_i32
2629 #define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
2630 #define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
2631 #define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
2632 #define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
2633 #define tcg_gen_ld32u_tl tcg_gen_ld_i32
2634 #define tcg_gen_ld32s_tl tcg_gen_ld_i32
2635 #define tcg_gen_ld_tl tcg_gen_ld_i32
2636 #define tcg_gen_st8_tl tcg_gen_st8_i32
2637 #define tcg_gen_st16_tl tcg_gen_st16_i32
2638 #define tcg_gen_st32_tl tcg_gen_st_i32
2639 #define tcg_gen_st_tl tcg_gen_st_i32
2640 #define tcg_gen_add_tl tcg_gen_add_i32
2641 #define tcg_gen_addi_tl tcg_gen_addi_i32
2642 #define tcg_gen_sub_tl tcg_gen_sub_i32
2643 #define tcg_gen_neg_tl tcg_gen_neg_i32
2644 #define tcg_gen_subfi_tl tcg_gen_subfi_i32
2645 #define tcg_gen_subi_tl tcg_gen_subi_i32
2646 #define tcg_gen_and_tl tcg_gen_and_i32
2647 #define tcg_gen_andi_tl tcg_gen_andi_i32
2648 #define tcg_gen_or_tl tcg_gen_or_i32
2649 #define tcg_gen_ori_tl tcg_gen_ori_i32
2650 #define tcg_gen_xor_tl tcg_gen_xor_i32
2651 #define tcg_gen_xori_tl tcg_gen_xori_i32
2652 #define tcg_gen_not_tl tcg_gen_not_i32
2653 #define tcg_gen_shl_tl tcg_gen_shl_i32
2654 #define tcg_gen_shli_tl tcg_gen_shli_i32
2655 #define tcg_gen_shr_tl tcg_gen_shr_i32
2656 #define tcg_gen_shri_tl tcg_gen_shri_i32
2657 #define tcg_gen_sar_tl tcg_gen_sar_i32
2658 #define tcg_gen_sari_tl tcg_gen_sari_i32
2659 #define tcg_gen_brcond_tl tcg_gen_brcond_i32
2660 #define tcg_gen_brcondi_tl tcg_gen_brcondi_i32
2661 #define tcg_gen_setcond_tl tcg_gen_setcond_i32
2662 #define tcg_gen_setcondi_tl tcg_gen_setcondi_i32
2663 #define tcg_gen_mul_tl tcg_gen_mul_i32
2664 #define tcg_gen_muli_tl tcg_gen_muli_i32
2665 #define tcg_gen_div_tl tcg_gen_div_i32
2666 #define tcg_gen_rem_tl tcg_gen_rem_i32
2667 #define tcg_gen_divu_tl tcg_gen_divu_i32
2668 #define tcg_gen_remu_tl tcg_gen_remu_i32
2669 #define tcg_gen_discard_tl tcg_gen_discard_i32
2670 #define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
2671 #define tcg_gen_trunc_i64_tl tcg_gen_trunc_i64_i32
2672 #define tcg_gen_extu_i32_tl tcg_gen_mov_i32
2673 #define tcg_gen_ext_i32_tl tcg_gen_mov_i32
2674 #define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
2675 #define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
2676 #define tcg_gen_ext8u_tl tcg_gen_ext8u_i32
2677 #define tcg_gen_ext8s_tl tcg_gen_ext8s_i32
2678 #define tcg_gen_ext16u_tl tcg_gen_ext16u_i32
2679 #define tcg_gen_ext16s_tl tcg_gen_ext16s_i32
2680 #define tcg_gen_ext32u_tl tcg_gen_mov_i32
2681 #define tcg_gen_ext32s_tl tcg_gen_mov_i32
2682 #define tcg_gen_bswap16_tl tcg_gen_bswap16_i32
2683 #define tcg_gen_bswap32_tl tcg_gen_bswap32_i32
2684 #define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
2685 #define tcg_gen_andc_tl tcg_gen_andc_i32
2686 #define tcg_gen_eqv_tl tcg_gen_eqv_i32
2687 #define tcg_gen_nand_tl tcg_gen_nand_i32
2688 #define tcg_gen_nor_tl tcg_gen_nor_i32
2689 #define tcg_gen_orc_tl tcg_gen_orc_i32
2690 #define tcg_gen_rotl_tl tcg_gen_rotl_i32
2691 #define tcg_gen_rotli_tl tcg_gen_rotli_i32
2692 #define tcg_gen_rotr_tl tcg_gen_rotr_i32
2693 #define tcg_gen_rotri_tl tcg_gen_rotri_i32
2694 #define tcg_gen_deposit_tl tcg_gen_deposit_i32
2695 #define tcg_const_tl tcg_const_i32
2696 #define tcg_const_local_tl tcg_const_local_i32
2697 #define tcg_gen_movcond_tl tcg_gen_movcond_i32
2698 #endif
2699
2700 #if TCG_TARGET_REG_BITS == 32
2701 #define tcg_gen_add_ptr(R, A, B) tcg_gen_add_i32(TCGV_PTR_TO_NAT(R), \
2702                                                TCGV_PTR_TO_NAT(A), \
2703                                                TCGV_PTR_TO_NAT(B))
2704 #define tcg_gen_addi_ptr(R, A, B) tcg_gen_addi_i32(TCGV_PTR_TO_NAT(R), \
2705                                                  TCGV_PTR_TO_NAT(A), (B))
2706 #define tcg_gen_ext_i32_ptr(R, A) tcg_gen_mov_i32(TCGV_PTR_TO_NAT(R), (A))
2707 #else /* TCG_TARGET_REG_BITS == 32 */
2708 #define tcg_gen_add_ptr(R, A, B) tcg_gen_add_i64(TCGV_PTR_TO_NAT(R), \
2709                                                TCGV_PTR_TO_NAT(A), \
2710                                                TCGV_PTR_TO_NAT(B))
2711 #define tcg_gen_addi_ptr(R, A, B) tcg_gen_addi_i64(TCGV_PTR_TO_NAT(R),   \
2712                                                  TCGV_PTR_TO_NAT(A), (B))
2713 #define tcg_gen_ext_i32_ptr(R, A) tcg_gen_ext_i32_i64(TCGV_PTR_TO_NAT(R), (A))
2714 #endif /* TCG_TARGET_REG_BITS != 32 */