tcg/tcg-op.h

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2008 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "tcg.h"
  25
  26 #ifdef CONFIG_DYNGEN_OP
  27 /* legacy dyngen operations */
  28 #include "gen-op.h"
  29 #endif
  30
  31 int gen_new_label(void);
  32
  33 static inline void tcg_gen_op1_i32(int opc, TCGv_i32 arg1)
  34 {
  35     *gen_opc_ptr++ = opc;
  36     *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
  37 }
  38
  39 static inline void tcg_gen_op1_i64(int opc, TCGv_i64 arg1)
  40 {
  41     *gen_opc_ptr++ = opc;
  42     *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
  43 }
  44
  45 static inline void tcg_gen_op1i(int opc, TCGArg arg1)
  46 {
  47     *gen_opc_ptr++ = opc;
  48     *gen_opparam_ptr++ = arg1;
  49 }
  50
  51 static inline void tcg_gen_op2_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2)
  52 {
  53     *gen_opc_ptr++ = opc;
  54     *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
  55     *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
  56 }
  57
  58 static inline void tcg_gen_op2_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2)
  59 {
  60     *gen_opc_ptr++ = opc;
  61     *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
  62     *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
  63 }
  64
  65 static inline void tcg_gen_op2i_i32(int opc, TCGv_i32 arg1, TCGArg arg2)
  66 {
  67     *gen_opc_ptr++ = opc;
  68     *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
  69     *gen_opparam_ptr++ = arg2;
  70 }
  71
  72 static inline void tcg_gen_op2i_i64(int opc, TCGv_i64 arg1, TCGArg arg2)
  73 {
  74     *gen_opc_ptr++ = opc;
  75     *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
  76     *gen_opparam_ptr++ = arg2;
  77 }
  78
  79 static inline void tcg_gen_op2ii(int opc, TCGArg arg1, TCGArg arg2)
  80 {
  81     *gen_opc_ptr++ = opc;
  82     *gen_opparam_ptr++ = arg1;
  83     *gen_opparam_ptr++ = arg2;
  84 }
  85
  86 static inline void tcg_gen_op3_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
  87                                    TCGv_i32 arg3)
  88 {
  89     *gen_opc_ptr++ = opc;
  90     *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
  91     *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
  92     *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
  93 }
  94
  95 static inline void tcg_gen_op3_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
  96                                    TCGv_i64 arg3)
  97 {
  98     *gen_opc_ptr++ = opc;
  99     *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
 100     *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
 101     *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
 102 }
 103
 104 static inline void tcg_gen_op3i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
 105                                     TCGArg arg3)
 106 {
 107     *gen_opc_ptr++ = opc;
 108     *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
 109     *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
 110     *gen_opparam_ptr++ = arg3;
 111 }
 112
 113 static inline void tcg_gen_op3i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
 114                                     TCGArg arg3)
 115 {
 116     *gen_opc_ptr++ = opc;
 117     *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
 118     *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
 119     *gen_opparam_ptr++ = arg3;
 120 }
 121
 122 static inline void tcg_gen_ldst_op_i32(int opc, TCGv_i32 val, TCGv_ptr base,
 123                                        TCGArg offset)
 124 {
 125     *gen_opc_ptr++ = opc;
 126     *gen_opparam_ptr++ = GET_TCGV_I32(val);
 127     *gen_opparam_ptr++ = GET_TCGV_PTR(base);
 128     *gen_opparam_ptr++ = offset;
 129 }
 130
 131 static inline void tcg_gen_ldst_op_i64(int opc, TCGv_i64 val, TCGv_ptr base,
 132                                        TCGArg offset)
 133 {
 134     *gen_opc_ptr++ = opc;
 135     *gen_opparam_ptr++ = GET_TCGV_I32(val);
 136     *gen_opparam_ptr++ = GET_TCGV_PTR(base);
 137     *gen_opparam_ptr++ = offset;
 138 }
 139
 140 static inline void tcg_gen_qemu_ldst_op_i64_i32(int opc, TCGv_i64 val, TCGv_i32 addr,
 141                                                 TCGArg mem_index)
 142 {
 143     *gen_opc_ptr++ = opc;
 144     *gen_opparam_ptr++ = GET_TCGV_I64(val);
 145     *gen_opparam_ptr++ = GET_TCGV_I32(addr);
 146     *gen_opparam_ptr++ = mem_index;
 147 }
 148
 149 static inline void tcg_gen_qemu_ldst_op_i64_i64(int opc, TCGv_i64 val, TCGv_i64 addr,
 150                                                 TCGArg mem_index)
 151 {
 152     *gen_opc_ptr++ = opc;
 153     *gen_opparam_ptr++ = GET_TCGV_I64(val);
 154     *gen_opparam_ptr++ = GET_TCGV_I64(addr);
 155     *gen_opparam_ptr++ = mem_index;
 156 }
 157
 158 static inline void tcg_gen_op4_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
 159                                    TCGv_i32 arg3, TCGv_i32 arg4)
 160 {
 161     *gen_opc_ptr++ = opc;
 162     *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
 163     *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
 164     *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
 165     *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
 166 }
 167
 168 static inline void tcg_gen_op4_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
 169                                    TCGv_i64 arg3, TCGv_i32 arg4)
 170 {
 171     *gen_opc_ptr++ = opc;
 172     *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
 173     *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
 174     *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
 175     *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
 176 }
 177
 178 static inline void tcg_gen_op4i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
 179                                     TCGv_i32 arg3, TCGArg arg4)
 180 {
 181     *gen_opc_ptr++ = opc;
 182     *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
 183     *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
 184     *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
 185     *gen_opparam_ptr++ = arg4;
 186 }
 187
 188 static inline void tcg_gen_op4i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
 189                                     TCGv_i64 arg3, TCGArg arg4)
 190 {
 191     *gen_opc_ptr++ = opc;
 192     *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
 193     *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
 194     *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
 195     *gen_opparam_ptr++ = arg4;
 196 }
 197
 198 static inline void tcg_gen_op4ii_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
 199                                      TCGArg arg3, TCGArg arg4)
 200 {
 201     *gen_opc_ptr++ = opc;
 202     *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
 203     *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
 204     *gen_opparam_ptr++ = arg3;
 205     *gen_opparam_ptr++ = arg4;
 206 }
 207
 208 static inline void tcg_gen_op4ii_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
 209                                      TCGArg arg3, TCGArg arg4)
 210 {
 211     *gen_opc_ptr++ = opc;
 212     *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
 213     *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
 214     *gen_opparam_ptr++ = arg3;
 215     *gen_opparam_ptr++ = arg4;
 216 }
 217
 218 static inline void tcg_gen_op5_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
 219                                    TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5)
 220 {
 221     *gen_opc_ptr++ = opc;
 222     *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
 223     *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
 224     *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
 225     *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
 226     *gen_opparam_ptr++ = GET_TCGV_I32(arg5);
 227 }
 228
 229 static inline void tcg_gen_op5_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
 230                                    TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5)
 231 {
 232     *gen_opc_ptr++ = opc;
 233     *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
 234     *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
 235     *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
 236     *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
 237     *gen_opparam_ptr++ = GET_TCGV_I64(arg5);
 238 }
 239
 240 static inline void tcg_gen_op5i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
 241                                     TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5)
 242 {
 243     *gen_opc_ptr++ = opc;
 244     *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
 245     *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
 246     *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
 247     *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
 248     *gen_opparam_ptr++ = arg5;
 249 }
 250
 251 static inline void tcg_gen_op5i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
 252                                     TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5)
 253 {
 254     *gen_opc_ptr++ = opc;
 255     *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
 256     *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
 257     *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
 258     *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
 259     *gen_opparam_ptr++ = arg5;
 260 }
 261
 262 static inline void tcg_gen_op6_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
 263                                    TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5,
 264                                    TCGv_i32 arg6)
 265 {
 266     *gen_opc_ptr++ = opc;
 267     *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
 268     *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
 269     *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
 270     *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
 271     *gen_opparam_ptr++ = GET_TCGV_I32(arg5);
 272     *gen_opparam_ptr++ = GET_TCGV_I32(arg6);
 273 }
 274
 275 static inline void tcg_gen_op6_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
 276                                    TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5,
 277                                    TCGv_i64 arg6)
 278 {
 279     *gen_opc_ptr++ = opc;
 280     *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
 281     *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
 282     *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
 283     *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
 284     *gen_opparam_ptr++ = GET_TCGV_I64(arg5);
 285     *gen_opparam_ptr++ = GET_TCGV_I64(arg6);
 286 }
 287
 288 static inline void tcg_gen_op6ii_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
 289                                      TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5,
 290                                      TCGArg arg6)
 291 {
 292     *gen_opc_ptr++ = opc;
 293     *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
 294     *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
 295     *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
 296     *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
 297     *gen_opparam_ptr++ = arg5;
 298     *gen_opparam_ptr++ = arg6;
 299 }
 300
 301 static inline void tcg_gen_op6ii_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
 302                                      TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5,
 303                                      TCGArg arg6)
 304 {
 305     *gen_opc_ptr++ = opc;
 306     *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
 307     *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
 308     *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
 309     *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
 310     *gen_opparam_ptr++ = arg5;
 311     *gen_opparam_ptr++ = arg6;
 312 }
 313
 314 static inline void gen_set_label(int n)
 315 {
 316     tcg_gen_op1i(INDEX_op_set_label, n);
 317 }
 318
 319 static inline void tcg_gen_br(int label)
 320 {
 321     tcg_gen_op1i(INDEX_op_br, label);
 322 }
 323
 324 static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg)
 325 {
 326     if (GET_TCGV_I32(ret) != GET_TCGV_I32(arg))
 327         tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg);
 328 }
 329
 330 static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg)
 331 {
 332     tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg);
 333 }
 334
 335 /* helper calls */
 336 static inline void tcg_gen_helperN(void *func, int flags, int sizemask,
 337                                    TCGArg ret, int nargs, TCGArg *args)
 338 {
 339     TCGv_ptr fn;
 340     fn = tcg_const_ptr((tcg_target_long)func);
 341     tcg_gen_callN(&tcg_ctx, fn, flags, sizemask, ret,
 342                   nargs, args);
 343     tcg_temp_free_ptr(fn);
 344 }
 345
 346 /* FIXME: Should this be pure?  */
 347 static inline void tcg_gen_helper64(void *func, TCGv_i64 ret,
 348                                     TCGv_i64 a, TCGv_i64 b)
 349 {
 350     TCGv_ptr fn;
 351     TCGArg args[2];
 352     fn = tcg_const_ptr((tcg_target_long)func);
 353     args[0] = GET_TCGV_I64(a);
 354     args[1] = GET_TCGV_I64(b);
 355     tcg_gen_callN(&tcg_ctx, fn, 0, 7, GET_TCGV_I64(ret), 2, args);
 356     tcg_temp_free_ptr(fn);
 357 }
 358
 359 /* 32 bit ops */
 360
 361 static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
 362 {
 363     tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset);
 364 }
 365
 366 static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
 367 {
 368     tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset);
 369 }
 370
 371 static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
 372 {
 373     tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset);
 374 }
 375
 376 static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
 377 {
 378     tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset);
 379 }
 380
 381 static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
 382 {
 383     tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset);
 384 }
 385
 386 static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
 387 {
 388     tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset);
 389 }
 390
 391 static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
 392 {
 393     tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset);
 394 }
 395
 396 static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
 397 {
 398     tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset);
 399 }
 400
 401 static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 402 {
 403     tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2);
 404 }
 405
 406 static inline void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
 407 {
 408     /* some cases can be optimized here */
 409     if (arg2 == 0) {
 410         tcg_gen_mov_i32(ret, arg1);
 411     } else {
 412         TCGv_i32 t0 = tcg_const_i32(arg2);
 413         tcg_gen_add_i32(ret, arg1, t0);
 414         tcg_temp_free_i32(t0);
 415     }
 416 }
 417
 418 static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 419 {
 420     tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2);
 421 }
 422
 423 static inline void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2)
 424 {
 425     TCGv_i32 t0 = tcg_const_i32(arg1);
 426     tcg_gen_sub_i32(ret, t0, arg2);
 427     tcg_temp_free_i32(t0);
 428 }
 429
 430 static inline void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
 431 {
 432     /* some cases can be optimized here */
 433     if (arg2 == 0) {
 434         tcg_gen_mov_i32(ret, arg1);
 435     } else {
 436         TCGv_i32 t0 = tcg_const_i32(arg2);
 437         tcg_gen_sub_i32(ret, arg1, t0);
 438         tcg_temp_free_i32(t0);
 439     }
 440 }
 441
 442 static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 443 {
 444     tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2);
 445 }
 446
 447 static inline void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
 448 {
 449     /* some cases can be optimized here */
 450     if (arg2 == 0) {
 451         tcg_gen_movi_i32(ret, 0);
 452     } else if (arg2 == 0xffffffff) {
 453         tcg_gen_mov_i32(ret, arg1);
 454     } else {
 455         TCGv_i32 t0 = tcg_const_i32(arg2);
 456         tcg_gen_and_i32(ret, arg1, t0);
 457         tcg_temp_free_i32(t0);
 458     }
 459 }
 460
 461 static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 462 {
 463     tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2);
 464 }
 465
 466 static inline void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
 467 {
 468     /* some cases can be optimized here */
 469     if (arg2 == 0xffffffff) {
 470         tcg_gen_movi_i32(ret, 0xffffffff);
 471     } else if (arg2 == 0) {
 472         tcg_gen_mov_i32(ret, arg1);
 473     } else {
 474         TCGv_i32 t0 = tcg_const_i32(arg2);
 475         tcg_gen_or_i32(ret, arg1, t0);
 476         tcg_temp_free_i32(t0);
 477     }
 478 }
 479
 480 static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 481 {
 482     tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2);
 483 }
 484
 485 static inline void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
 486 {
 487     /* some cases can be optimized here */
 488     if (arg2 == 0) {
 489         tcg_gen_mov_i32(ret, arg1);
 490     } else {
 491         TCGv_i32 t0 = tcg_const_i32(arg2);
 492         tcg_gen_xor_i32(ret, arg1, t0);
 493         tcg_temp_free_i32(t0);
 494     }
 495 }
 496
 497 static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 498 {
 499     tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2);
 500 }
 501
 502 static inline void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
 503 {
 504     if (arg2 == 0) {
 505         tcg_gen_mov_i32(ret, arg1);
 506     } else {
 507         TCGv_i32 t0 = tcg_const_i32(arg2);
 508         tcg_gen_shl_i32(ret, arg1, t0);
 509         tcg_temp_free_i32(t0);
 510     }
 511 }
 512
 513 static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 514 {
 515     tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2);
 516 }
 517
 518 static inline void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
 519 {
 520     if (arg2 == 0) {
 521         tcg_gen_mov_i32(ret, arg1);
 522     } else {
 523         TCGv_i32 t0 = tcg_const_i32(arg2);
 524         tcg_gen_shr_i32(ret, arg1, t0);
 525         tcg_temp_free_i32(t0);
 526     }
 527 }
 528
 529 static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 530 {
 531     tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2);
 532 }
 533
 534 static inline void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
 535 {
 536     if (arg2 == 0) {
 537         tcg_gen_mov_i32(ret, arg1);
 538     } else {
 539         TCGv_i32 t0 = tcg_const_i32(arg2);
 540         tcg_gen_sar_i32(ret, arg1, t0);
 541         tcg_temp_free_i32(t0);
 542     }
 543 }
 544
 545 static inline void tcg_gen_brcond_i32(int cond, TCGv_i32 arg1, TCGv_i32 arg2,
 546                                       int label_index)
 547 {
 548     tcg_gen_op4ii_i32(INDEX_op_brcond_i32, arg1, arg2, cond, label_index);
 549 }
 550
 551 static inline void tcg_gen_brcondi_i32(int cond, TCGv_i32 arg1, int32_t arg2,
 552                                        int label_index)
 553 {
 554     TCGv_i32 t0 = tcg_const_i32(arg2);
 555     tcg_gen_brcond_i32(cond, arg1, t0, label_index);
 556     tcg_temp_free_i32(t0);
 557 }
 558
 559 static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 560 {
 561     tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2);
 562 }
 563
 564 static inline void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
 565 {
 566     TCGv_i32 t0 = tcg_const_i32(arg2);
 567     tcg_gen_mul_i32(ret, arg1, t0);
 568     tcg_temp_free_i32(t0);
 569 }
 570
 571 #ifdef TCG_TARGET_HAS_div_i32
 572 static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 573 {
 574     tcg_gen_op3_i32(INDEX_op_div_i32, ret, arg1, arg2);
 575 }
 576
 577 static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 578 {
 579     tcg_gen_op3_i32(INDEX_op_rem_i32, ret, arg1, arg2);
 580 }
 581
 582 static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 583 {
 584     tcg_gen_op3_i32(INDEX_op_divu_i32, ret, arg1, arg2);
 585 }
 586
 587 static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 588 {
 589     tcg_gen_op3_i32(INDEX_op_remu_i32, ret, arg1, arg2);
 590 }
 591 #else
 592 static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 593 {
 594     TCGv_i32 t0;
 595     t0 = tcg_temp_new_i32();
 596     tcg_gen_sari_i32(t0, arg1, 31);
 597     tcg_gen_op5_i32(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2);
 598     tcg_temp_free_i32(t0);
 599 }
 600
 601 static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 602 {
 603     TCGv_i32 t0;
 604     t0 = tcg_temp_new_i32();
 605     tcg_gen_sari_i32(t0, arg1, 31);
 606     tcg_gen_op5_i32(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2);
 607     tcg_temp_free_i32(t0);
 608 }
 609
 610 static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 611 {
 612     TCGv_i32 t0;
 613     t0 = tcg_temp_new_i32();
 614     tcg_gen_movi_i32(t0, 0);
 615     tcg_gen_op5_i32(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2);
 616     tcg_temp_free_i32(t0);
 617 }
 618
 619 static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 620 {
 621     TCGv_i32 t0;
 622     t0 = tcg_temp_new_i32();
 623     tcg_gen_movi_i32(t0, 0);
 624     tcg_gen_op5_i32(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2);
 625     tcg_temp_free_i32(t0);
 626 }
 627 #endif
 628
 629 #if TCG_TARGET_REG_BITS == 32
 630
 631 static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
 632 {
 633     if (GET_TCGV_I64(ret) != GET_TCGV_I64(arg)) {
 634         tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
 635         tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
 636     }
 637 }
 638
 639 static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
 640 {
 641     tcg_gen_movi_i32(TCGV_LOW(ret), arg);
 642     tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32);
 643 }
 644
 645 static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2,
 646                                     tcg_target_long offset)
 647 {
 648     tcg_gen_ld8u_i32(TCGV_LOW(ret), arg2, offset);
 649     tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
 650 }
 651
 652 static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2,
 653                                     tcg_target_long offset)
 654 {
 655     tcg_gen_ld8s_i32(TCGV_LOW(ret), arg2, offset);
 656     tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), 31);
 657 }
 658
 659 static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2,
 660                                      tcg_target_long offset)
 661 {
 662     tcg_gen_ld16u_i32(TCGV_LOW(ret), TCGV_LOW(arg2), offset);
 663     tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
 664 }
 665
 666 static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2,
 667                                      tcg_target_long offset)
 668 {
 669     tcg_gen_ld16s_i32(TCGV_LOW(ret), arg2, offset);
 670     tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
 671 }
 672
 673 static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2,
 674                                      tcg_target_long offset)
 675 {
 676     tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
 677     tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
 678 }
 679
 680 static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2,
 681                                      tcg_target_long offset)
 682 {
 683     tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
 684     tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
 685 }
 686
 687 static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2,
 688                                   tcg_target_long offset)
 689 {
 690     /* since arg2 and ret have different types, they cannot be the
 691        same temporary */
 692 #ifdef TCG_TARGET_WORDS_BIGENDIAN
 693     tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset);
 694     tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset + 4);
 695 #else
 696     tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
 697     tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4);
 698 #endif
 699 }
 700
 701 static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
 702                                    tcg_target_long offset)
 703 {
 704     tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset);
 705 }
 706
 707 static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
 708                                     tcg_target_long offset)
 709 {
 710     tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset);
 711 }
 712
 713 static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
 714                                     tcg_target_long offset)
 715 {
 716     tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
 717 }
 718
 719 static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2,
 720                                   tcg_target_long offset)
 721 {
 722 #ifdef TCG_TARGET_WORDS_BIGENDIAN
 723     tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset);
 724     tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset + 4);
 725 #else
 726     tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
 727     tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4);
 728 #endif
 729 }
 730
 731 static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 732 {
 733     tcg_gen_op6_i32(INDEX_op_add2_i32, TCGV_LOW(ret), TCGV_HIGH(ret),
 734                     TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
 735                     TCGV_HIGH(arg2));
 736 }
 737
 738 static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 739 {
 740     tcg_gen_op6_i32(INDEX_op_sub2_i32, TCGV_LOW(ret), TCGV_HIGH(ret),
 741                     TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
 742                     TCGV_HIGH(arg2));
 743 }
 744
 745 static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 746 {
 747     tcg_gen_and_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
 748     tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
 749 }
 750
 751 static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
 752 {
 753     tcg_gen_andi_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
 754     tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
 755 }
 756
 757 static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 758 {
 759     tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
 760     tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
 761 }
 762
 763 static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
 764 {
 765     tcg_gen_ori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
 766     tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
 767 }
 768
 769 static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 770 {
 771     tcg_gen_xor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
 772     tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
 773 }
 774
 775 static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
 776 {
 777     tcg_gen_xori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
 778     tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
 779 }
 780
 781 /* XXX: use generic code when basic block handling is OK or CPU
 782    specific code (x86) */
 783 static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 784 {
 785     tcg_gen_helper64(tcg_helper_shl_i64, ret, arg1, arg2);
 786 }
 787
 788 static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
 789 {
 790     tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0);
 791 }
 792
 793 static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 794 {
 795     tcg_gen_helper64(tcg_helper_shr_i64, ret, arg1, arg2);
 796 }
 797
 798 static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
 799 {
 800     tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0);
 801 }
 802
 803 static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 804 {
 805     tcg_gen_helper64(tcg_helper_sar_i64, ret, arg1, arg2);
 806 }
 807
 808 static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
 809 {
 810     tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1);
 811 }
 812
 813 static inline void tcg_gen_brcond_i64(int cond, TCGv_i64 arg1, TCGv_i64 arg2,
 814                                       int label_index)
 815 {
 816     tcg_gen_op6ii_i32(INDEX_op_brcond2_i32,
 817                       TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
 818                       TCGV_HIGH(arg2), cond, label_index);
 819 }
 820
 821 static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 822 {
 823     TCGv_i64 t0;
 824     TCGv_i32 t1;
 825
 826     t0 = tcg_temp_new_i64();
 827     t1 = tcg_temp_new_i32();
 828
 829     tcg_gen_op4_i32(INDEX_op_mulu2_i32, TCGV_LOW(t0), TCGV_HIGH(t0),
 830                     TCGV_LOW(arg1), TCGV_LOW(arg2));
 831
 832     tcg_gen_mul_i32(t1, TCGV_LOW(arg1), TCGV_HIGH(arg2));
 833     tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
 834     tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), TCGV_LOW(arg2));
 835     tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
 836
 837     tcg_gen_mov_i64(ret, t0);
 838     tcg_temp_free_i64(t0);
 839     tcg_temp_free_i32(t1);
 840 }
 841
 842 static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 843 {
 844     tcg_gen_helper64(tcg_helper_div_i64, ret, arg1, arg2);
 845 }
 846
 847 static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 848 {
 849     tcg_gen_helper64(tcg_helper_rem_i64, ret, arg1, arg2);
 850 }
 851
 852 static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 853 {
 854     tcg_gen_helper64(tcg_helper_divu_i64, ret, arg1, arg2);
 855 }
 856
 857 static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 858 {
 859     tcg_gen_helper64(tcg_helper_remu_i64, ret, arg1, arg2);
 860 }
 861
 862 #else
 863
 864 static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
 865 {
 866     if (GET_TCGV_I64(ret) != GET_TCGV_I64(arg))
 867         tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg);
 868 }
 869
 870 static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
 871 {
 872     tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg);
 873 }
 874
 875 static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_i64 arg2,
 876                                     tcg_target_long offset)
 877 {
 878     tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset);
 879 }
 880
 881 static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_i64 arg2,
 882                                     tcg_target_long offset)
 883 {
 884     tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset);
 885 }
 886
 887 static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_i64 arg2,
 888                                      tcg_target_long offset)
 889 {
 890     tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset);
 891 }
 892
 893 static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_i64 arg2,
 894                                      tcg_target_long offset)
 895 {
 896     tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset);
 897 }
 898
 899 static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_i64 arg2,
 900                                      tcg_target_long offset)
 901 {
 902     tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset);
 903 }
 904
 905 static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_i64 arg2,
 906                                      tcg_target_long offset)
 907 {
 908     tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset);
 909 }
 910
 911 static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_i64 arg2, tcg_target_long offset)
 912 {
 913     tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset);
 914 }
 915
 916 static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_i64 arg2,
 917                                    tcg_target_long offset)
 918 {
 919     tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset);
 920 }
 921
 922 static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_i64 arg2,
 923                                     tcg_target_long offset)
 924 {
 925     tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset);
 926 }
 927
 928 static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_i64 arg2,
 929                                     tcg_target_long offset)
 930 {
 931     tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset);
 932 }
 933
 934 static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_i64 arg2, tcg_target_long offset)
 935 {
 936     tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset);
 937 }
 938
 939 static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 940 {
 941     tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2);
 942 }
 943
 944 static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 945 {
 946     tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2);
 947 }
 948
 949 static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 950 {
 951     tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2);
 952 }
 953
 954 static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
 955 {
 956     TCGv_i64 t0 = tcg_const_i64(arg2);
 957     tcg_gen_and_i64(ret, arg1, t0);
 958     tcg_temp_free_i64(t0);
 959 }
 960
 961 static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 962 {
 963     tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2);
 964 }
 965
 966 static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
 967 {
 968     TCGv_i64 t0 = tcg_const_i64(arg2);
 969     tcg_gen_or_i64(ret, arg1, t0);
 970     tcg_temp_free_i64(t0);
 971 }
 972
 973 static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 974 {
 975     tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2);
 976 }
 977
 978 static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
 979 {
 980     TCGv_i64 t0 = tcg_const_i64(arg2);
 981     tcg_gen_xor_i64(ret, arg1, t0);
 982     tcg_temp_free_i64(t0);
 983 }
 984
 985 static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 986 {
 987     tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2);
 988 }
 989
 990 static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
 991 {
 992     if (arg2 == 0) {
 993         tcg_gen_mov_i64(ret, arg1);
 994     } else {
 995         TCGv_i64 t0 = tcg_const_i64(arg2);
 996         tcg_gen_shl_i64(ret, arg1, t0);
 997         tcg_temp_free_i64(t0);
 998     }
 999 }
1000
1001 static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1002 {
1003     tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2);
1004 }
1005
1006 static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1007 {
1008     if (arg2 == 0) {
1009         tcg_gen_mov_i64(ret, arg1);
1010     } else {
1011         TCGv_i64 t0 = tcg_const_i64(arg2);
1012         tcg_gen_shr_i64(ret, arg1, t0);
1013         tcg_temp_free_i64(t0);
1014     }
1015 }
1016
1017 static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1018 {
1019     tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2);
1020 }
1021
1022 static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1023 {
1024     if (arg2 == 0) {
1025         tcg_gen_mov_i64(ret, arg1);
1026     } else {
1027         TCGv_i64 t0 = tcg_const_i64(arg2);
1028         tcg_gen_sar_i64(ret, arg1, t0);
1029         tcg_temp_free_i64(t0);
1030     }
1031 }
1032
1033 static inline void tcg_gen_brcond_i64(int cond, TCGv_i64 arg1, TCGv_i64 arg2,
1034                                       int label_index)
1035 {
1036     tcg_gen_op4ii_i64(INDEX_op_brcond_i64, arg1, arg2, cond, label_index);
1037 }
1038
1039 static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1040 {
1041     tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2);
1042 }
1043
1044 #ifdef TCG_TARGET_HAS_div_i64
1045 static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1046 {
1047     tcg_gen_op3_i64(INDEX_op_div_i64, ret, arg1, arg2);
1048 }
1049
1050 static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1051 {
1052     tcg_gen_op3_i64(INDEX_op_rem_i64, ret, arg1, arg2);
1053 }
1054
1055 static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1056 {
1057     tcg_gen_op3_i64(INDEX_op_divu_i64, ret, arg1, arg2);
1058 }
1059
1060 static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1061 {
1062     tcg_gen_op3_i64(INDEX_op_remu_i64, ret, arg1, arg2);
1063 }
1064 #else
1065 static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1066 {
1067     TCGv_i64 t0;
1068     t0 = tcg_temp_new_i64();
1069     tcg_gen_sari_i64(t0, arg1, 63);
1070     tcg_gen_op5_i64(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2);
1071     tcg_temp_free_i64(t0);
1072 }
1073
1074 static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1075 {
1076     TCGv_i64 t0;
1077     t0 = tcg_temp_new_i64();
1078     tcg_gen_sari_i64(t0, arg1, 63);
1079     tcg_gen_op5_i64(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2);
1080     tcg_temp_free_i64(t0);
1081 }
1082
1083 static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1084 {
1085     TCGv_i64 t0;
1086     t0 = tcg_temp_new_i64();
1087     tcg_gen_movi_i64(t0, 0);
1088     tcg_gen_op5_i64(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2);
1089     tcg_temp_free_i64(t0);
1090 }
1091
1092 static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1093 {
1094     TCGv_i64 t0;
1095     t0 = tcg_temp_new_i64();
1096     tcg_gen_movi_i64(t0, 0);
1097     tcg_gen_op5_i64(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2);
1098     tcg_temp_free_i64(t0);
1099 }
1100 #endif
1101
1102 #endif
1103
1104 static inline void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1105 {
1106     /* some cases can be optimized here */
1107     if (arg2 == 0) {
1108         tcg_gen_mov_i64(ret, arg1);
1109     } else {
1110         TCGv_i64 t0 = tcg_const_i64(arg2);
1111         tcg_gen_add_i64(ret, arg1, t0);
1112         tcg_temp_free_i64(t0);
1113     }
1114 }
1115
1116 static inline void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2)
1117 {
1118     TCGv_i64 t0 = tcg_const_i64(arg1);
1119     tcg_gen_sub_i64(ret, t0, arg2);
1120     tcg_temp_free_i64(t0);
1121 }
1122
1123 static inline void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1124 {
1125     /* some cases can be optimized here */
1126     if (arg2 == 0) {
1127         tcg_gen_mov_i64(ret, arg1);
1128     } else {
1129         TCGv_i64 t0 = tcg_const_i64(arg2);
1130         tcg_gen_sub_i64(ret, arg1, t0);
1131         tcg_temp_free_i64(t0);
1132     }
1133 }
1134 static inline void tcg_gen_brcondi_i64(int cond, TCGv_i64 arg1, int64_t arg2,
1135                                        int label_index)
1136 {
1137     TCGv_i64 t0 = tcg_const_i64(arg2);
1138     tcg_gen_brcond_i64(cond, arg1, t0, label_index);
1139     tcg_temp_free_i64(t0);
1140 }
1141
1142 static inline void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1143 {
1144     TCGv_i64 t0 = tcg_const_i64(arg2);
1145     tcg_gen_mul_i64(ret, arg1, t0);
1146     tcg_temp_free_i64(t0);
1147 }
1148
1149
1150 /***************************************/
1151 /* optional operations */
1152
1153 static inline void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg)
1154 {
1155 #ifdef TCG_TARGET_HAS_ext8s_i32
1156     tcg_gen_op2_i32(INDEX_op_ext8s_i32, ret, arg);
1157 #else
1158     tcg_gen_shli_i32(ret, arg, 24);
1159     tcg_gen_sari_i32(ret, ret, 24);
1160 #endif
1161 }
1162
1163 static inline void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg)
1164 {
1165 #ifdef TCG_TARGET_HAS_ext16s_i32
1166     tcg_gen_op2_i32(INDEX_op_ext16s_i32, ret, arg);
1167 #else
1168     tcg_gen_shli_i32(ret, arg, 16);
1169     tcg_gen_sari_i32(ret, ret, 16);
1170 #endif
1171 }
1172
1173 /* These are currently just for convenience.
1174    We assume a target will recognise these automatically .  */
1175 static inline void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg)
1176 {
1177     tcg_gen_andi_i32(ret, arg, 0xffu);
1178 }
1179
1180 static inline void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg)
1181 {
1182     tcg_gen_andi_i32(ret, arg, 0xffffu);
1183 }
1184
1185 /* Note: we assume the two high bytes are set to zero */
1186 static inline void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg)
1187 {
1188 #ifdef TCG_TARGET_HAS_bswap16_i32
1189     tcg_gen_op2_i32(INDEX_op_bswap16_i32, ret, arg);
1190 #else
1191     TCGv_i32 t0, t1;
1192     t0 = tcg_temp_new_i32();
1193     t1 = tcg_temp_new_i32();
1194
1195     tcg_gen_shri_i32(t0, arg, 8);
1196     tcg_gen_andi_i32(t1, arg, 0x000000ff);
1197     tcg_gen_shli_i32(t1, t1, 8);
1198     tcg_gen_or_i32(ret, t0, t1);
1199     tcg_temp_free_i32(t0);
1200     tcg_temp_free_i32(t1);
1201 #endif
1202 }
1203
1204 static inline void tcg_gen_bswap_i32(TCGv_i32 ret, TCGv_i32 arg)
1205 {
1206 #ifdef TCG_TARGET_HAS_bswap_i32
1207     tcg_gen_op2_i32(INDEX_op_bswap_i32, ret, arg);
1208 #else
1209     TCGv_i32 t0, t1;
1210     t0 = tcg_temp_new_i32();
1211     t1 = tcg_temp_new_i32();
1212
1213     tcg_gen_shli_i32(t0, arg, 24);
1214
1215     tcg_gen_andi_i32(t1, arg, 0x0000ff00);
1216     tcg_gen_shli_i32(t1, t1, 8);
1217     tcg_gen_or_i32(t0, t0, t1);
1218
1219     tcg_gen_shri_i32(t1, arg, 8);
1220     tcg_gen_andi_i32(t1, t1, 0x0000ff00);
1221     tcg_gen_or_i32(t0, t0, t1);
1222
1223     tcg_gen_shri_i32(t1, arg, 24);
1224     tcg_gen_or_i32(ret, t0, t1);
1225     tcg_temp_free_i32(t0);
1226     tcg_temp_free_i32(t1);
1227 #endif
1228 }
1229
1230 #if TCG_TARGET_REG_BITS == 32
1231 static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg)
1232 {
1233     tcg_gen_ext8s_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1234     tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1235 }
1236
1237 static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg)
1238 {
1239     tcg_gen_ext16s_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1240     tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1241 }
1242
1243 static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg)
1244 {
1245     tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1246     tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1247 }
1248
1249 static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg)
1250 {
1251     tcg_gen_ext8u_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1252     tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1253 }
1254
1255 static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg)
1256 {
1257     tcg_gen_ext16u_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1258     tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1259 }
1260
1261 static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg)
1262 {
1263     tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1264     tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1265 }
1266
1267 static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
1268 {
1269     tcg_gen_mov_i32(ret, TCGV_LOW(arg));
1270 }
1271
1272 static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1273 {
1274     tcg_gen_mov_i32(TCGV_LOW(ret), arg);
1275     tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1276 }
1277
1278 static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1279 {
1280     tcg_gen_mov_i32(TCGV_LOW(ret), arg);
1281     tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1282 }
1283
1284 static inline void tcg_gen_bswap_i64(TCGv_i64 ret, TCGv_i64 arg)
1285 {
1286     TCGv_i32 t0, t1;
1287     t0 = tcg_temp_new_i32();
1288     t1 = tcg_temp_new_i32();
1289
1290     tcg_gen_bswap_i32(t0, TCGV_LOW(arg));
1291     tcg_gen_bswap_i32(t1, TCGV_HIGH(arg));
1292     tcg_gen_mov_i32(TCGV_LOW(ret), t1);
1293     tcg_gen_mov_i32(TCGV_HIGH(ret), t0);
1294     tcg_temp_free_i32(t0);
1295     tcg_temp_free_i32(t1);
1296 }
1297 #else
1298
1299 static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg)
1300 {
1301 #ifdef TCG_TARGET_HAS_ext8s_i64
1302     tcg_gen_op2_i64(INDEX_op_ext8s_i64, ret, arg);
1303 #else
1304     tcg_gen_shli_i64(ret, arg, 56);
1305     tcg_gen_sari_i64(ret, ret, 56);
1306 #endif
1307 }
1308
1309 static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg)
1310 {
1311 #ifdef TCG_TARGET_HAS_ext16s_i64
1312     tcg_gen_op2_i64(INDEX_op_ext16s_i64, ret, arg);
1313 #else
1314     tcg_gen_shli_i64(ret, arg, 48);
1315     tcg_gen_sari_i64(ret, ret, 48);
1316 #endif
1317 }
1318
1319 static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg)
1320 {
1321 #ifdef TCG_TARGET_HAS_ext32s_i64
1322     tcg_gen_op2_i64(INDEX_op_ext32s_i64, ret, arg);
1323 #else
1324     tcg_gen_shli_i64(ret, arg, 32);
1325     tcg_gen_sari_i64(ret, ret, 32);
1326 #endif
1327 }
1328
1329 static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg)
1330 {
1331     tcg_gen_andi_i64(ret, arg, 0xffu);
1332 }
1333
1334 static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg)
1335 {
1336     tcg_gen_andi_i64(ret, arg, 0xffffu);
1337 }
1338
1339 static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg)
1340 {
1341     tcg_gen_andi_i64(ret, arg, 0xffffffffu);
1342 }
1343
1344 /* Note: we assume the target supports move between 32 and 64 bit
1345    registers.  This will probably break MIPS64 targets.  */
1346 static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
1347 {
1348     tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg)));
1349 }
1350
1351 /* Note: we assume the target supports move between 32 and 64 bit
1352    registers */
1353 static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1354 {
1355     tcg_gen_andi_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg)), 0xffffffffu);
1356 }
1357
1358 /* Note: we assume the target supports move between 32 and 64 bit
1359    registers */
1360 static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1361 {
1362     tcg_gen_ext32s_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg)));
1363 }
1364
1365 static inline void tcg_gen_bswap_i64(TCGv_i64 ret, TCGv_i64 arg)
1366 {
1367 #ifdef TCG_TARGET_HAS_bswap_i64
1368     tcg_gen_op2_i64(INDEX_op_bswap_i64, ret, arg);
1369 #else
1370     TCGv_i32 t0, t1;
1371     t0 = tcg_temp_new_i32();
1372     t1 = tcg_temp_new_i32();
1373
1374     tcg_gen_shli_i64(t0, arg, 56);
1375
1376     tcg_gen_andi_i64(t1, arg, 0x0000ff00);
1377     tcg_gen_shli_i64(t1, t1, 40);
1378     tcg_gen_or_i64(t0, t0, t1);
1379
1380     tcg_gen_andi_i64(t1, arg, 0x00ff0000);
1381     tcg_gen_shli_i64(t1, t1, 24);
1382     tcg_gen_or_i64(t0, t0, t1);
1383
1384     tcg_gen_andi_i64(t1, arg, 0xff000000);
1385     tcg_gen_shli_i64(t1, t1, 8);
1386     tcg_gen_or_i64(t0, t0, t1);
1387
1388     tcg_gen_shri_i64(t1, arg, 8);
1389     tcg_gen_andi_i64(t1, t1, 0xff000000);
1390     tcg_gen_or_i64(t0, t0, t1);
1391
1392     tcg_gen_shri_i64(t1, arg, 24);
1393     tcg_gen_andi_i64(t1, t1, 0x00ff0000);
1394     tcg_gen_or_i64(t0, t0, t1);
1395
1396     tcg_gen_shri_i64(t1, arg, 40);
1397     tcg_gen_andi_i64(t1, t1, 0x0000ff00);
1398     tcg_gen_or_i64(t0, t0, t1);
1399
1400     tcg_gen_shri_i64(t1, arg, 56);
1401     tcg_gen_or_i64(ret, t0, t1);
1402     tcg_temp_free_i32(t0);
1403     tcg_temp_free_i32(t1);
1404 #endif
1405 }
1406
1407 #endif
1408
1409 static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg)
1410 {
1411 #ifdef TCG_TARGET_HAS_neg_i32
1412     tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg);
1413 #else
1414     TCGv_i32 t0 = tcg_const_i32(0);
1415     tcg_gen_sub_i32(ret, t0, arg);
1416     tcg_temp_free_i32(t0);
1417 #endif
1418 }
1419
1420 static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg)
1421 {
1422 #ifdef TCG_TARGET_HAS_neg_i64
1423     tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg);
1424 #else
1425     TCGv_i64 t0 = tcg_const_i64(0);
1426     tcg_gen_sub_i64(ret, t0, arg);
1427     tcg_temp_free_i64(t0);
1428 #endif
1429 }
1430
1431 static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg)
1432 {
1433     tcg_gen_xori_i32(ret, arg, -1);
1434 }
1435
1436 static inline void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg)
1437 {
1438     tcg_gen_xori_i64(ret, arg, -1);
1439 }
1440
1441 static inline void tcg_gen_discard_i32(TCGv_i32 arg)
1442 {
1443     tcg_gen_op1_i32(INDEX_op_discard, arg);
1444 }
1445
1446 #if TCG_TARGET_REG_BITS == 32
1447 static inline void tcg_gen_discard_i64(TCGv_i64 arg)
1448 {
1449     tcg_gen_discard_i32(TCGV_LOW(arg));
1450     tcg_gen_discard_i32(TCGV_HIGH(arg));
1451 }
1452 #else
1453 static inline void tcg_gen_discard_i64(TCGv_i64 arg)
1454 {
1455     tcg_gen_op1_i64(INDEX_op_discard, arg);
1456 }
1457 #endif
1458
1459 static inline void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high)
1460 {
1461 #if TCG_TARGET_REG_BITS == 32
1462     tcg_gen_mov_i32(TCGV_LOW(dest), low);
1463     tcg_gen_mov_i32(TCGV_HIGH(dest), high);
1464 #else
1465     TCGv_i64 tmp = tcg_temp_new_i64();
1466     /* This extension is only needed for type correctness.
1467        We may be able to do better given target specific information.  */
1468     tcg_gen_extu_i32_i64(tmp, high);
1469     tcg_gen_shli_i64(tmp, tmp, 32);
1470     tcg_gen_extu_i32_i64(dest, low);
1471     tcg_gen_or_i64(dest, dest, tmp);
1472     tcg_temp_free_i64(tmp);
1473 #endif
1474 }
1475
1476 static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low, TCGv_i64 high)
1477 {
1478 #if TCG_TARGET_REG_BITS == 32
1479     tcg_gen_concat_i32_i64(dest, TCGV_LOW(low), TCGV_LOW(high));
1480 #else
1481     TCGv_i64 tmp = tcg_temp_new_i64();
1482     tcg_gen_ext32u_i64(dest, low);
1483     tcg_gen_shli_i64(tmp, high, 32);
1484     tcg_gen_or_i64(dest, dest, tmp);
1485     tcg_temp_free_i64(tmp);
1486 #endif
1487 }
1488
1489 static inline void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1490 {
1491     TCGv_i32 t0;
1492     t0 = tcg_temp_new_i32();
1493     tcg_gen_not_i32(t0, arg2);
1494     tcg_gen_and_i32(ret, arg1, t0);
1495     tcg_temp_free_i32(t0);
1496 }
1497
1498 static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1499 {
1500     TCGv_i64 t0;
1501     t0 = tcg_temp_new_i64();
1502     tcg_gen_not_i64(t0, arg2);
1503     tcg_gen_and_i64(ret, arg1, t0);
1504     tcg_temp_free_i64(t0);
1505 }
1506
1507 static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1508 {
1509     TCGv_i32 t0;
1510     t0 = tcg_temp_new_i32();
1511     tcg_gen_xor_i32(t0, arg1, arg2);
1512     tcg_gen_not_i32(ret, t0);
1513     tcg_temp_free_i32(t0);
1514 }
1515
1516 static inline void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1517 {
1518     TCGv_i64 t0;
1519     t0 = tcg_temp_new_i64();
1520     tcg_gen_xor_i64(t0, arg1, arg2);
1521     tcg_gen_not_i64(ret, t0);
1522     tcg_temp_free_i64(t0);
1523 }
1524
1525 static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1526 {
1527     TCGv_i32 t0;
1528     t0 = tcg_temp_new_i32();
1529     tcg_gen_and_i32(t0, arg1, arg2);
1530     tcg_gen_not_i32(ret, t0);
1531     tcg_temp_free_i32(t0);
1532 }
1533
1534 static inline void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1535 {
1536     TCGv_i64 t0;
1537     t0 = tcg_temp_new_i64();
1538     tcg_gen_and_i64(t0, arg1, arg2);
1539     tcg_gen_not_i64(ret, t0);
1540     tcg_temp_free_i64(t0);
1541 }
1542
1543 static inline void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1544 {
1545     TCGv_i32 t0;
1546     t0 = tcg_temp_new_i32();
1547     tcg_gen_or_i32(t0, arg1, arg2);
1548     tcg_gen_not_i32(ret, t0);
1549     tcg_temp_free_i32(t0);
1550 }
1551
1552 static inline void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1553 {
1554     TCGv_i64 t0;
1555     t0 = tcg_temp_new_i64();
1556     tcg_gen_or_i64(t0, arg1, arg2);
1557     tcg_gen_not_i64(ret, t0);
1558     tcg_temp_free_i64(t0);
1559 }
1560
1561 static inline void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1562 {
1563     TCGv_i32 t0;
1564     t0 = tcg_temp_new_i32();
1565     tcg_gen_not_i32(t0, arg2);
1566     tcg_gen_or_i32(ret, arg1, t0);
1567     tcg_temp_free_i32(t0);
1568 }
1569
1570 static inline void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1571 {
1572     TCGv_i64 t0;
1573     t0 = tcg_temp_new_i64();
1574     tcg_gen_not_i64(t0, arg2);
1575     tcg_gen_or_i64(ret, arg1, t0);
1576     tcg_temp_free_i64(t0);
1577 }
1578
1579 static inline void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1580 {
1581     TCGv_i32 t0, t1;
1582
1583     t0 = tcg_temp_new_i32();
1584     t1 = tcg_temp_new_i32();
1585     tcg_gen_shl_i32(t0, arg1, arg2);
1586     tcg_gen_subfi_i32(t1, 32, arg2);
1587     tcg_gen_shr_i32(t1, arg1, t1);
1588     tcg_gen_or_i32(ret, t0, t1);
1589     tcg_temp_free_i32(t0);
1590     tcg_temp_free_i32(t1);
1591 }
1592
1593 static inline void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1594 {
1595     TCGv_i64 t0, t1;
1596
1597     t0 = tcg_temp_new_i64();
1598     t1 = tcg_temp_new_i64();
1599     tcg_gen_shl_i64(t0, arg1, arg2);
1600     tcg_gen_subfi_i64(t1, 64, arg2);
1601     tcg_gen_shr_i64(t1, arg1, t1);
1602     tcg_gen_or_i64(ret, t0, t1);
1603     tcg_temp_free_i64(t0);
1604     tcg_temp_free_i64(t1);
1605 }
1606
1607 static inline void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
1608 {
1609     /* some cases can be optimized here */
1610     if (arg2 == 0) {
1611         tcg_gen_mov_i32(ret, arg1);
1612     } else {
1613         TCGv_i32 t0, t1;
1614         t0 = tcg_temp_new_i32();
1615         t1 = tcg_temp_new_i32();
1616         tcg_gen_shli_i32(t0, arg1, arg2);
1617         tcg_gen_shri_i32(t1, arg1, 32 - arg2);
1618         tcg_gen_or_i32(ret, t0, t1);
1619         tcg_temp_free_i32(t0);
1620         tcg_temp_free_i32(t1);
1621     }
1622 }
1623
1624 static inline void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1625 {
1626     /* some cases can be optimized here */
1627     if (arg2 == 0) {
1628         tcg_gen_mov_i64(ret, arg1);
1629     } else {
1630         TCGv_i64 t0, t1;
1631         t0 = tcg_temp_new_i64();
1632         t1 = tcg_temp_new_i64();
1633         tcg_gen_shli_i64(t0, arg1, arg2);
1634         tcg_gen_shri_i64(t1, arg1, 64 - arg2);
1635         tcg_gen_or_i64(ret, t0, t1);
1636         tcg_temp_free_i64(t0);
1637         tcg_temp_free_i64(t1);
1638     }
1639 }
1640
1641 static inline void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1642 {
1643     TCGv_i32 t0, t1;
1644
1645     t0 = tcg_temp_new_i32();
1646     t1 = tcg_temp_new_i32();
1647     tcg_gen_shr_i32(t0, arg1, arg2);
1648     tcg_gen_subfi_i32(t1, 32, arg2);
1649     tcg_gen_shl_i32(t1, arg1, t1);
1650     tcg_gen_or_i32(ret, t0, t1);
1651     tcg_temp_free_i32(t0);
1652     tcg_temp_free_i32(t1);
1653 }
1654
1655 static inline void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1656 {
1657     TCGv_i64 t0, t1;
1658
1659     t0 = tcg_temp_new_i64();
1660     t1 = tcg_temp_new_i64();
1661     tcg_gen_shl_i64(t0, arg1, arg2);
1662     tcg_gen_subfi_i64(t1, 64, arg2);
1663     tcg_gen_shl_i64(t1, arg1, t1);
1664     tcg_gen_or_i64(ret, t0, t1);
1665     tcg_temp_free_i64(t0);
1666     tcg_temp_free_i64(t1);
1667 }
1668
1669 static inline void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
1670 {
1671     /* some cases can be optimized here */
1672     if (arg2 == 0) {
1673         tcg_gen_mov_i32(ret, arg1);
1674     } else {
1675         tcg_gen_rotli_i32(ret, arg1, 32 - arg2);
1676     }
1677 }
1678
1679 static inline void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1680 {
1681     /* some cases can be optimized here */
1682     if (arg2 == 0) {
1683         tcg_gen_mov_i64(ret, arg1);
1684     } else {
1685         tcg_gen_rotli_i64(ret, arg1, 64 - arg2);
1686     }
1687 }
1688
1689 /***************************************/
1690 /* QEMU specific operations. Their type depend on the QEMU CPU
1691    type. */
1692 #ifndef TARGET_LONG_BITS
1693 #error must include QEMU headers
1694 #endif
1695
1696 #if TARGET_LONG_BITS == 32
1697 #define TCGv TCGv_i32
1698 #define tcg_temp_new() tcg_temp_new_i32()
1699 #define tcg_global_reg_new tcg_global_reg_new_i32
1700 #define tcg_global_mem_new tcg_global_mem_new_i32
1701 #define tcg_temp_local_new(t) tcg_temp_local_new_i32()
1702 #define tcg_temp_free tcg_temp_free_i32
1703 #define tcg_gen_qemu_ldst_op tcg_gen_op3i_i32
1704 #define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i32
1705 #define TCGV_UNUSED(x) TCGV_UNUSED_I32(x)
1706 #define TCGV_EQUAL(a, b) (GET_TCGV_I32(a) == GET_TCGV_I32(b))
1707 #else
1708 #define TCGv TCGv_i64
1709 #define tcg_temp_new() tcg_temp_new_i64()
1710 #define tcg_global_reg_new tcg_global_reg_new_i64
1711 #define tcg_global_mem_new tcg_global_mem_new_i64
1712 #define tcg_temp_local_new(t) tcg_temp_local_new_i64()
1713 #define tcg_temp_free tcg_temp_free_i64
1714 #define tcg_gen_qemu_ldst_op tcg_gen_op3i_i64
1715 #define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i64
1716 #define TCGV_UNUSED(x) TCGV_UNUSED_I64(x)
1717 #define TCGV_EQUAL(a, b) (GET_TCGV_I64(a) == GET_TCGV_I64(b))
1718 #endif
1719
1720 /* debug info: write the PC of the corresponding QEMU CPU instruction */
1721 static inline void tcg_gen_debug_insn_start(uint64_t pc)
1722 {
1723     /* XXX: must really use a 32 bit size for TCGArg in all cases */
1724 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
1725     tcg_gen_op2ii(INDEX_op_debug_insn_start,
1726                   (uint32_t)(pc), (uint32_t)(pc >> 32));
1727 #else
1728     tcg_gen_op1i(INDEX_op_debug_insn_start, pc);
1729 #endif
1730 }
1731
1732 static inline void tcg_gen_exit_tb(tcg_target_long val)
1733 {
1734     tcg_gen_op1i(INDEX_op_exit_tb, val);
1735 }
1736
1737 static inline void tcg_gen_goto_tb(int idx)
1738 {
1739     tcg_gen_op1i(INDEX_op_goto_tb, idx);
1740 }
1741
1742 #if TCG_TARGET_REG_BITS == 32
1743 static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
1744 {
1745 #if TARGET_LONG_BITS == 32
1746     tcg_gen_op3i_i32(INDEX_op_qemu_ld8u, ret, addr, mem_index);
1747 #else
1748     tcg_gen_op4i_i32(INDEX_op_qemu_ld8u, TCGV_LOW(ret), TCGV_LOW(addr),
1749                      TCGV_HIGH(addr), mem_index);
1750     tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1751 #endif
1752 }
1753
1754 static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
1755 {
1756 #if TARGET_LONG_BITS == 32
1757     tcg_gen_op3i_i32(INDEX_op_qemu_ld8s, ret, addr, mem_index);
1758 #else
1759     tcg_gen_op4i_i32(INDEX_op_qemu_ld8s, TCGV_LOW(ret), TCGV_LOW(addr),
1760                      TCGV_HIGH(addr), mem_index);
1761     tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1762 #endif
1763 }
1764
1765 static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
1766 {
1767 #if TARGET_LONG_BITS == 32
1768     tcg_gen_op3i_i32(INDEX_op_qemu_ld16u, ret, addr, mem_index);
1769 #else
1770     tcg_gen_op4i_i32(INDEX_op_qemu_ld16u, TCGV_LOW(ret), TCGV_LOW(addr),
1771                      TCGV_HIGH(addr), mem_index);
1772     tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1773 #endif
1774 }
1775
1776 static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
1777 {
1778 #if TARGET_LONG_BITS == 32
1779     tcg_gen_op3i_i32(INDEX_op_qemu_ld16s, ret, addr, mem_index);
1780 #else
1781     tcg_gen_op4i_i32(INDEX_op_qemu_ld16s, TCGV_LOW(ret), TCGV_LOW(addr),
1782                      TCGV_HIGH(addr), mem_index);
1783     tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1784 #endif
1785 }
1786
1787 static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
1788 {
1789 #if TARGET_LONG_BITS == 32
1790     tcg_gen_op3i_i32(INDEX_op_qemu_ld32u, ret, addr, mem_index);
1791 #else
1792     tcg_gen_op4i_i32(INDEX_op_qemu_ld32u, TCGV_LOW(ret), TCGV_LOW(addr),
1793                      TCGV_HIGH(addr), mem_index);
1794     tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1795 #endif
1796 }
1797
1798 static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
1799 {
1800 #if TARGET_LONG_BITS == 32
1801     tcg_gen_op3i_i32(INDEX_op_qemu_ld32u, ret, addr, mem_index);
1802 #else
1803     tcg_gen_op4i_i32(INDEX_op_qemu_ld32u, TCGV_LOW(ret), TCGV_LOW(addr),
1804                      TCGV_HIGH(addr), mem_index);
1805     tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1806 #endif
1807 }
1808
1809 static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
1810 {
1811 #if TARGET_LONG_BITS == 32
1812     tcg_gen_op4i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), addr, mem_index);
1813 #else
1814     tcg_gen_op5i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret),
1815                      TCGV_LOW(addr), TCGV_HIGH(addr), mem_index);
1816 #endif
1817 }
1818
1819 static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
1820 {
1821 #if TARGET_LONG_BITS == 32
1822     tcg_gen_op3i_i32(INDEX_op_qemu_st8, arg, addr, mem_index);
1823 #else
1824     tcg_gen_op4i_i32(INDEX_op_qemu_st8, TCGV_LOW(arg), TCGV_LOW(addr),
1825                      TCGV_HIGH(addr), mem_index);
1826 #endif
1827 }
1828
1829 static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
1830 {
1831 #if TARGET_LONG_BITS == 32
1832     tcg_gen_op3i_i32(INDEX_op_qemu_st16, arg, addr, mem_index);
1833 #else
1834     tcg_gen_op4i_i32(INDEX_op_qemu_st16, TCGV_LOW(arg), TCGV_LOW(addr),
1835                      TCGV_HIGH(addr), mem_index);
1836 #endif
1837 }
1838
1839 static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
1840 {
1841 #if TARGET_LONG_BITS == 32
1842     tcg_gen_op3i_i32(INDEX_op_qemu_st32, arg, addr, mem_index);
1843 #else
1844     tcg_gen_op4i_i32(INDEX_op_qemu_st32, TCGV_LOW(arg), TCGV_LOW(addr),
1845                      TCGV_HIGH(addr), mem_index);
1846 #endif
1847 }
1848
1849 static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
1850 {
1851 #if TARGET_LONG_BITS == 32
1852     tcg_gen_op4i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), addr,
1853                      mem_index);
1854 #else
1855     tcg_gen_op5i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg),
1856                      TCGV_LOW(addr), TCGV_HIGH(addr), mem_index);
1857 #endif
1858 }
1859
1860 #define tcg_gen_ld_ptr tcg_gen_ld_i32
1861 #define tcg_gen_discard_ptr tcg_gen_discard_i32
1862
1863 #else /* TCG_TARGET_REG_BITS == 32 */
1864
1865 static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
1866 {
1867     tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8u, ret, addr, mem_index);
1868 }
1869
1870 static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
1871 {
1872     tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8s, ret, addr, mem_index);
1873 }
1874
1875 static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
1876 {
1877     tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16u, ret, addr, mem_index);
1878 }
1879
1880 static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
1881 {
1882     tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16s, ret, addr, mem_index);
1883 }
1884
1885 static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
1886 {
1887     tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32u, ret, addr, mem_index);
1888 }
1889
1890 static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
1891 {
1892     tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32s, ret, addr, mem_index);
1893 }
1894
1895 static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
1896 {
1897     tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_ld64, ret, addr, mem_index);
1898 }
1899
1900 static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
1901 {
1902     tcg_gen_qemu_ldst_op(INDEX_op_qemu_st8, arg, addr, mem_index);
1903 }
1904
1905 static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
1906 {
1907     tcg_gen_qemu_ldst_op(INDEX_op_qemu_st16, arg, addr, mem_index);
1908 }
1909
1910 static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
1911 {
1912     tcg_gen_qemu_ldst_op(INDEX_op_qemu_st32, arg, addr, mem_index);
1913 }
1914
1915 static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
1916 {
1917     tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_st64, arg, addr, mem_index);
1918 }
1919
1920 #define tcg_gen_ld_ptr tcg_gen_ld_i64
1921 #define tcg_gen_discard_ptr tcg_gen_discard_i64
1922
1923 #endif /* TCG_TARGET_REG_BITS != 32 */
1924
1925 #if TARGET_LONG_BITS == 64
1926 #define TCG_TYPE_TL TCG_TYPE_I64
1927 #define tcg_gen_movi_tl tcg_gen_movi_i64
1928 #define tcg_gen_mov_tl tcg_gen_mov_i64
1929 #define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
1930 #define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
1931 #define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
1932 #define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
1933 #define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
1934 #define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
1935 #define tcg_gen_ld_tl tcg_gen_ld_i64
1936 #define tcg_gen_st8_tl tcg_gen_st8_i64
1937 #define tcg_gen_st16_tl tcg_gen_st16_i64
1938 #define tcg_gen_st32_tl tcg_gen_st32_i64
1939 #define tcg_gen_st_tl tcg_gen_st_i64
1940 #define tcg_gen_add_tl tcg_gen_add_i64
1941 #define tcg_gen_addi_tl tcg_gen_addi_i64
1942 #define tcg_gen_sub_tl tcg_gen_sub_i64
1943 #define tcg_gen_neg_tl tcg_gen_neg_i64
1944 #define tcg_gen_subfi_tl tcg_gen_subfi_i64
1945 #define tcg_gen_subi_tl tcg_gen_subi_i64
1946 #define tcg_gen_and_tl tcg_gen_and_i64
1947 #define tcg_gen_andi_tl tcg_gen_andi_i64
1948 #define tcg_gen_or_tl tcg_gen_or_i64
1949 #define tcg_gen_ori_tl tcg_gen_ori_i64
1950 #define tcg_gen_xor_tl tcg_gen_xor_i64
1951 #define tcg_gen_xori_tl tcg_gen_xori_i64
1952 #define tcg_gen_not_tl tcg_gen_not_i64
1953 #define tcg_gen_shl_tl tcg_gen_shl_i64
1954 #define tcg_gen_shli_tl tcg_gen_shli_i64
1955 #define tcg_gen_shr_tl tcg_gen_shr_i64
1956 #define tcg_gen_shri_tl tcg_gen_shri_i64
1957 #define tcg_gen_sar_tl tcg_gen_sar_i64
1958 #define tcg_gen_sari_tl tcg_gen_sari_i64
1959 #define tcg_gen_brcond_tl tcg_gen_brcond_i64
1960 #define tcg_gen_brcondi_tl tcg_gen_brcondi_i64
1961 #define tcg_gen_mul_tl tcg_gen_mul_i64
1962 #define tcg_gen_muli_tl tcg_gen_muli_i64
1963 #define tcg_gen_discard_tl tcg_gen_discard_i64
1964 #define tcg_gen_trunc_tl_i32 tcg_gen_trunc_i64_i32
1965 #define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
1966 #define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
1967 #define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
1968 #define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
1969 #define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
1970 #define tcg_gen_ext8u_tl tcg_gen_ext8u_i64
1971 #define tcg_gen_ext8s_tl tcg_gen_ext8s_i64
1972 #define tcg_gen_ext16u_tl tcg_gen_ext16u_i64
1973 #define tcg_gen_ext16s_tl tcg_gen_ext16s_i64
1974 #define tcg_gen_ext32u_tl tcg_gen_ext32u_i64
1975 #define tcg_gen_ext32s_tl tcg_gen_ext32s_i64
1976 #define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
1977 #define tcg_gen_andc_tl tcg_gen_andc_i64
1978 #define tcg_gen_eqv_tl tcg_gen_eqv_i64
1979 #define tcg_gen_nand_tl tcg_gen_nand_i64
1980 #define tcg_gen_nor_tl tcg_gen_nor_i64
1981 #define tcg_gen_orc_tl tcg_gen_orc_i64
1982 #define tcg_gen_rotl_tl tcg_gen_rotl_i64
1983 #define tcg_gen_rotli_tl tcg_gen_rotli_i64
1984 #define tcg_gen_rotr_tl tcg_gen_rotr_i64
1985 #define tcg_gen_rotri_tl tcg_gen_rotri_i64
1986 #define tcg_const_tl tcg_const_i64
1987 #define tcg_const_local_tl tcg_const_local_i64
1988 #else
1989 #define TCG_TYPE_TL TCG_TYPE_I32
1990 #define tcg_gen_movi_tl tcg_gen_movi_i32
1991 #define tcg_gen_mov_tl tcg_gen_mov_i32
1992 #define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
1993 #define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
1994 #define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
1995 #define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
1996 #define tcg_gen_ld32u_tl tcg_gen_ld_i32
1997 #define tcg_gen_ld32s_tl tcg_gen_ld_i32
1998 #define tcg_gen_ld_tl tcg_gen_ld_i32
1999 #define tcg_gen_st8_tl tcg_gen_st8_i32
2000 #define tcg_gen_st16_tl tcg_gen_st16_i32
2001 #define tcg_gen_st32_tl tcg_gen_st_i32
2002 #define tcg_gen_st_tl tcg_gen_st_i32
2003 #define tcg_gen_add_tl tcg_gen_add_i32
2004 #define tcg_gen_addi_tl tcg_gen_addi_i32
2005 #define tcg_gen_sub_tl tcg_gen_sub_i32
2006 #define tcg_gen_neg_tl tcg_gen_neg_i32
2007 #define tcg_gen_subfi_tl tcg_gen_subfi_i32
2008 #define tcg_gen_subi_tl tcg_gen_subi_i32
2009 #define tcg_gen_and_tl tcg_gen_and_i32
2010 #define tcg_gen_andi_tl tcg_gen_andi_i32
2011 #define tcg_gen_or_tl tcg_gen_or_i32
2012 #define tcg_gen_ori_tl tcg_gen_ori_i32
2013 #define tcg_gen_xor_tl tcg_gen_xor_i32
2014 #define tcg_gen_xori_tl tcg_gen_xori_i32
2015 #define tcg_gen_not_tl tcg_gen_not_i32
2016 #define tcg_gen_shl_tl tcg_gen_shl_i32
2017 #define tcg_gen_shli_tl tcg_gen_shli_i32
2018 #define tcg_gen_shr_tl tcg_gen_shr_i32
2019 #define tcg_gen_shri_tl tcg_gen_shri_i32
2020 #define tcg_gen_sar_tl tcg_gen_sar_i32
2021 #define tcg_gen_sari_tl tcg_gen_sari_i32
2022 #define tcg_gen_brcond_tl tcg_gen_brcond_i32
2023 #define tcg_gen_brcondi_tl tcg_gen_brcondi_i32
2024 #define tcg_gen_mul_tl tcg_gen_mul_i32
2025 #define tcg_gen_muli_tl tcg_gen_muli_i32
2026 #define tcg_gen_discard_tl tcg_gen_discard_i32
2027 #define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
2028 #define tcg_gen_trunc_i64_tl tcg_gen_trunc_i64_i32
2029 #define tcg_gen_extu_i32_tl tcg_gen_mov_i32
2030 #define tcg_gen_ext_i32_tl tcg_gen_mov_i32
2031 #define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
2032 #define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
2033 #define tcg_gen_ext8u_tl tcg_gen_ext8u_i32
2034 #define tcg_gen_ext8s_tl tcg_gen_ext8s_i32
2035 #define tcg_gen_ext16u_tl tcg_gen_ext16u_i32
2036 #define tcg_gen_ext16s_tl tcg_gen_ext16s_i32
2037 #define tcg_gen_ext32u_tl tcg_gen_mov_i32
2038 #define tcg_gen_ext32s_tl tcg_gen_mov_i32
2039 #define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
2040 #define tcg_gen_andc_tl tcg_gen_andc_i32
2041 #define tcg_gen_eqv_tl tcg_gen_eqv_i32
2042 #define tcg_gen_nand_tl tcg_gen_nand_i32
2043 #define tcg_gen_nor_tl tcg_gen_nor_i32
2044 #define tcg_gen_orc_tl tcg_gen_orc_i32
2045 #define tcg_gen_rotl_tl tcg_gen_rotl_i32
2046 #define tcg_gen_rotli_tl tcg_gen_rotli_i32
2047 #define tcg_gen_rotr_tl tcg_gen_rotr_i32
2048 #define tcg_gen_rotri_tl tcg_gen_rotri_i32
2049 #define tcg_const_tl tcg_const_i32
2050 #define tcg_const_local_tl tcg_const_local_i32
2051 #endif
2052
2053 #if TCG_TARGET_REG_BITS == 32
2054 #define tcg_gen_add_ptr tcg_gen_add_i32
2055 #define tcg_gen_addi_ptr tcg_gen_addi_i32
2056 #define tcg_gen_ext_i32_ptr tcg_gen_mov_i32
2057 #else /* TCG_TARGET_REG_BITS == 32 */
2058 #define tcg_gen_add_ptr tcg_gen_add_i64
2059 #define tcg_gen_addi_ptr tcg_gen_addi_i64
2060 #define tcg_gen_ext_i32_ptr tcg_gen_ext_i32_i64
2061 #endif /* TCG_TARGET_REG_BITS != 32 */
2062