2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 * DEF(name, oargs, iargs, cargs, flags)
30 DEF(end
, 0, 0, 0, 0) /* must be kept first */
35 DEF(nopn
, 0, 0, 1, 0) /* variable number of parameters */
37 DEF(discard
, 1, 0, 0, 0)
39 DEF(set_label
, 0, 0, 1, TCG_OPF_BB_END
)
40 DEF(call
, 0, 1, 2, TCG_OPF_SIDE_EFFECTS
) /* variable number of parameters */
41 DEF(jmp
, 0, 1, 0, TCG_OPF_BB_END
| TCG_OPF_SIDE_EFFECTS
)
42 DEF(br
, 0, 0, 1, TCG_OPF_BB_END
| TCG_OPF_SIDE_EFFECTS
)
44 #define IMPL(X) (X ? 0 : TCG_OPF_NOT_PRESENT)
45 #if TCG_TARGET_REG_BITS == 32
46 # define IMPL64 TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT
48 # define IMPL64 TCG_OPF_64BIT
51 DEF(mov_i32
, 1, 1, 0, 0)
52 DEF(movi_i32
, 1, 0, 1, 0)
53 DEF(setcond_i32
, 1, 2, 1, 0)
54 DEF(movcond_i32
, 1, 4, 1, IMPL(TCG_TARGET_HAS_movcond_i32
))
56 DEF(ld8u_i32
, 1, 1, 1, 0)
57 DEF(ld8s_i32
, 1, 1, 1, 0)
58 DEF(ld16u_i32
, 1, 1, 1, 0)
59 DEF(ld16s_i32
, 1, 1, 1, 0)
60 DEF(ld_i32
, 1, 1, 1, 0)
61 DEF(st8_i32
, 0, 2, 1, TCG_OPF_SIDE_EFFECTS
)
62 DEF(st16_i32
, 0, 2, 1, TCG_OPF_SIDE_EFFECTS
)
63 DEF(st_i32
, 0, 2, 1, TCG_OPF_SIDE_EFFECTS
)
65 DEF(add_i32
, 1, 2, 0, 0)
66 DEF(sub_i32
, 1, 2, 0, 0)
67 DEF(mul_i32
, 1, 2, 0, 0)
68 DEF(div_i32
, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32
))
69 DEF(divu_i32
, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32
))
70 DEF(rem_i32
, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32
))
71 DEF(remu_i32
, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32
))
72 DEF(div2_i32
, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32
))
73 DEF(divu2_i32
, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32
))
74 DEF(and_i32
, 1, 2, 0, 0)
75 DEF(or_i32
, 1, 2, 0, 0)
76 DEF(xor_i32
, 1, 2, 0, 0)
78 DEF(shl_i32
, 1, 2, 0, 0)
79 DEF(shr_i32
, 1, 2, 0, 0)
80 DEF(sar_i32
, 1, 2, 0, 0)
81 DEF(rotl_i32
, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32
))
82 DEF(rotr_i32
, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32
))
83 DEF(deposit_i32
, 1, 2, 2, IMPL(TCG_TARGET_HAS_deposit_i32
))
85 DEF(brcond_i32
, 0, 2, 2, TCG_OPF_BB_END
| TCG_OPF_SIDE_EFFECTS
)
87 DEF(add2_i32
, 2, 4, 0, IMPL(TCG_TARGET_REG_BITS
== 32))
88 DEF(sub2_i32
, 2, 4, 0, IMPL(TCG_TARGET_REG_BITS
== 32))
89 DEF(brcond2_i32
, 0, 4, 2,
90 TCG_OPF_BB_END
| TCG_OPF_SIDE_EFFECTS
| IMPL(TCG_TARGET_REG_BITS
== 32))
91 DEF(mulu2_i32
, 2, 2, 0, IMPL(TCG_TARGET_REG_BITS
== 32))
92 DEF(setcond2_i32
, 1, 4, 1, IMPL(TCG_TARGET_REG_BITS
== 32))
94 DEF(ext8s_i32
, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8s_i32
))
95 DEF(ext16s_i32
, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16s_i32
))
96 DEF(ext8u_i32
, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8u_i32
))
97 DEF(ext16u_i32
, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16u_i32
))
98 DEF(bswap16_i32
, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap16_i32
))
99 DEF(bswap32_i32
, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap32_i32
))
100 DEF(not_i32
, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_i32
))
101 DEF(neg_i32
, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_i32
))
102 DEF(andc_i32
, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_i32
))
103 DEF(orc_i32
, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_i32
))
104 DEF(eqv_i32
, 1, 2, 0, IMPL(TCG_TARGET_HAS_eqv_i32
))
105 DEF(nand_i32
, 1, 2, 0, IMPL(TCG_TARGET_HAS_nand_i32
))
106 DEF(nor_i32
, 1, 2, 0, IMPL(TCG_TARGET_HAS_nor_i32
))
108 DEF(mov_i64
, 1, 1, 0, IMPL64
)
109 DEF(movi_i64
, 1, 0, 1, IMPL64
)
110 DEF(setcond_i64
, 1, 2, 1, IMPL64
)
111 DEF(movcond_i64
, 1, 4, 1, IMPL64
| IMPL(TCG_TARGET_HAS_movcond_i64
))
113 DEF(ld8u_i64
, 1, 1, 1, IMPL64
)
114 DEF(ld8s_i64
, 1, 1, 1, IMPL64
)
115 DEF(ld16u_i64
, 1, 1, 1, IMPL64
)
116 DEF(ld16s_i64
, 1, 1, 1, IMPL64
)
117 DEF(ld32u_i64
, 1, 1, 1, IMPL64
)
118 DEF(ld32s_i64
, 1, 1, 1, IMPL64
)
119 DEF(ld_i64
, 1, 1, 1, IMPL64
)
120 DEF(st8_i64
, 0, 2, 1, TCG_OPF_SIDE_EFFECTS
| IMPL64
)
121 DEF(st16_i64
, 0, 2, 1, TCG_OPF_SIDE_EFFECTS
| IMPL64
)
122 DEF(st32_i64
, 0, 2, 1, TCG_OPF_SIDE_EFFECTS
| IMPL64
)
123 DEF(st_i64
, 0, 2, 1, TCG_OPF_SIDE_EFFECTS
| IMPL64
)
125 DEF(add_i64
, 1, 2, 0, IMPL64
)
126 DEF(sub_i64
, 1, 2, 0, IMPL64
)
127 DEF(mul_i64
, 1, 2, 0, IMPL64
)
128 DEF(div_i64
, 1, 2, 0, IMPL64
| IMPL(TCG_TARGET_HAS_div_i64
))
129 DEF(divu_i64
, 1, 2, 0, IMPL64
| IMPL(TCG_TARGET_HAS_div_i64
))
130 DEF(rem_i64
, 1, 2, 0, IMPL64
| IMPL(TCG_TARGET_HAS_div_i64
))
131 DEF(remu_i64
, 1, 2, 0, IMPL64
| IMPL(TCG_TARGET_HAS_div_i64
))
132 DEF(div2_i64
, 2, 3, 0, IMPL64
| IMPL(TCG_TARGET_HAS_div2_i64
))
133 DEF(divu2_i64
, 2, 3, 0, IMPL64
| IMPL(TCG_TARGET_HAS_div2_i64
))
134 DEF(and_i64
, 1, 2, 0, IMPL64
)
135 DEF(or_i64
, 1, 2, 0, IMPL64
)
136 DEF(xor_i64
, 1, 2, 0, IMPL64
)
138 DEF(shl_i64
, 1, 2, 0, IMPL64
)
139 DEF(shr_i64
, 1, 2, 0, IMPL64
)
140 DEF(sar_i64
, 1, 2, 0, IMPL64
)
141 DEF(rotl_i64
, 1, 2, 0, IMPL64
| IMPL(TCG_TARGET_HAS_rot_i64
))
142 DEF(rotr_i64
, 1, 2, 0, IMPL64
| IMPL(TCG_TARGET_HAS_rot_i64
))
143 DEF(deposit_i64
, 1, 2, 2, IMPL64
| IMPL(TCG_TARGET_HAS_deposit_i64
))
145 DEF(brcond_i64
, 0, 2, 2, TCG_OPF_BB_END
| TCG_OPF_SIDE_EFFECTS
| IMPL64
)
146 DEF(ext8s_i64
, 1, 1, 0, IMPL64
| IMPL(TCG_TARGET_HAS_ext8s_i64
))
147 DEF(ext16s_i64
, 1, 1, 0, IMPL64
| IMPL(TCG_TARGET_HAS_ext16s_i64
))
148 DEF(ext32s_i64
, 1, 1, 0, IMPL64
| IMPL(TCG_TARGET_HAS_ext32s_i64
))
149 DEF(ext8u_i64
, 1, 1, 0, IMPL64
| IMPL(TCG_TARGET_HAS_ext8u_i64
))
150 DEF(ext16u_i64
, 1, 1, 0, IMPL64
| IMPL(TCG_TARGET_HAS_ext16u_i64
))
151 DEF(ext32u_i64
, 1, 1, 0, IMPL64
| IMPL(TCG_TARGET_HAS_ext32u_i64
))
152 DEF(bswap16_i64
, 1, 1, 0, IMPL64
| IMPL(TCG_TARGET_HAS_bswap16_i64
))
153 DEF(bswap32_i64
, 1, 1, 0, IMPL64
| IMPL(TCG_TARGET_HAS_bswap32_i64
))
154 DEF(bswap64_i64
, 1, 1, 0, IMPL64
| IMPL(TCG_TARGET_HAS_bswap64_i64
))
155 DEF(not_i64
, 1, 1, 0, IMPL64
| IMPL(TCG_TARGET_HAS_not_i64
))
156 DEF(neg_i64
, 1, 1, 0, IMPL64
| IMPL(TCG_TARGET_HAS_neg_i64
))
157 DEF(andc_i64
, 1, 2, 0, IMPL64
| IMPL(TCG_TARGET_HAS_andc_i64
))
158 DEF(orc_i64
, 1, 2, 0, IMPL64
| IMPL(TCG_TARGET_HAS_orc_i64
))
159 DEF(eqv_i64
, 1, 2, 0, IMPL64
| IMPL(TCG_TARGET_HAS_eqv_i64
))
160 DEF(nand_i64
, 1, 2, 0, IMPL64
| IMPL(TCG_TARGET_HAS_nand_i64
))
161 DEF(nor_i64
, 1, 2, 0, IMPL64
| IMPL(TCG_TARGET_HAS_nor_i64
))
164 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
165 DEF(debug_insn_start
, 0, 0, 2, 0)
167 DEF(debug_insn_start
, 0, 0, 1, 0)
169 DEF(exit_tb
, 0, 0, 1, TCG_OPF_BB_END
| TCG_OPF_SIDE_EFFECTS
)
170 DEF(goto_tb
, 0, 0, 1, TCG_OPF_BB_END
| TCG_OPF_SIDE_EFFECTS
)
171 /* Note: even if TARGET_LONG_BITS is not defined, the INDEX_op
172 constants must be defined */
173 #if TCG_TARGET_REG_BITS == 32
174 #if TARGET_LONG_BITS == 32
175 DEF(qemu_ld8u
, 1, 1, 1, TCG_OPF_CALL_CLOBBER
| TCG_OPF_SIDE_EFFECTS
)
177 DEF(qemu_ld8u
, 1, 2, 1, TCG_OPF_CALL_CLOBBER
| TCG_OPF_SIDE_EFFECTS
)
179 #if TARGET_LONG_BITS == 32
180 DEF(qemu_ld8s
, 1, 1, 1, TCG_OPF_CALL_CLOBBER
| TCG_OPF_SIDE_EFFECTS
)
182 DEF(qemu_ld8s
, 1, 2, 1, TCG_OPF_CALL_CLOBBER
| TCG_OPF_SIDE_EFFECTS
)
184 #if TARGET_LONG_BITS == 32
185 DEF(qemu_ld16u
, 1, 1, 1, TCG_OPF_CALL_CLOBBER
| TCG_OPF_SIDE_EFFECTS
)
187 DEF(qemu_ld16u
, 1, 2, 1, TCG_OPF_CALL_CLOBBER
| TCG_OPF_SIDE_EFFECTS
)
189 #if TARGET_LONG_BITS == 32
190 DEF(qemu_ld16s
, 1, 1, 1, TCG_OPF_CALL_CLOBBER
| TCG_OPF_SIDE_EFFECTS
)
192 DEF(qemu_ld16s
, 1, 2, 1, TCG_OPF_CALL_CLOBBER
| TCG_OPF_SIDE_EFFECTS
)
194 #if TARGET_LONG_BITS == 32
195 DEF(qemu_ld32
, 1, 1, 1, TCG_OPF_CALL_CLOBBER
| TCG_OPF_SIDE_EFFECTS
)
197 DEF(qemu_ld32
, 1, 2, 1, TCG_OPF_CALL_CLOBBER
| TCG_OPF_SIDE_EFFECTS
)
199 #if TARGET_LONG_BITS == 32
200 DEF(qemu_ld64
, 2, 1, 1, TCG_OPF_CALL_CLOBBER
| TCG_OPF_SIDE_EFFECTS
)
202 DEF(qemu_ld64
, 2, 2, 1, TCG_OPF_CALL_CLOBBER
| TCG_OPF_SIDE_EFFECTS
)
205 #if TARGET_LONG_BITS == 32
206 DEF(qemu_st8
, 0, 2, 1, TCG_OPF_CALL_CLOBBER
| TCG_OPF_SIDE_EFFECTS
)
208 DEF(qemu_st8
, 0, 3, 1, TCG_OPF_CALL_CLOBBER
| TCG_OPF_SIDE_EFFECTS
)
210 #if TARGET_LONG_BITS == 32
211 DEF(qemu_st16
, 0, 2, 1, TCG_OPF_CALL_CLOBBER
| TCG_OPF_SIDE_EFFECTS
)
213 DEF(qemu_st16
, 0, 3, 1, TCG_OPF_CALL_CLOBBER
| TCG_OPF_SIDE_EFFECTS
)
215 #if TARGET_LONG_BITS == 32
216 DEF(qemu_st32
, 0, 2, 1, TCG_OPF_CALL_CLOBBER
| TCG_OPF_SIDE_EFFECTS
)
218 DEF(qemu_st32
, 0, 3, 1, TCG_OPF_CALL_CLOBBER
| TCG_OPF_SIDE_EFFECTS
)
220 #if TARGET_LONG_BITS == 32
221 DEF(qemu_st64
, 0, 3, 1, TCG_OPF_CALL_CLOBBER
| TCG_OPF_SIDE_EFFECTS
)
223 DEF(qemu_st64
, 0, 4, 1, TCG_OPF_CALL_CLOBBER
| TCG_OPF_SIDE_EFFECTS
)
226 #else /* TCG_TARGET_REG_BITS == 32 */
228 DEF(qemu_ld8u
, 1, 1, 1, TCG_OPF_CALL_CLOBBER
| TCG_OPF_SIDE_EFFECTS
)
229 DEF(qemu_ld8s
, 1, 1, 1, TCG_OPF_CALL_CLOBBER
| TCG_OPF_SIDE_EFFECTS
)
230 DEF(qemu_ld16u
, 1, 1, 1, TCG_OPF_CALL_CLOBBER
| TCG_OPF_SIDE_EFFECTS
)
231 DEF(qemu_ld16s
, 1, 1, 1, TCG_OPF_CALL_CLOBBER
| TCG_OPF_SIDE_EFFECTS
)
232 DEF(qemu_ld32
, 1, 1, 1, TCG_OPF_CALL_CLOBBER
| TCG_OPF_SIDE_EFFECTS
)
233 DEF(qemu_ld32u
, 1, 1, 1, TCG_OPF_CALL_CLOBBER
| TCG_OPF_SIDE_EFFECTS
)
234 DEF(qemu_ld32s
, 1, 1, 1, TCG_OPF_CALL_CLOBBER
| TCG_OPF_SIDE_EFFECTS
)
235 DEF(qemu_ld64
, 1, 1, 1, TCG_OPF_CALL_CLOBBER
| TCG_OPF_SIDE_EFFECTS
)
237 DEF(qemu_st8
, 0, 2, 1, TCG_OPF_CALL_CLOBBER
| TCG_OPF_SIDE_EFFECTS
)
238 DEF(qemu_st16
, 0, 2, 1, TCG_OPF_CALL_CLOBBER
| TCG_OPF_SIDE_EFFECTS
)
239 DEF(qemu_st32
, 0, 2, 1, TCG_OPF_CALL_CLOBBER
| TCG_OPF_SIDE_EFFECTS
)
240 DEF(qemu_st64
, 0, 2, 1, TCG_OPF_CALL_CLOBBER
| TCG_OPF_SIDE_EFFECTS
)
242 #endif /* TCG_TARGET_REG_BITS != 32 */