2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2009, 2011 Stefan Weil
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "tcg-be-null.h"
28 * - See TODO comments in code.
31 /* Marker for missing code. */
34 fprintf(stderr, "TODO %s:%u: %s()\n", \
35 __FILE__, __LINE__, __func__); \
39 /* Bitfield n...m (in 32 bit value). */
40 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
42 /* Macros used in tcg_target_op_defs. */
45 #if TCG_TARGET_REG_BITS == 32
50 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
58 /* TODO: documentation. */
59 static const TCGTargetOpDef tcg_target_op_defs
[] = {
60 { INDEX_op_exit_tb
, { NULL
} },
61 { INDEX_op_goto_tb
, { NULL
} },
62 { INDEX_op_call
, { RI
} },
63 { INDEX_op_br
, { NULL
} },
65 { INDEX_op_mov_i32
, { R
, R
} },
66 { INDEX_op_movi_i32
, { R
} },
68 { INDEX_op_ld8u_i32
, { R
, R
} },
69 { INDEX_op_ld8s_i32
, { R
, R
} },
70 { INDEX_op_ld16u_i32
, { R
, R
} },
71 { INDEX_op_ld16s_i32
, { R
, R
} },
72 { INDEX_op_ld_i32
, { R
, R
} },
73 { INDEX_op_st8_i32
, { R
, R
} },
74 { INDEX_op_st16_i32
, { R
, R
} },
75 { INDEX_op_st_i32
, { R
, R
} },
77 { INDEX_op_add_i32
, { R
, RI
, RI
} },
78 { INDEX_op_sub_i32
, { R
, RI
, RI
} },
79 { INDEX_op_mul_i32
, { R
, RI
, RI
} },
80 #if TCG_TARGET_HAS_div_i32
81 { INDEX_op_div_i32
, { R
, R
, R
} },
82 { INDEX_op_divu_i32
, { R
, R
, R
} },
83 { INDEX_op_rem_i32
, { R
, R
, R
} },
84 { INDEX_op_remu_i32
, { R
, R
, R
} },
85 #elif TCG_TARGET_HAS_div2_i32
86 { INDEX_op_div2_i32
, { R
, R
, "0", "1", R
} },
87 { INDEX_op_divu2_i32
, { R
, R
, "0", "1", R
} },
89 /* TODO: Does R, RI, RI result in faster code than R, R, RI?
90 If both operands are constants, we can optimize. */
91 { INDEX_op_and_i32
, { R
, RI
, RI
} },
92 #if TCG_TARGET_HAS_andc_i32
93 { INDEX_op_andc_i32
, { R
, RI
, RI
} },
95 #if TCG_TARGET_HAS_eqv_i32
96 { INDEX_op_eqv_i32
, { R
, RI
, RI
} },
98 #if TCG_TARGET_HAS_nand_i32
99 { INDEX_op_nand_i32
, { R
, RI
, RI
} },
101 #if TCG_TARGET_HAS_nor_i32
102 { INDEX_op_nor_i32
, { R
, RI
, RI
} },
104 { INDEX_op_or_i32
, { R
, RI
, RI
} },
105 #if TCG_TARGET_HAS_orc_i32
106 { INDEX_op_orc_i32
, { R
, RI
, RI
} },
108 { INDEX_op_xor_i32
, { R
, RI
, RI
} },
109 { INDEX_op_shl_i32
, { R
, RI
, RI
} },
110 { INDEX_op_shr_i32
, { R
, RI
, RI
} },
111 { INDEX_op_sar_i32
, { R
, RI
, RI
} },
112 #if TCG_TARGET_HAS_rot_i32
113 { INDEX_op_rotl_i32
, { R
, RI
, RI
} },
114 { INDEX_op_rotr_i32
, { R
, RI
, RI
} },
116 #if TCG_TARGET_HAS_deposit_i32
117 { INDEX_op_deposit_i32
, { R
, "0", R
} },
120 { INDEX_op_brcond_i32
, { R
, RI
} },
122 { INDEX_op_setcond_i32
, { R
, R
, RI
} },
123 #if TCG_TARGET_REG_BITS == 64
124 { INDEX_op_setcond_i64
, { R
, R
, RI
} },
125 #endif /* TCG_TARGET_REG_BITS == 64 */
127 #if TCG_TARGET_REG_BITS == 32
128 /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */
129 { INDEX_op_add2_i32
, { R
, R
, R
, R
, R
, R
} },
130 { INDEX_op_sub2_i32
, { R
, R
, R
, R
, R
, R
} },
131 { INDEX_op_brcond2_i32
, { R
, R
, RI
, RI
} },
132 { INDEX_op_mulu2_i32
, { R
, R
, R
, R
} },
133 { INDEX_op_setcond2_i32
, { R
, R
, R
, RI
, RI
} },
136 #if TCG_TARGET_HAS_not_i32
137 { INDEX_op_not_i32
, { R
, R
} },
139 #if TCG_TARGET_HAS_neg_i32
140 { INDEX_op_neg_i32
, { R
, R
} },
143 #if TCG_TARGET_REG_BITS == 64
144 { INDEX_op_mov_i64
, { R
, R
} },
145 { INDEX_op_movi_i64
, { R
} },
147 { INDEX_op_ld8u_i64
, { R
, R
} },
148 { INDEX_op_ld8s_i64
, { R
, R
} },
149 { INDEX_op_ld16u_i64
, { R
, R
} },
150 { INDEX_op_ld16s_i64
, { R
, R
} },
151 { INDEX_op_ld32u_i64
, { R
, R
} },
152 { INDEX_op_ld32s_i64
, { R
, R
} },
153 { INDEX_op_ld_i64
, { R
, R
} },
155 { INDEX_op_st8_i64
, { R
, R
} },
156 { INDEX_op_st16_i64
, { R
, R
} },
157 { INDEX_op_st32_i64
, { R
, R
} },
158 { INDEX_op_st_i64
, { R
, R
} },
160 { INDEX_op_add_i64
, { R
, RI
, RI
} },
161 { INDEX_op_sub_i64
, { R
, RI
, RI
} },
162 { INDEX_op_mul_i64
, { R
, RI
, RI
} },
163 #if TCG_TARGET_HAS_div_i64
164 { INDEX_op_div_i64
, { R
, R
, R
} },
165 { INDEX_op_divu_i64
, { R
, R
, R
} },
166 { INDEX_op_rem_i64
, { R
, R
, R
} },
167 { INDEX_op_remu_i64
, { R
, R
, R
} },
168 #elif TCG_TARGET_HAS_div2_i64
169 { INDEX_op_div2_i64
, { R
, R
, "0", "1", R
} },
170 { INDEX_op_divu2_i64
, { R
, R
, "0", "1", R
} },
172 { INDEX_op_and_i64
, { R
, RI
, RI
} },
173 #if TCG_TARGET_HAS_andc_i64
174 { INDEX_op_andc_i64
, { R
, RI
, RI
} },
176 #if TCG_TARGET_HAS_eqv_i64
177 { INDEX_op_eqv_i64
, { R
, RI
, RI
} },
179 #if TCG_TARGET_HAS_nand_i64
180 { INDEX_op_nand_i64
, { R
, RI
, RI
} },
182 #if TCG_TARGET_HAS_nor_i64
183 { INDEX_op_nor_i64
, { R
, RI
, RI
} },
185 { INDEX_op_or_i64
, { R
, RI
, RI
} },
186 #if TCG_TARGET_HAS_orc_i64
187 { INDEX_op_orc_i64
, { R
, RI
, RI
} },
189 { INDEX_op_xor_i64
, { R
, RI
, RI
} },
190 { INDEX_op_shl_i64
, { R
, RI
, RI
} },
191 { INDEX_op_shr_i64
, { R
, RI
, RI
} },
192 { INDEX_op_sar_i64
, { R
, RI
, RI
} },
193 #if TCG_TARGET_HAS_rot_i64
194 { INDEX_op_rotl_i64
, { R
, RI
, RI
} },
195 { INDEX_op_rotr_i64
, { R
, RI
, RI
} },
197 #if TCG_TARGET_HAS_deposit_i64
198 { INDEX_op_deposit_i64
, { R
, "0", R
} },
200 { INDEX_op_brcond_i64
, { R
, RI
} },
202 #if TCG_TARGET_HAS_ext8s_i64
203 { INDEX_op_ext8s_i64
, { R
, R
} },
205 #if TCG_TARGET_HAS_ext16s_i64
206 { INDEX_op_ext16s_i64
, { R
, R
} },
208 #if TCG_TARGET_HAS_ext32s_i64
209 { INDEX_op_ext32s_i64
, { R
, R
} },
211 #if TCG_TARGET_HAS_ext8u_i64
212 { INDEX_op_ext8u_i64
, { R
, R
} },
214 #if TCG_TARGET_HAS_ext16u_i64
215 { INDEX_op_ext16u_i64
, { R
, R
} },
217 #if TCG_TARGET_HAS_ext32u_i64
218 { INDEX_op_ext32u_i64
, { R
, R
} },
220 #if TCG_TARGET_HAS_bswap16_i64
221 { INDEX_op_bswap16_i64
, { R
, R
} },
223 #if TCG_TARGET_HAS_bswap32_i64
224 { INDEX_op_bswap32_i64
, { R
, R
} },
226 #if TCG_TARGET_HAS_bswap64_i64
227 { INDEX_op_bswap64_i64
, { R
, R
} },
229 #if TCG_TARGET_HAS_not_i64
230 { INDEX_op_not_i64
, { R
, R
} },
232 #if TCG_TARGET_HAS_neg_i64
233 { INDEX_op_neg_i64
, { R
, R
} },
235 #endif /* TCG_TARGET_REG_BITS == 64 */
237 { INDEX_op_qemu_ld8u
, { R
, L
} },
238 { INDEX_op_qemu_ld8s
, { R
, L
} },
239 { INDEX_op_qemu_ld16u
, { R
, L
} },
240 { INDEX_op_qemu_ld16s
, { R
, L
} },
241 { INDEX_op_qemu_ld32
, { R
, L
} },
242 #if TCG_TARGET_REG_BITS == 64
243 { INDEX_op_qemu_ld32u
, { R
, L
} },
244 { INDEX_op_qemu_ld32s
, { R
, L
} },
246 { INDEX_op_qemu_ld64
, { R64
, L
} },
248 { INDEX_op_qemu_st8
, { R
, S
} },
249 { INDEX_op_qemu_st16
, { R
, S
} },
250 { INDEX_op_qemu_st32
, { R
, S
} },
251 { INDEX_op_qemu_st64
, { R64
, S
} },
253 #if TCG_TARGET_HAS_ext8s_i32
254 { INDEX_op_ext8s_i32
, { R
, R
} },
256 #if TCG_TARGET_HAS_ext16s_i32
257 { INDEX_op_ext16s_i32
, { R
, R
} },
259 #if TCG_TARGET_HAS_ext8u_i32
260 { INDEX_op_ext8u_i32
, { R
, R
} },
262 #if TCG_TARGET_HAS_ext16u_i32
263 { INDEX_op_ext16u_i32
, { R
, R
} },
266 #if TCG_TARGET_HAS_bswap16_i32
267 { INDEX_op_bswap16_i32
, { R
, R
} },
269 #if TCG_TARGET_HAS_bswap32_i32
270 { INDEX_op_bswap32_i32
, { R
, R
} },
276 static const int tcg_target_reg_alloc_order
[] = {
281 #if 0 /* used for TCG_REG_CALL_STACK */
287 #if TCG_TARGET_NB_REGS >= 16
299 #if MAX_OPC_PARAM_IARGS != 5
300 # error Fix needed, number of supported input arguments changed!
303 static const int tcg_target_call_iarg_regs
[] = {
308 #if 0 /* used for TCG_REG_CALL_STACK */
312 #if TCG_TARGET_REG_BITS == 32
313 /* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */
316 #if TCG_TARGET_NB_REGS >= 16
321 # error Too few input registers available
326 static const int tcg_target_call_oarg_regs
[] = {
328 #if TCG_TARGET_REG_BITS == 32
334 static const char *const tcg_target_reg_names
[TCG_TARGET_NB_REGS
] = {
343 #if TCG_TARGET_NB_REGS >= 16
352 #if TCG_TARGET_NB_REGS >= 32
374 static void patch_reloc(uint8_t *code_ptr
, int type
,
375 intptr_t value
, intptr_t addend
)
377 /* tcg_out_reloc always uses the same type, addend. */
378 assert(type
== sizeof(tcg_target_long
));
381 *(tcg_target_long
*)code_ptr
= value
;
384 /* Parse target specific constraints. */
385 static int target_parse_constraint(TCGArgConstraint
*ct
, const char **pct_str
)
387 const char *ct_str
= *pct_str
;
390 case 'L': /* qemu_ld constraint */
391 case 'S': /* qemu_st constraint */
392 ct
->ct
|= TCG_CT_REG
;
393 tcg_regset_set32(ct
->u
.regs
, 0, BIT(TCG_TARGET_NB_REGS
) - 1);
403 #if defined(CONFIG_DEBUG_TCG_INTERPRETER)
404 /* Show current bytecode. Used by tcg interpreter. */
405 void tci_disas(uint8_t opc
)
407 const TCGOpDef
*def
= &tcg_op_defs
[opc
];
408 fprintf(stderr
, "TCG %s %u, %u, %u\n",
409 def
->name
, def
->nb_oargs
, def
->nb_iargs
, def
->nb_cargs
);
413 /* Write value (native size). */
414 static void tcg_out_i(TCGContext
*s
, tcg_target_ulong v
)
416 *(tcg_target_ulong
*)s
->code_ptr
= v
;
417 s
->code_ptr
+= sizeof(tcg_target_ulong
);
421 static void tcg_out_op_t(TCGContext
*s
, TCGOpcode op
)
427 /* Write register. */
428 static void tcg_out_r(TCGContext
*s
, TCGArg t0
)
430 assert(t0
< TCG_TARGET_NB_REGS
);
434 /* Write register or constant (native size). */
435 static void tcg_out_ri(TCGContext
*s
, int const_arg
, TCGArg arg
)
438 assert(const_arg
== 1);
439 tcg_out8(s
, TCG_CONST
);
446 /* Write register or constant (32 bit). */
447 static void tcg_out_ri32(TCGContext
*s
, int const_arg
, TCGArg arg
)
450 assert(const_arg
== 1);
451 tcg_out8(s
, TCG_CONST
);
458 #if TCG_TARGET_REG_BITS == 64
459 /* Write register or constant (64 bit). */
460 static void tcg_out_ri64(TCGContext
*s
, int const_arg
, TCGArg arg
)
463 assert(const_arg
== 1);
464 tcg_out8(s
, TCG_CONST
);
473 static void tci_out_label(TCGContext
*s
, TCGArg arg
)
475 TCGLabel
*label
= &s
->labels
[arg
];
476 if (label
->has_value
) {
477 tcg_out_i(s
, label
->u
.value
);
478 assert(label
->u
.value
);
480 tcg_out_reloc(s
, s
->code_ptr
, sizeof(tcg_target_ulong
), arg
, 0);
481 s
->code_ptr
+= sizeof(tcg_target_ulong
);
485 static void tcg_out_ld(TCGContext
*s
, TCGType type
, TCGReg ret
, TCGReg arg1
,
488 uint8_t *old_code_ptr
= s
->code_ptr
;
489 if (type
== TCG_TYPE_I32
) {
490 tcg_out_op_t(s
, INDEX_op_ld_i32
);
495 assert(type
== TCG_TYPE_I64
);
496 #if TCG_TARGET_REG_BITS == 64
497 tcg_out_op_t(s
, INDEX_op_ld_i64
);
500 assert(arg2
== (int32_t)arg2
);
506 old_code_ptr
[1] = s
->code_ptr
- old_code_ptr
;
509 static void tcg_out_mov(TCGContext
*s
, TCGType type
, TCGReg ret
, TCGReg arg
)
511 uint8_t *old_code_ptr
= s
->code_ptr
;
513 #if TCG_TARGET_REG_BITS == 32
514 tcg_out_op_t(s
, INDEX_op_mov_i32
);
516 tcg_out_op_t(s
, INDEX_op_mov_i64
);
520 old_code_ptr
[1] = s
->code_ptr
- old_code_ptr
;
523 static void tcg_out_movi(TCGContext
*s
, TCGType type
,
524 TCGReg t0
, tcg_target_long arg
)
526 uint8_t *old_code_ptr
= s
->code_ptr
;
527 uint32_t arg32
= arg
;
528 if (type
== TCG_TYPE_I32
|| arg
== arg32
) {
529 tcg_out_op_t(s
, INDEX_op_movi_i32
);
533 assert(type
== TCG_TYPE_I64
);
534 #if TCG_TARGET_REG_BITS == 64
535 tcg_out_op_t(s
, INDEX_op_movi_i64
);
542 old_code_ptr
[1] = s
->code_ptr
- old_code_ptr
;
545 static void tcg_out_op(TCGContext
*s
, TCGOpcode opc
, const TCGArg
*args
,
546 const int *const_args
)
548 uint8_t *old_code_ptr
= s
->code_ptr
;
550 tcg_out_op_t(s
, opc
);
553 case INDEX_op_exit_tb
:
554 tcg_out64(s
, args
[0]);
556 case INDEX_op_goto_tb
:
557 if (s
->tb_jmp_offset
) {
558 /* Direct jump method. */
559 assert(args
[0] < ARRAY_SIZE(s
->tb_jmp_offset
));
560 s
->tb_jmp_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
563 /* Indirect jump method. */
566 assert(args
[0] < ARRAY_SIZE(s
->tb_next_offset
));
567 s
->tb_next_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
570 tci_out_label(s
, args
[0]);
573 tcg_out_ri(s
, const_args
[0], args
[0]);
575 case INDEX_op_setcond_i32
:
576 tcg_out_r(s
, args
[0]);
577 tcg_out_r(s
, args
[1]);
578 tcg_out_ri32(s
, const_args
[2], args
[2]);
579 tcg_out8(s
, args
[3]); /* condition */
581 #if TCG_TARGET_REG_BITS == 32
582 case INDEX_op_setcond2_i32
:
583 /* setcond2_i32 cond, t0, t1_low, t1_high, t2_low, t2_high */
584 tcg_out_r(s
, args
[0]);
585 tcg_out_r(s
, args
[1]);
586 tcg_out_r(s
, args
[2]);
587 tcg_out_ri32(s
, const_args
[3], args
[3]);
588 tcg_out_ri32(s
, const_args
[4], args
[4]);
589 tcg_out8(s
, args
[5]); /* condition */
591 #elif TCG_TARGET_REG_BITS == 64
592 case INDEX_op_setcond_i64
:
593 tcg_out_r(s
, args
[0]);
594 tcg_out_r(s
, args
[1]);
595 tcg_out_ri64(s
, const_args
[2], args
[2]);
596 tcg_out8(s
, args
[3]); /* condition */
599 case INDEX_op_movi_i32
:
600 TODO(); /* Handled by tcg_out_movi? */
602 case INDEX_op_ld8u_i32
:
603 case INDEX_op_ld8s_i32
:
604 case INDEX_op_ld16u_i32
:
605 case INDEX_op_ld16s_i32
:
606 case INDEX_op_ld_i32
:
607 case INDEX_op_st8_i32
:
608 case INDEX_op_st16_i32
:
609 case INDEX_op_st_i32
:
610 case INDEX_op_ld8u_i64
:
611 case INDEX_op_ld8s_i64
:
612 case INDEX_op_ld16u_i64
:
613 case INDEX_op_ld16s_i64
:
614 case INDEX_op_ld32u_i64
:
615 case INDEX_op_ld32s_i64
:
616 case INDEX_op_ld_i64
:
617 case INDEX_op_st8_i64
:
618 case INDEX_op_st16_i64
:
619 case INDEX_op_st32_i64
:
620 case INDEX_op_st_i64
:
621 tcg_out_r(s
, args
[0]);
622 tcg_out_r(s
, args
[1]);
623 assert(args
[2] == (int32_t)args
[2]);
624 tcg_out32(s
, args
[2]);
626 case INDEX_op_add_i32
:
627 case INDEX_op_sub_i32
:
628 case INDEX_op_mul_i32
:
629 case INDEX_op_and_i32
:
630 case INDEX_op_andc_i32
: /* Optional (TCG_TARGET_HAS_andc_i32). */
631 case INDEX_op_eqv_i32
: /* Optional (TCG_TARGET_HAS_eqv_i32). */
632 case INDEX_op_nand_i32
: /* Optional (TCG_TARGET_HAS_nand_i32). */
633 case INDEX_op_nor_i32
: /* Optional (TCG_TARGET_HAS_nor_i32). */
634 case INDEX_op_or_i32
:
635 case INDEX_op_orc_i32
: /* Optional (TCG_TARGET_HAS_orc_i32). */
636 case INDEX_op_xor_i32
:
637 case INDEX_op_shl_i32
:
638 case INDEX_op_shr_i32
:
639 case INDEX_op_sar_i32
:
640 case INDEX_op_rotl_i32
: /* Optional (TCG_TARGET_HAS_rot_i32). */
641 case INDEX_op_rotr_i32
: /* Optional (TCG_TARGET_HAS_rot_i32). */
642 tcg_out_r(s
, args
[0]);
643 tcg_out_ri32(s
, const_args
[1], args
[1]);
644 tcg_out_ri32(s
, const_args
[2], args
[2]);
646 case INDEX_op_deposit_i32
: /* Optional (TCG_TARGET_HAS_deposit_i32). */
647 tcg_out_r(s
, args
[0]);
648 tcg_out_r(s
, args
[1]);
649 tcg_out_r(s
, args
[2]);
650 assert(args
[3] <= UINT8_MAX
);
651 tcg_out8(s
, args
[3]);
652 assert(args
[4] <= UINT8_MAX
);
653 tcg_out8(s
, args
[4]);
656 #if TCG_TARGET_REG_BITS == 64
657 case INDEX_op_mov_i64
:
658 case INDEX_op_movi_i64
:
661 case INDEX_op_add_i64
:
662 case INDEX_op_sub_i64
:
663 case INDEX_op_mul_i64
:
664 case INDEX_op_and_i64
:
665 case INDEX_op_andc_i64
: /* Optional (TCG_TARGET_HAS_andc_i64). */
666 case INDEX_op_eqv_i64
: /* Optional (TCG_TARGET_HAS_eqv_i64). */
667 case INDEX_op_nand_i64
: /* Optional (TCG_TARGET_HAS_nand_i64). */
668 case INDEX_op_nor_i64
: /* Optional (TCG_TARGET_HAS_nor_i64). */
669 case INDEX_op_or_i64
:
670 case INDEX_op_orc_i64
: /* Optional (TCG_TARGET_HAS_orc_i64). */
671 case INDEX_op_xor_i64
:
672 case INDEX_op_shl_i64
:
673 case INDEX_op_shr_i64
:
674 case INDEX_op_sar_i64
:
675 case INDEX_op_rotl_i64
: /* Optional (TCG_TARGET_HAS_rot_i64). */
676 case INDEX_op_rotr_i64
: /* Optional (TCG_TARGET_HAS_rot_i64). */
677 tcg_out_r(s
, args
[0]);
678 tcg_out_ri64(s
, const_args
[1], args
[1]);
679 tcg_out_ri64(s
, const_args
[2], args
[2]);
681 case INDEX_op_deposit_i64
: /* Optional (TCG_TARGET_HAS_deposit_i64). */
682 tcg_out_r(s
, args
[0]);
683 tcg_out_r(s
, args
[1]);
684 tcg_out_r(s
, args
[2]);
685 assert(args
[3] <= UINT8_MAX
);
686 tcg_out8(s
, args
[3]);
687 assert(args
[4] <= UINT8_MAX
);
688 tcg_out8(s
, args
[4]);
690 case INDEX_op_div_i64
: /* Optional (TCG_TARGET_HAS_div_i64). */
691 case INDEX_op_divu_i64
: /* Optional (TCG_TARGET_HAS_div_i64). */
692 case INDEX_op_rem_i64
: /* Optional (TCG_TARGET_HAS_div_i64). */
693 case INDEX_op_remu_i64
: /* Optional (TCG_TARGET_HAS_div_i64). */
696 case INDEX_op_div2_i64
: /* Optional (TCG_TARGET_HAS_div2_i64). */
697 case INDEX_op_divu2_i64
: /* Optional (TCG_TARGET_HAS_div2_i64). */
700 case INDEX_op_brcond_i64
:
701 tcg_out_r(s
, args
[0]);
702 tcg_out_ri64(s
, const_args
[1], args
[1]);
703 tcg_out8(s
, args
[2]); /* condition */
704 tci_out_label(s
, args
[3]);
706 case INDEX_op_bswap16_i64
: /* Optional (TCG_TARGET_HAS_bswap16_i64). */
707 case INDEX_op_bswap32_i64
: /* Optional (TCG_TARGET_HAS_bswap32_i64). */
708 case INDEX_op_bswap64_i64
: /* Optional (TCG_TARGET_HAS_bswap64_i64). */
709 case INDEX_op_not_i64
: /* Optional (TCG_TARGET_HAS_not_i64). */
710 case INDEX_op_neg_i64
: /* Optional (TCG_TARGET_HAS_neg_i64). */
711 case INDEX_op_ext8s_i64
: /* Optional (TCG_TARGET_HAS_ext8s_i64). */
712 case INDEX_op_ext8u_i64
: /* Optional (TCG_TARGET_HAS_ext8u_i64). */
713 case INDEX_op_ext16s_i64
: /* Optional (TCG_TARGET_HAS_ext16s_i64). */
714 case INDEX_op_ext16u_i64
: /* Optional (TCG_TARGET_HAS_ext16u_i64). */
715 case INDEX_op_ext32s_i64
: /* Optional (TCG_TARGET_HAS_ext32s_i64). */
716 case INDEX_op_ext32u_i64
: /* Optional (TCG_TARGET_HAS_ext32u_i64). */
717 #endif /* TCG_TARGET_REG_BITS == 64 */
718 case INDEX_op_neg_i32
: /* Optional (TCG_TARGET_HAS_neg_i32). */
719 case INDEX_op_not_i32
: /* Optional (TCG_TARGET_HAS_not_i32). */
720 case INDEX_op_ext8s_i32
: /* Optional (TCG_TARGET_HAS_ext8s_i32). */
721 case INDEX_op_ext16s_i32
: /* Optional (TCG_TARGET_HAS_ext16s_i32). */
722 case INDEX_op_ext8u_i32
: /* Optional (TCG_TARGET_HAS_ext8u_i32). */
723 case INDEX_op_ext16u_i32
: /* Optional (TCG_TARGET_HAS_ext16u_i32). */
724 case INDEX_op_bswap16_i32
: /* Optional (TCG_TARGET_HAS_bswap16_i32). */
725 case INDEX_op_bswap32_i32
: /* Optional (TCG_TARGET_HAS_bswap32_i32). */
726 tcg_out_r(s
, args
[0]);
727 tcg_out_r(s
, args
[1]);
729 case INDEX_op_div_i32
: /* Optional (TCG_TARGET_HAS_div_i32). */
730 case INDEX_op_divu_i32
: /* Optional (TCG_TARGET_HAS_div_i32). */
731 case INDEX_op_rem_i32
: /* Optional (TCG_TARGET_HAS_div_i32). */
732 case INDEX_op_remu_i32
: /* Optional (TCG_TARGET_HAS_div_i32). */
733 tcg_out_r(s
, args
[0]);
734 tcg_out_ri32(s
, const_args
[1], args
[1]);
735 tcg_out_ri32(s
, const_args
[2], args
[2]);
737 case INDEX_op_div2_i32
: /* Optional (TCG_TARGET_HAS_div2_i32). */
738 case INDEX_op_divu2_i32
: /* Optional (TCG_TARGET_HAS_div2_i32). */
741 #if TCG_TARGET_REG_BITS == 32
742 case INDEX_op_add2_i32
:
743 case INDEX_op_sub2_i32
:
744 tcg_out_r(s
, args
[0]);
745 tcg_out_r(s
, args
[1]);
746 tcg_out_r(s
, args
[2]);
747 tcg_out_r(s
, args
[3]);
748 tcg_out_r(s
, args
[4]);
749 tcg_out_r(s
, args
[5]);
751 case INDEX_op_brcond2_i32
:
752 tcg_out_r(s
, args
[0]);
753 tcg_out_r(s
, args
[1]);
754 tcg_out_ri32(s
, const_args
[2], args
[2]);
755 tcg_out_ri32(s
, const_args
[3], args
[3]);
756 tcg_out8(s
, args
[4]); /* condition */
757 tci_out_label(s
, args
[5]);
759 case INDEX_op_mulu2_i32
:
760 tcg_out_r(s
, args
[0]);
761 tcg_out_r(s
, args
[1]);
762 tcg_out_r(s
, args
[2]);
763 tcg_out_r(s
, args
[3]);
766 case INDEX_op_brcond_i32
:
767 tcg_out_r(s
, args
[0]);
768 tcg_out_ri32(s
, const_args
[1], args
[1]);
769 tcg_out8(s
, args
[2]); /* condition */
770 tci_out_label(s
, args
[3]);
772 case INDEX_op_qemu_ld8u
:
773 case INDEX_op_qemu_ld8s
:
774 case INDEX_op_qemu_ld16u
:
775 case INDEX_op_qemu_ld16s
:
776 case INDEX_op_qemu_ld32
:
777 #if TCG_TARGET_REG_BITS == 64
778 case INDEX_op_qemu_ld32s
:
779 case INDEX_op_qemu_ld32u
:
781 tcg_out_r(s
, *args
++);
782 tcg_out_r(s
, *args
++);
783 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
784 tcg_out_r(s
, *args
++);
786 #ifdef CONFIG_SOFTMMU
790 case INDEX_op_qemu_ld64
:
791 tcg_out_r(s
, *args
++);
792 #if TCG_TARGET_REG_BITS == 32
793 tcg_out_r(s
, *args
++);
795 tcg_out_r(s
, *args
++);
796 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
797 tcg_out_r(s
, *args
++);
799 #ifdef CONFIG_SOFTMMU
803 case INDEX_op_qemu_st8
:
804 case INDEX_op_qemu_st16
:
805 case INDEX_op_qemu_st32
:
806 tcg_out_r(s
, *args
++);
807 tcg_out_r(s
, *args
++);
808 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
809 tcg_out_r(s
, *args
++);
811 #ifdef CONFIG_SOFTMMU
815 case INDEX_op_qemu_st64
:
816 tcg_out_r(s
, *args
++);
817 #if TCG_TARGET_REG_BITS == 32
818 tcg_out_r(s
, *args
++);
820 tcg_out_r(s
, *args
++);
821 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
822 tcg_out_r(s
, *args
++);
824 #ifdef CONFIG_SOFTMMU
832 fprintf(stderr
, "Missing: %s\n", tcg_op_defs
[opc
].name
);
835 old_code_ptr
[1] = s
->code_ptr
- old_code_ptr
;
838 static void tcg_out_st(TCGContext
*s
, TCGType type
, TCGReg arg
, TCGReg arg1
,
841 uint8_t *old_code_ptr
= s
->code_ptr
;
842 if (type
== TCG_TYPE_I32
) {
843 tcg_out_op_t(s
, INDEX_op_st_i32
);
848 assert(type
== TCG_TYPE_I64
);
849 #if TCG_TARGET_REG_BITS == 64
850 tcg_out_op_t(s
, INDEX_op_st_i64
);
858 old_code_ptr
[1] = s
->code_ptr
- old_code_ptr
;
861 /* Test if a constant matches the constraint. */
862 static int tcg_target_const_match(tcg_target_long val
,
863 const TCGArgConstraint
*arg_ct
)
865 /* No need to return 0 or 1, 0 or != 0 is good enough. */
866 return arg_ct
->ct
& TCG_CT_CONST
;
869 static void tcg_target_init(TCGContext
*s
)
871 #if defined(CONFIG_DEBUG_TCG_INTERPRETER)
872 const char *envval
= getenv("DEBUG_TCG");
874 qemu_set_log(strtol(envval
, NULL
, 0));
878 /* The current code uses uint8_t for tcg operations. */
879 assert(ARRAY_SIZE(tcg_op_defs
) <= UINT8_MAX
);
881 /* Registers available for 32 bit operations. */
882 tcg_regset_set32(tcg_target_available_regs
[TCG_TYPE_I32
], 0,
883 BIT(TCG_TARGET_NB_REGS
) - 1);
884 /* Registers available for 64 bit operations. */
885 tcg_regset_set32(tcg_target_available_regs
[TCG_TYPE_I64
], 0,
886 BIT(TCG_TARGET_NB_REGS
) - 1);
887 /* TODO: Which registers should be set here? */
888 tcg_regset_set32(tcg_target_call_clobber_regs
, 0,
889 BIT(TCG_TARGET_NB_REGS
) - 1);
891 tcg_regset_clear(s
->reserved_regs
);
892 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_CALL_STACK
);
893 tcg_add_target_add_op_defs(tcg_target_op_defs
);
895 /* We use negative offsets from "sp" so that we can distinguish
896 stores that might pretend to be call arguments. */
897 tcg_set_frame(s
, TCG_REG_CALL_STACK
,
898 -CPU_TEMP_BUF_NLONGS
* sizeof(long),
899 CPU_TEMP_BUF_NLONGS
* sizeof(long));
902 /* Generate global QEMU prologue and epilogue code. */
903 static inline void tcg_target_qemu_prologue(TCGContext
*s
)