translate.c

   1 /*
   2  *  Host code generation
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include <stdarg.h>
  21 #include <stdlib.h>
  22 #include <stdio.h>
  23 #include <string.h>
  24 #include <inttypes.h>
  25
  26 #include "config.h"
  27
  28 #define IN_OP_I386
  29 #if defined(TARGET_I386)
  30 #include "cpu-i386.h"
  31 #define OPC_CPU_H "opc-i386.h"
  32 #elif defined(TARGET_ARM)
  33 #include "cpu-arm.h"
  34 #define OPC_CPU_H "opc-arm.h"
  35 #else
  36 #error unsupported target CPU
  37 #endif
  38
  39 #include "exec.h"
  40 #include "disas.h"
  41
  42 enum {
  43 #define DEF(s, n, copy_size) INDEX_op_ ## s,
  44 #include OPC_CPU_H
  45 #undef DEF
  46     NB_OPS,
  47 };
  48
  49 #include "dyngen.h"
  50 #if defined(TARGET_I386)
  51 #include "op-i386.h"
  52 #elif defined(TARGET_ARM)
  53 #include "op-arm.h"
  54 #else
  55 #error unsupported target CPU
  56 #endif
  57
  58 uint16_t gen_opc_buf[OPC_BUF_SIZE];
  59 uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
  60 uint32_t gen_opc_pc[OPC_BUF_SIZE];
  61 uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
  62
  63
  64 #ifdef DEBUG_DISAS
  65 static const char *op_str[] = {
  66 #define DEF(s, n, copy_size) #s,
  67 #include OPC_CPU_H
  68 #undef DEF
  69 };
  70
  71 static uint8_t op_nb_args[] = {
  72 #define DEF(s, n, copy_size) n,
  73 #include OPC_CPU_H
  74 #undef DEF
  75 };
  76
  77 void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf)
  78 {
  79     const uint16_t *opc_ptr;
  80     const uint32_t *opparam_ptr;
  81     int c, n, i;
  82
  83     opc_ptr = opc_buf;
  84     opparam_ptr = opparam_buf;
  85     for(;;) {
  86         c = *opc_ptr++;
  87         n = op_nb_args[c];
  88         fprintf(logfile, "0x%04x: %s",
  89                 (int)(opc_ptr - opc_buf - 1), op_str[c]);
  90         for(i = 0; i < n; i++) {
  91             fprintf(logfile, " 0x%x", opparam_ptr[i]);
  92         }
  93         fprintf(logfile, "\n");
  94         if (c == INDEX_op_end)
  95             break;
  96         opparam_ptr += n;
  97     }
  98 }
  99
 100 #endif
 101
 102 /* return non zero if the very first instruction is invalid so that
 103    the virtual CPU can trigger an exception.
 104
 105    '*gen_code_size_ptr' contains the size of the generated code (host
 106    code).
 107 */
 108 int cpu_gen_code(TranslationBlock *tb,
 109                  int max_code_size, int *gen_code_size_ptr)
 110 {
 111     uint8_t *gen_code_buf;
 112     int gen_code_size;
 113
 114     if (gen_intermediate_code(tb, 0) < 0)
 115         return -1;
 116
 117     /* generate machine code */
 118     tb->tb_next_offset[0] = 0xffff;
 119     tb->tb_next_offset[1] = 0xffff;
 120     gen_code_buf = tb->tc_ptr;
 121     gen_code_size = dyngen_code(gen_code_buf, tb->tb_next_offset,
 122 #ifdef USE_DIRECT_JUMP
 123                                 tb->tb_jmp_offset,
 124 #else
 125                                 NULL,
 126 #endif
 127                                 gen_opc_buf, gen_opparam_buf);
 128     *gen_code_size_ptr = gen_code_size;
 129 #ifdef DEBUG_DISAS
 130     if (loglevel) {
 131         fprintf(logfile, "OUT: [size=%d]\n", *gen_code_size_ptr);
 132         disas(logfile, gen_code_buf, *gen_code_size_ptr, 1, 0);
 133         fprintf(logfile, "\n");
 134         fflush(logfile);
 135     }
 136 #endif
 137     return 0;
 138 }
 139
 140 static const unsigned short opc_copy_size[] = {
 141 #define DEF(s, n, copy_size) copy_size,
 142 #include OPC_CPU_H
 143 #undef DEF
 144 };
 145
 146 /* The simulated PC corresponding to
 147    'searched_pc' in the generated code is searched. 0 is returned if
 148    found. *found_pc contains the found PC.
 149  */
 150 int cpu_search_pc(TranslationBlock *tb,
 151                   uint32_t *found_pc, unsigned long searched_pc)
 152 {
 153     int j, c;
 154     unsigned long tc_ptr;
 155     uint16_t *opc_ptr;
 156
 157     if (gen_intermediate_code(tb, 1) < 0)
 158         return -1;
 159
 160     /* find opc index corresponding to search_pc */
 161     tc_ptr = (unsigned long)tb->tc_ptr;
 162     if (searched_pc < tc_ptr)
 163         return -1;
 164     j = 0;
 165     opc_ptr = gen_opc_buf;
 166     for(;;) {
 167         c = *opc_ptr;
 168         if (c == INDEX_op_end)
 169             return -1;
 170         tc_ptr += opc_copy_size[c];
 171         if (searched_pc < tc_ptr)
 172             break;
 173         opc_ptr++;
 174     }
 175     j = opc_ptr - gen_opc_buf;
 176     /* now find start of instruction before */
 177     while (gen_opc_instr_start[j] == 0)
 178         j--;
 179     *found_pc = gen_opc_pc[j];
 180     return 0;
 181 }
 182
 183