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1 /*
2 * QEMU PC System Emulator
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include <stdlib.h>
25 #include <stdio.h>
26 #include <stdarg.h>
27 #include <string.h>
28 #include <getopt.h>
29 #include <inttypes.h>
30 #include <unistd.h>
31 #include <sys/mman.h>
32 #include <fcntl.h>
33 #include <signal.h>
34 #include <time.h>
35 #include <sys/time.h>
36 #include <malloc.h>
37 #include <termios.h>
38 #include <sys/poll.h>
39 #include <errno.h>
40 #include <sys/wait.h>
41
42 #include <sys/ioctl.h>
43 #include <sys/socket.h>
44 #include <linux/if.h>
45 #include <linux/if_tun.h>
46
47 #include "cpu-i386.h"
48 #include "disas.h"
49 #include "thunk.h"
50
51 #include "vl.h"
52
53 #define DEBUG_LOGFILE "/tmp/vl.log"
54 #define DEFAULT_NETWORK_SCRIPT "/etc/vl-ifup"
55
56 //#define DEBUG_UNUSED_IOPORT
57 //#define DEBUG_IRQ_LATENCY
58
59 #define PHYS_RAM_BASE 0xa8000000
60 #define KERNEL_LOAD_ADDR 0x00100000
61 #define INITRD_LOAD_ADDR 0x00400000
62 #define KERNEL_PARAMS_ADDR 0x00090000
63
64 /* from plex86 (BSD license) */
65 struct __attribute__ ((packed)) linux_params {
66 // For 0x00..0x3f, see 'struct screen_info' in linux/include/linux/tty.h.
67 // I just padded out the VESA parts, rather than define them.
68
69 /* 0x000 */ uint8_t orig_x;
70 /* 0x001 */ uint8_t orig_y;
71 /* 0x002 */ uint16_t ext_mem_k;
72 /* 0x004 */ uint16_t orig_video_page;
73 /* 0x006 */ uint8_t orig_video_mode;
74 /* 0x007 */ uint8_t orig_video_cols;
75 /* 0x008 */ uint16_t unused1;
76 /* 0x00a */ uint16_t orig_video_ega_bx;
77 /* 0x00c */ uint16_t unused2;
78 /* 0x00e */ uint8_t orig_video_lines;
79 /* 0x00f */ uint8_t orig_video_isVGA;
80 /* 0x010 */ uint16_t orig_video_points;
81 /* 0x012 */ uint8_t pad0[0x20 - 0x12]; // VESA info.
82 /* 0x020 */ uint16_t cl_magic; // Commandline magic number (0xA33F)
83 /* 0x022 */ uint16_t cl_offset; // Commandline offset. Address of commandline
84 // is calculated as 0x90000 + cl_offset, bu
85 // only if cl_magic == 0xA33F.
86 /* 0x024 */ uint8_t pad1[0x40 - 0x24]; // VESA info.
87
88 /* 0x040 */ uint8_t apm_bios_info[20]; // struct apm_bios_info
89 /* 0x054 */ uint8_t pad2[0x80 - 0x54];
90
91 // Following 2 from 'struct drive_info_struct' in drivers/block/cciss.h.
92 // Might be truncated?
93 /* 0x080 */ uint8_t hd0_info[16]; // hd0-disk-parameter from intvector 0x41
94 /* 0x090 */ uint8_t hd1_info[16]; // hd1-disk-parameter from intvector 0x46
95
96 // System description table truncated to 16 bytes
97 // From 'struct sys_desc_table_struct' in linux/arch/i386/kernel/setup.c.
98 /* 0x0a0 */ uint16_t sys_description_len;
99 /* 0x0a2 */ uint8_t sys_description_table[14];
100 // [0] machine id
101 // [1] machine submodel id
102 // [2] BIOS revision
103 // [3] bit1: MCA bus
104
105 /* 0x0b0 */ uint8_t pad3[0x1e0 - 0xb0];
106 /* 0x1e0 */ uint32_t alt_mem_k;
107 /* 0x1e4 */ uint8_t pad4[4];
108 /* 0x1e8 */ uint8_t e820map_entries;
109 /* 0x1e9 */ uint8_t eddbuf_entries; // EDD_NR
110 /* 0x1ea */ uint8_t pad5[0x1f1 - 0x1ea];
111 /* 0x1f1 */ uint8_t setup_sects; // size of setup.S, number of sectors
112 /* 0x1f2 */ uint16_t mount_root_rdonly; // MOUNT_ROOT_RDONLY (if !=0)
113 /* 0x1f4 */ uint16_t sys_size; // size of compressed kernel-part in the
114 // (b)zImage-file (in 16 byte units, rounded up)
115 /* 0x1f6 */ uint16_t swap_dev; // (unused AFAIK)
116 /* 0x1f8 */ uint16_t ramdisk_flags;
117 /* 0x1fa */ uint16_t vga_mode; // (old one)
118 /* 0x1fc */ uint16_t orig_root_dev; // (high=Major, low=minor)
119 /* 0x1fe */ uint8_t pad6[1];
120 /* 0x1ff */ uint8_t aux_device_info;
121 /* 0x200 */ uint16_t jump_setup; // Jump to start of setup code,
122 // aka "reserved" field.
123 /* 0x202 */ uint8_t setup_signature[4]; // Signature for SETUP-header, ="HdrS"
124 /* 0x206 */ uint16_t header_format_version; // Version number of header format;
125 /* 0x208 */ uint8_t setup_S_temp0[8]; // Used by setup.S for communication with
126 // boot loaders, look there.
127 /* 0x210 */ uint8_t loader_type;
128 // 0 for old one.
129 // else 0xTV:
130 // T=0: LILO
131 // T=1: Loadlin
132 // T=2: bootsect-loader
133 // T=3: SYSLINUX
134 // T=4: ETHERBOOT
135 // V=version
136 /* 0x211 */ uint8_t loadflags;
137 // bit0 = 1: kernel is loaded high (bzImage)
138 // bit7 = 1: Heap and pointer (see below) set by boot
139 // loader.
140 /* 0x212 */ uint16_t setup_S_temp1;
141 /* 0x214 */ uint32_t kernel_start;
142 /* 0x218 */ uint32_t initrd_start;
143 /* 0x21c */ uint32_t initrd_size;
144 /* 0x220 */ uint8_t setup_S_temp2[4];
145 /* 0x224 */ uint16_t setup_S_heap_end_pointer;
146 /* 0x226 */ uint8_t pad7[0x2d0 - 0x226];
147
148 /* 0x2d0 : Int 15, ax=e820 memory map. */
149 // (linux/include/asm-i386/e820.h, 'struct e820entry')
150 #define E820MAX 32
151 #define E820_RAM 1
152 #define E820_RESERVED 2
153 #define E820_ACPI 3 /* usable as RAM once ACPI tables have been read */
154 #define E820_NVS 4
155 struct {
156 uint64_t addr;
157 uint64_t size;
158 uint32_t type;
159 } e820map[E820MAX];
160
161 /* 0x550 */ uint8_t pad8[0x600 - 0x550];
162
163 // BIOS Enhanced Disk Drive Services.
164 // (From linux/include/asm-i386/edd.h, 'struct edd_info')
165 // Each 'struct edd_info is 78 bytes, times a max of 6 structs in array.
166 /* 0x600 */ uint8_t eddbuf[0x7d4 - 0x600];
167
168 /* 0x7d4 */ uint8_t pad9[0x800 - 0x7d4];
169 /* 0x800 */ uint8_t commandline[0x800];
170
171 /* 0x1000 */
172 uint64_t gdt_table[256];
173 uint64_t idt_table[48];
174 };
175
176 #define KERNEL_CS 0x10
177 #define KERNEL_DS 0x18
178
179 typedef void (IOPortWriteFunc)(CPUX86State *env, uint32_t address, uint32_t data);
180 typedef uint32_t (IOPortReadFunc)(CPUX86State *env, uint32_t address);
181
182 #define MAX_IOPORTS 4096
183
184 char phys_ram_file[1024];
185 CPUX86State *global_env;
186 CPUX86State *cpu_single_env;
187 FILE *logfile = NULL;
188 int loglevel;
189 IOPortReadFunc *ioport_read_table[3][MAX_IOPORTS];
190 IOPortWriteFunc *ioport_write_table[3][MAX_IOPORTS];
191
192 /***********************************************************/
193 /* x86 io ports */
194
195 uint32_t default_ioport_readb(CPUX86State *env, uint32_t address)
196 {
197 #ifdef DEBUG_UNUSED_IOPORT
198 fprintf(stderr, "inb: port=0x%04x\n", address);
199 #endif
200 return 0xff;
201 }
202
203 void default_ioport_writeb(CPUX86State *env, uint32_t address, uint32_t data)
204 {
205 #ifdef DEBUG_UNUSED_IOPORT
206 fprintf(stderr, "outb: port=0x%04x data=0x%02x\n", address, data);
207 #endif
208 }
209
210 /* default is to make two byte accesses */
211 uint32_t default_ioport_readw(CPUX86State *env, uint32_t address)
212 {
213 uint32_t data;
214 data = ioport_read_table[0][address](env, address);
215 data |= ioport_read_table[0][address + 1](env, address + 1) << 8;
216 return data;
217 }
218
219 void default_ioport_writew(CPUX86State *env, uint32_t address, uint32_t data)
220 {
221 ioport_write_table[0][address](env, address, data & 0xff);
222 ioport_write_table[0][address + 1](env, address + 1, (data >> 8) & 0xff);
223 }
224
225 uint32_t default_ioport_readl(CPUX86State *env, uint32_t address)
226 {
227 #ifdef DEBUG_UNUSED_IOPORT
228 fprintf(stderr, "inl: port=0x%04x\n", address);
229 #endif
230 return 0xffffffff;
231 }
232
233 void default_ioport_writel(CPUX86State *env, uint32_t address, uint32_t data)
234 {
235 #ifdef DEBUG_UNUSED_IOPORT
236 fprintf(stderr, "outl: port=0x%04x data=0x%02x\n", address, data);
237 #endif
238 }
239
240 void init_ioports(void)
241 {
242 int i;
243
244 for(i = 0; i < MAX_IOPORTS; i++) {
245 ioport_read_table[0][i] = default_ioport_readb;
246 ioport_write_table[0][i] = default_ioport_writeb;
247 ioport_read_table[1][i] = default_ioport_readw;
248 ioport_write_table[1][i] = default_ioport_writew;
249 ioport_read_table[2][i] = default_ioport_readl;
250 ioport_write_table[2][i] = default_ioport_writel;
251 }
252 }
253
254 /* size is the word size in byte */
255 int register_ioport_read(int start, int length, IOPortReadFunc *func, int size)
256 {
257 int i, bsize;
258
259 if (size == 1)
260 bsize = 0;
261 else if (size == 2)
262 bsize = 1;
263 else if (size == 4)
264 bsize = 2;
265 else
266 return -1;
267 for(i = start; i < start + length; i += size)
268 ioport_read_table[bsize][i] = func;
269 return 0;
270 }
271
272 /* size is the word size in byte */
273 int register_ioport_write(int start, int length, IOPortWriteFunc *func, int size)
274 {
275 int i, bsize;
276
277 if (size == 1)
278 bsize = 0;
279 else if (size == 2)
280 bsize = 1;
281 else if (size == 4)
282 bsize = 2;
283 else
284 return -1;
285 for(i = start; i < start + length; i += size)
286 ioport_write_table[bsize][i] = func;
287 return 0;
288 }
289
290 void pstrcpy(char *buf, int buf_size, const char *str)
291 {
292 int c;
293 char *q = buf;
294
295 if (buf_size <= 0)
296 return;
297
298 for(;;) {
299 c = *str++;
300 if (c == 0 || q >= buf + buf_size - 1)
301 break;
302 *q++ = c;
303 }
304 *q = '\0';
305 }
306
307 /* strcat and truncate. */
308 char *pstrcat(char *buf, int buf_size, const char *s)
309 {
310 int len;
311 len = strlen(buf);
312 if (len < buf_size)
313 pstrcpy(buf + len, buf_size - len, s);
314 return buf;
315 }
316
317 int load_kernel(const char *filename, uint8_t *addr)
318 {
319 int fd, size, setup_sects;
320 uint8_t bootsect[512];
321
322 fd = open(filename, O_RDONLY);
323 if (fd < 0)
324 return -1;
325 if (read(fd, bootsect, 512) != 512)
326 goto fail;
327 setup_sects = bootsect[0x1F1];
328 if (!setup_sects)
329 setup_sects = 4;
330 /* skip 16 bit setup code */
331 lseek(fd, (setup_sects + 1) * 512, SEEK_SET);
332 size = read(fd, addr, 16 * 1024 * 1024);
333 if (size < 0)
334 goto fail;
335 close(fd);
336 return size;
337 fail:
338 close(fd);
339 return -1;
340 }
341
342 /* return the size or -1 if error */
343 int load_image(const char *filename, uint8_t *addr)
344 {
345 int fd, size;
346 fd = open(filename, O_RDONLY);
347 if (fd < 0)
348 return -1;
349 size = lseek(fd, 0, SEEK_END);
350 lseek(fd, 0, SEEK_SET);
351 if (read(fd, addr, size) != size) {
352 close(fd);
353 return -1;
354 }
355 close(fd);
356 return size;
357 }
358
359 void cpu_x86_outb(CPUX86State *env, int addr, int val)
360 {
361 ioport_write_table[0][addr & (MAX_IOPORTS - 1)](env, addr, val);
362 }
363
364 void cpu_x86_outw(CPUX86State *env, int addr, int val)
365 {
366 ioport_write_table[1][addr & (MAX_IOPORTS - 1)](env, addr, val);
367 }
368
369 void cpu_x86_outl(CPUX86State *env, int addr, int val)
370 {
371 ioport_write_table[2][addr & (MAX_IOPORTS - 1)](env, addr, val);
372 }
373
374 int cpu_x86_inb(CPUX86State *env, int addr)
375 {
376 return ioport_read_table[0][addr & (MAX_IOPORTS - 1)](env, addr);
377 }
378
379 int cpu_x86_inw(CPUX86State *env, int addr)
380 {
381 return ioport_read_table[1][addr & (MAX_IOPORTS - 1)](env, addr);
382 }
383
384 int cpu_x86_inl(CPUX86State *env, int addr)
385 {
386 return ioport_read_table[2][addr & (MAX_IOPORTS - 1)](env, addr);
387 }
388
389 /***********************************************************/
390 void ioport80_write(CPUX86State *env, uint32_t addr, uint32_t data)
391 {
392 }
393
394 void hw_error(const char *fmt, ...)
395 {
396 va_list ap;
397
398 va_start(ap, fmt);
399 fprintf(stderr, "qemu: hardware error: ");
400 vfprintf(stderr, fmt, ap);
401 fprintf(stderr, "\n");
402 #ifdef TARGET_I386
403 cpu_x86_dump_state(global_env, stderr, X86_DUMP_FPU | X86_DUMP_CCOP);
404 #endif
405 va_end(ap);
406 abort();
407 }
408
409 /***********************************************************/
410 /* vga emulation */
411 static uint8_t vga_index;
412 static uint8_t vga_regs[256];
413 static int last_cursor_pos;
414
415 void update_console_messages(void)
416 {
417 int c, i, cursor_pos, eol;
418
419 cursor_pos = vga_regs[0x0f] | (vga_regs[0x0e] << 8);
420 eol = 0;
421 for(i = last_cursor_pos; i < cursor_pos; i++) {
422 c = phys_ram_base[0xb8000 + (i) * 2];
423 if (c >= ' ') {
424 putchar(c);
425 eol = 0;
426 } else {
427 if (!eol)
428 putchar('\n');
429 eol = 1;
430 }
431 }
432 fflush(stdout);
433 last_cursor_pos = cursor_pos;
434 }
435
436 /* just to see first Linux console messages, we intercept cursor position */
437 void vga_ioport_write(CPUX86State *env, uint32_t addr, uint32_t data)
438 {
439 switch(addr) {
440 case 0x3d4:
441 vga_index = data;
442 break;
443 case 0x3d5:
444 vga_regs[vga_index] = data;
445 if (vga_index == 0x0f)
446 update_console_messages();
447 break;
448 }
449
450 }
451
452 /***********************************************************/
453 /* cmos emulation */
454
455 #define RTC_SECONDS 0
456 #define RTC_SECONDS_ALARM 1
457 #define RTC_MINUTES 2
458 #define RTC_MINUTES_ALARM 3
459 #define RTC_HOURS 4
460 #define RTC_HOURS_ALARM 5
461 #define RTC_ALARM_DONT_CARE 0xC0
462
463 #define RTC_DAY_OF_WEEK 6
464 #define RTC_DAY_OF_MONTH 7
465 #define RTC_MONTH 8
466 #define RTC_YEAR 9
467
468 #define RTC_REG_A 10
469 #define RTC_REG_B 11
470 #define RTC_REG_C 12
471 #define RTC_REG_D 13
472
473 /* PC cmos mappings */
474 #define REG_EQUIPMENT_BYTE 0x14
475
476 uint8_t cmos_data[128];
477 uint8_t cmos_index;
478
479 void cmos_ioport_write(CPUX86State *env, uint32_t addr, uint32_t data)
480 {
481 if (addr == 0x70) {
482 cmos_index = data & 0x7f;
483 }
484 }
485
486 uint32_t cmos_ioport_read(CPUX86State *env, uint32_t addr)
487 {
488 int ret;
489
490 if (addr == 0x70) {
491 return 0xff;
492 } else {
493 /* toggle update-in-progress bit for Linux (same hack as
494 plex86) */
495 ret = cmos_data[cmos_index];
496 if (cmos_index == RTC_REG_A)
497 cmos_data[RTC_REG_A] ^= 0x80;
498 else if (cmos_index == RTC_REG_C)
499 cmos_data[RTC_REG_C] = 0x00;
500 return ret;
501 }
502 }
503
504
505 static inline int to_bcd(int a)
506 {
507 return ((a / 10) << 4) | (a % 10);
508 }
509
510 void cmos_init(void)
511 {
512 struct tm *tm;
513 time_t ti;
514
515 ti = time(NULL);
516 tm = gmtime(&ti);
517 cmos_data[RTC_SECONDS] = to_bcd(tm->tm_sec);
518 cmos_data[RTC_MINUTES] = to_bcd(tm->tm_min);
519 cmos_data[RTC_HOURS] = to_bcd(tm->tm_hour);
520 cmos_data[RTC_DAY_OF_WEEK] = to_bcd(tm->tm_wday);
521 cmos_data[RTC_DAY_OF_MONTH] = to_bcd(tm->tm_mday);
522 cmos_data[RTC_MONTH] = to_bcd(tm->tm_mon);
523 cmos_data[RTC_YEAR] = to_bcd(tm->tm_year % 100);
524
525 cmos_data[RTC_REG_A] = 0x26;
526 cmos_data[RTC_REG_B] = 0x02;
527 cmos_data[RTC_REG_C] = 0x00;
528 cmos_data[RTC_REG_D] = 0x80;
529
530 cmos_data[REG_EQUIPMENT_BYTE] = 0x02; /* FPU is there */
531
532 register_ioport_write(0x70, 2, cmos_ioport_write, 1);
533 register_ioport_read(0x70, 2, cmos_ioport_read, 1);
534 }
535
536 /***********************************************************/
537 /* 8259 pic emulation */
538
539 typedef struct PicState {
540 uint8_t last_irr; /* edge detection */
541 uint8_t irr; /* interrupt request register */
542 uint8_t imr; /* interrupt mask register */
543 uint8_t isr; /* interrupt service register */
544 uint8_t priority_add; /* used to compute irq priority */
545 uint8_t irq_base;
546 uint8_t read_reg_select;
547 uint8_t special_mask;
548 uint8_t init_state;
549 uint8_t auto_eoi;
550 uint8_t rotate_on_autoeoi;
551 uint8_t init4; /* true if 4 byte init */
552 } PicState;
553
554 /* 0 is master pic, 1 is slave pic */
555 PicState pics[2];
556 int pic_irq_requested;
557
558 /* set irq level. If an edge is detected, then the IRR is set to 1 */
559 static inline void pic_set_irq1(PicState *s, int irq, int level)
560 {
561 int mask;
562 mask = 1 << irq;
563 if (level) {
564 if ((s->last_irr & mask) == 0)
565 s->irr |= mask;
566 s->last_irr |= mask;
567 } else {
568 s->last_irr &= ~mask;
569 }
570 }
571
572 static inline int get_priority(PicState *s, int mask)
573 {
574 int priority;
575 if (mask == 0)
576 return -1;
577 priority = 7;
578 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
579 priority--;
580 return priority;
581 }
582
583 /* return the pic wanted interrupt. return -1 if none */
584 static int pic_get_irq(PicState *s)
585 {
586 int mask, cur_priority, priority;
587
588 mask = s->irr & ~s->imr;
589 priority = get_priority(s, mask);
590 if (priority < 0)
591 return -1;
592 /* compute current priority */
593 cur_priority = get_priority(s, s->isr);
594 if (priority > cur_priority) {
595 /* higher priority found: an irq should be generated */
596 return priority;
597 } else {
598 return -1;
599 }
600 }
601
602 /* raise irq to CPU if necessary. must be called every time the active
603 irq may change */
604 static void pic_update_irq(void)
605 {
606 int irq2, irq;
607
608 /* first look at slave pic */
609 irq2 = pic_get_irq(&pics[1]);
610 if (irq2 >= 0) {
611 /* if irq request by slave pic, signal master PIC */
612 pic_set_irq1(&pics[0], 2, 1);
613 pic_set_irq1(&pics[0], 2, 0);
614 }
615 /* look at requested irq */
616 irq = pic_get_irq(&pics[0]);
617 if (irq >= 0) {
618 if (irq == 2) {
619 /* from slave pic */
620 pic_irq_requested = 8 + irq2;
621 } else {
622 /* from master pic */
623 pic_irq_requested = irq;
624 }
625 cpu_x86_interrupt(global_env, CPU_INTERRUPT_HARD);
626 }
627 }
628
629 #ifdef DEBUG_IRQ_LATENCY
630 int64_t irq_time[16];
631 int64_t cpu_get_ticks(void);
632 #endif
633
634 void pic_set_irq(int irq, int level)
635 {
636 #ifdef DEBUG_IRQ_LATENCY
637 if (level) {
638 irq_time[irq] = cpu_get_ticks();
639 }
640 #endif
641 pic_set_irq1(&pics[irq >> 3], irq & 7, level);
642 pic_update_irq();
643 }
644
645 int cpu_x86_get_pic_interrupt(CPUX86State *env)
646 {
647 int irq, irq2, intno;
648
649 /* signal the pic that the irq was acked by the CPU */
650 irq = pic_irq_requested;
651 #ifdef DEBUG_IRQ_LATENCY
652 printf("IRQ%d latency=%Ld\n", irq, cpu_get_ticks() - irq_time[irq]);
653 #endif
654
655 if (irq >= 8) {
656 irq2 = irq & 7;
657 pics[1].isr |= (1 << irq2);
658 pics[1].irr &= ~(1 << irq2);
659 irq = 2;
660 intno = pics[1].irq_base + irq2;
661 } else {
662 intno = pics[0].irq_base + irq;
663 }
664 pics[0].isr |= (1 << irq);
665 pics[0].irr &= ~(1 << irq);
666 return intno;
667 }
668
669 void pic_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
670 {
671 PicState *s;
672 int priority;
673
674 s = &pics[addr >> 7];
675 addr &= 1;
676 if (addr == 0) {
677 if (val & 0x10) {
678 /* init */
679 memset(s, 0, sizeof(PicState));
680 s->init_state = 1;
681 s->init4 = val & 1;
682 if (val & 0x02)
683 hw_error("single mode not supported");
684 if (val & 0x08)
685 hw_error("level sensitive irq not supported");
686 } else if (val & 0x08) {
687 if (val & 0x02)
688 s->read_reg_select = val & 1;
689 if (val & 0x40)
690 s->special_mask = (val >> 5) & 1;
691 } else {
692 switch(val) {
693 case 0x00:
694 case 0x80:
695 s->rotate_on_autoeoi = val >> 7;
696 break;
697 case 0x20: /* end of interrupt */
698 case 0xa0:
699 priority = get_priority(s, s->isr);
700 if (priority >= 0) {
701 s->isr &= ~(1 << ((priority + s->priority_add) & 7));
702 }
703 if (val == 0xa0)
704 s->priority_add = (s->priority_add + 1) & 7;
705 break;
706 case 0x60 ... 0x67:
707 priority = val & 7;
708 s->isr &= ~(1 << priority);
709 break;
710 case 0xc0 ... 0xc7:
711 s->priority_add = (val + 1) & 7;
712 break;
713 case 0xe0 ... 0xe7:
714 priority = val & 7;
715 s->isr &= ~(1 << priority);
716 s->priority_add = (priority + 1) & 7;
717 break;
718 }
719 }
720 } else {
721 switch(s->init_state) {
722 case 0:
723 /* normal mode */
724 s->imr = val;
725 pic_update_irq();
726 break;
727 case 1:
728 s->irq_base = val & 0xf8;
729 s->init_state = 2;
730 break;
731 case 2:
732 if (s->init4) {
733 s->init_state = 3;
734 } else {
735 s->init_state = 0;
736 }
737 break;
738 case 3:
739 s->auto_eoi = (val >> 1) & 1;
740 s->init_state = 0;
741 break;
742 }
743 }
744 }
745
746 uint32_t pic_ioport_read(CPUX86State *env, uint32_t addr)
747 {
748 PicState *s;
749 s = &pics[addr >> 7];
750 addr &= 1;
751 if (addr == 0) {
752 if (s->read_reg_select)
753 return s->isr;
754 else
755 return s->irr;
756 } else {
757 return s->imr;
758 }
759 }
760
761 void pic_init(void)
762 {
763 register_ioport_write(0x20, 2, pic_ioport_write, 1);
764 register_ioport_read(0x20, 2, pic_ioport_read, 1);
765 register_ioport_write(0xa0, 2, pic_ioport_write, 1);
766 register_ioport_read(0xa0, 2, pic_ioport_read, 1);
767 }
768
769 /***********************************************************/
770 /* 8253 PIT emulation */
771
772 #define PIT_FREQ 1193182
773
774 #define RW_STATE_LSB 0
775 #define RW_STATE_MSB 1
776 #define RW_STATE_WORD0 2
777 #define RW_STATE_WORD1 3
778 #define RW_STATE_LATCHED_WORD0 4
779 #define RW_STATE_LATCHED_WORD1 5
780
781 typedef struct PITChannelState {
782 int count; /* can be 65536 */
783 uint16_t latched_count;
784 uint8_t rw_state;
785 uint8_t mode;
786 uint8_t bcd; /* not supported */
787 uint8_t gate; /* timer start */
788 int64_t count_load_time;
789 int64_t count_last_edge_check_time;
790 } PITChannelState;
791
792 PITChannelState pit_channels[3];
793 int speaker_data_on;
794 int pit_min_timer_count = 0;
795
796 int64_t ticks_per_sec;
797
798 int64_t get_clock(void)
799 {
800 struct timeval tv;
801 gettimeofday(&tv, NULL);
802 return tv.tv_sec * 1000000LL + tv.tv_usec;
803 }
804
805 int64_t cpu_get_ticks(void)
806 {
807 int64_t val;
808 asm("rdtsc" : "=A" (val));
809 return val;
810 }
811
812 void cpu_calibrate_ticks(void)
813 {
814 int64_t usec, ticks;
815
816 usec = get_clock();
817 ticks = cpu_get_ticks();
818 usleep(50 * 1000);
819 usec = get_clock() - usec;
820 ticks = cpu_get_ticks() - ticks;
821 ticks_per_sec = (ticks * 1000000LL + (usec >> 1)) / usec;
822 }
823
824 /* compute with 96 bit intermediate result: (a*b)/c */
825 static uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c)
826 {
827 union {
828 uint64_t ll;
829 struct {
830 #ifdef WORDS_BIGENDIAN
831 uint32_t high, low;
832 #else
833 uint32_t low, high;
834 #endif
835 } l;
836 } u, res;
837 uint64_t rl, rh;
838
839 u.ll = a;
840 rl = (uint64_t)u.l.low * (uint64_t)b;
841 rh = (uint64_t)u.l.high * (uint64_t)b;
842 rh += (rl >> 32);
843 res.l.high = rh / c;
844 res.l.low = (((rh % c) << 32) + (rl & 0xffffffff)) / c;
845 return res.ll;
846 }
847
848 static int pit_get_count(PITChannelState *s)
849 {
850 uint64_t d;
851 int counter;
852
853 d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec);
854 switch(s->mode) {
855 case 0:
856 case 1:
857 case 4:
858 case 5:
859 counter = (s->count - d) & 0xffff;
860 break;
861 default:
862 counter = s->count - (d % s->count);
863 break;
864 }
865 return counter;
866 }
867
868 /* get pit output bit */
869 static int pit_get_out(PITChannelState *s)
870 {
871 uint64_t d;
872 int out;
873
874 d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec);
875 switch(s->mode) {
876 default:
877 case 0:
878 out = (d >= s->count);
879 break;
880 case 1:
881 out = (d < s->count);
882 break;
883 case 2:
884 if ((d % s->count) == 0 && d != 0)
885 out = 1;
886 else
887 out = 0;
888 break;
889 case 3:
890 out = (d % s->count) < (s->count >> 1);
891 break;
892 case 4:
893 case 5:
894 out = (d == s->count);
895 break;
896 }
897 return out;
898 }
899
900 /* get the number of 0 to 1 transitions we had since we call this
901 function */
902 /* XXX: maybe better to use ticks precision to avoid getting edges
903 twice if checks are done at very small intervals */
904 static int pit_get_out_edges(PITChannelState *s)
905 {
906 uint64_t d1, d2;
907 int64_t ticks;
908 int ret, v;
909
910 ticks = cpu_get_ticks();
911 d1 = muldiv64(s->count_last_edge_check_time - s->count_load_time,
912 PIT_FREQ, ticks_per_sec);
913 d2 = muldiv64(ticks - s->count_load_time,
914 PIT_FREQ, ticks_per_sec);
915 s->count_last_edge_check_time = ticks;
916 switch(s->mode) {
917 default:
918 case 0:
919 if (d1 < s->count && d2 >= s->count)
920 ret = 1;
921 else
922 ret = 0;
923 break;
924 case 1:
925 ret = 0;
926 break;
927 case 2:
928 d1 /= s->count;
929 d2 /= s->count;
930 ret = d2 - d1;
931 break;
932 case 3:
933 v = s->count - (s->count >> 1);
934 d1 = (d1 + v) / s->count;
935 d2 = (d2 + v) / s->count;
936 ret = d2 - d1;
937 break;
938 case 4:
939 case 5:
940 if (d1 < s->count && d2 >= s->count)
941 ret = 1;
942 else
943 ret = 0;
944 break;
945 }
946 return ret;
947 }
948
949 static inline void pit_load_count(PITChannelState *s, int val)
950 {
951 if (val == 0)
952 val = 0x10000;
953 s->count_load_time = cpu_get_ticks();
954 s->count_last_edge_check_time = s->count_load_time;
955 s->count = val;
956 if (s == &pit_channels[0] && val <= pit_min_timer_count) {
957 fprintf(stderr,
958 "\nWARNING: vl: on your system, accurate timer emulation is impossible if its frequency is more than %d Hz. If using a 2.5.xx Linux kernel, you must patch asm/param.h to change HZ from 1000 to 100.\n\n",
959 PIT_FREQ / pit_min_timer_count);
960 }
961 }
962
963 void pit_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
964 {
965 int channel, access;
966 PITChannelState *s;
967
968 addr &= 3;
969 if (addr == 3) {
970 channel = val >> 6;
971 if (channel == 3)
972 return;
973 s = &pit_channels[channel];
974 access = (val >> 4) & 3;
975 switch(access) {
976 case 0:
977 s->latched_count = pit_get_count(s);
978 s->rw_state = RW_STATE_LATCHED_WORD0;
979 break;
980 default:
981 s->mode = (val >> 1) & 7;
982 s->bcd = val & 1;
983 s->rw_state = access - 1 + RW_STATE_LSB;
984 break;
985 }
986 } else {
987 s = &pit_channels[addr];
988 switch(s->rw_state) {
989 case RW_STATE_LSB:
990 pit_load_count(s, val);
991 break;
992 case RW_STATE_MSB:
993 pit_load_count(s, val << 8);
994 break;
995 case RW_STATE_WORD0:
996 case RW_STATE_WORD1:
997 if (s->rw_state & 1) {
998 pit_load_count(s, (s->latched_count & 0xff) | (val << 8));
999 } else {
1000 s->latched_count = val;
1001 }
1002 s->rw_state ^= 1;
1003 break;
1004 }
1005 }
1006 }
1007
1008 uint32_t pit_ioport_read(CPUX86State *env, uint32_t addr)
1009 {
1010 int ret, count;
1011 PITChannelState *s;
1012
1013 addr &= 3;
1014 s = &pit_channels[addr];
1015 switch(s->rw_state) {
1016 case RW_STATE_LSB:
1017 case RW_STATE_MSB:
1018 case RW_STATE_WORD0:
1019 case RW_STATE_WORD1:
1020 count = pit_get_count(s);
1021 if (s->rw_state & 1)
1022 ret = (count >> 8) & 0xff;
1023 else
1024 ret = count & 0xff;
1025 if (s->rw_state & 2)
1026 s->rw_state ^= 1;
1027 break;
1028 default:
1029 case RW_STATE_LATCHED_WORD0:
1030 case RW_STATE_LATCHED_WORD1:
1031 if (s->rw_state & 1)
1032 ret = s->latched_count >> 8;
1033 else
1034 ret = s->latched_count & 0xff;
1035 s->rw_state ^= 1;
1036 break;
1037 }
1038 return ret;
1039 }
1040
1041 void speaker_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
1042 {
1043 speaker_data_on = (val >> 1) & 1;
1044 pit_channels[2].gate = val & 1;
1045 }
1046
1047 uint32_t speaker_ioport_read(CPUX86State *env, uint32_t addr)
1048 {
1049 int out;
1050 out = pit_get_out(&pit_channels[2]);
1051 return (speaker_data_on << 1) | pit_channels[2].gate | (out << 5);
1052 }
1053
1054 void pit_init(void)
1055 {
1056 PITChannelState *s;
1057 int i;
1058
1059 cpu_calibrate_ticks();
1060
1061 for(i = 0;i < 3; i++) {
1062 s = &pit_channels[i];
1063 s->mode = 3;
1064 s->gate = (i != 2);
1065 pit_load_count(s, 0);
1066 }
1067
1068 register_ioport_write(0x40, 4, pit_ioport_write, 1);
1069 register_ioport_read(0x40, 3, pit_ioport_read, 1);
1070
1071 register_ioport_read(0x61, 1, speaker_ioport_read, 1);
1072 register_ioport_write(0x61, 1, speaker_ioport_write, 1);
1073 }
1074
1075 /***********************************************************/
1076 /* serial port emulation */
1077
1078 #define UART_IRQ 4
1079
1080 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
1081
1082 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
1083 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
1084 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
1085 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
1086
1087 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
1088 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
1089
1090 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
1091 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
1092 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
1093 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
1094
1095 #define UART_LSR_TEMT 0x40 /* Transmitter empty */
1096 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
1097 #define UART_LSR_BI 0x10 /* Break interrupt indicator */
1098 #define UART_LSR_FE 0x08 /* Frame error indicator */
1099 #define UART_LSR_PE 0x04 /* Parity error indicator */
1100 #define UART_LSR_OE 0x02 /* Overrun error indicator */
1101 #define UART_LSR_DR 0x01 /* Receiver data ready */
1102
1103 typedef struct SerialState {
1104 uint8_t divider;
1105 uint8_t rbr; /* receive register */
1106 uint8_t ier;
1107 uint8_t iir; /* read only */
1108 uint8_t lcr;
1109 uint8_t mcr;
1110 uint8_t lsr; /* read only */
1111 uint8_t msr;
1112 uint8_t scr;
1113 } SerialState;
1114
1115 SerialState serial_ports[1];
1116
1117 void serial_update_irq(void)
1118 {
1119 SerialState *s = &serial_ports[0];
1120
1121 if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
1122 s->iir = UART_IIR_RDI;
1123 } else if ((s->lsr & UART_LSR_THRE) && (s->ier & UART_IER_THRI)) {
1124 s->iir = UART_IIR_THRI;
1125 } else {
1126 s->iir = UART_IIR_NO_INT;
1127 }
1128 if (s->iir != UART_IIR_NO_INT) {
1129 pic_set_irq(UART_IRQ, 1);
1130 } else {
1131 pic_set_irq(UART_IRQ, 0);
1132 }
1133 }
1134
1135 void serial_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
1136 {
1137 SerialState *s = &serial_ports[0];
1138 unsigned char ch;
1139 int ret;
1140
1141 addr &= 7;
1142 switch(addr) {
1143 default:
1144 case 0:
1145 if (s->lcr & UART_LCR_DLAB) {
1146 s->divider = (s->divider & 0xff00) | val;
1147 } else {
1148 s->lsr &= ~UART_LSR_THRE;
1149 serial_update_irq();
1150
1151 ch = val;
1152 do {
1153 ret = write(1, &ch, 1);
1154 } while (ret != 1);
1155 s->lsr |= UART_LSR_THRE;
1156 s->lsr |= UART_LSR_TEMT;
1157 serial_update_irq();
1158 }
1159 break;
1160 case 1:
1161 if (s->lcr & UART_LCR_DLAB) {
1162 s->divider = (s->divider & 0x00ff) | (val << 8);
1163 } else {
1164 s->ier = val;
1165 serial_update_irq();
1166 }
1167 break;
1168 case 2:
1169 break;
1170 case 3:
1171 s->lcr = val;
1172 break;
1173 case 4:
1174 s->mcr = val;
1175 break;
1176 case 5:
1177 break;
1178 case 6:
1179 s->msr = val;
1180 break;
1181 case 7:
1182 s->scr = val;
1183 break;
1184 }
1185 }
1186
1187 uint32_t serial_ioport_read(CPUX86State *env, uint32_t addr)
1188 {
1189 SerialState *s = &serial_ports[0];
1190 uint32_t ret;
1191
1192 addr &= 7;
1193 switch(addr) {
1194 default:
1195 case 0:
1196 if (s->lcr & UART_LCR_DLAB) {
1197 ret = s->divider & 0xff;
1198 } else {
1199 ret = s->rbr;
1200 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
1201 serial_update_irq();
1202 }
1203 break;
1204 case 1:
1205 if (s->lcr & UART_LCR_DLAB) {
1206 ret = (s->divider >> 8) & 0xff;
1207 } else {
1208 ret = s->ier;
1209 }
1210 break;
1211 case 2:
1212 ret = s->iir;
1213 break;
1214 case 3:
1215 ret = s->lcr;
1216 break;
1217 case 4:
1218 ret = s->mcr;
1219 break;
1220 case 5:
1221 ret = s->lsr;
1222 break;
1223 case 6:
1224 ret = s->msr;
1225 break;
1226 case 7:
1227 ret = s->scr;
1228 break;
1229 }
1230 return ret;
1231 }
1232
1233 #define TERM_ESCAPE 0x01 /* ctrl-a is used for escape */
1234 static int term_got_escape;
1235
1236 void term_print_help(void)
1237 {
1238 printf("\n"
1239 "C-a h print this help\n"
1240 "C-a x exit emulatior\n"
1241 "C-a b send break (magic sysrq)\n"
1242 "C-a C-a send C-a\n"
1243 );
1244 }
1245
1246 /* called when a char is received */
1247 void serial_received_byte(SerialState *s, int ch)
1248 {
1249 if (term_got_escape) {
1250 term_got_escape = 0;
1251 switch(ch) {
1252 case 'h':
1253 term_print_help();
1254 break;
1255 case 'x':
1256 exit(0);
1257 break;
1258 case 'b':
1259 /* send break */
1260 s->rbr = 0;
1261 s->lsr |= UART_LSR_BI | UART_LSR_DR;
1262 serial_update_irq();
1263 break;
1264 case TERM_ESCAPE:
1265 goto send_char;
1266 }
1267 } else if (ch == TERM_ESCAPE) {
1268 term_got_escape = 1;
1269 } else {
1270 send_char:
1271 s->rbr = ch;
1272 s->lsr |= UART_LSR_DR;
1273 serial_update_irq();
1274 }
1275 }
1276
1277 /* init terminal so that we can grab keys */
1278 static struct termios oldtty;
1279
1280 static void term_exit(void)
1281 {
1282 tcsetattr (0, TCSANOW, &oldtty);
1283 }
1284
1285 static void term_init(void)
1286 {
1287 struct termios tty;
1288
1289 tcgetattr (0, &tty);
1290 oldtty = tty;
1291
1292 tty.c_iflag &= ~(IGNBRK|BRKINT|PARMRK|ISTRIP
1293 |INLCR|IGNCR|ICRNL|IXON);
1294 tty.c_oflag |= OPOST;
1295 tty.c_lflag &= ~(ECHO|ECHONL|ICANON|IEXTEN|ISIG);
1296 tty.c_cflag &= ~(CSIZE|PARENB);
1297 tty.c_cflag |= CS8;
1298 tty.c_cc[VMIN] = 1;
1299 tty.c_cc[VTIME] = 0;
1300
1301 tcsetattr (0, TCSANOW, &tty);
1302
1303 atexit(term_exit);
1304
1305 fcntl(0, F_SETFL, O_NONBLOCK);
1306 }
1307
1308 void serial_init(void)
1309 {
1310 SerialState *s = &serial_ports[0];
1311
1312 s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
1313
1314 register_ioport_write(0x3f8, 8, serial_ioport_write, 1);
1315 register_ioport_read(0x3f8, 8, serial_ioport_read, 1);
1316
1317 term_init();
1318 }
1319
1320 /***********************************************************/
1321 /* ne2000 emulation */
1322
1323 //#define DEBUG_NE2000
1324
1325 #define NE2000_IOPORT 0x300
1326 #define NE2000_IRQ 9
1327
1328 #define MAX_ETH_FRAME_SIZE 1514
1329
1330 #define E8390_CMD 0x00 /* The command register (for all pages) */
1331 /* Page 0 register offsets. */
1332 #define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */
1333 #define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */
1334 #define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */
1335 #define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */
1336 #define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */
1337 #define EN0_TSR 0x04 /* Transmit status reg RD */
1338 #define EN0_TPSR 0x04 /* Transmit starting page WR */
1339 #define EN0_NCR 0x05 /* Number of collision reg RD */
1340 #define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */
1341 #define EN0_FIFO 0x06 /* FIFO RD */
1342 #define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */
1343 #define EN0_ISR 0x07 /* Interrupt status reg RD WR */
1344 #define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */
1345 #define EN0_RSARLO 0x08 /* Remote start address reg 0 */
1346 #define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */
1347 #define EN0_RSARHI 0x09 /* Remote start address reg 1 */
1348 #define EN0_RCNTLO 0x0a /* Remote byte count reg WR */
1349 #define EN0_RCNTHI 0x0b /* Remote byte count reg WR */
1350 #define EN0_RSR 0x0c /* rx status reg RD */
1351 #define EN0_RXCR 0x0c /* RX configuration reg WR */
1352 #define EN0_TXCR 0x0d /* TX configuration reg WR */
1353 #define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */
1354 #define EN0_DCFG 0x0e /* Data configuration reg WR */
1355 #define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */
1356 #define EN0_IMR 0x0f /* Interrupt mask reg WR */
1357 #define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */
1358
1359 #define EN1_PHYS 0x11
1360 #define EN1_CURPAG 0x17
1361 #define EN1_MULT 0x18
1362
1363 /* Register accessed at EN_CMD, the 8390 base addr. */
1364 #define E8390_STOP 0x01 /* Stop and reset the chip */
1365 #define E8390_START 0x02 /* Start the chip, clear reset */
1366 #define E8390_TRANS 0x04 /* Transmit a frame */
1367 #define E8390_RREAD 0x08 /* Remote read */
1368 #define E8390_RWRITE 0x10 /* Remote write */
1369 #define E8390_NODMA 0x20 /* Remote DMA */
1370 #define E8390_PAGE0 0x00 /* Select page chip registers */
1371 #define E8390_PAGE1 0x40 /* using the two high-order bits */
1372 #define E8390_PAGE2 0x80 /* Page 3 is invalid. */
1373
1374 /* Bits in EN0_ISR - Interrupt status register */
1375 #define ENISR_RX 0x01 /* Receiver, no error */
1376 #define ENISR_TX 0x02 /* Transmitter, no error */
1377 #define ENISR_RX_ERR 0x04 /* Receiver, with error */
1378 #define ENISR_TX_ERR 0x08 /* Transmitter, with error */
1379 #define ENISR_OVER 0x10 /* Receiver overwrote the ring */
1380 #define ENISR_COUNTERS 0x20 /* Counters need emptying */
1381 #define ENISR_RDC 0x40 /* remote dma complete */
1382 #define ENISR_RESET 0x80 /* Reset completed */
1383 #define ENISR_ALL 0x3f /* Interrupts we will enable */
1384
1385 /* Bits in received packet status byte and EN0_RSR*/
1386 #define ENRSR_RXOK 0x01 /* Received a good packet */
1387 #define ENRSR_CRC 0x02 /* CRC error */
1388 #define ENRSR_FAE 0x04 /* frame alignment error */
1389 #define ENRSR_FO 0x08 /* FIFO overrun */
1390 #define ENRSR_MPA 0x10 /* missed pkt */
1391 #define ENRSR_PHY 0x20 /* physical/multicast address */
1392 #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
1393 #define ENRSR_DEF 0x80 /* deferring */
1394
1395 /* Transmitted packet status, EN0_TSR. */
1396 #define ENTSR_PTX 0x01 /* Packet transmitted without error */
1397 #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
1398 #define ENTSR_COL 0x04 /* The transmit collided at least once. */
1399 #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */
1400 #define ENTSR_CRS 0x10 /* The carrier sense was lost. */
1401 #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */
1402 #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
1403 #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */
1404
1405 #define NE2000_MEM_SIZE 32768
1406
1407 typedef struct NE2000State {
1408 uint8_t cmd;
1409 uint32_t start;
1410 uint32_t stop;
1411 uint8_t boundary;
1412 uint8_t tsr;
1413 uint8_t tpsr;
1414 uint16_t tcnt;
1415 uint16_t rcnt;
1416 uint32_t rsar;
1417 uint8_t isr;
1418 uint8_t dcfg;
1419 uint8_t imr;
1420 uint8_t phys[6]; /* mac address */
1421 uint8_t curpag;
1422 uint8_t mult[8]; /* multicast mask array */
1423 uint8_t mem[NE2000_MEM_SIZE];
1424 } NE2000State;
1425
1426 NE2000State ne2000_state;
1427 int net_fd = -1;
1428 char network_script[1024];
1429
1430 void ne2000_reset(void)
1431 {
1432 NE2000State *s = &ne2000_state;
1433 int i;
1434
1435 s->isr = ENISR_RESET;
1436 s->mem[0] = 0x52;
1437 s->mem[1] = 0x54;
1438 s->mem[2] = 0x00;
1439 s->mem[3] = 0x12;
1440 s->mem[4] = 0x34;
1441 s->mem[5] = 0x56;
1442 s->mem[14] = 0x57;
1443 s->mem[15] = 0x57;
1444
1445 /* duplicate prom data */
1446 for(i = 15;i >= 0; i--) {
1447 s->mem[2 * i] = s->mem[i];
1448 s->mem[2 * i + 1] = s->mem[i];
1449 }
1450 }
1451
1452 void ne2000_update_irq(NE2000State *s)
1453 {
1454 int isr;
1455 isr = s->isr & s->imr;
1456 if (isr)
1457 pic_set_irq(NE2000_IRQ, 1);
1458 else
1459 pic_set_irq(NE2000_IRQ, 0);
1460 }
1461
1462 int net_init(void)
1463 {
1464 struct ifreq ifr;
1465 int fd, ret, pid, status;
1466
1467 fd = open("/dev/net/tun", O_RDWR);
1468 if (fd < 0) {
1469 fprintf(stderr, "warning: could not open /dev/net/tun: no virtual network emulation\n");
1470 return -1;
1471 }
1472 memset(&ifr, 0, sizeof(ifr));
1473 ifr.ifr_flags = IFF_TAP | IFF_NO_PI;
1474 pstrcpy(ifr.ifr_name, IFNAMSIZ, "tun%d");
1475 ret = ioctl(fd, TUNSETIFF, (void *) &ifr);
1476 if (ret != 0) {
1477 fprintf(stderr, "warning: could not configure /dev/net/tun: no virtual network emulation\n");
1478 close(fd);
1479 return -1;
1480 }
1481 printf("Connected to host network interface: %s\n", ifr.ifr_name);
1482 fcntl(fd, F_SETFL, O_NONBLOCK);
1483 net_fd = fd;
1484
1485 /* try to launch network init script */
1486 pid = fork();
1487 if (pid >= 0) {
1488 if (pid == 0) {
1489 execl(network_script, network_script, ifr.ifr_name, NULL);
1490 exit(1);
1491 }
1492 while (waitpid(pid, &status, 0) != pid);
1493 if (!WIFEXITED(status) ||
1494 WEXITSTATUS(status) != 0) {
1495 fprintf(stderr, "%s: could not launch network script for '%s'\n",
1496 network_script, ifr.ifr_name);
1497 }
1498 }
1499 return 0;
1500 }
1501
1502 void net_send_packet(NE2000State *s, const uint8_t *buf, int size)
1503 {
1504 #ifdef DEBUG_NE2000
1505 printf("NE2000: sending packet size=%d\n", size);
1506 #endif
1507 write(net_fd, buf, size);
1508 }
1509
1510 /* return true if the NE2000 can receive more data */
1511 int ne2000_can_receive(NE2000State *s)
1512 {
1513 int avail, index, boundary;
1514
1515 if (s->cmd & E8390_STOP)
1516 return 0;
1517 index = s->curpag << 8;
1518 boundary = s->boundary << 8;
1519 if (index < boundary)
1520 avail = boundary - index;
1521 else
1522 avail = (s->stop - s->start) - (index - boundary);
1523 if (avail < (MAX_ETH_FRAME_SIZE + 4))
1524 return 0;
1525 return 1;
1526 }
1527
1528 void ne2000_receive(NE2000State *s, uint8_t *buf, int size)
1529 {
1530 uint8_t *p;
1531 int total_len, next, avail, len, index;
1532
1533 #if defined(DEBUG_NE2000)
1534 printf("NE2000: received len=%d\n", size);
1535 #endif
1536
1537 index = s->curpag << 8;
1538 /* 4 bytes for header */
1539 total_len = size + 4;
1540 /* address for next packet (4 bytes for CRC) */
1541 next = index + ((total_len + 4 + 255) & ~0xff);
1542 if (next >= s->stop)
1543 next -= (s->stop - s->start);
1544 /* prepare packet header */
1545 p = s->mem + index;
1546 p[0] = ENRSR_RXOK; /* receive status */
1547 p[1] = next >> 8;
1548 p[2] = total_len;
1549 p[3] = total_len >> 8;
1550 index += 4;
1551
1552 /* write packet data */
1553 while (size > 0) {
1554 avail = s->stop - index;
1555 len = size;
1556 if (len > avail)
1557 len = avail;
1558 memcpy(s->mem + index, buf, len);
1559 buf += len;
1560 index += len;
1561 if (index == s->stop)
1562 index = s->start;
1563 size -= len;
1564 }
1565 s->curpag = next >> 8;
1566
1567 /* now we can signal we have receive something */
1568 s->isr |= ENISR_RX;
1569 ne2000_update_irq(s);
1570 }
1571
1572 void ne2000_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
1573 {
1574 NE2000State *s = &ne2000_state;
1575 int offset, page;
1576
1577 addr &= 0xf;
1578 #ifdef DEBUG_NE2000
1579 printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
1580 #endif
1581 if (addr == E8390_CMD) {
1582 /* control register */
1583 s->cmd = val;
1584 if (val & E8390_START) {
1585 /* test specific case: zero length transfert */
1586 if ((val & (E8390_RREAD | E8390_RWRITE)) &&
1587 s->rcnt == 0) {
1588 s->isr |= ENISR_RDC;
1589 ne2000_update_irq(s);
1590 }
1591 if (val & E8390_TRANS) {
1592 net_send_packet(s, s->mem + (s->tpsr << 8), s->tcnt);
1593 /* signal end of transfert */
1594 s->tsr = ENTSR_PTX;
1595 s->isr |= ENISR_TX;
1596 ne2000_update_irq(s);
1597 }
1598 }
1599 } else {
1600 page = s->cmd >> 6;
1601 offset = addr | (page << 4);
1602 switch(offset) {
1603 case EN0_STARTPG:
1604 s->start = val << 8;
1605 break;
1606 case EN0_STOPPG:
1607 s->stop = val << 8;
1608 break;
1609 case EN0_BOUNDARY:
1610 s->boundary = val;
1611 break;
1612 case EN0_IMR:
1613 s->imr = val;
1614 ne2000_update_irq(s);
1615 break;
1616 case EN0_TPSR:
1617 s->tpsr = val;
1618 break;
1619 case EN0_TCNTLO:
1620 s->tcnt = (s->tcnt & 0xff00) | val;
1621 break;
1622 case EN0_TCNTHI:
1623 s->tcnt = (s->tcnt & 0x00ff) | (val << 8);
1624 break;
1625 case EN0_RSARLO:
1626 s->rsar = (s->rsar & 0xff00) | val;
1627 break;
1628 case EN0_RSARHI:
1629 s->rsar = (s->rsar & 0x00ff) | (val << 8);
1630 break;
1631 case EN0_RCNTLO:
1632 s->rcnt = (s->rcnt & 0xff00) | val;
1633 break;
1634 case EN0_RCNTHI:
1635 s->rcnt = (s->rcnt & 0x00ff) | (val << 8);
1636 break;
1637 case EN0_DCFG:
1638 s->dcfg = val;
1639 break;
1640 case EN0_ISR:
1641 s->isr &= ~val;
1642 ne2000_update_irq(s);
1643 break;
1644 case EN1_PHYS ... EN1_PHYS + 5:
1645 s->phys[offset - EN1_PHYS] = val;
1646 break;
1647 case EN1_CURPAG:
1648 s->curpag = val;
1649 break;
1650 case EN1_MULT ... EN1_MULT + 7:
1651 s->mult[offset - EN1_MULT] = val;
1652 break;
1653 }
1654 }
1655 }
1656
1657 uint32_t ne2000_ioport_read(CPUX86State *env, uint32_t addr)
1658 {
1659 NE2000State *s = &ne2000_state;
1660 int offset, page, ret;
1661
1662 addr &= 0xf;
1663 if (addr == E8390_CMD) {
1664 ret = s->cmd;
1665 } else {
1666 page = s->cmd >> 6;
1667 offset = addr | (page << 4);
1668 switch(offset) {
1669 case EN0_TSR:
1670 ret = s->tsr;
1671 break;
1672 case EN0_BOUNDARY:
1673 ret = s->boundary;
1674 break;
1675 case EN0_ISR:
1676 ret = s->isr;
1677 break;
1678 case EN1_PHYS ... EN1_PHYS + 5:
1679 ret = s->phys[offset - EN1_PHYS];
1680 break;
1681 case EN1_CURPAG:
1682 ret = s->curpag;
1683 break;
1684 case EN1_MULT ... EN1_MULT + 7:
1685 ret = s->mult[offset - EN1_MULT];
1686 break;
1687 default:
1688 ret = 0x00;
1689 break;
1690 }
1691 }
1692 #ifdef DEBUG_NE2000
1693 printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
1694 #endif
1695 return ret;
1696 }
1697
1698 void ne2000_asic_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
1699 {
1700 NE2000State *s = &ne2000_state;
1701 uint8_t *p;
1702
1703 #ifdef DEBUG_NE2000
1704 printf("NE2000: asic write val=0x%04x\n", val);
1705 #endif
1706 p = s->mem + s->rsar;
1707 if (s->dcfg & 0x01) {
1708 /* 16 bit access */
1709 p[0] = val;
1710 p[1] = val >> 8;
1711 s->rsar += 2;
1712 s->rcnt -= 2;
1713 } else {
1714 /* 8 bit access */
1715 p[0] = val;
1716 s->rsar++;
1717 s->rcnt--;
1718 }
1719 /* wrap */
1720 if (s->rsar == s->stop)
1721 s->rsar = s->start;
1722 if (s->rcnt == 0) {
1723 /* signal end of transfert */
1724 s->isr |= ENISR_RDC;
1725 ne2000_update_irq(s);
1726 }
1727 }
1728
1729 uint32_t ne2000_asic_ioport_read(CPUX86State *env, uint32_t addr)
1730 {
1731 NE2000State *s = &ne2000_state;
1732 uint8_t *p;
1733 int ret;
1734
1735 p = s->mem + s->rsar;
1736 if (s->dcfg & 0x01) {
1737 /* 16 bit access */
1738 ret = p[0] | (p[1] << 8);
1739 s->rsar += 2;
1740 s->rcnt -= 2;
1741 } else {
1742 /* 8 bit access */
1743 ret = p[0];
1744 s->rsar++;
1745 s->rcnt--;
1746 }
1747 /* wrap */
1748 if (s->rsar == s->stop)
1749 s->rsar = s->start;
1750 if (s->rcnt == 0) {
1751 /* signal end of transfert */
1752 s->isr |= ENISR_RDC;
1753 ne2000_update_irq(s);
1754 }
1755 #ifdef DEBUG_NE2000
1756 printf("NE2000: asic read val=0x%04x\n", ret);
1757 #endif
1758 return ret;
1759 }
1760
1761 void ne2000_reset_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
1762 {
1763 /* nothing to do (end of reset pulse) */
1764 }
1765
1766 uint32_t ne2000_reset_ioport_read(CPUX86State *env, uint32_t addr)
1767 {
1768 ne2000_reset();
1769 return 0;
1770 }
1771
1772 void ne2000_init(void)
1773 {
1774 register_ioport_write(NE2000_IOPORT, 16, ne2000_ioport_write, 1);
1775 register_ioport_read(NE2000_IOPORT, 16, ne2000_ioport_read, 1);
1776
1777 register_ioport_write(NE2000_IOPORT + 0x10, 1, ne2000_asic_ioport_write, 1);
1778 register_ioport_read(NE2000_IOPORT + 0x10, 1, ne2000_asic_ioport_read, 1);
1779 register_ioport_write(NE2000_IOPORT + 0x10, 2, ne2000_asic_ioport_write, 2);
1780 register_ioport_read(NE2000_IOPORT + 0x10, 2, ne2000_asic_ioport_read, 2);
1781
1782 register_ioport_write(NE2000_IOPORT + 0x1f, 1, ne2000_reset_ioport_write, 1);
1783 register_ioport_read(NE2000_IOPORT + 0x1f, 1, ne2000_reset_ioport_read, 1);
1784 ne2000_reset();
1785 }
1786
1787 /***********************************************************/
1788 /* ide emulation */
1789
1790 //#define DEBUG_IDE
1791
1792 /* Bits of HD_STATUS */
1793 #define ERR_STAT 0x01
1794 #define INDEX_STAT 0x02
1795 #define ECC_STAT 0x04 /* Corrected error */
1796 #define DRQ_STAT 0x08
1797 #define SEEK_STAT 0x10
1798 #define SRV_STAT 0x10
1799 #define WRERR_STAT 0x20
1800 #define READY_STAT 0x40
1801 #define BUSY_STAT 0x80
1802
1803 /* Bits for HD_ERROR */
1804 #define MARK_ERR 0x01 /* Bad address mark */
1805 #define TRK0_ERR 0x02 /* couldn't find track 0 */
1806 #define ABRT_ERR 0x04 /* Command aborted */
1807 #define MCR_ERR 0x08 /* media change request */
1808 #define ID_ERR 0x10 /* ID field not found */
1809 #define MC_ERR 0x20 /* media changed */
1810 #define ECC_ERR 0x40 /* Uncorrectable ECC error */
1811 #define BBD_ERR 0x80 /* pre-EIDE meaning: block marked bad */
1812 #define ICRC_ERR 0x80 /* new meaning: CRC error during transfer */
1813
1814 /* Bits of HD_NSECTOR */
1815 #define CD 0x01
1816 #define IO 0x02
1817 #define REL 0x04
1818 #define TAG_MASK 0xf8
1819
1820 #define IDE_CMD_RESET 0x04
1821 #define IDE_CMD_DISABLE_IRQ 0x02
1822
1823 /* ATA/ATAPI Commands pre T13 Spec */
1824 #define WIN_NOP 0x00
1825 /*
1826 * 0x01->0x02 Reserved
1827 */
1828 #define CFA_REQ_EXT_ERROR_CODE 0x03 /* CFA Request Extended Error Code */
1829 /*
1830 * 0x04->0x07 Reserved
1831 */
1832 #define WIN_SRST 0x08 /* ATAPI soft reset command */
1833 #define WIN_DEVICE_RESET 0x08
1834 /*
1835 * 0x09->0x0F Reserved
1836 */
1837 #define WIN_RECAL 0x10
1838 #define WIN_RESTORE WIN_RECAL
1839 /*
1840 * 0x10->0x1F Reserved
1841 */
1842 #define WIN_READ 0x20 /* 28-Bit */
1843 #define WIN_READ_ONCE 0x21 /* 28-Bit without retries */
1844 #define WIN_READ_LONG 0x22 /* 28-Bit */
1845 #define WIN_READ_LONG_ONCE 0x23 /* 28-Bit without retries */
1846 #define WIN_READ_EXT 0x24 /* 48-Bit */
1847 #define WIN_READDMA_EXT 0x25 /* 48-Bit */
1848 #define WIN_READDMA_QUEUED_EXT 0x26 /* 48-Bit */
1849 #define WIN_READ_NATIVE_MAX_EXT 0x27 /* 48-Bit */
1850 /*
1851 * 0x28
1852 */
1853 #define WIN_MULTREAD_EXT 0x29 /* 48-Bit */
1854 /*
1855 * 0x2A->0x2F Reserved
1856 */
1857 #define WIN_WRITE 0x30 /* 28-Bit */
1858 #define WIN_WRITE_ONCE 0x31 /* 28-Bit without retries */
1859 #define WIN_WRITE_LONG 0x32 /* 28-Bit */
1860 #define WIN_WRITE_LONG_ONCE 0x33 /* 28-Bit without retries */
1861 #define WIN_WRITE_EXT 0x34 /* 48-Bit */
1862 #define WIN_WRITEDMA_EXT 0x35 /* 48-Bit */
1863 #define WIN_WRITEDMA_QUEUED_EXT 0x36 /* 48-Bit */
1864 #define WIN_SET_MAX_EXT 0x37 /* 48-Bit */
1865 #define CFA_WRITE_SECT_WO_ERASE 0x38 /* CFA Write Sectors without erase */
1866 #define WIN_MULTWRITE_EXT 0x39 /* 48-Bit */
1867 /*
1868 * 0x3A->0x3B Reserved
1869 */
1870 #define WIN_WRITE_VERIFY 0x3C /* 28-Bit */
1871 /*
1872 * 0x3D->0x3F Reserved
1873 */
1874 #define WIN_VERIFY 0x40 /* 28-Bit - Read Verify Sectors */
1875 #define WIN_VERIFY_ONCE 0x41 /* 28-Bit - without retries */
1876 #define WIN_VERIFY_EXT 0x42 /* 48-Bit */
1877 /*
1878 * 0x43->0x4F Reserved
1879 */
1880 #define WIN_FORMAT 0x50
1881 /*
1882 * 0x51->0x5F Reserved
1883 */
1884 #define WIN_INIT 0x60
1885 /*
1886 * 0x61->0x5F Reserved
1887 */
1888 #define WIN_SEEK 0x70 /* 0x70-0x7F Reserved */
1889 #define CFA_TRANSLATE_SECTOR 0x87 /* CFA Translate Sector */
1890 #define WIN_DIAGNOSE 0x90
1891 #define WIN_SPECIFY 0x91 /* set drive geometry translation */
1892 #define WIN_DOWNLOAD_MICROCODE 0x92
1893 #define WIN_STANDBYNOW2 0x94
1894 #define WIN_STANDBY2 0x96
1895 #define WIN_SETIDLE2 0x97
1896 #define WIN_CHECKPOWERMODE2 0x98
1897 #define WIN_SLEEPNOW2 0x99
1898 /*
1899 * 0x9A VENDOR
1900 */
1901 #define WIN_PACKETCMD 0xA0 /* Send a packet command. */
1902 #define WIN_PIDENTIFY 0xA1 /* identify ATAPI device */
1903 #define WIN_QUEUED_SERVICE 0xA2
1904 #define WIN_SMART 0xB0 /* self-monitoring and reporting */
1905 #define CFA_ERASE_SECTORS 0xC0
1906 #define WIN_MULTREAD 0xC4 /* read sectors using multiple mode*/
1907 #define WIN_MULTWRITE 0xC5 /* write sectors using multiple mode */
1908 #define WIN_SETMULT 0xC6 /* enable/disable multiple mode */
1909 #define WIN_READDMA_QUEUED 0xC7 /* read sectors using Queued DMA transfers */
1910 #define WIN_READDMA 0xC8 /* read sectors using DMA transfers */
1911 #define WIN_READDMA_ONCE 0xC9 /* 28-Bit - without retries */
1912 #define WIN_WRITEDMA 0xCA /* write sectors using DMA transfers */
1913 #define WIN_WRITEDMA_ONCE 0xCB /* 28-Bit - without retries */
1914 #define WIN_WRITEDMA_QUEUED 0xCC /* write sectors using Queued DMA transfers */
1915 #define CFA_WRITE_MULTI_WO_ERASE 0xCD /* CFA Write multiple without erase */
1916 #define WIN_GETMEDIASTATUS 0xDA
1917 #define WIN_ACKMEDIACHANGE 0xDB /* ATA-1, ATA-2 vendor */
1918 #define WIN_POSTBOOT 0xDC
1919 #define WIN_PREBOOT 0xDD
1920 #define WIN_DOORLOCK 0xDE /* lock door on removable drives */
1921 #define WIN_DOORUNLOCK 0xDF /* unlock door on removable drives */
1922 #define WIN_STANDBYNOW1 0xE0
1923 #define WIN_IDLEIMMEDIATE 0xE1 /* force drive to become "ready" */
1924 #define WIN_STANDBY 0xE2 /* Set device in Standby Mode */
1925 #define WIN_SETIDLE1 0xE3
1926 #define WIN_READ_BUFFER 0xE4 /* force read only 1 sector */
1927 #define WIN_CHECKPOWERMODE1 0xE5
1928 #define WIN_SLEEPNOW1 0xE6
1929 #define WIN_FLUSH_CACHE 0xE7
1930 #define WIN_WRITE_BUFFER 0xE8 /* force write only 1 sector */
1931 #define WIN_WRITE_SAME 0xE9 /* read ata-2 to use */
1932 /* SET_FEATURES 0x22 or 0xDD */
1933 #define WIN_FLUSH_CACHE_EXT 0xEA /* 48-Bit */
1934 #define WIN_IDENTIFY 0xEC /* ask drive to identify itself */
1935 #define WIN_MEDIAEJECT 0xED
1936 #define WIN_IDENTIFY_DMA 0xEE /* same as WIN_IDENTIFY, but DMA */
1937 #define WIN_SETFEATURES 0xEF /* set special drive features */
1938 #define EXABYTE_ENABLE_NEST 0xF0
1939 #define WIN_SECURITY_SET_PASS 0xF1
1940 #define WIN_SECURITY_UNLOCK 0xF2
1941 #define WIN_SECURITY_ERASE_PREPARE 0xF3
1942 #define WIN_SECURITY_ERASE_UNIT 0xF4
1943 #define WIN_SECURITY_FREEZE_LOCK 0xF5
1944 #define WIN_SECURITY_DISABLE 0xF6
1945 #define WIN_READ_NATIVE_MAX 0xF8 /* return the native maximum address */
1946 #define WIN_SET_MAX 0xF9
1947 #define DISABLE_SEAGATE 0xFB
1948
1949 /* set to 1 set disable mult support */
1950 #define MAX_MULT_SECTORS 8
1951
1952 #define MAX_DISKS 2
1953
1954 struct IDEState;
1955
1956 typedef void EndTransferFunc(struct IDEState *);
1957
1958 typedef struct IDEState {
1959 /* ide config */
1960 int cylinders, heads, sectors;
1961 int64_t nb_sectors;
1962 int mult_sectors;
1963 int irq;
1964 /* ide regs */
1965 uint8_t feature;
1966 uint8_t error;
1967 uint16_t nsector; /* 0 is 256 to ease computations */
1968 uint8_t sector;
1969 uint8_t lcyl;
1970 uint8_t hcyl;
1971 uint8_t select;
1972 uint8_t status;
1973 /* 0x3f6 command, only meaningful for drive 0 */
1974 uint8_t cmd;
1975 /* depends on bit 4 in select, only meaningful for drive 0 */
1976 struct IDEState *cur_drive;
1977 BlockDriverState *bs;
1978 int req_nb_sectors; /* number of sectors per interrupt */
1979 EndTransferFunc *end_transfer_func;
1980 uint8_t *data_ptr;
1981 uint8_t *data_end;
1982 uint8_t io_buffer[MAX_MULT_SECTORS*512 + 4];
1983 } IDEState;
1984
1985 BlockDriverState *bs_table[MAX_DISKS];
1986 IDEState ide_state[MAX_DISKS];
1987
1988 static void padstr(char *str, const char *src, int len)
1989 {
1990 int i, v;
1991 for(i = 0; i < len; i++) {
1992 if (*src)
1993 v = *src++;
1994 else
1995 v = ' ';
1996 *(char *)((long)str ^ 1) = v;
1997 str++;
1998 }
1999 }
2000
2001 static void ide_identify(IDEState *s)
2002 {
2003 uint16_t *p;
2004 unsigned int oldsize;
2005
2006 memset(s->io_buffer, 0, 512);
2007 p = (uint16_t *)s->io_buffer;
2008 stw(p + 0, 0x0040);
2009 stw(p + 1, s->cylinders);
2010 stw(p + 3, s->heads);
2011 stw(p + 4, 512 * s->sectors); /* sectors */
2012 stw(p + 5, 512); /* sector size */
2013 stw(p + 6, s->sectors);
2014 stw(p + 20, 3); /* buffer type */
2015 stw(p + 21, 512); /* cache size in sectors */
2016 stw(p + 22, 4); /* ecc bytes */
2017 padstr((uint8_t *)(p + 27), "QEMU HARDDISK", 40);
2018 #if MAX_MULT_SECTORS > 1
2019 stw(p + 47, MAX_MULT_SECTORS);
2020 #endif
2021 stw(p + 48, 1); /* dword I/O */
2022 stw(p + 49, 1 << 9); /* LBA supported, no DMA */
2023 stw(p + 51, 0x200); /* PIO transfer cycle */
2024 stw(p + 52, 0x200); /* DMA transfer cycle */
2025 stw(p + 54, s->cylinders);
2026 stw(p + 55, s->heads);
2027 stw(p + 56, s->sectors);
2028 oldsize = s->cylinders * s->heads * s->sectors;
2029 stw(p + 57, oldsize);
2030 stw(p + 58, oldsize >> 16);
2031 if (s->mult_sectors)
2032 stw(p + 59, 0x100 | s->mult_sectors);
2033 stw(p + 60, s->nb_sectors);
2034 stw(p + 61, s->nb_sectors >> 16);
2035 stw(p + 80, (1 << 1) | (1 << 2));
2036 stw(p + 82, (1 << 14));
2037 stw(p + 83, (1 << 14));
2038 stw(p + 84, (1 << 14));
2039 stw(p + 85, (1 << 14));
2040 stw(p + 86, 0);
2041 stw(p + 87, (1 << 14));
2042 }
2043
2044 static inline void ide_abort_command(IDEState *s)
2045 {
2046 s->status = READY_STAT | ERR_STAT;
2047 s->error = ABRT_ERR;
2048 }
2049
2050 static inline void ide_set_irq(IDEState *s)
2051 {
2052 if (!(ide_state[0].cmd & IDE_CMD_DISABLE_IRQ)) {
2053 pic_set_irq(s->irq, 1);
2054 }
2055 }
2056
2057 /* prepare data transfer and tell what to do after */
2058 static void ide_transfer_start(IDEState *s, int size,
2059 EndTransferFunc *end_transfer_func)
2060 {
2061 s->end_transfer_func = end_transfer_func;
2062 s->data_ptr = s->io_buffer;
2063 s->data_end = s->io_buffer + size;
2064 s->status |= DRQ_STAT;
2065 }
2066
2067 static void ide_transfer_stop(IDEState *s)
2068 {
2069 s->end_transfer_func = ide_transfer_stop;
2070 s->data_ptr = s->io_buffer;
2071 s->data_end = s->io_buffer;
2072 s->status &= ~DRQ_STAT;
2073 }
2074
2075 static int64_t ide_get_sector(IDEState *s)
2076 {
2077 int64_t sector_num;
2078 if (s->select & 0x40) {
2079 /* lba */
2080 sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
2081 (s->lcyl << 8) | s->sector;
2082 } else {
2083 sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
2084 (s->select & 0x0f) * s->sectors +
2085 (s->sector - 1);
2086 }
2087 return sector_num;
2088 }
2089
2090 static void ide_set_sector(IDEState *s, int64_t sector_num)
2091 {
2092 unsigned int cyl, r;
2093 if (s->select & 0x40) {
2094 s->select = (s->select & 0xf0) | (sector_num >> 24);
2095 s->hcyl = (sector_num >> 16);
2096 s->lcyl = (sector_num >> 8);
2097 s->sector = (sector_num);
2098 } else {
2099 cyl = sector_num / (s->heads * s->sectors);
2100 r = sector_num % (s->heads * s->sectors);
2101 s->hcyl = cyl >> 8;
2102 s->lcyl = cyl;
2103 s->select = (s->select & 0xf0) | (r / s->sectors);
2104 s->sector = (r % s->sectors) + 1;
2105 }
2106 }
2107
2108 static void ide_sector_read(IDEState *s)
2109 {
2110 int64_t sector_num;
2111 int ret, n;
2112
2113 s->status = READY_STAT | SEEK_STAT;
2114 sector_num = ide_get_sector(s);
2115 n = s->nsector;
2116 if (n == 0) {
2117 /* no more sector to read from disk */
2118 ide_transfer_stop(s);
2119 } else {
2120 #if defined(DEBUG_IDE)
2121 printf("read sector=%Ld\n", sector_num);
2122 #endif
2123 if (n > s->req_nb_sectors)
2124 n = s->req_nb_sectors;
2125 ret = bdrv_read(s->bs, sector_num, s->io_buffer, n);
2126 ide_transfer_start(s, 512 * n, ide_sector_read);
2127 ide_set_irq(s);
2128 ide_set_sector(s, sector_num + n);
2129 s->nsector -= n;
2130 }
2131 }
2132
2133 static void ide_sector_write(IDEState *s)
2134 {
2135 int64_t sector_num;
2136 int ret, n, n1;
2137
2138 s->status = READY_STAT | SEEK_STAT;
2139 sector_num = ide_get_sector(s);
2140 #if defined(DEBUG_IDE)
2141 printf("write sector=%Ld\n", sector_num);
2142 #endif
2143 n = s->nsector;
2144 if (n > s->req_nb_sectors)
2145 n = s->req_nb_sectors;
2146 ret = bdrv_write(s->bs, sector_num, s->io_buffer, n);
2147 s->nsector -= n;
2148 if (s->nsector == 0) {
2149 /* no more sector to write */
2150 ide_transfer_stop(s);
2151 } else {
2152 n1 = s->nsector;
2153 if (n1 > s->req_nb_sectors)
2154 n1 = s->req_nb_sectors;
2155 ide_transfer_start(s, 512 * n1, ide_sector_write);
2156 }
2157 ide_set_sector(s, sector_num + n);
2158 ide_set_irq(s);
2159 }
2160
2161 void ide_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
2162 {
2163 IDEState *s = ide_state[0].cur_drive;
2164 int unit, n;
2165
2166 addr &= 7;
2167 #ifdef DEBUG_IDE
2168 printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
2169 #endif
2170 switch(addr) {
2171 case 0:
2172 break;
2173 case 1:
2174 s->feature = val;
2175 break;
2176 case 2:
2177 if (val == 0)
2178 val = 256;
2179 s->nsector = val;
2180 break;
2181 case 3:
2182 s->sector = val;
2183 break;
2184 case 4:
2185 s->lcyl = val;
2186 break;
2187 case 5:
2188 s->hcyl = val;
2189 break;
2190 case 6:
2191 /* select drive */
2192 unit = (val >> 4) & 1;
2193 s = &ide_state[unit];
2194 ide_state[0].cur_drive = s;
2195 s->select = val;
2196 break;
2197 default:
2198 case 7:
2199 /* command */
2200 #if defined(DEBUG_IDE)
2201 printf("ide: CMD=%02x\n", val);
2202 #endif
2203 switch(val) {
2204 case WIN_PIDENTIFY:
2205 case WIN_IDENTIFY:
2206 if (s->bs) {
2207 ide_identify(s);
2208 s->status = READY_STAT;
2209 ide_transfer_start(s, 512, ide_transfer_stop);
2210 } else {
2211 ide_abort_command(s);
2212 }
2213 ide_set_irq(s);
2214 break;
2215 case WIN_SPECIFY:
2216 case WIN_RECAL:
2217 s->status = READY_STAT;
2218 ide_set_irq(s);
2219 break;
2220 case WIN_SETMULT:
2221 if (s->nsector > MAX_MULT_SECTORS ||
2222 s->nsector == 0 ||
2223 (s->nsector & (s->nsector - 1)) != 0) {
2224 ide_abort_command(s);
2225 } else {
2226 s->mult_sectors = s->nsector;
2227 s->status = READY_STAT;
2228 }
2229 ide_set_irq(s);
2230 break;
2231 case WIN_READ:
2232 case WIN_READ_ONCE:
2233 s->req_nb_sectors = 1;
2234 ide_sector_read(s);
2235 break;
2236 case WIN_WRITE:
2237 case WIN_WRITE_ONCE:
2238 s->status = SEEK_STAT;
2239 s->req_nb_sectors = 1;
2240 ide_transfer_start(s, 512, ide_sector_write);
2241 break;
2242 case WIN_MULTREAD:
2243 if (!s->mult_sectors)
2244 goto abort_cmd;
2245 s->req_nb_sectors = s->mult_sectors;
2246 ide_sector_read(s);
2247 break;
2248 case WIN_MULTWRITE:
2249 if (!s->mult_sectors)
2250 goto abort_cmd;
2251 s->status = SEEK_STAT;
2252 s->req_nb_sectors = s->mult_sectors;
2253 n = s->nsector;
2254 if (n > s->req_nb_sectors)
2255 n = s->req_nb_sectors;
2256 ide_transfer_start(s, 512 * n, ide_sector_write);
2257 break;
2258 default:
2259 abort_cmd:
2260 ide_abort_command(s);
2261 ide_set_irq(s);
2262 break;
2263 }
2264 }
2265 }
2266
2267 uint32_t ide_ioport_read(CPUX86State *env, uint32_t addr)
2268 {
2269 IDEState *s = ide_state[0].cur_drive;
2270 int ret;
2271
2272 addr &= 7;
2273 switch(addr) {
2274 case 0:
2275 ret = 0xff;
2276 break;
2277 case 1:
2278 ret = s->error;
2279 break;
2280 case 2:
2281 ret = s->nsector & 0xff;
2282 break;
2283 case 3:
2284 ret = s->sector;
2285 break;
2286 case 4:
2287 ret = s->lcyl;
2288 break;
2289 case 5:
2290 ret = s->hcyl;
2291 break;
2292 case 6:
2293 ret = s->select;
2294 break;
2295 default:
2296 case 7:
2297 ret = s->status;
2298 pic_set_irq(s->irq, 0);
2299 break;
2300 }
2301 #ifdef DEBUG_IDE
2302 printf("ide: read addr=0x%x val=%02x\n", addr, ret);
2303 #endif
2304 return ret;
2305 }
2306
2307 uint32_t ide_status_read(CPUX86State *env, uint32_t addr)
2308 {
2309 IDEState *s = ide_state[0].cur_drive;
2310 int ret;
2311 ret = s->status;
2312 #ifdef DEBUG_IDE
2313 printf("ide: read addr=0x%x val=%02x\n", addr, ret);
2314 #endif
2315 return ret;
2316 }
2317
2318 void ide_cmd_write(CPUX86State *env, uint32_t addr, uint32_t val)
2319 {
2320 IDEState *s = &ide_state[0];
2321 /* common for both drives */
2322 s->cmd = val;
2323 }
2324
2325 void ide_data_writew(CPUX86State *env, uint32_t addr, uint32_t val)
2326 {
2327 IDEState *s = ide_state[0].cur_drive;
2328 uint8_t *p;
2329
2330 p = s->data_ptr;
2331 *(uint16_t *)p = tswap16(val);
2332 p += 2;
2333 s->data_ptr = p;
2334 if (p >= s->data_end)
2335 s->end_transfer_func(s);
2336 }
2337
2338 uint32_t ide_data_readw(CPUX86State *env, uint32_t addr)
2339 {
2340 IDEState *s = ide_state[0].cur_drive;
2341 uint8_t *p;
2342 int ret;
2343
2344 p = s->data_ptr;
2345 ret = tswap16(*(uint16_t *)p);
2346 p += 2;
2347 s->data_ptr = p;
2348 if (p >= s->data_end)
2349 s->end_transfer_func(s);
2350 return ret;
2351 }
2352
2353 void ide_data_writel(CPUX86State *env, uint32_t addr, uint32_t val)
2354 {
2355 IDEState *s = ide_state[0].cur_drive;
2356 uint8_t *p;
2357
2358 p = s->data_ptr;
2359 *(uint32_t *)p = tswap32(val);
2360 p += 4;
2361 s->data_ptr = p;
2362 if (p >= s->data_end)
2363 s->end_transfer_func(s);
2364 }
2365
2366 uint32_t ide_data_readl(CPUX86State *env, uint32_t addr)
2367 {
2368 IDEState *s = ide_state[0].cur_drive;
2369 uint8_t *p;
2370 int ret;
2371
2372 p = s->data_ptr;
2373 ret = tswap32(*(uint32_t *)p);
2374 p += 4;
2375 s->data_ptr = p;
2376 if (p >= s->data_end)
2377 s->end_transfer_func(s);
2378 return ret;
2379 }
2380
2381 void ide_reset(IDEState *s)
2382 {
2383 s->mult_sectors = MAX_MULT_SECTORS;
2384 s->status = READY_STAT;
2385 s->cur_drive = s;
2386 s->select = 0xa0;
2387 }
2388
2389 void ide_init(void)
2390 {
2391 IDEState *s;
2392 int i, cylinders;
2393 int64_t nb_sectors;
2394
2395 for(i = 0; i < MAX_DISKS; i++) {
2396 s = &ide_state[i];
2397 s->bs = bs_table[i];
2398 if (s->bs) {
2399 bdrv_get_geometry(s->bs, &nb_sectors);
2400 cylinders = nb_sectors / (16 * 63);
2401 if (cylinders > 16383)
2402 cylinders = 16383;
2403 else if (cylinders < 2)
2404 cylinders = 2;
2405 s->cylinders = cylinders;
2406 s->heads = 16;
2407 s->sectors = 63;
2408 s->nb_sectors = nb_sectors;
2409 }
2410 s->irq = 14;
2411 ide_reset(s);
2412 }
2413 register_ioport_write(0x1f0, 8, ide_ioport_write, 1);
2414 register_ioport_read(0x1f0, 8, ide_ioport_read, 1);
2415 register_ioport_read(0x3f6, 1, ide_status_read, 1);
2416 register_ioport_write(0x3f6, 1, ide_cmd_write, 1);
2417
2418 /* data ports */
2419 register_ioport_write(0x1f0, 2, ide_data_writew, 2);
2420 register_ioport_read(0x1f0, 2, ide_data_readw, 2);
2421 register_ioport_write(0x1f0, 4, ide_data_writel, 4);
2422 register_ioport_read(0x1f0, 4, ide_data_readl, 4);
2423 }
2424
2425 /***********************************************************/
2426 /* cpu signal handler */
2427 static void host_segv_handler(int host_signum, siginfo_t *info,
2428 void *puc)
2429 {
2430 if (cpu_signal_handler(host_signum, info, puc))
2431 return;
2432 term_exit();
2433 abort();
2434 }
2435
2436 static int timer_irq_pending;
2437 static int timer_irq_count;
2438
2439 static void host_alarm_handler(int host_signum, siginfo_t *info,
2440 void *puc)
2441 {
2442 /* NOTE: since usually the OS asks a 100 Hz clock, there can be
2443 some drift between cpu_get_ticks() and the interrupt time. So
2444 we queue some interrupts to avoid missing some */
2445 timer_irq_count += pit_get_out_edges(&pit_channels[0]);
2446 if (timer_irq_count) {
2447 if (timer_irq_count > 2)
2448 timer_irq_count = 2;
2449 timer_irq_count--;
2450 /* just exit from the cpu to have a chance to handle timers */
2451 cpu_x86_interrupt(global_env, CPU_INTERRUPT_EXIT);
2452 timer_irq_pending = 1;
2453 }
2454 }
2455
2456 /* main execution loop */
2457
2458 CPUState *cpu_gdbstub_get_env(void *opaque)
2459 {
2460 return global_env;
2461 }
2462
2463 void main_loop(void *opaque)
2464 {
2465 struct pollfd ufds[2], *pf, *serial_ufd, *net_ufd, *gdb_ufd;
2466 int ret, n, timeout;
2467 uint8_t ch;
2468 CPUState *env = global_env;
2469
2470 for(;;) {
2471
2472 ret = cpu_x86_exec(env);
2473
2474 /* if hlt instruction, we wait until the next IRQ */
2475 if (ret == EXCP_HLT)
2476 timeout = 10;
2477 else
2478 timeout = 0;
2479 /* poll any events */
2480 serial_ufd = NULL;
2481 pf = ufds;
2482 if (!(serial_ports[0].lsr & UART_LSR_DR)) {
2483 serial_ufd = pf;
2484 pf->fd = 0;
2485 pf->events = POLLIN;
2486 pf++;
2487 }
2488 net_ufd = NULL;
2489 if (net_fd > 0 && ne2000_can_receive(&ne2000_state)) {
2490 net_ufd = pf;
2491 pf->fd = net_fd;
2492 pf->events = POLLIN;
2493 pf++;
2494 }
2495 gdb_ufd = NULL;
2496 if (gdbstub_fd > 0) {
2497 gdb_ufd = pf;
2498 pf->fd = gdbstub_fd;
2499 pf->events = POLLIN;
2500 pf++;
2501 }
2502
2503 ret = poll(ufds, pf - ufds, timeout);
2504 if (ret > 0) {
2505 if (serial_ufd && (serial_ufd->revents & POLLIN)) {
2506 n = read(0, &ch, 1);
2507 if (n == 1) {
2508 serial_received_byte(&serial_ports[0], ch);
2509 }
2510 }
2511 if (net_ufd && (net_ufd->revents & POLLIN)) {
2512 uint8_t buf[MAX_ETH_FRAME_SIZE];
2513
2514 n = read(net_fd, buf, MAX_ETH_FRAME_SIZE);
2515 if (n > 0) {
2516 if (n < 60) {
2517 memset(buf + n, 0, 60 - n);
2518 n = 60;
2519 }
2520 ne2000_receive(&ne2000_state, buf, n);
2521 }
2522 }
2523 if (gdb_ufd && (gdb_ufd->revents & POLLIN)) {
2524 uint8_t buf[1];
2525 /* stop emulation if requested by gdb */
2526 n = read(gdbstub_fd, buf, 1);
2527 if (n == 1)
2528 break;
2529 }
2530 }
2531
2532 /* timer IRQ */
2533 if (timer_irq_pending) {
2534 pic_set_irq(0, 1);
2535 pic_set_irq(0, 0);
2536 timer_irq_pending = 0;
2537 }
2538 }
2539 }
2540
2541 void help(void)
2542 {
2543 printf("Virtual Linux version " QEMU_VERSION ", Copyright (c) 2003 Fabrice Bellard\n"
2544 "usage: vl [options] bzImage [kernel parameters...]\n"
2545 "\n"
2546 "'bzImage' is a Linux kernel image (PAGE_OFFSET must be defined\n"
2547 "to 0x90000000 in asm/page.h and arch/i386/vmlinux.lds)\n"
2548 "\n"
2549 "General options:\n"
2550 "-initrd file use 'file' as initial ram disk\n"
2551 "-hda file use 'file' as hard disk 0 image\n"
2552 "-hdb file use 'file' as hard disk 1 image\n"
2553 "-m megs set virtual RAM size to megs MB\n"
2554 "-n script set network init script [default=%s]\n"
2555 "\n"
2556 "Debug options:\n"
2557 "-s wait gdb connection to port %d\n"
2558 "-p port change gdb connection port\n"
2559 "-d output log in /tmp/vl.log\n"
2560 "\n"
2561 "During emulation, use C-a h to get terminal commands:\n",
2562 DEFAULT_NETWORK_SCRIPT, DEFAULT_GDBSTUB_PORT);
2563 term_print_help();
2564 exit(1);
2565 }
2566
2567 struct option long_options[] = {
2568 { "initrd", 1, NULL, 0, },
2569 { "hda", 1, NULL, 0, },
2570 { "hdb", 1, NULL, 0, },
2571 { NULL, 0, NULL, 0 },
2572 };
2573
2574 int main(int argc, char **argv)
2575 {
2576 int c, ret, initrd_size, i, use_gdbstub, gdbstub_port, long_index;
2577 struct linux_params *params;
2578 struct sigaction act;
2579 struct itimerval itv;
2580 CPUX86State *env;
2581 const char *tmpdir, *initrd_filename;
2582 const char *hd_filename[MAX_DISKS];
2583
2584 /* we never want that malloc() uses mmap() */
2585 mallopt(M_MMAP_THRESHOLD, 4096 * 1024);
2586 initrd_filename = NULL;
2587 for(i = 0; i < MAX_DISKS; i++)
2588 hd_filename[i] = NULL;
2589 phys_ram_size = 32 * 1024 * 1024;
2590 pstrcpy(network_script, sizeof(network_script), DEFAULT_NETWORK_SCRIPT);
2591 use_gdbstub = 0;
2592 gdbstub_port = DEFAULT_GDBSTUB_PORT;
2593 for(;;) {
2594 c = getopt_long_only(argc, argv, "hm:dn:sp:", long_options, &long_index);
2595 if (c == -1)
2596 break;
2597 switch(c) {
2598 case 0:
2599 switch(long_index) {
2600 case 0:
2601 initrd_filename = optarg;
2602 break;
2603 case 1:
2604 hd_filename[0] = optarg;
2605 break;
2606 case 2:
2607 hd_filename[1] = optarg;
2608 break;
2609 }
2610 break;
2611 case 'h':
2612 help();
2613 break;
2614 case 'm':
2615 phys_ram_size = atoi(optarg) * 1024 * 1024;
2616 if (phys_ram_size <= 0)
2617 help();
2618 break;
2619 case 'd':
2620 loglevel = 1;
2621 break;
2622 case 'n':
2623 pstrcpy(network_script, sizeof(network_script), optarg);
2624 break;
2625 case 's':
2626 use_gdbstub = 1;
2627 break;
2628 case 'p':
2629 gdbstub_port = atoi(optarg);
2630 break;
2631 }
2632 }
2633 if (optind >= argc)
2634 help();
2635
2636 /* init debug */
2637 if (loglevel) {
2638 logfile = fopen(DEBUG_LOGFILE, "w");
2639 if (!logfile) {
2640 perror(DEBUG_LOGFILE);
2641 _exit(1);
2642 }
2643 setvbuf(logfile, NULL, _IOLBF, 0);
2644 }
2645
2646 /* open the virtual block devices */
2647 for(i = 0; i < MAX_DISKS; i++) {
2648 if (hd_filename[i]) {
2649 bs_table[i] = bdrv_open(hd_filename[i]);
2650 if (!bs_table[i]) {
2651 fprintf(stderr, "vl: could not open hard disk image '%s\n",
2652 hd_filename[i]);
2653 exit(1);
2654 }
2655 }
2656 }
2657
2658 /* init network tun interface */
2659 net_init();
2660
2661 /* init the memory */
2662 tmpdir = getenv("VLTMPDIR");
2663 if (!tmpdir)
2664 tmpdir = "/tmp";
2665 snprintf(phys_ram_file, sizeof(phys_ram_file), "%s/vlXXXXXX", tmpdir);
2666 if (mkstemp(phys_ram_file) < 0) {
2667 fprintf(stderr, "Could not create temporary memory file '%s'\n",
2668 phys_ram_file);
2669 exit(1);
2670 }
2671 phys_ram_fd = open(phys_ram_file, O_CREAT | O_TRUNC | O_RDWR, 0600);
2672 if (phys_ram_fd < 0) {
2673 fprintf(stderr, "Could not open temporary memory file '%s'\n",
2674 phys_ram_file);
2675 exit(1);
2676 }
2677 ftruncate(phys_ram_fd, phys_ram_size);
2678 unlink(phys_ram_file);
2679 phys_ram_base = mmap((void *)PHYS_RAM_BASE, phys_ram_size,
2680 PROT_WRITE | PROT_READ, MAP_SHARED | MAP_FIXED,
2681 phys_ram_fd, 0);
2682 if (phys_ram_base == MAP_FAILED) {
2683 fprintf(stderr, "Could not map physical memory\n");
2684 exit(1);
2685 }
2686
2687 /* now we can load the kernel */
2688 ret = load_kernel(argv[optind], phys_ram_base + KERNEL_LOAD_ADDR);
2689 if (ret < 0) {
2690 fprintf(stderr, "vl: could not load kernel '%s'\n", argv[optind]);
2691 exit(1);
2692 }
2693
2694 /* load initrd */
2695 initrd_size = 0;
2696 if (initrd_filename) {
2697 initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
2698 if (initrd_size < 0) {
2699 fprintf(stderr, "vl: could not load initial ram disk '%s'\n",
2700 initrd_filename);
2701 exit(1);
2702 }
2703 }
2704
2705 /* init kernel params */
2706 params = (void *)(phys_ram_base + KERNEL_PARAMS_ADDR);
2707 memset(params, 0, sizeof(struct linux_params));
2708 params->mount_root_rdonly = 0;
2709 params->cl_magic = 0xA33F;
2710 params->cl_offset = params->commandline - (uint8_t *)params;
2711 params->ext_mem_k = (phys_ram_size / 1024) - 1024;
2712 for(i = optind + 1; i < argc; i++) {
2713 if (i != optind + 1)
2714 pstrcat(params->commandline, sizeof(params->commandline), " ");
2715 pstrcat(params->commandline, sizeof(params->commandline), argv[i]);
2716 }
2717 params->loader_type = 0x01;
2718 if (initrd_size > 0) {
2719 params->initrd_start = INITRD_LOAD_ADDR;
2720 params->initrd_size = initrd_size;
2721 }
2722 params->orig_video_lines = 25;
2723 params->orig_video_cols = 80;
2724
2725 /* init basic PC hardware */
2726 init_ioports();
2727 register_ioport_write(0x80, 1, ioport80_write, 1);
2728
2729 register_ioport_write(0x3d4, 2, vga_ioport_write, 1);
2730
2731 cmos_init();
2732 pic_init();
2733 pit_init();
2734 serial_init();
2735 ne2000_init();
2736 ide_init();
2737
2738 /* setup cpu signal handlers for MMU / self modifying code handling */
2739 sigfillset(&act.sa_mask);
2740 act.sa_flags = SA_SIGINFO;
2741 act.sa_sigaction = host_segv_handler;
2742 sigaction(SIGSEGV, &act, NULL);
2743 sigaction(SIGBUS, &act, NULL);
2744
2745 act.sa_sigaction = host_alarm_handler;
2746 sigaction(SIGALRM, &act, NULL);
2747
2748 /* init CPU state */
2749 env = cpu_init();
2750 global_env = env;
2751 cpu_single_env = env;
2752
2753 /* setup basic memory access */
2754 env->cr[0] = 0x00000033;
2755 cpu_x86_init_mmu(env);
2756
2757 memset(params->idt_table, 0, sizeof(params->idt_table));
2758
2759 params->gdt_table[2] = 0x00cf9a000000ffffLL; /* KERNEL_CS */
2760 params->gdt_table[3] = 0x00cf92000000ffffLL; /* KERNEL_DS */
2761
2762 env->idt.base = (void *)params->idt_table;
2763 env->idt.limit = sizeof(params->idt_table) - 1;
2764 env->gdt.base = (void *)params->gdt_table;
2765 env->gdt.limit = sizeof(params->gdt_table) - 1;
2766
2767 cpu_x86_load_seg(env, R_CS, KERNEL_CS);
2768 cpu_x86_load_seg(env, R_DS, KERNEL_DS);
2769 cpu_x86_load_seg(env, R_ES, KERNEL_DS);
2770 cpu_x86_load_seg(env, R_SS, KERNEL_DS);
2771 cpu_x86_load_seg(env, R_FS, KERNEL_DS);
2772 cpu_x86_load_seg(env, R_GS, KERNEL_DS);
2773
2774 env->eip = KERNEL_LOAD_ADDR;
2775 env->regs[R_ESI] = KERNEL_PARAMS_ADDR;
2776 env->eflags = 0x2;
2777
2778 itv.it_interval.tv_sec = 0;
2779 itv.it_interval.tv_usec = 1000;
2780 itv.it_value.tv_sec = 0;
2781 itv.it_value.tv_usec = 10 * 1000;
2782 setitimer(ITIMER_REAL, &itv, NULL);
2783 /* we probe the tick duration of the kernel to inform the user if
2784 the emulated kernel requested a too high timer frequency */
2785 getitimer(ITIMER_REAL, &itv);
2786 pit_min_timer_count = ((uint64_t)itv.it_interval.tv_usec * PIT_FREQ) /
2787 1000000;
2788
2789 if (use_gdbstub) {
2790 cpu_gdbstub(NULL, main_loop, gdbstub_port);
2791 } else {
2792 main_loop(NULL);
2793 }
2794 return 0;
2795 }
Qemu copy for testing