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added VGA emulation - added PS/2 mouse and keyboard emulation - use SDL for VGA display
[qemu.git] / vl.c
1 /*
2 * QEMU PC System Emulator
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include <stdlib.h>
25 #include <stdio.h>
26 #include <stdarg.h>
27 #include <string.h>
28 #include <getopt.h>
29 #include <inttypes.h>
30 #include <unistd.h>
31 #include <sys/mman.h>
32 #include <fcntl.h>
33 #include <signal.h>
34 #include <time.h>
35 #include <sys/time.h>
36 #include <malloc.h>
37 #include <termios.h>
38 #include <sys/poll.h>
39 #include <errno.h>
40 #include <sys/wait.h>
41
42 #include <sys/ioctl.h>
43 #include <sys/socket.h>
44 #include <linux/if.h>
45 #include <linux/if_tun.h>
46
47 #include "cpu-i386.h"
48 #include "disas.h"
49 #include "thunk.h"
50
51 #include "vl.h"
52
53 #define DEBUG_LOGFILE "/tmp/vl.log"
54 #define DEFAULT_NETWORK_SCRIPT "/etc/vl-ifup"
55 #define BIOS_FILENAME "bios.bin"
56 #define VGABIOS_FILENAME "vgabios.bin"
57
58 //#define DEBUG_UNUSED_IOPORT
59
60 //#define DEBUG_IRQ_LATENCY
61
62 /* output Bochs bios info messages */
63 //#define DEBUG_BIOS
64
65 /* debug IDE devices */
66 //#define DEBUG_IDE
67
68 /* debug PIC */
69 //#define DEBUG_PIC
70
71 /* debug NE2000 card */
72 //#define DEBUG_NE2000
73
74 /* debug PC keyboard */
75 //#define DEBUG_KBD
76
77 /* debug PC keyboard : only mouse */
78 //#define DEBUG_MOUSE
79
80 #define PHYS_RAM_BASE 0xac000000
81 #define PHYS_RAM_MAX_SIZE (256 * 1024 * 1024)
82
83 #define KERNEL_LOAD_ADDR 0x00100000
84 #define INITRD_LOAD_ADDR 0x00400000
85 #define KERNEL_PARAMS_ADDR 0x00090000
86
87 #define GUI_REFRESH_INTERVAL 30
88
89 #define MAX_DISKS 2
90
91 /* from plex86 (BSD license) */
92 struct __attribute__ ((packed)) linux_params {
93 // For 0x00..0x3f, see 'struct screen_info' in linux/include/linux/tty.h.
94 // I just padded out the VESA parts, rather than define them.
95
96 /* 0x000 */ uint8_t orig_x;
97 /* 0x001 */ uint8_t orig_y;
98 /* 0x002 */ uint16_t ext_mem_k;
99 /* 0x004 */ uint16_t orig_video_page;
100 /* 0x006 */ uint8_t orig_video_mode;
101 /* 0x007 */ uint8_t orig_video_cols;
102 /* 0x008 */ uint16_t unused1;
103 /* 0x00a */ uint16_t orig_video_ega_bx;
104 /* 0x00c */ uint16_t unused2;
105 /* 0x00e */ uint8_t orig_video_lines;
106 /* 0x00f */ uint8_t orig_video_isVGA;
107 /* 0x010 */ uint16_t orig_video_points;
108 /* 0x012 */ uint8_t pad0[0x20 - 0x12]; // VESA info.
109 /* 0x020 */ uint16_t cl_magic; // Commandline magic number (0xA33F)
110 /* 0x022 */ uint16_t cl_offset; // Commandline offset. Address of commandline
111 // is calculated as 0x90000 + cl_offset, bu
112 // only if cl_magic == 0xA33F.
113 /* 0x024 */ uint8_t pad1[0x40 - 0x24]; // VESA info.
114
115 /* 0x040 */ uint8_t apm_bios_info[20]; // struct apm_bios_info
116 /* 0x054 */ uint8_t pad2[0x80 - 0x54];
117
118 // Following 2 from 'struct drive_info_struct' in drivers/block/cciss.h.
119 // Might be truncated?
120 /* 0x080 */ uint8_t hd0_info[16]; // hd0-disk-parameter from intvector 0x41
121 /* 0x090 */ uint8_t hd1_info[16]; // hd1-disk-parameter from intvector 0x46
122
123 // System description table truncated to 16 bytes
124 // From 'struct sys_desc_table_struct' in linux/arch/i386/kernel/setup.c.
125 /* 0x0a0 */ uint16_t sys_description_len;
126 /* 0x0a2 */ uint8_t sys_description_table[14];
127 // [0] machine id
128 // [1] machine submodel id
129 // [2] BIOS revision
130 // [3] bit1: MCA bus
131
132 /* 0x0b0 */ uint8_t pad3[0x1e0 - 0xb0];
133 /* 0x1e0 */ uint32_t alt_mem_k;
134 /* 0x1e4 */ uint8_t pad4[4];
135 /* 0x1e8 */ uint8_t e820map_entries;
136 /* 0x1e9 */ uint8_t eddbuf_entries; // EDD_NR
137 /* 0x1ea */ uint8_t pad5[0x1f1 - 0x1ea];
138 /* 0x1f1 */ uint8_t setup_sects; // size of setup.S, number of sectors
139 /* 0x1f2 */ uint16_t mount_root_rdonly; // MOUNT_ROOT_RDONLY (if !=0)
140 /* 0x1f4 */ uint16_t sys_size; // size of compressed kernel-part in the
141 // (b)zImage-file (in 16 byte units, rounded up)
142 /* 0x1f6 */ uint16_t swap_dev; // (unused AFAIK)
143 /* 0x1f8 */ uint16_t ramdisk_flags;
144 /* 0x1fa */ uint16_t vga_mode; // (old one)
145 /* 0x1fc */ uint16_t orig_root_dev; // (high=Major, low=minor)
146 /* 0x1fe */ uint8_t pad6[1];
147 /* 0x1ff */ uint8_t aux_device_info;
148 /* 0x200 */ uint16_t jump_setup; // Jump to start of setup code,
149 // aka "reserved" field.
150 /* 0x202 */ uint8_t setup_signature[4]; // Signature for SETUP-header, ="HdrS"
151 /* 0x206 */ uint16_t header_format_version; // Version number of header format;
152 /* 0x208 */ uint8_t setup_S_temp0[8]; // Used by setup.S for communication with
153 // boot loaders, look there.
154 /* 0x210 */ uint8_t loader_type;
155 // 0 for old one.
156 // else 0xTV:
157 // T=0: LILO
158 // T=1: Loadlin
159 // T=2: bootsect-loader
160 // T=3: SYSLINUX
161 // T=4: ETHERBOOT
162 // V=version
163 /* 0x211 */ uint8_t loadflags;
164 // bit0 = 1: kernel is loaded high (bzImage)
165 // bit7 = 1: Heap and pointer (see below) set by boot
166 // loader.
167 /* 0x212 */ uint16_t setup_S_temp1;
168 /* 0x214 */ uint32_t kernel_start;
169 /* 0x218 */ uint32_t initrd_start;
170 /* 0x21c */ uint32_t initrd_size;
171 /* 0x220 */ uint8_t setup_S_temp2[4];
172 /* 0x224 */ uint16_t setup_S_heap_end_pointer;
173 /* 0x226 */ uint8_t pad7[0x2d0 - 0x226];
174
175 /* 0x2d0 : Int 15, ax=e820 memory map. */
176 // (linux/include/asm-i386/e820.h, 'struct e820entry')
177 #define E820MAX 32
178 #define E820_RAM 1
179 #define E820_RESERVED 2
180 #define E820_ACPI 3 /* usable as RAM once ACPI tables have been read */
181 #define E820_NVS 4
182 struct {
183 uint64_t addr;
184 uint64_t size;
185 uint32_t type;
186 } e820map[E820MAX];
187
188 /* 0x550 */ uint8_t pad8[0x600 - 0x550];
189
190 // BIOS Enhanced Disk Drive Services.
191 // (From linux/include/asm-i386/edd.h, 'struct edd_info')
192 // Each 'struct edd_info is 78 bytes, times a max of 6 structs in array.
193 /* 0x600 */ uint8_t eddbuf[0x7d4 - 0x600];
194
195 /* 0x7d4 */ uint8_t pad9[0x800 - 0x7d4];
196 /* 0x800 */ uint8_t commandline[0x800];
197
198 /* 0x1000 */
199 uint64_t gdt_table[256];
200 uint64_t idt_table[48];
201 };
202
203 #define KERNEL_CS 0x10
204 #define KERNEL_DS 0x18
205
206 #define MAX_IOPORTS 4096
207
208 static const char *interp_prefix = CONFIG_QEMU_PREFIX;
209 char phys_ram_file[1024];
210 CPUX86State *global_env;
211 CPUX86State *cpu_single_env;
212 FILE *logfile = NULL;
213 int loglevel;
214 IOPortReadFunc *ioport_read_table[3][MAX_IOPORTS];
215 IOPortWriteFunc *ioport_write_table[3][MAX_IOPORTS];
216 BlockDriverState *bs_table[MAX_DISKS];
217 int vga_ram_size;
218 static DisplayState display_state;
219 int nodisp;
220 int term_inited;
221 int64_t ticks_per_sec;
222
223 /***********************************************************/
224 /* x86 io ports */
225
226 uint32_t default_ioport_readb(CPUX86State *env, uint32_t address)
227 {
228 #ifdef DEBUG_UNUSED_IOPORT
229 fprintf(stderr, "inb: port=0x%04x\n", address);
230 #endif
231 return 0xff;
232 }
233
234 void default_ioport_writeb(CPUX86State *env, uint32_t address, uint32_t data)
235 {
236 #ifdef DEBUG_UNUSED_IOPORT
237 fprintf(stderr, "outb: port=0x%04x data=0x%02x\n", address, data);
238 #endif
239 }
240
241 /* default is to make two byte accesses */
242 uint32_t default_ioport_readw(CPUX86State *env, uint32_t address)
243 {
244 uint32_t data;
245 data = ioport_read_table[0][address & (MAX_IOPORTS - 1)](env, address);
246 data |= ioport_read_table[0][(address + 1) & (MAX_IOPORTS - 1)](env, address + 1) << 8;
247 return data;
248 }
249
250 void default_ioport_writew(CPUX86State *env, uint32_t address, uint32_t data)
251 {
252 ioport_write_table[0][address & (MAX_IOPORTS - 1)](env, address, data & 0xff);
253 ioport_write_table[0][(address + 1) & (MAX_IOPORTS - 1)](env, address + 1, (data >> 8) & 0xff);
254 }
255
256 uint32_t default_ioport_readl(CPUX86State *env, uint32_t address)
257 {
258 #ifdef DEBUG_UNUSED_IOPORT
259 fprintf(stderr, "inl: port=0x%04x\n", address);
260 #endif
261 return 0xffffffff;
262 }
263
264 void default_ioport_writel(CPUX86State *env, uint32_t address, uint32_t data)
265 {
266 #ifdef DEBUG_UNUSED_IOPORT
267 fprintf(stderr, "outl: port=0x%04x data=0x%02x\n", address, data);
268 #endif
269 }
270
271 void init_ioports(void)
272 {
273 int i;
274
275 for(i = 0; i < MAX_IOPORTS; i++) {
276 ioport_read_table[0][i] = default_ioport_readb;
277 ioport_write_table[0][i] = default_ioport_writeb;
278 ioport_read_table[1][i] = default_ioport_readw;
279 ioport_write_table[1][i] = default_ioport_writew;
280 ioport_read_table[2][i] = default_ioport_readl;
281 ioport_write_table[2][i] = default_ioport_writel;
282 }
283 }
284
285 /* size is the word size in byte */
286 int register_ioport_read(int start, int length, IOPortReadFunc *func, int size)
287 {
288 int i, bsize;
289
290 if (size == 1)
291 bsize = 0;
292 else if (size == 2)
293 bsize = 1;
294 else if (size == 4)
295 bsize = 2;
296 else
297 return -1;
298 for(i = start; i < start + length; i += size)
299 ioport_read_table[bsize][i] = func;
300 return 0;
301 }
302
303 /* size is the word size in byte */
304 int register_ioport_write(int start, int length, IOPortWriteFunc *func, int size)
305 {
306 int i, bsize;
307
308 if (size == 1)
309 bsize = 0;
310 else if (size == 2)
311 bsize = 1;
312 else if (size == 4)
313 bsize = 2;
314 else
315 return -1;
316 for(i = start; i < start + length; i += size)
317 ioport_write_table[bsize][i] = func;
318 return 0;
319 }
320
321 void pstrcpy(char *buf, int buf_size, const char *str)
322 {
323 int c;
324 char *q = buf;
325
326 if (buf_size <= 0)
327 return;
328
329 for(;;) {
330 c = *str++;
331 if (c == 0 || q >= buf + buf_size - 1)
332 break;
333 *q++ = c;
334 }
335 *q = '\0';
336 }
337
338 /* strcat and truncate. */
339 char *pstrcat(char *buf, int buf_size, const char *s)
340 {
341 int len;
342 len = strlen(buf);
343 if (len < buf_size)
344 pstrcpy(buf + len, buf_size - len, s);
345 return buf;
346 }
347
348 int load_kernel(const char *filename, uint8_t *addr)
349 {
350 int fd, size, setup_sects;
351 uint8_t bootsect[512];
352
353 fd = open(filename, O_RDONLY);
354 if (fd < 0)
355 return -1;
356 if (read(fd, bootsect, 512) != 512)
357 goto fail;
358 setup_sects = bootsect[0x1F1];
359 if (!setup_sects)
360 setup_sects = 4;
361 /* skip 16 bit setup code */
362 lseek(fd, (setup_sects + 1) * 512, SEEK_SET);
363 size = read(fd, addr, 16 * 1024 * 1024);
364 if (size < 0)
365 goto fail;
366 close(fd);
367 return size;
368 fail:
369 close(fd);
370 return -1;
371 }
372
373 /* return the size or -1 if error */
374 int load_image(const char *filename, uint8_t *addr)
375 {
376 int fd, size;
377 fd = open(filename, O_RDONLY);
378 if (fd < 0)
379 return -1;
380 size = lseek(fd, 0, SEEK_END);
381 lseek(fd, 0, SEEK_SET);
382 if (read(fd, addr, size) != size) {
383 close(fd);
384 return -1;
385 }
386 close(fd);
387 return size;
388 }
389
390 void cpu_x86_outb(CPUX86State *env, int addr, int val)
391 {
392 ioport_write_table[0][addr & (MAX_IOPORTS - 1)](env, addr, val);
393 }
394
395 void cpu_x86_outw(CPUX86State *env, int addr, int val)
396 {
397 ioport_write_table[1][addr & (MAX_IOPORTS - 1)](env, addr, val);
398 }
399
400 void cpu_x86_outl(CPUX86State *env, int addr, int val)
401 {
402 ioport_write_table[2][addr & (MAX_IOPORTS - 1)](env, addr, val);
403 }
404
405 int cpu_x86_inb(CPUX86State *env, int addr)
406 {
407 return ioport_read_table[0][addr & (MAX_IOPORTS - 1)](env, addr);
408 }
409
410 int cpu_x86_inw(CPUX86State *env, int addr)
411 {
412 return ioport_read_table[1][addr & (MAX_IOPORTS - 1)](env, addr);
413 }
414
415 int cpu_x86_inl(CPUX86State *env, int addr)
416 {
417 return ioport_read_table[2][addr & (MAX_IOPORTS - 1)](env, addr);
418 }
419
420 /***********************************************************/
421 void ioport80_write(CPUX86State *env, uint32_t addr, uint32_t data)
422 {
423 }
424
425 void hw_error(const char *fmt, ...)
426 {
427 va_list ap;
428
429 va_start(ap, fmt);
430 fprintf(stderr, "qemu: hardware error: ");
431 vfprintf(stderr, fmt, ap);
432 fprintf(stderr, "\n");
433 #ifdef TARGET_I386
434 cpu_x86_dump_state(global_env, stderr, X86_DUMP_FPU | X86_DUMP_CCOP);
435 #endif
436 va_end(ap);
437 abort();
438 }
439
440 /***********************************************************/
441 /* cmos emulation */
442
443 #define RTC_SECONDS 0
444 #define RTC_SECONDS_ALARM 1
445 #define RTC_MINUTES 2
446 #define RTC_MINUTES_ALARM 3
447 #define RTC_HOURS 4
448 #define RTC_HOURS_ALARM 5
449 #define RTC_ALARM_DONT_CARE 0xC0
450
451 #define RTC_DAY_OF_WEEK 6
452 #define RTC_DAY_OF_MONTH 7
453 #define RTC_MONTH 8
454 #define RTC_YEAR 9
455
456 #define RTC_REG_A 10
457 #define RTC_REG_B 11
458 #define RTC_REG_C 12
459 #define RTC_REG_D 13
460
461 /* PC cmos mappings */
462 #define REG_EQUIPMENT_BYTE 0x14
463
464 uint8_t cmos_data[128];
465 uint8_t cmos_index;
466
467 void cmos_ioport_write(CPUX86State *env, uint32_t addr, uint32_t data)
468 {
469 if (addr == 0x70) {
470 cmos_index = data & 0x7f;
471 }
472 }
473
474 uint32_t cmos_ioport_read(CPUX86State *env, uint32_t addr)
475 {
476 int ret;
477
478 if (addr == 0x70) {
479 return 0xff;
480 } else {
481 /* toggle update-in-progress bit for Linux (same hack as
482 plex86) */
483 ret = cmos_data[cmos_index];
484 if (cmos_index == RTC_REG_A)
485 cmos_data[RTC_REG_A] ^= 0x80;
486 else if (cmos_index == RTC_REG_C)
487 cmos_data[RTC_REG_C] = 0x00;
488 return ret;
489 }
490 }
491
492
493 static inline int to_bcd(int a)
494 {
495 return ((a / 10) << 4) | (a % 10);
496 }
497
498 void cmos_init(void)
499 {
500 struct tm *tm;
501 time_t ti;
502 int val;
503
504 ti = time(NULL);
505 tm = gmtime(&ti);
506 cmos_data[RTC_SECONDS] = to_bcd(tm->tm_sec);
507 cmos_data[RTC_MINUTES] = to_bcd(tm->tm_min);
508 cmos_data[RTC_HOURS] = to_bcd(tm->tm_hour);
509 cmos_data[RTC_DAY_OF_WEEK] = to_bcd(tm->tm_wday);
510 cmos_data[RTC_DAY_OF_MONTH] = to_bcd(tm->tm_mday);
511 cmos_data[RTC_MONTH] = to_bcd(tm->tm_mon + 1);
512 cmos_data[RTC_YEAR] = to_bcd(tm->tm_year % 100);
513
514 cmos_data[RTC_REG_A] = 0x26;
515 cmos_data[RTC_REG_B] = 0x02;
516 cmos_data[RTC_REG_C] = 0x00;
517 cmos_data[RTC_REG_D] = 0x80;
518
519 /* various important CMOS locations needed by PC/Bochs bios */
520
521 cmos_data[REG_EQUIPMENT_BYTE] = 0x02; /* FPU is there */
522 cmos_data[REG_EQUIPMENT_BYTE] |= 0x04; /* PS/2 mouse installed */
523
524 /* memory size */
525 val = (phys_ram_size / 1024) - 1024;
526 if (val > 65535)
527 val = 65535;
528 cmos_data[0x17] = val;
529 cmos_data[0x18] = val >> 8;
530 cmos_data[0x30] = val;
531 cmos_data[0x31] = val >> 8;
532
533 val = (phys_ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
534 if (val > 65535)
535 val = 65535;
536 cmos_data[0x34] = val;
537 cmos_data[0x35] = val >> 8;
538
539 cmos_data[0x3d] = 0x02; /* hard drive boot */
540
541 register_ioport_write(0x70, 2, cmos_ioport_write, 1);
542 register_ioport_read(0x70, 2, cmos_ioport_read, 1);
543 }
544
545 /***********************************************************/
546 /* 8259 pic emulation */
547
548 typedef struct PicState {
549 uint8_t last_irr; /* edge detection */
550 uint8_t irr; /* interrupt request register */
551 uint8_t imr; /* interrupt mask register */
552 uint8_t isr; /* interrupt service register */
553 uint8_t priority_add; /* used to compute irq priority */
554 uint8_t irq_base;
555 uint8_t read_reg_select;
556 uint8_t special_mask;
557 uint8_t init_state;
558 uint8_t auto_eoi;
559 uint8_t rotate_on_autoeoi;
560 uint8_t init4; /* true if 4 byte init */
561 } PicState;
562
563 /* 0 is master pic, 1 is slave pic */
564 PicState pics[2];
565 int pic_irq_requested;
566
567 /* set irq level. If an edge is detected, then the IRR is set to 1 */
568 static inline void pic_set_irq1(PicState *s, int irq, int level)
569 {
570 int mask;
571 mask = 1 << irq;
572 if (level) {
573 if ((s->last_irr & mask) == 0)
574 s->irr |= mask;
575 s->last_irr |= mask;
576 } else {
577 s->last_irr &= ~mask;
578 }
579 }
580
581 static inline int get_priority(PicState *s, int mask)
582 {
583 int priority;
584 if (mask == 0)
585 return -1;
586 priority = 7;
587 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
588 priority--;
589 return priority;
590 }
591
592 /* return the pic wanted interrupt. return -1 if none */
593 static int pic_get_irq(PicState *s)
594 {
595 int mask, cur_priority, priority;
596
597 mask = s->irr & ~s->imr;
598 priority = get_priority(s, mask);
599 if (priority < 0)
600 return -1;
601 /* compute current priority */
602 cur_priority = get_priority(s, s->isr);
603 if (priority > cur_priority) {
604 /* higher priority found: an irq should be generated */
605 return priority;
606 } else {
607 return -1;
608 }
609 }
610
611 /* raise irq to CPU if necessary. must be called every time the active
612 irq may change */
613 static void pic_update_irq(void)
614 {
615 int irq2, irq;
616
617 /* first look at slave pic */
618 irq2 = pic_get_irq(&pics[1]);
619 if (irq2 >= 0) {
620 /* if irq request by slave pic, signal master PIC */
621 pic_set_irq1(&pics[0], 2, 1);
622 pic_set_irq1(&pics[0], 2, 0);
623 }
624 /* look at requested irq */
625 irq = pic_get_irq(&pics[0]);
626 if (irq >= 0) {
627 if (irq == 2) {
628 /* from slave pic */
629 pic_irq_requested = 8 + irq2;
630 } else {
631 /* from master pic */
632 pic_irq_requested = irq;
633 }
634 cpu_x86_interrupt(global_env, CPU_INTERRUPT_HARD);
635 }
636 }
637
638 #ifdef DEBUG_IRQ_LATENCY
639 int64_t irq_time[16];
640 int64_t cpu_get_ticks(void);
641 #endif
642 #if defined(DEBUG_PIC)
643 int irq_level[16];
644 #endif
645
646 void pic_set_irq(int irq, int level)
647 {
648 #if defined(DEBUG_PIC)
649 if (level != irq_level[irq]) {
650 printf("pic_set_irq: irq=%d level=%d\n", irq, level);
651 irq_level[irq] = level;
652 }
653 #endif
654 #ifdef DEBUG_IRQ_LATENCY
655 if (level) {
656 irq_time[irq] = cpu_get_ticks();
657 }
658 #endif
659 pic_set_irq1(&pics[irq >> 3], irq & 7, level);
660 pic_update_irq();
661 }
662
663 int cpu_x86_get_pic_interrupt(CPUX86State *env)
664 {
665 int irq, irq2, intno;
666
667 /* signal the pic that the irq was acked by the CPU */
668 irq = pic_irq_requested;
669 #ifdef DEBUG_IRQ_LATENCY
670 printf("IRQ%d latency=%0.3fus\n",
671 irq,
672 (double)(cpu_get_ticks() - irq_time[irq]) * 1000000.0 / ticks_per_sec);
673 #endif
674 #ifdef DEBUG_PIC
675 printf("pic_interrupt: irq=%d\n", irq);
676 #endif
677
678 if (irq >= 8) {
679 irq2 = irq & 7;
680 pics[1].isr |= (1 << irq2);
681 pics[1].irr &= ~(1 << irq2);
682 irq = 2;
683 intno = pics[1].irq_base + irq2;
684 } else {
685 intno = pics[0].irq_base + irq;
686 }
687 pics[0].isr |= (1 << irq);
688 pics[0].irr &= ~(1 << irq);
689 return intno;
690 }
691
692 void pic_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
693 {
694 PicState *s;
695 int priority;
696
697 #ifdef DEBUG_PIC
698 printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
699 #endif
700 s = &pics[addr >> 7];
701 addr &= 1;
702 if (addr == 0) {
703 if (val & 0x10) {
704 /* init */
705 memset(s, 0, sizeof(PicState));
706 s->init_state = 1;
707 s->init4 = val & 1;
708 if (val & 0x02)
709 hw_error("single mode not supported");
710 if (val & 0x08)
711 hw_error("level sensitive irq not supported");
712 } else if (val & 0x08) {
713 if (val & 0x02)
714 s->read_reg_select = val & 1;
715 if (val & 0x40)
716 s->special_mask = (val >> 5) & 1;
717 } else {
718 switch(val) {
719 case 0x00:
720 case 0x80:
721 s->rotate_on_autoeoi = val >> 7;
722 break;
723 case 0x20: /* end of interrupt */
724 case 0xa0:
725 priority = get_priority(s, s->isr);
726 if (priority >= 0) {
727 s->isr &= ~(1 << ((priority + s->priority_add) & 7));
728 }
729 if (val == 0xa0)
730 s->priority_add = (s->priority_add + 1) & 7;
731 pic_update_irq();
732 break;
733 case 0x60 ... 0x67:
734 priority = val & 7;
735 s->isr &= ~(1 << priority);
736 pic_update_irq();
737 break;
738 case 0xc0 ... 0xc7:
739 s->priority_add = (val + 1) & 7;
740 pic_update_irq();
741 break;
742 case 0xe0 ... 0xe7:
743 priority = val & 7;
744 s->isr &= ~(1 << priority);
745 s->priority_add = (priority + 1) & 7;
746 pic_update_irq();
747 break;
748 }
749 }
750 } else {
751 switch(s->init_state) {
752 case 0:
753 /* normal mode */
754 s->imr = val;
755 pic_update_irq();
756 break;
757 case 1:
758 s->irq_base = val & 0xf8;
759 s->init_state = 2;
760 break;
761 case 2:
762 if (s->init4) {
763 s->init_state = 3;
764 } else {
765 s->init_state = 0;
766 }
767 break;
768 case 3:
769 s->auto_eoi = (val >> 1) & 1;
770 s->init_state = 0;
771 break;
772 }
773 }
774 }
775
776 uint32_t pic_ioport_read(CPUX86State *env, uint32_t addr1)
777 {
778 PicState *s;
779 unsigned int addr;
780 int ret;
781
782 addr = addr1;
783 s = &pics[addr >> 7];
784 addr &= 1;
785 if (addr == 0) {
786 if (s->read_reg_select)
787 ret = s->isr;
788 else
789 ret = s->irr;
790 } else {
791 ret = s->imr;
792 }
793 #ifdef DEBUG_PIC
794 printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
795 #endif
796 return ret;
797 }
798
799 void pic_init(void)
800 {
801 register_ioport_write(0x20, 2, pic_ioport_write, 1);
802 register_ioport_read(0x20, 2, pic_ioport_read, 1);
803 register_ioport_write(0xa0, 2, pic_ioport_write, 1);
804 register_ioport_read(0xa0, 2, pic_ioport_read, 1);
805 }
806
807 /***********************************************************/
808 /* 8253 PIT emulation */
809
810 #define PIT_FREQ 1193182
811
812 #define RW_STATE_LSB 0
813 #define RW_STATE_MSB 1
814 #define RW_STATE_WORD0 2
815 #define RW_STATE_WORD1 3
816 #define RW_STATE_LATCHED_WORD0 4
817 #define RW_STATE_LATCHED_WORD1 5
818
819 typedef struct PITChannelState {
820 int count; /* can be 65536 */
821 uint16_t latched_count;
822 uint8_t rw_state;
823 uint8_t mode;
824 uint8_t bcd; /* not supported */
825 uint8_t gate; /* timer start */
826 int64_t count_load_time;
827 int64_t count_last_edge_check_time;
828 } PITChannelState;
829
830 PITChannelState pit_channels[3];
831 int speaker_data_on;
832 int dummy_refresh_clock;
833 int pit_min_timer_count = 0;
834
835 int64_t get_clock(void)
836 {
837 struct timeval tv;
838 gettimeofday(&tv, NULL);
839 return tv.tv_sec * 1000000LL + tv.tv_usec;
840 }
841
842 int64_t cpu_get_ticks(void)
843 {
844 int64_t val;
845 asm("rdtsc" : "=A" (val));
846 return val;
847 }
848
849 void cpu_calibrate_ticks(void)
850 {
851 int64_t usec, ticks;
852
853 usec = get_clock();
854 ticks = cpu_get_ticks();
855 usleep(50 * 1000);
856 usec = get_clock() - usec;
857 ticks = cpu_get_ticks() - ticks;
858 ticks_per_sec = (ticks * 1000000LL + (usec >> 1)) / usec;
859 }
860
861 /* compute with 96 bit intermediate result: (a*b)/c */
862 static uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c)
863 {
864 union {
865 uint64_t ll;
866 struct {
867 #ifdef WORDS_BIGENDIAN
868 uint32_t high, low;
869 #else
870 uint32_t low, high;
871 #endif
872 } l;
873 } u, res;
874 uint64_t rl, rh;
875
876 u.ll = a;
877 rl = (uint64_t)u.l.low * (uint64_t)b;
878 rh = (uint64_t)u.l.high * (uint64_t)b;
879 rh += (rl >> 32);
880 res.l.high = rh / c;
881 res.l.low = (((rh % c) << 32) + (rl & 0xffffffff)) / c;
882 return res.ll;
883 }
884
885 static int pit_get_count(PITChannelState *s)
886 {
887 uint64_t d;
888 int counter;
889
890 d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec);
891 switch(s->mode) {
892 case 0:
893 case 1:
894 case 4:
895 case 5:
896 counter = (s->count - d) & 0xffff;
897 break;
898 default:
899 counter = s->count - (d % s->count);
900 break;
901 }
902 return counter;
903 }
904
905 /* get pit output bit */
906 static int pit_get_out(PITChannelState *s)
907 {
908 uint64_t d;
909 int out;
910
911 d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec);
912 switch(s->mode) {
913 default:
914 case 0:
915 out = (d >= s->count);
916 break;
917 case 1:
918 out = (d < s->count);
919 break;
920 case 2:
921 if ((d % s->count) == 0 && d != 0)
922 out = 1;
923 else
924 out = 0;
925 break;
926 case 3:
927 out = (d % s->count) < (s->count >> 1);
928 break;
929 case 4:
930 case 5:
931 out = (d == s->count);
932 break;
933 }
934 return out;
935 }
936
937 /* get the number of 0 to 1 transitions we had since we call this
938 function */
939 /* XXX: maybe better to use ticks precision to avoid getting edges
940 twice if checks are done at very small intervals */
941 static int pit_get_out_edges(PITChannelState *s)
942 {
943 uint64_t d1, d2;
944 int64_t ticks;
945 int ret, v;
946
947 ticks = cpu_get_ticks();
948 d1 = muldiv64(s->count_last_edge_check_time - s->count_load_time,
949 PIT_FREQ, ticks_per_sec);
950 d2 = muldiv64(ticks - s->count_load_time,
951 PIT_FREQ, ticks_per_sec);
952 s->count_last_edge_check_time = ticks;
953 switch(s->mode) {
954 default:
955 case 0:
956 if (d1 < s->count && d2 >= s->count)
957 ret = 1;
958 else
959 ret = 0;
960 break;
961 case 1:
962 ret = 0;
963 break;
964 case 2:
965 d1 /= s->count;
966 d2 /= s->count;
967 ret = d2 - d1;
968 break;
969 case 3:
970 v = s->count - (s->count >> 1);
971 d1 = (d1 + v) / s->count;
972 d2 = (d2 + v) / s->count;
973 ret = d2 - d1;
974 break;
975 case 4:
976 case 5:
977 if (d1 < s->count && d2 >= s->count)
978 ret = 1;
979 else
980 ret = 0;
981 break;
982 }
983 return ret;
984 }
985
986 static inline void pit_load_count(PITChannelState *s, int val)
987 {
988 if (val == 0)
989 val = 0x10000;
990 s->count_load_time = cpu_get_ticks();
991 s->count_last_edge_check_time = s->count_load_time;
992 s->count = val;
993 if (s == &pit_channels[0] && val <= pit_min_timer_count) {
994 fprintf(stderr,
995 "\nWARNING: vl: on your system, accurate timer emulation is impossible if its frequency is more than %d Hz. If using a 2.5.xx Linux kernel, you must patch asm/param.h to change HZ from 1000 to 100.\n\n",
996 PIT_FREQ / pit_min_timer_count);
997 }
998 }
999
1000 void pit_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
1001 {
1002 int channel, access;
1003 PITChannelState *s;
1004
1005 addr &= 3;
1006 if (addr == 3) {
1007 channel = val >> 6;
1008 if (channel == 3)
1009 return;
1010 s = &pit_channels[channel];
1011 access = (val >> 4) & 3;
1012 switch(access) {
1013 case 0:
1014 s->latched_count = pit_get_count(s);
1015 s->rw_state = RW_STATE_LATCHED_WORD0;
1016 break;
1017 default:
1018 s->mode = (val >> 1) & 7;
1019 s->bcd = val & 1;
1020 s->rw_state = access - 1 + RW_STATE_LSB;
1021 break;
1022 }
1023 } else {
1024 s = &pit_channels[addr];
1025 switch(s->rw_state) {
1026 case RW_STATE_LSB:
1027 pit_load_count(s, val);
1028 break;
1029 case RW_STATE_MSB:
1030 pit_load_count(s, val << 8);
1031 break;
1032 case RW_STATE_WORD0:
1033 case RW_STATE_WORD1:
1034 if (s->rw_state & 1) {
1035 pit_load_count(s, (s->latched_count & 0xff) | (val << 8));
1036 } else {
1037 s->latched_count = val;
1038 }
1039 s->rw_state ^= 1;
1040 break;
1041 }
1042 }
1043 }
1044
1045 uint32_t pit_ioport_read(CPUX86State *env, uint32_t addr)
1046 {
1047 int ret, count;
1048 PITChannelState *s;
1049
1050 addr &= 3;
1051 s = &pit_channels[addr];
1052 switch(s->rw_state) {
1053 case RW_STATE_LSB:
1054 case RW_STATE_MSB:
1055 case RW_STATE_WORD0:
1056 case RW_STATE_WORD1:
1057 count = pit_get_count(s);
1058 if (s->rw_state & 1)
1059 ret = (count >> 8) & 0xff;
1060 else
1061 ret = count & 0xff;
1062 if (s->rw_state & 2)
1063 s->rw_state ^= 1;
1064 break;
1065 default:
1066 case RW_STATE_LATCHED_WORD0:
1067 case RW_STATE_LATCHED_WORD1:
1068 if (s->rw_state & 1)
1069 ret = s->latched_count >> 8;
1070 else
1071 ret = s->latched_count & 0xff;
1072 s->rw_state ^= 1;
1073 break;
1074 }
1075 return ret;
1076 }
1077
1078 void speaker_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
1079 {
1080 speaker_data_on = (val >> 1) & 1;
1081 pit_channels[2].gate = val & 1;
1082 }
1083
1084 uint32_t speaker_ioport_read(CPUX86State *env, uint32_t addr)
1085 {
1086 int out;
1087 out = pit_get_out(&pit_channels[2]);
1088 dummy_refresh_clock ^= 1;
1089 return (speaker_data_on << 1) | pit_channels[2].gate | (out << 5) |
1090 (dummy_refresh_clock << 4);
1091 }
1092
1093 void pit_init(void)
1094 {
1095 PITChannelState *s;
1096 int i;
1097
1098 cpu_calibrate_ticks();
1099
1100 for(i = 0;i < 3; i++) {
1101 s = &pit_channels[i];
1102 s->mode = 3;
1103 s->gate = (i != 2);
1104 pit_load_count(s, 0);
1105 }
1106
1107 register_ioport_write(0x40, 4, pit_ioport_write, 1);
1108 register_ioport_read(0x40, 3, pit_ioport_read, 1);
1109
1110 register_ioport_read(0x61, 1, speaker_ioport_read, 1);
1111 register_ioport_write(0x61, 1, speaker_ioport_write, 1);
1112 }
1113
1114 /***********************************************************/
1115 /* serial port emulation */
1116
1117 #define UART_IRQ 4
1118
1119 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
1120
1121 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
1122 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
1123 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
1124 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
1125
1126 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
1127 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
1128
1129 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
1130 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
1131 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
1132 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
1133
1134 #define UART_LSR_TEMT 0x40 /* Transmitter empty */
1135 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
1136 #define UART_LSR_BI 0x10 /* Break interrupt indicator */
1137 #define UART_LSR_FE 0x08 /* Frame error indicator */
1138 #define UART_LSR_PE 0x04 /* Parity error indicator */
1139 #define UART_LSR_OE 0x02 /* Overrun error indicator */
1140 #define UART_LSR_DR 0x01 /* Receiver data ready */
1141
1142 typedef struct SerialState {
1143 uint8_t divider;
1144 uint8_t rbr; /* receive register */
1145 uint8_t ier;
1146 uint8_t iir; /* read only */
1147 uint8_t lcr;
1148 uint8_t mcr;
1149 uint8_t lsr; /* read only */
1150 uint8_t msr;
1151 uint8_t scr;
1152 } SerialState;
1153
1154 SerialState serial_ports[1];
1155
1156 void serial_update_irq(void)
1157 {
1158 SerialState *s = &serial_ports[0];
1159
1160 if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
1161 s->iir = UART_IIR_RDI;
1162 } else if ((s->lsr & UART_LSR_THRE) && (s->ier & UART_IER_THRI)) {
1163 s->iir = UART_IIR_THRI;
1164 } else {
1165 s->iir = UART_IIR_NO_INT;
1166 }
1167 if (s->iir != UART_IIR_NO_INT) {
1168 pic_set_irq(UART_IRQ, 1);
1169 } else {
1170 pic_set_irq(UART_IRQ, 0);
1171 }
1172 }
1173
1174 void serial_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
1175 {
1176 SerialState *s = &serial_ports[0];
1177 unsigned char ch;
1178 int ret;
1179
1180 addr &= 7;
1181 switch(addr) {
1182 default:
1183 case 0:
1184 if (s->lcr & UART_LCR_DLAB) {
1185 s->divider = (s->divider & 0xff00) | val;
1186 } else {
1187 s->lsr &= ~UART_LSR_THRE;
1188 serial_update_irq();
1189
1190 ch = val;
1191 do {
1192 ret = write(1, &ch, 1);
1193 } while (ret != 1);
1194 s->lsr |= UART_LSR_THRE;
1195 s->lsr |= UART_LSR_TEMT;
1196 serial_update_irq();
1197 }
1198 break;
1199 case 1:
1200 if (s->lcr & UART_LCR_DLAB) {
1201 s->divider = (s->divider & 0x00ff) | (val << 8);
1202 } else {
1203 s->ier = val;
1204 serial_update_irq();
1205 }
1206 break;
1207 case 2:
1208 break;
1209 case 3:
1210 s->lcr = val;
1211 break;
1212 case 4:
1213 s->mcr = val;
1214 break;
1215 case 5:
1216 break;
1217 case 6:
1218 s->msr = val;
1219 break;
1220 case 7:
1221 s->scr = val;
1222 break;
1223 }
1224 }
1225
1226 uint32_t serial_ioport_read(CPUX86State *env, uint32_t addr)
1227 {
1228 SerialState *s = &serial_ports[0];
1229 uint32_t ret;
1230
1231 addr &= 7;
1232 switch(addr) {
1233 default:
1234 case 0:
1235 if (s->lcr & UART_LCR_DLAB) {
1236 ret = s->divider & 0xff;
1237 } else {
1238 ret = s->rbr;
1239 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
1240 serial_update_irq();
1241 }
1242 break;
1243 case 1:
1244 if (s->lcr & UART_LCR_DLAB) {
1245 ret = (s->divider >> 8) & 0xff;
1246 } else {
1247 ret = s->ier;
1248 }
1249 break;
1250 case 2:
1251 ret = s->iir;
1252 break;
1253 case 3:
1254 ret = s->lcr;
1255 break;
1256 case 4:
1257 ret = s->mcr;
1258 break;
1259 case 5:
1260 ret = s->lsr;
1261 break;
1262 case 6:
1263 ret = s->msr;
1264 break;
1265 case 7:
1266 ret = s->scr;
1267 break;
1268 }
1269 return ret;
1270 }
1271
1272 #define TERM_ESCAPE 0x01 /* ctrl-a is used for escape */
1273 static int term_got_escape;
1274
1275 void term_print_help(void)
1276 {
1277 printf("\n"
1278 "C-a h print this help\n"
1279 "C-a x exit emulatior\n"
1280 "C-a s save disk data back to file (if -snapshot)\n"
1281 "C-a b send break (magic sysrq)\n"
1282 "C-a C-a send C-a\n"
1283 );
1284 }
1285
1286 /* called when a char is received */
1287 void serial_received_byte(SerialState *s, int ch)
1288 {
1289 if (term_got_escape) {
1290 term_got_escape = 0;
1291 switch(ch) {
1292 case 'h':
1293 term_print_help();
1294 break;
1295 case 'x':
1296 exit(0);
1297 break;
1298 case 's':
1299 {
1300 int i;
1301 for (i = 0; i < MAX_DISKS; i++) {
1302 if (bs_table[i])
1303 bdrv_commit(bs_table[i]);
1304 }
1305 }
1306 break;
1307 case 'b':
1308 /* send break */
1309 s->rbr = 0;
1310 s->lsr |= UART_LSR_BI | UART_LSR_DR;
1311 serial_update_irq();
1312 break;
1313 case TERM_ESCAPE:
1314 goto send_char;
1315 }
1316 } else if (ch == TERM_ESCAPE) {
1317 term_got_escape = 1;
1318 } else {
1319 send_char:
1320 s->rbr = ch;
1321 s->lsr |= UART_LSR_DR;
1322 serial_update_irq();
1323 }
1324 }
1325
1326 void serial_init(void)
1327 {
1328 SerialState *s = &serial_ports[0];
1329
1330 s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
1331
1332 register_ioport_write(0x3f8, 8, serial_ioport_write, 1);
1333 register_ioport_read(0x3f8, 8, serial_ioport_read, 1);
1334 }
1335
1336 /***********************************************************/
1337 /* ne2000 emulation */
1338
1339 #define NE2000_IOPORT 0x300
1340 #define NE2000_IRQ 9
1341
1342 #define MAX_ETH_FRAME_SIZE 1514
1343
1344 #define E8390_CMD 0x00 /* The command register (for all pages) */
1345 /* Page 0 register offsets. */
1346 #define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */
1347 #define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */
1348 #define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */
1349 #define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */
1350 #define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */
1351 #define EN0_TSR 0x04 /* Transmit status reg RD */
1352 #define EN0_TPSR 0x04 /* Transmit starting page WR */
1353 #define EN0_NCR 0x05 /* Number of collision reg RD */
1354 #define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */
1355 #define EN0_FIFO 0x06 /* FIFO RD */
1356 #define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */
1357 #define EN0_ISR 0x07 /* Interrupt status reg RD WR */
1358 #define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */
1359 #define EN0_RSARLO 0x08 /* Remote start address reg 0 */
1360 #define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */
1361 #define EN0_RSARHI 0x09 /* Remote start address reg 1 */
1362 #define EN0_RCNTLO 0x0a /* Remote byte count reg WR */
1363 #define EN0_RCNTHI 0x0b /* Remote byte count reg WR */
1364 #define EN0_RSR 0x0c /* rx status reg RD */
1365 #define EN0_RXCR 0x0c /* RX configuration reg WR */
1366 #define EN0_TXCR 0x0d /* TX configuration reg WR */
1367 #define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */
1368 #define EN0_DCFG 0x0e /* Data configuration reg WR */
1369 #define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */
1370 #define EN0_IMR 0x0f /* Interrupt mask reg WR */
1371 #define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */
1372
1373 #define EN1_PHYS 0x11
1374 #define EN1_CURPAG 0x17
1375 #define EN1_MULT 0x18
1376
1377 /* Register accessed at EN_CMD, the 8390 base addr. */
1378 #define E8390_STOP 0x01 /* Stop and reset the chip */
1379 #define E8390_START 0x02 /* Start the chip, clear reset */
1380 #define E8390_TRANS 0x04 /* Transmit a frame */
1381 #define E8390_RREAD 0x08 /* Remote read */
1382 #define E8390_RWRITE 0x10 /* Remote write */
1383 #define E8390_NODMA 0x20 /* Remote DMA */
1384 #define E8390_PAGE0 0x00 /* Select page chip registers */
1385 #define E8390_PAGE1 0x40 /* using the two high-order bits */
1386 #define E8390_PAGE2 0x80 /* Page 3 is invalid. */
1387
1388 /* Bits in EN0_ISR - Interrupt status register */
1389 #define ENISR_RX 0x01 /* Receiver, no error */
1390 #define ENISR_TX 0x02 /* Transmitter, no error */
1391 #define ENISR_RX_ERR 0x04 /* Receiver, with error */
1392 #define ENISR_TX_ERR 0x08 /* Transmitter, with error */
1393 #define ENISR_OVER 0x10 /* Receiver overwrote the ring */
1394 #define ENISR_COUNTERS 0x20 /* Counters need emptying */
1395 #define ENISR_RDC 0x40 /* remote dma complete */
1396 #define ENISR_RESET 0x80 /* Reset completed */
1397 #define ENISR_ALL 0x3f /* Interrupts we will enable */
1398
1399 /* Bits in received packet status byte and EN0_RSR*/
1400 #define ENRSR_RXOK 0x01 /* Received a good packet */
1401 #define ENRSR_CRC 0x02 /* CRC error */
1402 #define ENRSR_FAE 0x04 /* frame alignment error */
1403 #define ENRSR_FO 0x08 /* FIFO overrun */
1404 #define ENRSR_MPA 0x10 /* missed pkt */
1405 #define ENRSR_PHY 0x20 /* physical/multicast address */
1406 #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
1407 #define ENRSR_DEF 0x80 /* deferring */
1408
1409 /* Transmitted packet status, EN0_TSR. */
1410 #define ENTSR_PTX 0x01 /* Packet transmitted without error */
1411 #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
1412 #define ENTSR_COL 0x04 /* The transmit collided at least once. */
1413 #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */
1414 #define ENTSR_CRS 0x10 /* The carrier sense was lost. */
1415 #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */
1416 #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
1417 #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */
1418
1419 #define NE2000_MEM_SIZE 32768
1420
1421 typedef struct NE2000State {
1422 uint8_t cmd;
1423 uint32_t start;
1424 uint32_t stop;
1425 uint8_t boundary;
1426 uint8_t tsr;
1427 uint8_t tpsr;
1428 uint16_t tcnt;
1429 uint16_t rcnt;
1430 uint32_t rsar;
1431 uint8_t isr;
1432 uint8_t dcfg;
1433 uint8_t imr;
1434 uint8_t phys[6]; /* mac address */
1435 uint8_t curpag;
1436 uint8_t mult[8]; /* multicast mask array */
1437 uint8_t mem[NE2000_MEM_SIZE];
1438 } NE2000State;
1439
1440 NE2000State ne2000_state;
1441 int net_fd = -1;
1442 char network_script[1024];
1443
1444 void ne2000_reset(void)
1445 {
1446 NE2000State *s = &ne2000_state;
1447 int i;
1448
1449 s->isr = ENISR_RESET;
1450 s->mem[0] = 0x52;
1451 s->mem[1] = 0x54;
1452 s->mem[2] = 0x00;
1453 s->mem[3] = 0x12;
1454 s->mem[4] = 0x34;
1455 s->mem[5] = 0x56;
1456 s->mem[14] = 0x57;
1457 s->mem[15] = 0x57;
1458
1459 /* duplicate prom data */
1460 for(i = 15;i >= 0; i--) {
1461 s->mem[2 * i] = s->mem[i];
1462 s->mem[2 * i + 1] = s->mem[i];
1463 }
1464 }
1465
1466 void ne2000_update_irq(NE2000State *s)
1467 {
1468 int isr;
1469 isr = s->isr & s->imr;
1470 if (isr)
1471 pic_set_irq(NE2000_IRQ, 1);
1472 else
1473 pic_set_irq(NE2000_IRQ, 0);
1474 }
1475
1476 int net_init(void)
1477 {
1478 struct ifreq ifr;
1479 int fd, ret, pid, status;
1480
1481 fd = open("/dev/net/tun", O_RDWR);
1482 if (fd < 0) {
1483 fprintf(stderr, "warning: could not open /dev/net/tun: no virtual network emulation\n");
1484 return -1;
1485 }
1486 memset(&ifr, 0, sizeof(ifr));
1487 ifr.ifr_flags = IFF_TAP | IFF_NO_PI;
1488 pstrcpy(ifr.ifr_name, IFNAMSIZ, "tun%d");
1489 ret = ioctl(fd, TUNSETIFF, (void *) &ifr);
1490 if (ret != 0) {
1491 fprintf(stderr, "warning: could not configure /dev/net/tun: no virtual network emulation\n");
1492 close(fd);
1493 return -1;
1494 }
1495 printf("Connected to host network interface: %s\n", ifr.ifr_name);
1496 fcntl(fd, F_SETFL, O_NONBLOCK);
1497 net_fd = fd;
1498
1499 /* try to launch network init script */
1500 pid = fork();
1501 if (pid >= 0) {
1502 if (pid == 0) {
1503 execl(network_script, network_script, ifr.ifr_name, NULL);
1504 exit(1);
1505 }
1506 while (waitpid(pid, &status, 0) != pid);
1507 if (!WIFEXITED(status) ||
1508 WEXITSTATUS(status) != 0) {
1509 fprintf(stderr, "%s: could not launch network script for '%s'\n",
1510 network_script, ifr.ifr_name);
1511 }
1512 }
1513 return 0;
1514 }
1515
1516 void net_send_packet(NE2000State *s, const uint8_t *buf, int size)
1517 {
1518 #ifdef DEBUG_NE2000
1519 printf("NE2000: sending packet size=%d\n", size);
1520 #endif
1521 write(net_fd, buf, size);
1522 }
1523
1524 /* return true if the NE2000 can receive more data */
1525 int ne2000_can_receive(NE2000State *s)
1526 {
1527 int avail, index, boundary;
1528
1529 if (s->cmd & E8390_STOP)
1530 return 0;
1531 index = s->curpag << 8;
1532 boundary = s->boundary << 8;
1533 if (index < boundary)
1534 avail = boundary - index;
1535 else
1536 avail = (s->stop - s->start) - (index - boundary);
1537 if (avail < (MAX_ETH_FRAME_SIZE + 4))
1538 return 0;
1539 return 1;
1540 }
1541
1542 void ne2000_receive(NE2000State *s, uint8_t *buf, int size)
1543 {
1544 uint8_t *p;
1545 int total_len, next, avail, len, index;
1546
1547 #if defined(DEBUG_NE2000)
1548 printf("NE2000: received len=%d\n", size);
1549 #endif
1550
1551 index = s->curpag << 8;
1552 /* 4 bytes for header */
1553 total_len = size + 4;
1554 /* address for next packet (4 bytes for CRC) */
1555 next = index + ((total_len + 4 + 255) & ~0xff);
1556 if (next >= s->stop)
1557 next -= (s->stop - s->start);
1558 /* prepare packet header */
1559 p = s->mem + index;
1560 p[0] = ENRSR_RXOK; /* receive status */
1561 p[1] = next >> 8;
1562 p[2] = total_len;
1563 p[3] = total_len >> 8;
1564 index += 4;
1565
1566 /* write packet data */
1567 while (size > 0) {
1568 avail = s->stop - index;
1569 len = size;
1570 if (len > avail)
1571 len = avail;
1572 memcpy(s->mem + index, buf, len);
1573 buf += len;
1574 index += len;
1575 if (index == s->stop)
1576 index = s->start;
1577 size -= len;
1578 }
1579 s->curpag = next >> 8;
1580
1581 /* now we can signal we have receive something */
1582 s->isr |= ENISR_RX;
1583 ne2000_update_irq(s);
1584 }
1585
1586 void ne2000_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
1587 {
1588 NE2000State *s = &ne2000_state;
1589 int offset, page;
1590
1591 addr &= 0xf;
1592 #ifdef DEBUG_NE2000
1593 printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
1594 #endif
1595 if (addr == E8390_CMD) {
1596 /* control register */
1597 s->cmd = val;
1598 if (val & E8390_START) {
1599 /* test specific case: zero length transfert */
1600 if ((val & (E8390_RREAD | E8390_RWRITE)) &&
1601 s->rcnt == 0) {
1602 s->isr |= ENISR_RDC;
1603 ne2000_update_irq(s);
1604 }
1605 if (val & E8390_TRANS) {
1606 net_send_packet(s, s->mem + (s->tpsr << 8), s->tcnt);
1607 /* signal end of transfert */
1608 s->tsr = ENTSR_PTX;
1609 s->isr |= ENISR_TX;
1610 ne2000_update_irq(s);
1611 }
1612 }
1613 } else {
1614 page = s->cmd >> 6;
1615 offset = addr | (page << 4);
1616 switch(offset) {
1617 case EN0_STARTPG:
1618 s->start = val << 8;
1619 break;
1620 case EN0_STOPPG:
1621 s->stop = val << 8;
1622 break;
1623 case EN0_BOUNDARY:
1624 s->boundary = val;
1625 break;
1626 case EN0_IMR:
1627 s->imr = val;
1628 ne2000_update_irq(s);
1629 break;
1630 case EN0_TPSR:
1631 s->tpsr = val;
1632 break;
1633 case EN0_TCNTLO:
1634 s->tcnt = (s->tcnt & 0xff00) | val;
1635 break;
1636 case EN0_TCNTHI:
1637 s->tcnt = (s->tcnt & 0x00ff) | (val << 8);
1638 break;
1639 case EN0_RSARLO:
1640 s->rsar = (s->rsar & 0xff00) | val;
1641 break;
1642 case EN0_RSARHI:
1643 s->rsar = (s->rsar & 0x00ff) | (val << 8);
1644 break;
1645 case EN0_RCNTLO:
1646 s->rcnt = (s->rcnt & 0xff00) | val;
1647 break;
1648 case EN0_RCNTHI:
1649 s->rcnt = (s->rcnt & 0x00ff) | (val << 8);
1650 break;
1651 case EN0_DCFG:
1652 s->dcfg = val;
1653 break;
1654 case EN0_ISR:
1655 s->isr &= ~val;
1656 ne2000_update_irq(s);
1657 break;
1658 case EN1_PHYS ... EN1_PHYS + 5:
1659 s->phys[offset - EN1_PHYS] = val;
1660 break;
1661 case EN1_CURPAG:
1662 s->curpag = val;
1663 break;
1664 case EN1_MULT ... EN1_MULT + 7:
1665 s->mult[offset - EN1_MULT] = val;
1666 break;
1667 }
1668 }
1669 }
1670
1671 uint32_t ne2000_ioport_read(CPUX86State *env, uint32_t addr)
1672 {
1673 NE2000State *s = &ne2000_state;
1674 int offset, page, ret;
1675
1676 addr &= 0xf;
1677 if (addr == E8390_CMD) {
1678 ret = s->cmd;
1679 } else {
1680 page = s->cmd >> 6;
1681 offset = addr | (page << 4);
1682 switch(offset) {
1683 case EN0_TSR:
1684 ret = s->tsr;
1685 break;
1686 case EN0_BOUNDARY:
1687 ret = s->boundary;
1688 break;
1689 case EN0_ISR:
1690 ret = s->isr;
1691 break;
1692 case EN1_PHYS ... EN1_PHYS + 5:
1693 ret = s->phys[offset - EN1_PHYS];
1694 break;
1695 case EN1_CURPAG:
1696 ret = s->curpag;
1697 break;
1698 case EN1_MULT ... EN1_MULT + 7:
1699 ret = s->mult[offset - EN1_MULT];
1700 break;
1701 default:
1702 ret = 0x00;
1703 break;
1704 }
1705 }
1706 #ifdef DEBUG_NE2000
1707 printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
1708 #endif
1709 return ret;
1710 }
1711
1712 void ne2000_asic_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
1713 {
1714 NE2000State *s = &ne2000_state;
1715 uint8_t *p;
1716
1717 #ifdef DEBUG_NE2000
1718 printf("NE2000: asic write val=0x%04x\n", val);
1719 #endif
1720 p = s->mem + s->rsar;
1721 if (s->dcfg & 0x01) {
1722 /* 16 bit access */
1723 p[0] = val;
1724 p[1] = val >> 8;
1725 s->rsar += 2;
1726 s->rcnt -= 2;
1727 } else {
1728 /* 8 bit access */
1729 p[0] = val;
1730 s->rsar++;
1731 s->rcnt--;
1732 }
1733 /* wrap */
1734 if (s->rsar == s->stop)
1735 s->rsar = s->start;
1736 if (s->rcnt == 0) {
1737 /* signal end of transfert */
1738 s->isr |= ENISR_RDC;
1739 ne2000_update_irq(s);
1740 }
1741 }
1742
1743 uint32_t ne2000_asic_ioport_read(CPUX86State *env, uint32_t addr)
1744 {
1745 NE2000State *s = &ne2000_state;
1746 uint8_t *p;
1747 int ret;
1748
1749 p = s->mem + s->rsar;
1750 if (s->dcfg & 0x01) {
1751 /* 16 bit access */
1752 ret = p[0] | (p[1] << 8);
1753 s->rsar += 2;
1754 s->rcnt -= 2;
1755 } else {
1756 /* 8 bit access */
1757 ret = p[0];
1758 s->rsar++;
1759 s->rcnt--;
1760 }
1761 /* wrap */
1762 if (s->rsar == s->stop)
1763 s->rsar = s->start;
1764 if (s->rcnt == 0) {
1765 /* signal end of transfert */
1766 s->isr |= ENISR_RDC;
1767 ne2000_update_irq(s);
1768 }
1769 #ifdef DEBUG_NE2000
1770 printf("NE2000: asic read val=0x%04x\n", ret);
1771 #endif
1772 return ret;
1773 }
1774
1775 void ne2000_reset_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
1776 {
1777 /* nothing to do (end of reset pulse) */
1778 }
1779
1780 uint32_t ne2000_reset_ioport_read(CPUX86State *env, uint32_t addr)
1781 {
1782 ne2000_reset();
1783 return 0;
1784 }
1785
1786 void ne2000_init(void)
1787 {
1788 register_ioport_write(NE2000_IOPORT, 16, ne2000_ioport_write, 1);
1789 register_ioport_read(NE2000_IOPORT, 16, ne2000_ioport_read, 1);
1790
1791 register_ioport_write(NE2000_IOPORT + 0x10, 1, ne2000_asic_ioport_write, 1);
1792 register_ioport_read(NE2000_IOPORT + 0x10, 1, ne2000_asic_ioport_read, 1);
1793 register_ioport_write(NE2000_IOPORT + 0x10, 2, ne2000_asic_ioport_write, 2);
1794 register_ioport_read(NE2000_IOPORT + 0x10, 2, ne2000_asic_ioport_read, 2);
1795
1796 register_ioport_write(NE2000_IOPORT + 0x1f, 1, ne2000_reset_ioport_write, 1);
1797 register_ioport_read(NE2000_IOPORT + 0x1f, 1, ne2000_reset_ioport_read, 1);
1798 ne2000_reset();
1799 }
1800
1801 /***********************************************************/
1802 /* ide emulation */
1803
1804 /* Bits of HD_STATUS */
1805 #define ERR_STAT 0x01
1806 #define INDEX_STAT 0x02
1807 #define ECC_STAT 0x04 /* Corrected error */
1808 #define DRQ_STAT 0x08
1809 #define SEEK_STAT 0x10
1810 #define SRV_STAT 0x10
1811 #define WRERR_STAT 0x20
1812 #define READY_STAT 0x40
1813 #define BUSY_STAT 0x80
1814
1815 /* Bits for HD_ERROR */
1816 #define MARK_ERR 0x01 /* Bad address mark */
1817 #define TRK0_ERR 0x02 /* couldn't find track 0 */
1818 #define ABRT_ERR 0x04 /* Command aborted */
1819 #define MCR_ERR 0x08 /* media change request */
1820 #define ID_ERR 0x10 /* ID field not found */
1821 #define MC_ERR 0x20 /* media changed */
1822 #define ECC_ERR 0x40 /* Uncorrectable ECC error */
1823 #define BBD_ERR 0x80 /* pre-EIDE meaning: block marked bad */
1824 #define ICRC_ERR 0x80 /* new meaning: CRC error during transfer */
1825
1826 /* Bits of HD_NSECTOR */
1827 #define CD 0x01
1828 #define IO 0x02
1829 #define REL 0x04
1830 #define TAG_MASK 0xf8
1831
1832 #define IDE_CMD_RESET 0x04
1833 #define IDE_CMD_DISABLE_IRQ 0x02
1834
1835 /* ATA/ATAPI Commands pre T13 Spec */
1836 #define WIN_NOP 0x00
1837 /*
1838 * 0x01->0x02 Reserved
1839 */
1840 #define CFA_REQ_EXT_ERROR_CODE 0x03 /* CFA Request Extended Error Code */
1841 /*
1842 * 0x04->0x07 Reserved
1843 */
1844 #define WIN_SRST 0x08 /* ATAPI soft reset command */
1845 #define WIN_DEVICE_RESET 0x08
1846 /*
1847 * 0x09->0x0F Reserved
1848 */
1849 #define WIN_RECAL 0x10
1850 #define WIN_RESTORE WIN_RECAL
1851 /*
1852 * 0x10->0x1F Reserved
1853 */
1854 #define WIN_READ 0x20 /* 28-Bit */
1855 #define WIN_READ_ONCE 0x21 /* 28-Bit without retries */
1856 #define WIN_READ_LONG 0x22 /* 28-Bit */
1857 #define WIN_READ_LONG_ONCE 0x23 /* 28-Bit without retries */
1858 #define WIN_READ_EXT 0x24 /* 48-Bit */
1859 #define WIN_READDMA_EXT 0x25 /* 48-Bit */
1860 #define WIN_READDMA_QUEUED_EXT 0x26 /* 48-Bit */
1861 #define WIN_READ_NATIVE_MAX_EXT 0x27 /* 48-Bit */
1862 /*
1863 * 0x28
1864 */
1865 #define WIN_MULTREAD_EXT 0x29 /* 48-Bit */
1866 /*
1867 * 0x2A->0x2F Reserved
1868 */
1869 #define WIN_WRITE 0x30 /* 28-Bit */
1870 #define WIN_WRITE_ONCE 0x31 /* 28-Bit without retries */
1871 #define WIN_WRITE_LONG 0x32 /* 28-Bit */
1872 #define WIN_WRITE_LONG_ONCE 0x33 /* 28-Bit without retries */
1873 #define WIN_WRITE_EXT 0x34 /* 48-Bit */
1874 #define WIN_WRITEDMA_EXT 0x35 /* 48-Bit */
1875 #define WIN_WRITEDMA_QUEUED_EXT 0x36 /* 48-Bit */
1876 #define WIN_SET_MAX_EXT 0x37 /* 48-Bit */
1877 #define CFA_WRITE_SECT_WO_ERASE 0x38 /* CFA Write Sectors without erase */
1878 #define WIN_MULTWRITE_EXT 0x39 /* 48-Bit */
1879 /*
1880 * 0x3A->0x3B Reserved
1881 */
1882 #define WIN_WRITE_VERIFY 0x3C /* 28-Bit */
1883 /*
1884 * 0x3D->0x3F Reserved
1885 */
1886 #define WIN_VERIFY 0x40 /* 28-Bit - Read Verify Sectors */
1887 #define WIN_VERIFY_ONCE 0x41 /* 28-Bit - without retries */
1888 #define WIN_VERIFY_EXT 0x42 /* 48-Bit */
1889 /*
1890 * 0x43->0x4F Reserved
1891 */
1892 #define WIN_FORMAT 0x50
1893 /*
1894 * 0x51->0x5F Reserved
1895 */
1896 #define WIN_INIT 0x60
1897 /*
1898 * 0x61->0x5F Reserved
1899 */
1900 #define WIN_SEEK 0x70 /* 0x70-0x7F Reserved */
1901 #define CFA_TRANSLATE_SECTOR 0x87 /* CFA Translate Sector */
1902 #define WIN_DIAGNOSE 0x90
1903 #define WIN_SPECIFY 0x91 /* set drive geometry translation */
1904 #define WIN_DOWNLOAD_MICROCODE 0x92
1905 #define WIN_STANDBYNOW2 0x94
1906 #define WIN_STANDBY2 0x96
1907 #define WIN_SETIDLE2 0x97
1908 #define WIN_CHECKPOWERMODE2 0x98
1909 #define WIN_SLEEPNOW2 0x99
1910 /*
1911 * 0x9A VENDOR
1912 */
1913 #define WIN_PACKETCMD 0xA0 /* Send a packet command. */
1914 #define WIN_PIDENTIFY 0xA1 /* identify ATAPI device */
1915 #define WIN_QUEUED_SERVICE 0xA2
1916 #define WIN_SMART 0xB0 /* self-monitoring and reporting */
1917 #define CFA_ERASE_SECTORS 0xC0
1918 #define WIN_MULTREAD 0xC4 /* read sectors using multiple mode*/
1919 #define WIN_MULTWRITE 0xC5 /* write sectors using multiple mode */
1920 #define WIN_SETMULT 0xC6 /* enable/disable multiple mode */
1921 #define WIN_READDMA_QUEUED 0xC7 /* read sectors using Queued DMA transfers */
1922 #define WIN_READDMA 0xC8 /* read sectors using DMA transfers */
1923 #define WIN_READDMA_ONCE 0xC9 /* 28-Bit - without retries */
1924 #define WIN_WRITEDMA 0xCA /* write sectors using DMA transfers */
1925 #define WIN_WRITEDMA_ONCE 0xCB /* 28-Bit - without retries */
1926 #define WIN_WRITEDMA_QUEUED 0xCC /* write sectors using Queued DMA transfers */
1927 #define CFA_WRITE_MULTI_WO_ERASE 0xCD /* CFA Write multiple without erase */
1928 #define WIN_GETMEDIASTATUS 0xDA
1929 #define WIN_ACKMEDIACHANGE 0xDB /* ATA-1, ATA-2 vendor */
1930 #define WIN_POSTBOOT 0xDC
1931 #define WIN_PREBOOT 0xDD
1932 #define WIN_DOORLOCK 0xDE /* lock door on removable drives */
1933 #define WIN_DOORUNLOCK 0xDF /* unlock door on removable drives */
1934 #define WIN_STANDBYNOW1 0xE0
1935 #define WIN_IDLEIMMEDIATE 0xE1 /* force drive to become "ready" */
1936 #define WIN_STANDBY 0xE2 /* Set device in Standby Mode */
1937 #define WIN_SETIDLE1 0xE3
1938 #define WIN_READ_BUFFER 0xE4 /* force read only 1 sector */
1939 #define WIN_CHECKPOWERMODE1 0xE5
1940 #define WIN_SLEEPNOW1 0xE6
1941 #define WIN_FLUSH_CACHE 0xE7
1942 #define WIN_WRITE_BUFFER 0xE8 /* force write only 1 sector */
1943 #define WIN_WRITE_SAME 0xE9 /* read ata-2 to use */
1944 /* SET_FEATURES 0x22 or 0xDD */
1945 #define WIN_FLUSH_CACHE_EXT 0xEA /* 48-Bit */
1946 #define WIN_IDENTIFY 0xEC /* ask drive to identify itself */
1947 #define WIN_MEDIAEJECT 0xED
1948 #define WIN_IDENTIFY_DMA 0xEE /* same as WIN_IDENTIFY, but DMA */
1949 #define WIN_SETFEATURES 0xEF /* set special drive features */
1950 #define EXABYTE_ENABLE_NEST 0xF0
1951 #define WIN_SECURITY_SET_PASS 0xF1
1952 #define WIN_SECURITY_UNLOCK 0xF2
1953 #define WIN_SECURITY_ERASE_PREPARE 0xF3
1954 #define WIN_SECURITY_ERASE_UNIT 0xF4
1955 #define WIN_SECURITY_FREEZE_LOCK 0xF5
1956 #define WIN_SECURITY_DISABLE 0xF6
1957 #define WIN_READ_NATIVE_MAX 0xF8 /* return the native maximum address */
1958 #define WIN_SET_MAX 0xF9
1959 #define DISABLE_SEAGATE 0xFB
1960
1961 /* set to 1 set disable mult support */
1962 #define MAX_MULT_SECTORS 8
1963
1964 struct IDEState;
1965
1966 typedef void EndTransferFunc(struct IDEState *);
1967
1968 typedef struct IDEState {
1969 /* ide config */
1970 int cylinders, heads, sectors;
1971 int64_t nb_sectors;
1972 int mult_sectors;
1973 int irq;
1974 /* ide regs */
1975 uint8_t feature;
1976 uint8_t error;
1977 uint16_t nsector; /* 0 is 256 to ease computations */
1978 uint8_t sector;
1979 uint8_t lcyl;
1980 uint8_t hcyl;
1981 uint8_t select;
1982 uint8_t status;
1983 /* 0x3f6 command, only meaningful for drive 0 */
1984 uint8_t cmd;
1985 /* depends on bit 4 in select, only meaningful for drive 0 */
1986 struct IDEState *cur_drive;
1987 BlockDriverState *bs;
1988 int req_nb_sectors; /* number of sectors per interrupt */
1989 EndTransferFunc *end_transfer_func;
1990 uint8_t *data_ptr;
1991 uint8_t *data_end;
1992 uint8_t io_buffer[MAX_MULT_SECTORS*512 + 4];
1993 } IDEState;
1994
1995 IDEState ide_state[MAX_DISKS];
1996
1997 static void padstr(char *str, const char *src, int len)
1998 {
1999 int i, v;
2000 for(i = 0; i < len; i++) {
2001 if (*src)
2002 v = *src++;
2003 else
2004 v = ' ';
2005 *(char *)((long)str ^ 1) = v;
2006 str++;
2007 }
2008 }
2009
2010 static void ide_identify(IDEState *s)
2011 {
2012 uint16_t *p;
2013 unsigned int oldsize;
2014
2015 memset(s->io_buffer, 0, 512);
2016 p = (uint16_t *)s->io_buffer;
2017 stw(p + 0, 0x0040);
2018 stw(p + 1, s->cylinders);
2019 stw(p + 3, s->heads);
2020 stw(p + 4, 512 * s->sectors); /* sectors */
2021 stw(p + 5, 512); /* sector size */
2022 stw(p + 6, s->sectors);
2023 stw(p + 20, 3); /* buffer type */
2024 stw(p + 21, 512); /* cache size in sectors */
2025 stw(p + 22, 4); /* ecc bytes */
2026 padstr((uint8_t *)(p + 27), "QEMU HARDDISK", 40);
2027 #if MAX_MULT_SECTORS > 1
2028 stw(p + 47, MAX_MULT_SECTORS);
2029 #endif
2030 stw(p + 48, 1); /* dword I/O */
2031 stw(p + 49, 1 << 9); /* LBA supported, no DMA */
2032 stw(p + 51, 0x200); /* PIO transfer cycle */
2033 stw(p + 52, 0x200); /* DMA transfer cycle */
2034 stw(p + 54, s->cylinders);
2035 stw(p + 55, s->heads);
2036 stw(p + 56, s->sectors);
2037 oldsize = s->cylinders * s->heads * s->sectors;
2038 stw(p + 57, oldsize);
2039 stw(p + 58, oldsize >> 16);
2040 if (s->mult_sectors)
2041 stw(p + 59, 0x100 | s->mult_sectors);
2042 stw(p + 60, s->nb_sectors);
2043 stw(p + 61, s->nb_sectors >> 16);
2044 stw(p + 80, (1 << 1) | (1 << 2));
2045 stw(p + 82, (1 << 14));
2046 stw(p + 83, (1 << 14));
2047 stw(p + 84, (1 << 14));
2048 stw(p + 85, (1 << 14));
2049 stw(p + 86, 0);
2050 stw(p + 87, (1 << 14));
2051 }
2052
2053 static inline void ide_abort_command(IDEState *s)
2054 {
2055 s->status = READY_STAT | ERR_STAT;
2056 s->error = ABRT_ERR;
2057 }
2058
2059 static inline void ide_set_irq(IDEState *s)
2060 {
2061 if (!(ide_state[0].cmd & IDE_CMD_DISABLE_IRQ)) {
2062 pic_set_irq(s->irq, 1);
2063 }
2064 }
2065
2066 /* prepare data transfer and tell what to do after */
2067 static void ide_transfer_start(IDEState *s, int size,
2068 EndTransferFunc *end_transfer_func)
2069 {
2070 s->end_transfer_func = end_transfer_func;
2071 s->data_ptr = s->io_buffer;
2072 s->data_end = s->io_buffer + size;
2073 s->status |= DRQ_STAT;
2074 }
2075
2076 static void ide_transfer_stop(IDEState *s)
2077 {
2078 s->end_transfer_func = ide_transfer_stop;
2079 s->data_ptr = s->io_buffer;
2080 s->data_end = s->io_buffer;
2081 s->status &= ~DRQ_STAT;
2082 }
2083
2084 static int64_t ide_get_sector(IDEState *s)
2085 {
2086 int64_t sector_num;
2087 if (s->select & 0x40) {
2088 /* lba */
2089 sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
2090 (s->lcyl << 8) | s->sector;
2091 } else {
2092 sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
2093 (s->select & 0x0f) * s->sectors +
2094 (s->sector - 1);
2095 }
2096 return sector_num;
2097 }
2098
2099 static void ide_set_sector(IDEState *s, int64_t sector_num)
2100 {
2101 unsigned int cyl, r;
2102 if (s->select & 0x40) {
2103 s->select = (s->select & 0xf0) | (sector_num >> 24);
2104 s->hcyl = (sector_num >> 16);
2105 s->lcyl = (sector_num >> 8);
2106 s->sector = (sector_num);
2107 } else {
2108 cyl = sector_num / (s->heads * s->sectors);
2109 r = sector_num % (s->heads * s->sectors);
2110 s->hcyl = cyl >> 8;
2111 s->lcyl = cyl;
2112 s->select = (s->select & 0xf0) | (r / s->sectors);
2113 s->sector = (r % s->sectors) + 1;
2114 }
2115 }
2116
2117 static void ide_sector_read(IDEState *s)
2118 {
2119 int64_t sector_num;
2120 int ret, n;
2121
2122 s->status = READY_STAT | SEEK_STAT;
2123 sector_num = ide_get_sector(s);
2124 n = s->nsector;
2125 if (n == 0) {
2126 /* no more sector to read from disk */
2127 ide_transfer_stop(s);
2128 } else {
2129 #if defined(DEBUG_IDE)
2130 printf("read sector=%Ld\n", sector_num);
2131 #endif
2132 if (n > s->req_nb_sectors)
2133 n = s->req_nb_sectors;
2134 ret = bdrv_read(s->bs, sector_num, s->io_buffer, n);
2135 ide_transfer_start(s, 512 * n, ide_sector_read);
2136 ide_set_irq(s);
2137 ide_set_sector(s, sector_num + n);
2138 s->nsector -= n;
2139 }
2140 }
2141
2142 static void ide_sector_write(IDEState *s)
2143 {
2144 int64_t sector_num;
2145 int ret, n, n1;
2146
2147 s->status = READY_STAT | SEEK_STAT;
2148 sector_num = ide_get_sector(s);
2149 #if defined(DEBUG_IDE)
2150 printf("write sector=%Ld\n", sector_num);
2151 #endif
2152 n = s->nsector;
2153 if (n > s->req_nb_sectors)
2154 n = s->req_nb_sectors;
2155 ret = bdrv_write(s->bs, sector_num, s->io_buffer, n);
2156 s->nsector -= n;
2157 if (s->nsector == 0) {
2158 /* no more sector to write */
2159 ide_transfer_stop(s);
2160 } else {
2161 n1 = s->nsector;
2162 if (n1 > s->req_nb_sectors)
2163 n1 = s->req_nb_sectors;
2164 ide_transfer_start(s, 512 * n1, ide_sector_write);
2165 }
2166 ide_set_sector(s, sector_num + n);
2167 ide_set_irq(s);
2168 }
2169
2170 void ide_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
2171 {
2172 IDEState *s = ide_state[0].cur_drive;
2173 int unit, n;
2174
2175 addr &= 7;
2176 #ifdef DEBUG_IDE
2177 printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
2178 #endif
2179 switch(addr) {
2180 case 0:
2181 break;
2182 case 1:
2183 s->feature = val;
2184 break;
2185 case 2:
2186 if (val == 0)
2187 val = 256;
2188 s->nsector = val;
2189 break;
2190 case 3:
2191 s->sector = val;
2192 break;
2193 case 4:
2194 s->lcyl = val;
2195 break;
2196 case 5:
2197 s->hcyl = val;
2198 break;
2199 case 6:
2200 /* select drive */
2201 unit = (val >> 4) & 1;
2202 s = &ide_state[unit];
2203 ide_state[0].cur_drive = s;
2204 s->select = val;
2205 break;
2206 default:
2207 case 7:
2208 /* command */
2209 #if defined(DEBUG_IDE)
2210 printf("ide: CMD=%02x\n", val);
2211 #endif
2212 switch(val) {
2213 case WIN_PIDENTIFY:
2214 case WIN_IDENTIFY:
2215 if (s->bs) {
2216 ide_identify(s);
2217 s->status = READY_STAT;
2218 ide_transfer_start(s, 512, ide_transfer_stop);
2219 } else {
2220 ide_abort_command(s);
2221 }
2222 ide_set_irq(s);
2223 break;
2224 case WIN_SPECIFY:
2225 case WIN_RECAL:
2226 s->status = READY_STAT;
2227 ide_set_irq(s);
2228 break;
2229 case WIN_SETMULT:
2230 if (s->nsector > MAX_MULT_SECTORS ||
2231 s->nsector == 0 ||
2232 (s->nsector & (s->nsector - 1)) != 0) {
2233 ide_abort_command(s);
2234 } else {
2235 s->mult_sectors = s->nsector;
2236 s->status = READY_STAT;
2237 }
2238 ide_set_irq(s);
2239 break;
2240 case WIN_READ:
2241 case WIN_READ_ONCE:
2242 s->req_nb_sectors = 1;
2243 ide_sector_read(s);
2244 break;
2245 case WIN_WRITE:
2246 case WIN_WRITE_ONCE:
2247 s->status = SEEK_STAT;
2248 s->req_nb_sectors = 1;
2249 ide_transfer_start(s, 512, ide_sector_write);
2250 break;
2251 case WIN_MULTREAD:
2252 if (!s->mult_sectors)
2253 goto abort_cmd;
2254 s->req_nb_sectors = s->mult_sectors;
2255 ide_sector_read(s);
2256 break;
2257 case WIN_MULTWRITE:
2258 if (!s->mult_sectors)
2259 goto abort_cmd;
2260 s->status = SEEK_STAT;
2261 s->req_nb_sectors = s->mult_sectors;
2262 n = s->nsector;
2263 if (n > s->req_nb_sectors)
2264 n = s->req_nb_sectors;
2265 ide_transfer_start(s, 512 * n, ide_sector_write);
2266 break;
2267 case WIN_READ_NATIVE_MAX:
2268 ide_set_sector(s, s->nb_sectors - 1);
2269 s->status = READY_STAT;
2270 ide_set_irq(s);
2271 break;
2272 default:
2273 abort_cmd:
2274 ide_abort_command(s);
2275 ide_set_irq(s);
2276 break;
2277 }
2278 }
2279 }
2280
2281 uint32_t ide_ioport_read(CPUX86State *env, uint32_t addr)
2282 {
2283 IDEState *s = ide_state[0].cur_drive;
2284 int ret;
2285
2286 addr &= 7;
2287 switch(addr) {
2288 case 0:
2289 ret = 0xff;
2290 break;
2291 case 1:
2292 ret = s->error;
2293 break;
2294 case 2:
2295 ret = s->nsector & 0xff;
2296 break;
2297 case 3:
2298 ret = s->sector;
2299 break;
2300 case 4:
2301 ret = s->lcyl;
2302 break;
2303 case 5:
2304 ret = s->hcyl;
2305 break;
2306 case 6:
2307 ret = s->select;
2308 break;
2309 default:
2310 case 7:
2311 ret = s->status;
2312 pic_set_irq(s->irq, 0);
2313 break;
2314 }
2315 #ifdef DEBUG_IDE
2316 printf("ide: read addr=0x%x val=%02x\n", addr, ret);
2317 #endif
2318 return ret;
2319 }
2320
2321 uint32_t ide_status_read(CPUX86State *env, uint32_t addr)
2322 {
2323 IDEState *s = ide_state[0].cur_drive;
2324 int ret;
2325 ret = s->status;
2326 #ifdef DEBUG_IDE
2327 printf("ide: read status val=%02x\n", ret);
2328 #endif
2329 return ret;
2330 }
2331
2332 void ide_cmd_write(CPUX86State *env, uint32_t addr, uint32_t val)
2333 {
2334 IDEState *s;
2335 int i;
2336
2337 #ifdef DEBUG_IDE
2338 printf("ide: write control val=%02x\n", val);
2339 #endif
2340 /* common for both drives */
2341 if (!(ide_state[0].cmd & IDE_CMD_RESET) &&
2342 (val & IDE_CMD_RESET)) {
2343 /* reset low to high */
2344 for(i = 0;i < 2; i++) {
2345 s = &ide_state[i];
2346 s->status = BUSY_STAT | SEEK_STAT;
2347 s->error = 0x01;
2348 }
2349 } else if ((ide_state[0].cmd & IDE_CMD_RESET) &&
2350 !(val & IDE_CMD_RESET)) {
2351 /* high to low */
2352 for(i = 0;i < 2; i++) {
2353 s = &ide_state[i];
2354 s->status = READY_STAT;
2355 /* set hard disk drive ID */
2356 s->select &= 0xf0; /* clear head */
2357 s->nsector = 1;
2358 s->sector = 1;
2359 if (s->nb_sectors == 0) {
2360 /* no disk present */
2361 s->lcyl = 0x12;
2362 s->hcyl = 0x34;
2363 } else {
2364 s->lcyl = 0;
2365 s->hcyl = 0;
2366 }
2367 }
2368 }
2369
2370 ide_state[0].cmd = val;
2371 }
2372
2373 void ide_data_writew(CPUX86State *env, uint32_t addr, uint32_t val)
2374 {
2375 IDEState *s = ide_state[0].cur_drive;
2376 uint8_t *p;
2377
2378 p = s->data_ptr;
2379 *(uint16_t *)p = tswap16(val);
2380 p += 2;
2381 s->data_ptr = p;
2382 if (p >= s->data_end)
2383 s->end_transfer_func(s);
2384 }
2385
2386 uint32_t ide_data_readw(CPUX86State *env, uint32_t addr)
2387 {
2388 IDEState *s = ide_state[0].cur_drive;
2389 uint8_t *p;
2390 int ret;
2391
2392 p = s->data_ptr;
2393 ret = tswap16(*(uint16_t *)p);
2394 p += 2;
2395 s->data_ptr = p;
2396 if (p >= s->data_end)
2397 s->end_transfer_func(s);
2398 return ret;
2399 }
2400
2401 void ide_data_writel(CPUX86State *env, uint32_t addr, uint32_t val)
2402 {
2403 IDEState *s = ide_state[0].cur_drive;
2404 uint8_t *p;
2405
2406 p = s->data_ptr;
2407 *(uint32_t *)p = tswap32(val);
2408 p += 4;
2409 s->data_ptr = p;
2410 if (p >= s->data_end)
2411 s->end_transfer_func(s);
2412 }
2413
2414 uint32_t ide_data_readl(CPUX86State *env, uint32_t addr)
2415 {
2416 IDEState *s = ide_state[0].cur_drive;
2417 uint8_t *p;
2418 int ret;
2419
2420 p = s->data_ptr;
2421 ret = tswap32(*(uint32_t *)p);
2422 p += 4;
2423 s->data_ptr = p;
2424 if (p >= s->data_end)
2425 s->end_transfer_func(s);
2426 return ret;
2427 }
2428
2429 void ide_reset(IDEState *s)
2430 {
2431 s->mult_sectors = MAX_MULT_SECTORS;
2432 s->status = READY_STAT;
2433 s->cur_drive = s;
2434 s->select = 0xa0;
2435 }
2436
2437 void ide_init(void)
2438 {
2439 IDEState *s;
2440 int i, cylinders;
2441 int64_t nb_sectors;
2442
2443 for(i = 0; i < MAX_DISKS; i++) {
2444 s = &ide_state[i];
2445 s->bs = bs_table[i];
2446 if (s->bs) {
2447 bdrv_get_geometry(s->bs, &nb_sectors);
2448 if (s->cylinders == 0) {
2449 /* if no geometry, use a LBA compatible one */
2450 cylinders = nb_sectors / (16 * 63);
2451 if (cylinders > 16383)
2452 cylinders = 16383;
2453 else if (cylinders < 2)
2454 cylinders = 2;
2455 s->cylinders = cylinders;
2456 s->heads = 16;
2457 s->sectors = 63;
2458 }
2459 s->nb_sectors = nb_sectors;
2460 }
2461 s->irq = 14;
2462 ide_reset(s);
2463 }
2464 register_ioport_write(0x1f0, 8, ide_ioport_write, 1);
2465 register_ioport_read(0x1f0, 8, ide_ioport_read, 1);
2466 register_ioport_read(0x3f6, 1, ide_status_read, 1);
2467 register_ioport_write(0x3f6, 1, ide_cmd_write, 1);
2468
2469 /* data ports */
2470 register_ioport_write(0x1f0, 2, ide_data_writew, 2);
2471 register_ioport_read(0x1f0, 2, ide_data_readw, 2);
2472 register_ioport_write(0x1f0, 4, ide_data_writel, 4);
2473 register_ioport_read(0x1f0, 4, ide_data_readl, 4);
2474 }
2475
2476 /***********************************************************/
2477 /* keyboard emulation */
2478
2479 /* Keyboard Controller Commands */
2480 #define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */
2481 #define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */
2482 #define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */
2483 #define KBD_CCMD_MOUSE_DISABLE 0xA7 /* Disable mouse interface */
2484 #define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */
2485 #define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */
2486 #define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */
2487 #define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */
2488 #define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */
2489 #define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */
2490 #define KBD_CCMD_READ_INPORT 0xC0 /* read input port */
2491 #define KBD_CCMD_READ_OUTPORT 0xD0 /* read output port */
2492 #define KBD_CCMD_WRITE_OUTPORT 0xD1 /* write output port */
2493 #define KBD_CCMD_WRITE_OBUF 0xD2
2494 #define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if
2495 initiated by the auxiliary device */
2496 #define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */
2497 #define KBD_CCMD_ENABLE_A20 0xDD
2498 #define KBD_CCMD_DISABLE_A20 0xDF
2499 #define KBD_CCMD_RESET 0xFE
2500
2501 /* Keyboard Commands */
2502 #define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */
2503 #define KBD_CMD_ECHO 0xEE
2504 #define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */
2505 #define KBD_CMD_ENABLE 0xF4 /* Enable scanning */
2506 #define KBD_CMD_RESET_DISABLE 0xF5 /* reset and disable scanning */
2507 #define KBD_CMD_RESET_ENABLE 0xF6 /* reset and enable scanning */
2508 #define KBD_CMD_RESET 0xFF /* Reset */
2509
2510 /* Keyboard Replies */
2511 #define KBD_REPLY_POR 0xAA /* Power on reset */
2512 #define KBD_REPLY_ACK 0xFA /* Command ACK */
2513 #define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */
2514
2515 /* Status Register Bits */
2516 #define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */
2517 #define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */
2518 #define KBD_STAT_SELFTEST 0x04 /* Self test successful */
2519 #define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */
2520 #define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */
2521 #define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */
2522 #define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */
2523 #define KBD_STAT_PERR 0x80 /* Parity error */
2524
2525 /* Controller Mode Register Bits */
2526 #define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */
2527 #define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */
2528 #define KBD_MODE_SYS 0x04 /* The system flag (?) */
2529 #define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */
2530 #define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */
2531 #define KBD_MODE_DISABLE_MOUSE 0x20 /* Disable mouse interface */
2532 #define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */
2533 #define KBD_MODE_RFU 0x80
2534
2535 /* Mouse Commands */
2536 #define AUX_SET_SCALE11 0xE6 /* Set 1:1 scaling */
2537 #define AUX_SET_SCALE21 0xE7 /* Set 2:1 scaling */
2538 #define AUX_SET_RES 0xE8 /* Set resolution */
2539 #define AUX_GET_SCALE 0xE9 /* Get scaling factor */
2540 #define AUX_SET_STREAM 0xEA /* Set stream mode */
2541 #define AUX_POLL 0xEB /* Poll */
2542 #define AUX_RESET_WRAP 0xEC /* Reset wrap mode */
2543 #define AUX_SET_WRAP 0xEE /* Set wrap mode */
2544 #define AUX_SET_REMOTE 0xF0 /* Set remote mode */
2545 #define AUX_GET_TYPE 0xF2 /* Get type */
2546 #define AUX_SET_SAMPLE 0xF3 /* Set sample rate */
2547 #define AUX_ENABLE_DEV 0xF4 /* Enable aux device */
2548 #define AUX_DISABLE_DEV 0xF5 /* Disable aux device */
2549 #define AUX_SET_DEFAULT 0xF6
2550 #define AUX_RESET 0xFF /* Reset aux device */
2551 #define AUX_ACK 0xFA /* Command byte ACK. */
2552
2553 #define MOUSE_STATUS_REMOTE 0x40
2554 #define MOUSE_STATUS_ENABLED 0x20
2555 #define MOUSE_STATUS_SCALE21 0x10
2556
2557 #define KBD_QUEUE_SIZE 256
2558
2559 typedef struct {
2560 uint8_t data[KBD_QUEUE_SIZE];
2561 int rptr, wptr, count;
2562 } KBDQueue;
2563
2564 typedef struct KBDState {
2565 KBDQueue queues[2];
2566 uint8_t write_cmd; /* if non zero, write data to port 60 is expected */
2567 uint8_t status;
2568 uint8_t mode;
2569 /* keyboard state */
2570 int kbd_write_cmd;
2571 int scan_enabled;
2572 /* mouse state */
2573 int mouse_write_cmd;
2574 uint8_t mouse_status;
2575 uint8_t mouse_resolution;
2576 uint8_t mouse_sample_rate;
2577 uint8_t mouse_wrap;
2578 uint8_t mouse_type; /* 0 = PS2, 3 = IMPS/2, 4 = IMEX */
2579 uint8_t mouse_detect_state;
2580 int mouse_dx; /* current values, needed for 'poll' mode */
2581 int mouse_dy;
2582 int mouse_dz;
2583 uint8_t mouse_buttons;
2584 } KBDState;
2585
2586 KBDState kbd_state;
2587 int reset_requested;
2588 int a20_enabled;
2589
2590 /* update irq and KBD_STAT_[MOUSE_]OBF */
2591 static void kbd_update_irq(KBDState *s)
2592 {
2593 int irq12_level, irq1_level;
2594
2595 irq1_level = 0;
2596 irq12_level = 0;
2597 s->status &= ~(KBD_STAT_OBF | KBD_STAT_MOUSE_OBF);
2598 if (s->queues[0].count != 0 ||
2599 s->queues[1].count != 0) {
2600 s->status |= KBD_STAT_OBF;
2601 if (s->queues[1].count != 0) {
2602 s->status |= KBD_STAT_MOUSE_OBF;
2603 if (s->mode & KBD_MODE_MOUSE_INT)
2604 irq12_level = 1;
2605 } else {
2606 if (s->mode & KBD_MODE_KBD_INT)
2607 irq1_level = 1;
2608 }
2609 }
2610 pic_set_irq(1, irq1_level);
2611 pic_set_irq(12, irq12_level);
2612 }
2613
2614 static void kbd_queue(KBDState *s, int b, int aux)
2615 {
2616 KBDQueue *q = &kbd_state.queues[aux];
2617
2618 #if defined(DEBUG_MOUSE) || defined(DEBUG_KBD)
2619 if (aux)
2620 printf("mouse event: 0x%02x\n", b);
2621 #ifdef DEBUG_KBD
2622 else
2623 printf("kbd event: 0x%02x\n", b);
2624 #endif
2625 #endif
2626 if (q->count >= KBD_QUEUE_SIZE)
2627 return;
2628 q->data[q->wptr] = b;
2629 if (++q->wptr == KBD_QUEUE_SIZE)
2630 q->wptr = 0;
2631 q->count++;
2632 kbd_update_irq(s);
2633 }
2634
2635 void kbd_put_keycode(int keycode)
2636 {
2637 KBDState *s = &kbd_state;
2638 kbd_queue(s, keycode, 0);
2639 }
2640
2641 uint32_t kbd_read_status(CPUX86State *env, uint32_t addr)
2642 {
2643 KBDState *s = &kbd_state;
2644 int val;
2645 val = s->status;
2646 #if defined(DEBUG_KBD) && 0
2647 printf("kbd: read status=0x%02x\n", val);
2648 #endif
2649 return val;
2650 }
2651
2652 void kbd_write_command(CPUX86State *env, uint32_t addr, uint32_t val)
2653 {
2654 KBDState *s = &kbd_state;
2655
2656 #ifdef DEBUG_KBD
2657 printf("kbd: write cmd=0x%02x\n", val);
2658 #endif
2659 switch(val) {
2660 case KBD_CCMD_READ_MODE:
2661 kbd_queue(s, s->mode, 0);
2662 break;
2663 case KBD_CCMD_WRITE_MODE:
2664 case KBD_CCMD_WRITE_OBUF:
2665 case KBD_CCMD_WRITE_AUX_OBUF:
2666 case KBD_CCMD_WRITE_MOUSE:
2667 case KBD_CCMD_WRITE_OUTPORT:
2668 s->write_cmd = val;
2669 break;
2670 case KBD_CCMD_MOUSE_DISABLE:
2671 s->mode |= KBD_MODE_DISABLE_MOUSE;
2672 break;
2673 case KBD_CCMD_MOUSE_ENABLE:
2674 s->mode &= ~KBD_MODE_DISABLE_MOUSE;
2675 break;
2676 case KBD_CCMD_TEST_MOUSE:
2677 kbd_queue(s, 0x00, 0);
2678 break;
2679 case KBD_CCMD_SELF_TEST:
2680 s->status |= KBD_STAT_SELFTEST;
2681 kbd_queue(s, 0x55, 0);
2682 break;
2683 case KBD_CCMD_KBD_TEST:
2684 kbd_queue(s, 0x00, 0);
2685 break;
2686 case KBD_CCMD_KBD_DISABLE:
2687 s->mode |= KBD_MODE_DISABLE_KBD;
2688 break;
2689 case KBD_CCMD_KBD_ENABLE:
2690 s->mode &= ~KBD_MODE_DISABLE_KBD;
2691 break;
2692 case KBD_CCMD_READ_INPORT:
2693 kbd_queue(s, 0x00, 0);
2694 break;
2695 case KBD_CCMD_READ_OUTPORT:
2696 /* XXX: check that */
2697 val = 0x01 | (a20_enabled << 1);
2698 if (s->status & KBD_STAT_OBF)
2699 val |= 0x10;
2700 if (s->status & KBD_STAT_MOUSE_OBF)
2701 val |= 0x20;
2702 kbd_queue(s, val, 0);
2703 break;
2704 case KBD_CCMD_ENABLE_A20:
2705 a20_enabled = 1;
2706 break;
2707 case KBD_CCMD_DISABLE_A20:
2708 a20_enabled = 0;
2709 break;
2710 case KBD_CCMD_RESET:
2711 reset_requested = 1;
2712 cpu_x86_interrupt(global_env, CPU_INTERRUPT_EXIT);
2713 break;
2714 default:
2715 fprintf(stderr, "vl: unsupported keyboard cmd=0x%02x\n", val);
2716 break;
2717 }
2718 }
2719
2720 uint32_t kbd_read_data(CPUX86State *env, uint32_t addr)
2721 {
2722 KBDState *s = &kbd_state;
2723 KBDQueue *q;
2724 int val;
2725
2726 q = &s->queues[0]; /* first check KBD data */
2727 if (q->count == 0)
2728 q = &s->queues[1]; /* then check AUX data */
2729 if (q->count == 0) {
2730 /* XXX: return something else ? */
2731 val = 0;
2732 } else {
2733 val = q->data[q->rptr];
2734 if (++q->rptr == KBD_QUEUE_SIZE)
2735 q->rptr = 0;
2736 q->count--;
2737 /* reading deasserts IRQ */
2738 if (q == &s->queues[0])
2739 pic_set_irq(1, 0);
2740 else
2741 pic_set_irq(12, 0);
2742 }
2743 /* reassert IRQs if data left */
2744 kbd_update_irq(s);
2745 #ifdef DEBUG_KBD
2746 printf("kbd: read data=0x%02x\n", val);
2747 #endif
2748 return val;
2749 }
2750
2751 static void kbd_reset_keyboard(KBDState *s)
2752 {
2753 s->scan_enabled = 1;
2754 }
2755
2756 static void kbd_write_keyboard(KBDState *s, int val)
2757 {
2758 switch(s->kbd_write_cmd) {
2759 default:
2760 case -1:
2761 switch(val) {
2762 case 0x00:
2763 kbd_queue(s, KBD_REPLY_ACK, 0);
2764 break;
2765 case 0x05:
2766 kbd_queue(s, KBD_REPLY_RESEND, 0);
2767 break;
2768 case KBD_CMD_ECHO:
2769 kbd_queue(s, KBD_CMD_ECHO, 0);
2770 break;
2771 case KBD_CMD_ENABLE:
2772 s->scan_enabled = 1;
2773 kbd_queue(s, KBD_REPLY_ACK, 0);
2774 break;
2775 case KBD_CMD_SET_LEDS:
2776 case KBD_CMD_SET_RATE:
2777 s->kbd_write_cmd = val;
2778 break;
2779 case KBD_CMD_RESET_DISABLE:
2780 kbd_reset_keyboard(s);
2781 s->scan_enabled = 0;
2782 kbd_queue(s, KBD_REPLY_ACK, 0);
2783 break;
2784 case KBD_CMD_RESET_ENABLE:
2785 kbd_reset_keyboard(s);
2786 s->scan_enabled = 1;
2787 kbd_queue(s, KBD_REPLY_ACK, 0);
2788 break;
2789 case KBD_CMD_RESET:
2790 kbd_reset_keyboard(s);
2791 kbd_queue(s, KBD_REPLY_ACK, 0);
2792 kbd_queue(s, KBD_REPLY_POR, 0);
2793 break;
2794 default:
2795 kbd_queue(s, KBD_REPLY_ACK, 0);
2796 break;
2797 }
2798 break;
2799 case KBD_CMD_SET_LEDS:
2800 kbd_queue(s, KBD_REPLY_ACK, 0);
2801 s->kbd_write_cmd = -1;
2802 break;
2803 case KBD_CMD_SET_RATE:
2804 kbd_queue(s, KBD_REPLY_ACK, 0);
2805 s->kbd_write_cmd = -1;
2806 break;
2807 }
2808 }
2809
2810 static void kbd_mouse_send_packet(KBDState *s)
2811 {
2812 unsigned int b;
2813 int dx1, dy1, dz1;
2814
2815 dx1 = s->mouse_dx;
2816 dy1 = s->mouse_dy;
2817 dz1 = s->mouse_dz;
2818 /* XXX: increase range to 8 bits ? */
2819 if (dx1 > 127)
2820 dx1 = 127;
2821 else if (dx1 < -127)
2822 dx1 = -127;
2823 if (dy1 > 127)
2824 dy1 = 127;
2825 else if (dy1 < -127)
2826 dy1 = -127;
2827 b = 0x08 | ((dx1 < 0) << 4) | ((dy1 < 0) << 5) | (s->mouse_buttons & 0x07);
2828 kbd_queue(s, b, 1);
2829 kbd_queue(s, dx1 & 0xff, 1);
2830 kbd_queue(s, dy1 & 0xff, 1);
2831 /* extra byte for IMPS/2 or IMEX */
2832 switch(s->mouse_type) {
2833 default:
2834 break;
2835 case 3:
2836 if (dz1 > 127)
2837 dz1 = 127;
2838 else if (dz1 < -127)
2839 dz1 = -127;
2840 kbd_queue(s, dz1 & 0xff, 1);
2841 break;
2842 case 4:
2843 if (dz1 > 7)
2844 dz1 = 7;
2845 else if (dz1 < -7)
2846 dz1 = -7;
2847 b = (dz1 & 0x0f) | ((s->mouse_buttons & 0x18) << 1);
2848 kbd_queue(s, b, 1);
2849 break;
2850 }
2851
2852 /* update deltas */
2853 s->mouse_dx -= dx1;
2854 s->mouse_dy -= dy1;
2855 s->mouse_dz -= dz1;
2856 }
2857
2858 void kbd_mouse_event(int dx, int dy, int dz, int buttons_state)
2859 {
2860 KBDState *s = &kbd_state;
2861
2862 /* check if deltas are recorded when disabled */
2863 if (!(s->mouse_status & MOUSE_STATUS_ENABLED))
2864 return;
2865
2866 s->mouse_dx += dx;
2867 s->mouse_dy -= dy;
2868 s->mouse_dz += dz;
2869 s->mouse_buttons = buttons_state;
2870
2871 if (!(s->mouse_status & MOUSE_STATUS_REMOTE) &&
2872 (s->queues[1].count < (KBD_QUEUE_SIZE - 16))) {
2873 for(;;) {
2874 /* if not remote, send event. Multiple events are sent if
2875 too big deltas */
2876 kbd_mouse_send_packet(s);
2877 if (s->mouse_dx == 0 && s->mouse_dy == 0 && s->mouse_dz == 0)
2878 break;
2879 }
2880 }
2881 }
2882
2883 static void kbd_write_mouse(KBDState *s, int val)
2884 {
2885 #ifdef DEBUG_MOUSE
2886 printf("kbd: write mouse 0x%02x\n", val);
2887 #endif
2888 switch(s->mouse_write_cmd) {
2889 default:
2890 case -1:
2891 /* mouse command */
2892 if (s->mouse_wrap) {
2893 if (val == AUX_RESET_WRAP) {
2894 s->mouse_wrap = 0;
2895 kbd_queue(s, AUX_ACK, 1);
2896 return;
2897 } else if (val != AUX_RESET) {
2898 kbd_queue(s, val, 1);
2899 return;
2900 }
2901 }
2902 switch(val) {
2903 case AUX_SET_SCALE11:
2904 s->mouse_status &= ~MOUSE_STATUS_SCALE21;
2905 kbd_queue(s, AUX_ACK, 1);
2906 break;
2907 case AUX_SET_SCALE21:
2908 s->mouse_status |= MOUSE_STATUS_SCALE21;
2909 kbd_queue(s, AUX_ACK, 1);
2910 break;
2911 case AUX_SET_STREAM:
2912 s->mouse_status &= ~MOUSE_STATUS_REMOTE;
2913 kbd_queue(s, AUX_ACK, 1);
2914 break;
2915 case AUX_SET_WRAP:
2916 s->mouse_wrap = 1;
2917 kbd_queue(s, AUX_ACK, 1);
2918 break;
2919 case AUX_SET_REMOTE:
2920 s->mouse_status |= MOUSE_STATUS_REMOTE;
2921 kbd_queue(s, AUX_ACK, 1);
2922 break;
2923 case AUX_GET_TYPE:
2924 kbd_queue(s, AUX_ACK, 1);
2925 kbd_queue(s, s->mouse_type, 1);
2926 break;
2927 case AUX_SET_RES:
2928 case AUX_SET_SAMPLE:
2929 s->mouse_write_cmd = val;
2930 kbd_queue(s, AUX_ACK, 1);
2931 break;
2932 case AUX_GET_SCALE:
2933 kbd_queue(s, AUX_ACK, 1);
2934 kbd_queue(s, s->mouse_status, 1);
2935 kbd_queue(s, s->mouse_resolution, 1);
2936 kbd_queue(s, s->mouse_sample_rate, 1);
2937 break;
2938 case AUX_POLL:
2939 kbd_queue(s, AUX_ACK, 1);
2940 kbd_mouse_send_packet(s);
2941 break;
2942 case AUX_ENABLE_DEV:
2943 s->mouse_status |= MOUSE_STATUS_ENABLED;
2944 kbd_queue(s, AUX_ACK, 1);
2945 break;
2946 case AUX_DISABLE_DEV:
2947 s->mouse_status &= ~MOUSE_STATUS_ENABLED;
2948 kbd_queue(s, AUX_ACK, 1);
2949 break;
2950 case AUX_SET_DEFAULT:
2951 s->mouse_sample_rate = 100;
2952 s->mouse_resolution = 2;
2953 s->mouse_status = 0;
2954 kbd_queue(s, AUX_ACK, 1);
2955 break;
2956 case AUX_RESET:
2957 s->mouse_sample_rate = 100;
2958 s->mouse_resolution = 2;
2959 s->mouse_status = 0;
2960 kbd_queue(s, AUX_ACK, 1);
2961 kbd_queue(s, 0xaa, 1);
2962 kbd_queue(s, s->mouse_type, 1);
2963 break;
2964 default:
2965 break;
2966 }
2967 break;
2968 case AUX_SET_SAMPLE:
2969 s->mouse_sample_rate = val;
2970 #if 0
2971 /* detect IMPS/2 or IMEX */
2972 switch(s->mouse_detect_state) {
2973 default:
2974 case 0:
2975 if (val == 200)
2976 s->mouse_detect_state = 1;
2977 break;
2978 case 1:
2979 if (val == 100)
2980 s->mouse_detect_state = 2;
2981 else if (val == 200)
2982 s->mouse_detect_state = 3;
2983 else
2984 s->mouse_detect_state = 0;
2985 break;
2986 case 2:
2987 if (val == 80)
2988 s->mouse_type = 3; /* IMPS/2 */
2989 s->mouse_detect_state = 0;
2990 break;
2991 case 3:
2992 if (val == 80)
2993 s->mouse_type = 4; /* IMEX */
2994 s->mouse_detect_state = 0;
2995 break;
2996 }
2997 #endif
2998 kbd_queue(s, AUX_ACK, 1);
2999 s->mouse_write_cmd = -1;
3000 break;
3001 case AUX_SET_RES:
3002 s->mouse_resolution = val;
3003 kbd_queue(s, AUX_ACK, 1);
3004 s->mouse_write_cmd = -1;
3005 break;
3006 }
3007 }
3008
3009 void kbd_write_data(CPUX86State *env, uint32_t addr, uint32_t val)
3010 {
3011 KBDState *s = &kbd_state;
3012
3013 #ifdef DEBUG_KBD
3014 printf("kbd: write data=0x%02x\n", val);
3015 #endif
3016
3017 switch(s->write_cmd) {
3018 case 0:
3019 kbd_write_keyboard(s, val);
3020 break;
3021 case KBD_CCMD_WRITE_MODE:
3022 s->mode = val;
3023 kbd_update_irq(s);
3024 break;
3025 case KBD_CCMD_WRITE_OBUF:
3026 kbd_queue(s, val, 0);
3027 break;
3028 case KBD_CCMD_WRITE_AUX_OBUF:
3029 kbd_queue(s, val, 1);
3030 break;
3031 case KBD_CCMD_WRITE_OUTPORT:
3032 a20_enabled = (val >> 1) & 1;
3033 if (!(val & 1)) {
3034 reset_requested = 1;
3035 cpu_x86_interrupt(global_env, CPU_INTERRUPT_EXIT);
3036 }
3037 break;
3038 case KBD_CCMD_WRITE_MOUSE:
3039 kbd_write_mouse(s, val);
3040 break;
3041 default:
3042 break;
3043 }
3044 s->write_cmd = 0;
3045 }
3046
3047 void kbd_reset(KBDState *s)
3048 {
3049 KBDQueue *q;
3050 int i;
3051
3052 s->kbd_write_cmd = -1;
3053 s->mouse_write_cmd = -1;
3054 s->mode = KBD_MODE_KBD_INT | KBD_MODE_MOUSE_INT;
3055 s->status = KBD_STAT_CMD | KBD_STAT_UNLOCKED;
3056 for(i = 0; i < 2; i++) {
3057 q = &s->queues[i];
3058 q->rptr = 0;
3059 q->wptr = 0;
3060 q->count = 0;
3061 }
3062 }
3063
3064 void kbd_init(void)
3065 {
3066 kbd_reset(&kbd_state);
3067 register_ioport_read(0x60, 1, kbd_read_data, 1);
3068 register_ioport_write(0x60, 1, kbd_write_data, 1);
3069 register_ioport_read(0x64, 1, kbd_read_status, 1);
3070 register_ioport_write(0x64, 1, kbd_write_command, 1);
3071 }
3072
3073 /***********************************************************/
3074 /* Bochs BIOS debug ports */
3075
3076 void bochs_bios_write(CPUX86State *env, uint32_t addr, uint32_t val)
3077 {
3078 switch(addr) {
3079 /* Bochs BIOS messages */
3080 case 0x400:
3081 case 0x401:
3082 fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
3083 exit(1);
3084 case 0x402:
3085 case 0x403:
3086 #ifdef DEBUG_BIOS
3087 fprintf(stderr, "%c", val);
3088 #endif
3089 break;
3090
3091 /* LGPL'ed VGA BIOS messages */
3092 case 0x501:
3093 case 0x502:
3094 fprintf(stderr, "VGA BIOS panic, line %d\n", val);
3095 exit(1);
3096 case 0x500:
3097 case 0x503:
3098 #ifdef DEBUG_BIOS
3099 fprintf(stderr, "%c", val);
3100 #endif
3101 break;
3102 }
3103 }
3104
3105 void bochs_bios_init(void)
3106 {
3107 register_ioport_write(0x400, 1, bochs_bios_write, 2);
3108 register_ioport_write(0x401, 1, bochs_bios_write, 2);
3109 register_ioport_write(0x402, 1, bochs_bios_write, 1);
3110 register_ioport_write(0x403, 1, bochs_bios_write, 1);
3111
3112 register_ioport_write(0x501, 1, bochs_bios_write, 2);
3113 register_ioport_write(0x502, 1, bochs_bios_write, 2);
3114 register_ioport_write(0x500, 1, bochs_bios_write, 1);
3115 register_ioport_write(0x503, 1, bochs_bios_write, 1);
3116 }
3117
3118 /***********************************************************/
3119 /* dumb display */
3120
3121 /* init terminal so that we can grab keys */
3122 static struct termios oldtty;
3123
3124 static void term_exit(void)
3125 {
3126 tcsetattr (0, TCSANOW, &oldtty);
3127 }
3128
3129 static void term_init(void)
3130 {
3131 struct termios tty;
3132
3133 tcgetattr (0, &tty);
3134 oldtty = tty;
3135
3136 tty.c_iflag &= ~(IGNBRK|BRKINT|PARMRK|ISTRIP
3137 |INLCR|IGNCR|ICRNL|IXON);
3138 tty.c_oflag |= OPOST;
3139 tty.c_lflag &= ~(ECHO|ECHONL|ICANON|IEXTEN|ISIG);
3140 tty.c_cflag &= ~(CSIZE|PARENB);
3141 tty.c_cflag |= CS8;
3142 tty.c_cc[VMIN] = 1;
3143 tty.c_cc[VTIME] = 0;
3144
3145 tcsetattr (0, TCSANOW, &tty);
3146
3147 atexit(term_exit);
3148
3149 fcntl(0, F_SETFL, O_NONBLOCK);
3150 }
3151
3152 static void dumb_update(DisplayState *ds, int x, int y, int w, int h)
3153 {
3154 }
3155
3156 static void dumb_resize(DisplayState *ds, int w, int h)
3157 {
3158 }
3159
3160 static void dumb_refresh(DisplayState *ds)
3161 {
3162 vga_update_display();
3163 }
3164
3165 void dumb_display_init(DisplayState *ds)
3166 {
3167 ds->data = NULL;
3168 ds->linesize = 0;
3169 ds->depth = 0;
3170 ds->dpy_update = dumb_update;
3171 ds->dpy_resize = dumb_resize;
3172 ds->dpy_refresh = dumb_refresh;
3173 }
3174
3175 /***********************************************************/
3176 /* cpu signal handler */
3177 static void host_segv_handler(int host_signum, siginfo_t *info,
3178 void *puc)
3179 {
3180 if (cpu_signal_handler(host_signum, info, puc))
3181 return;
3182 term_exit();
3183 abort();
3184 }
3185
3186 static int timer_irq_pending;
3187 static int timer_irq_count;
3188
3189 static int timer_ms;
3190 static int gui_refresh_pending, gui_refresh_count;
3191
3192 static void host_alarm_handler(int host_signum, siginfo_t *info,
3193 void *puc)
3194 {
3195 /* NOTE: since usually the OS asks a 100 Hz clock, there can be
3196 some drift between cpu_get_ticks() and the interrupt time. So
3197 we queue some interrupts to avoid missing some */
3198 timer_irq_count += pit_get_out_edges(&pit_channels[0]);
3199 if (timer_irq_count) {
3200 if (timer_irq_count > 2)
3201 timer_irq_count = 2;
3202 timer_irq_count--;
3203 timer_irq_pending = 1;
3204 }
3205 gui_refresh_count += timer_ms;
3206 if (gui_refresh_count >= GUI_REFRESH_INTERVAL) {
3207 gui_refresh_count = 0;
3208 gui_refresh_pending = 1;
3209 }
3210
3211 if (gui_refresh_pending || timer_irq_pending) {
3212 /* just exit from the cpu to have a chance to handle timers */
3213 cpu_x86_interrupt(global_env, CPU_INTERRUPT_EXIT);
3214 }
3215 }
3216
3217 unsigned long mmap_addr = PHYS_RAM_BASE;
3218
3219 void *get_mmap_addr(unsigned long size)
3220 {
3221 unsigned long addr;
3222 addr = mmap_addr;
3223 mmap_addr += ((size + 4095) & ~4095) + 4096;
3224 return (void *)addr;
3225 }
3226
3227 /* main execution loop */
3228
3229 CPUState *cpu_gdbstub_get_env(void *opaque)
3230 {
3231 return global_env;
3232 }
3233
3234 int main_loop(void *opaque)
3235 {
3236 struct pollfd ufds[2], *pf, *serial_ufd, *net_ufd, *gdb_ufd;
3237 int ret, n, timeout;
3238 uint8_t ch;
3239 CPUState *env = global_env;
3240
3241 if (nodisp && !term_inited) {
3242 /* initialize terminal only there so that the user has a
3243 chance to stop QEMU with Ctrl-C before the gdb connection
3244 is launched */
3245 term_inited = 1;
3246 term_init();
3247 }
3248
3249 for(;;) {
3250
3251 ret = cpu_x86_exec(env);
3252 if (reset_requested)
3253 break;
3254 if (ret == EXCP_DEBUG)
3255 return EXCP_DEBUG;
3256 /* if hlt instruction, we wait until the next IRQ */
3257 if (ret == EXCP_HLT)
3258 timeout = 10;
3259 else
3260 timeout = 0;
3261 /* poll any events */
3262 serial_ufd = NULL;
3263 pf = ufds;
3264 if (!(serial_ports[0].lsr & UART_LSR_DR)) {
3265 serial_ufd = pf;
3266 pf->fd = 0;
3267 pf->events = POLLIN;
3268 pf++;
3269 }
3270 net_ufd = NULL;
3271 if (net_fd > 0 && ne2000_can_receive(&ne2000_state)) {
3272 net_ufd = pf;
3273 pf->fd = net_fd;
3274 pf->events = POLLIN;
3275 pf++;
3276 }
3277 gdb_ufd = NULL;
3278 if (gdbstub_fd > 0) {
3279 gdb_ufd = pf;
3280 pf->fd = gdbstub_fd;
3281 pf->events = POLLIN;
3282 pf++;
3283 }
3284
3285 ret = poll(ufds, pf - ufds, timeout);
3286 if (ret > 0) {
3287 if (serial_ufd && (serial_ufd->revents & POLLIN)) {
3288 n = read(0, &ch, 1);
3289 if (n == 1) {
3290 serial_received_byte(&serial_ports[0], ch);
3291 }
3292 }
3293 if (net_ufd && (net_ufd->revents & POLLIN)) {
3294 uint8_t buf[MAX_ETH_FRAME_SIZE];
3295
3296 n = read(net_fd, buf, MAX_ETH_FRAME_SIZE);
3297 if (n > 0) {
3298 if (n < 60) {
3299 memset(buf + n, 0, 60 - n);
3300 n = 60;
3301 }
3302 ne2000_receive(&ne2000_state, buf, n);
3303 }
3304 }
3305 if (gdb_ufd && (gdb_ufd->revents & POLLIN)) {
3306 uint8_t buf[1];
3307 /* stop emulation if requested by gdb */
3308 n = read(gdbstub_fd, buf, 1);
3309 if (n == 1)
3310 break;
3311 }
3312 }
3313
3314 /* timer IRQ */
3315 if (timer_irq_pending) {
3316 pic_set_irq(0, 1);
3317 pic_set_irq(0, 0);
3318 timer_irq_pending = 0;
3319 }
3320
3321 /* VGA */
3322 if (gui_refresh_pending) {
3323 display_state.dpy_refresh(&display_state);
3324 gui_refresh_pending = 0;
3325 }
3326 }
3327 return EXCP_INTERRUPT;
3328 }
3329
3330 void help(void)
3331 {
3332 printf("Virtual Linux version " QEMU_VERSION ", Copyright (c) 2003 Fabrice Bellard\n"
3333 "usage: vl [options] [bzImage [kernel parameters...]]\n"
3334 "\n"
3335 "'bzImage' is a Linux kernel image (PAGE_OFFSET must be defined\n"
3336 "to 0x90000000 in asm/page.h and arch/i386/vmlinux.lds)\n"
3337 "\n"
3338 "General options:\n"
3339 "-initrd file use 'file' as initial ram disk\n"
3340 "-hda file use 'file' as hard disk 0 image\n"
3341 "-hdb file use 'file' as hard disk 1 image\n"
3342 "-snapshot write to temporary files instead of disk image files\n"
3343 "-m megs set virtual RAM size to megs MB\n"
3344 "-n script set network init script [default=%s]\n"
3345 "\n"
3346 "Debug/Expert options:\n"
3347 "-s wait gdb connection to port %d\n"
3348 "-p port change gdb connection port\n"
3349 "-d output log in /tmp/vl.log\n"
3350 "-hdachs c,h,s force hard disk 0 geometry for non LBA disk images\n"
3351 "-L path set the directory for the BIOS and VGA BIOS\n"
3352 "\n"
3353 "During emulation, use C-a h to get terminal commands:\n",
3354 DEFAULT_NETWORK_SCRIPT, DEFAULT_GDBSTUB_PORT);
3355 term_print_help();
3356 exit(1);
3357 }
3358
3359 struct option long_options[] = {
3360 { "initrd", 1, NULL, 0, },
3361 { "hda", 1, NULL, 0, },
3362 { "hdb", 1, NULL, 0, },
3363 { "snapshot", 0, NULL, 0, },
3364 { "hdachs", 1, NULL, 0, },
3365 { "nodisp", 0, NULL, 0, },
3366 { NULL, 0, NULL, 0 },
3367 };
3368
3369 int main(int argc, char **argv)
3370 {
3371 int c, ret, initrd_size, i, use_gdbstub, gdbstub_port, long_index;
3372 int snapshot, linux_boot, total_ram_size;
3373 struct linux_params *params;
3374 struct sigaction act;
3375 struct itimerval itv;
3376 CPUX86State *env;
3377 const char *tmpdir, *initrd_filename;
3378 const char *hd_filename[MAX_DISKS];
3379 DisplayState *ds = &display_state;
3380
3381 /* we never want that malloc() uses mmap() */
3382 mallopt(M_MMAP_THRESHOLD, 4096 * 1024);
3383 initrd_filename = NULL;
3384 for(i = 0; i < MAX_DISKS; i++)
3385 hd_filename[i] = NULL;
3386 phys_ram_size = 32 * 1024 * 1024;
3387 vga_ram_size = VGA_RAM_SIZE;
3388 pstrcpy(network_script, sizeof(network_script), DEFAULT_NETWORK_SCRIPT);
3389 use_gdbstub = 0;
3390 gdbstub_port = DEFAULT_GDBSTUB_PORT;
3391 snapshot = 0;
3392 linux_boot = 0;
3393 nodisp = 0;
3394 for(;;) {
3395 c = getopt_long_only(argc, argv, "hm:dn:sp:L:", long_options, &long_index);
3396 if (c == -1)
3397 break;
3398 switch(c) {
3399 case 0:
3400 switch(long_index) {
3401 case 0:
3402 initrd_filename = optarg;
3403 break;
3404 case 1:
3405 hd_filename[0] = optarg;
3406 break;
3407 case 2:
3408 hd_filename[1] = optarg;
3409 break;
3410 case 3:
3411 snapshot = 1;
3412 break;
3413 case 4:
3414 {
3415 int cyls, heads, secs;
3416 const char *p;
3417 p = optarg;
3418 cyls = strtol(p, (char **)&p, 0);
3419 if (*p != ',')
3420 goto chs_fail;
3421 p++;
3422 heads = strtol(p, (char **)&p, 0);
3423 if (*p != ',')
3424 goto chs_fail;
3425 p++;
3426 secs = strtol(p, (char **)&p, 0);
3427 if (*p != '\0')
3428 goto chs_fail;
3429 ide_state[0].cylinders = cyls;
3430 ide_state[0].heads = heads;
3431 ide_state[0].sectors = secs;
3432 chs_fail: ;
3433 }
3434 break;
3435 case 5:
3436 nodisp = 1;
3437 break;
3438 }
3439 break;
3440 case 'h':
3441 help();
3442 break;
3443 case 'm':
3444 phys_ram_size = atoi(optarg) * 1024 * 1024;
3445 if (phys_ram_size <= 0)
3446 help();
3447 if (phys_ram_size > PHYS_RAM_MAX_SIZE) {
3448 fprintf(stderr, "vl: at most %d MB RAM can be simulated\n",
3449 PHYS_RAM_MAX_SIZE / (1024 * 1024));
3450 exit(1);
3451 }
3452 break;
3453 case 'd':
3454 loglevel = 1;
3455 break;
3456 case 'n':
3457 pstrcpy(network_script, sizeof(network_script), optarg);
3458 break;
3459 case 's':
3460 use_gdbstub = 1;
3461 break;
3462 case 'p':
3463 gdbstub_port = atoi(optarg);
3464 break;
3465 case 'L':
3466 interp_prefix = optarg;
3467 break;
3468 }
3469 }
3470
3471 linux_boot = (optind < argc);
3472
3473 if (!linux_boot && hd_filename[0] == '\0')
3474 help();
3475
3476 /* init debug */
3477 setvbuf(stdout, NULL, _IOLBF, 0);
3478 if (loglevel) {
3479 logfile = fopen(DEBUG_LOGFILE, "w");
3480 if (!logfile) {
3481 perror(DEBUG_LOGFILE);
3482 _exit(1);
3483 }
3484 setvbuf(logfile, NULL, _IOLBF, 0);
3485 }
3486
3487 /* init network tun interface */
3488 net_init();
3489
3490 /* init the memory */
3491 tmpdir = getenv("VLTMPDIR");
3492 if (!tmpdir)
3493 tmpdir = "/tmp";
3494 snprintf(phys_ram_file, sizeof(phys_ram_file), "%s/vlXXXXXX", tmpdir);
3495 if (mkstemp(phys_ram_file) < 0) {
3496 fprintf(stderr, "Could not create temporary memory file '%s'\n",
3497 phys_ram_file);
3498 exit(1);
3499 }
3500 phys_ram_fd = open(phys_ram_file, O_CREAT | O_TRUNC | O_RDWR, 0600);
3501 if (phys_ram_fd < 0) {
3502 fprintf(stderr, "Could not open temporary memory file '%s'\n",
3503 phys_ram_file);
3504 exit(1);
3505 }
3506 total_ram_size = phys_ram_size + vga_ram_size;
3507 ftruncate(phys_ram_fd, total_ram_size);
3508 unlink(phys_ram_file);
3509 phys_ram_base = mmap(get_mmap_addr(total_ram_size),
3510 total_ram_size,
3511 PROT_WRITE | PROT_READ, MAP_SHARED | MAP_FIXED,
3512 phys_ram_fd, 0);
3513 if (phys_ram_base == MAP_FAILED) {
3514 fprintf(stderr, "Could not map physical memory\n");
3515 exit(1);
3516 }
3517
3518 /* open the virtual block devices */
3519 for(i = 0; i < MAX_DISKS; i++) {
3520 if (hd_filename[i]) {
3521 bs_table[i] = bdrv_open(hd_filename[i], snapshot);
3522 if (!bs_table[i]) {
3523 fprintf(stderr, "vl: could not open hard disk image '%s\n",
3524 hd_filename[i]);
3525 exit(1);
3526 }
3527 }
3528 }
3529
3530 /* init CPU state */
3531 env = cpu_init();
3532 global_env = env;
3533 cpu_single_env = env;
3534
3535 init_ioports();
3536
3537 /* allocate RAM */
3538 cpu_register_physical_memory(0, phys_ram_size, 0);
3539
3540 if (linux_boot) {
3541 /* now we can load the kernel */
3542 ret = load_kernel(argv[optind], phys_ram_base + KERNEL_LOAD_ADDR);
3543 if (ret < 0) {
3544 fprintf(stderr, "vl: could not load kernel '%s'\n", argv[optind]);
3545 exit(1);
3546 }
3547
3548 /* load initrd */
3549 initrd_size = 0;
3550 if (initrd_filename) {
3551 initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
3552 if (initrd_size < 0) {
3553 fprintf(stderr, "vl: could not load initial ram disk '%s'\n",
3554 initrd_filename);
3555 exit(1);
3556 }
3557 }
3558
3559 /* init kernel params */
3560 params = (void *)(phys_ram_base + KERNEL_PARAMS_ADDR);
3561 memset(params, 0, sizeof(struct linux_params));
3562 params->mount_root_rdonly = 0;
3563 params->cl_magic = 0xA33F;
3564 params->cl_offset = params->commandline - (uint8_t *)params;
3565 params->alt_mem_k = (phys_ram_size / 1024) - 1024;
3566 for(i = optind + 1; i < argc; i++) {
3567 if (i != optind + 1)
3568 pstrcat(params->commandline, sizeof(params->commandline), " ");
3569 pstrcat(params->commandline, sizeof(params->commandline), argv[i]);
3570 }
3571 params->loader_type = 0x01;
3572 if (initrd_size > 0) {
3573 params->initrd_start = INITRD_LOAD_ADDR;
3574 params->initrd_size = initrd_size;
3575 }
3576 params->orig_video_lines = 25;
3577 params->orig_video_cols = 80;
3578
3579 /* setup basic memory access */
3580 env->cr[0] = 0x00000033;
3581 cpu_x86_init_mmu(env);
3582
3583 memset(params->idt_table, 0, sizeof(params->idt_table));
3584
3585 params->gdt_table[2] = 0x00cf9a000000ffffLL; /* KERNEL_CS */
3586 params->gdt_table[3] = 0x00cf92000000ffffLL; /* KERNEL_DS */
3587
3588 env->idt.base = (void *)params->idt_table;
3589 env->idt.limit = sizeof(params->idt_table) - 1;
3590 env->gdt.base = (void *)params->gdt_table;
3591 env->gdt.limit = sizeof(params->gdt_table) - 1;
3592
3593 cpu_x86_load_seg(env, R_CS, KERNEL_CS);
3594 cpu_x86_load_seg(env, R_DS, KERNEL_DS);
3595 cpu_x86_load_seg(env, R_ES, KERNEL_DS);
3596 cpu_x86_load_seg(env, R_SS, KERNEL_DS);
3597 cpu_x86_load_seg(env, R_FS, KERNEL_DS);
3598 cpu_x86_load_seg(env, R_GS, KERNEL_DS);
3599
3600 env->eip = KERNEL_LOAD_ADDR;
3601 env->regs[R_ESI] = KERNEL_PARAMS_ADDR;
3602 env->eflags = 0x2;
3603
3604 } else {
3605 char buf[1024];
3606
3607 /* RAW PC boot */
3608
3609 /* BIOS load */
3610 snprintf(buf, sizeof(buf), "%s/%s", interp_prefix, BIOS_FILENAME);
3611 ret = load_image(buf, phys_ram_base + 0x000f0000);
3612 if (ret != 0x10000) {
3613 fprintf(stderr, "vl: could not load PC bios '%s'\n", BIOS_FILENAME);
3614 exit(1);
3615 }
3616
3617 /* VGA BIOS load */
3618 snprintf(buf, sizeof(buf), "%s/%s", interp_prefix, VGABIOS_FILENAME);
3619 ret = load_image(buf, phys_ram_base + 0x000c0000);
3620
3621 /* setup basic memory access */
3622 env->cr[0] = 0x60000010;
3623 cpu_x86_init_mmu(env);
3624
3625 env->idt.limit = 0xffff;
3626 env->gdt.limit = 0xffff;
3627 env->ldt.limit = 0xffff;
3628
3629 /* not correct (CS base=0xffff0000) */
3630 cpu_x86_load_seg(env, R_CS, 0xf000);
3631 cpu_x86_load_seg(env, R_DS, 0);
3632 cpu_x86_load_seg(env, R_ES, 0);
3633 cpu_x86_load_seg(env, R_SS, 0);
3634 cpu_x86_load_seg(env, R_FS, 0);
3635 cpu_x86_load_seg(env, R_GS, 0);
3636
3637 env->eip = 0xfff0;
3638 env->regs[R_EDX] = 0x600; /* indicate P6 processor */
3639
3640 env->eflags = 0x2;
3641
3642 bochs_bios_init();
3643 }
3644
3645 /* terminal init */
3646 if (nodisp) {
3647 dumb_display_init(ds);
3648 } else {
3649 #ifdef CONFIG_SDL
3650 sdl_display_init(ds);
3651 /* the pthreads modify sigaction. We don't want that. */
3652 #define sigaction __sigaction
3653 #else
3654 dumb_display_init(ds);
3655 #endif
3656 }
3657 /* init basic PC hardware */
3658 register_ioport_write(0x80, 1, ioport80_write, 1);
3659
3660 vga_init(ds, phys_ram_base + phys_ram_size, phys_ram_size,
3661 vga_ram_size);
3662 cmos_init();
3663 pic_init();
3664 pit_init();
3665 serial_init();
3666 ne2000_init();
3667 ide_init();
3668 kbd_init();
3669
3670 /* setup cpu signal handlers for MMU / self modifying code handling */
3671 sigfillset(&act.sa_mask);
3672 act.sa_flags = SA_SIGINFO;
3673 act.sa_sigaction = host_segv_handler;
3674 sigaction(SIGSEGV, &act, NULL);
3675 sigaction(SIGBUS, &act, NULL);
3676
3677 act.sa_sigaction = host_alarm_handler;
3678 sigaction(SIGALRM, &act, NULL);
3679
3680 itv.it_interval.tv_sec = 0;
3681 itv.it_interval.tv_usec = 1000;
3682 itv.it_value.tv_sec = 0;
3683 itv.it_value.tv_usec = 10 * 1000;
3684 setitimer(ITIMER_REAL, &itv, NULL);
3685 /* we probe the tick duration of the kernel to inform the user if
3686 the emulated kernel requested a too high timer frequency */
3687 getitimer(ITIMER_REAL, &itv);
3688 timer_ms = itv.it_interval.tv_usec / 1000;
3689 pit_min_timer_count = ((uint64_t)itv.it_interval.tv_usec * PIT_FREQ) /
3690 1000000;
3691
3692 if (use_gdbstub) {
3693 cpu_gdbstub(NULL, main_loop, gdbstub_port);
3694 } else {
3695 main_loop(NULL);
3696 }
3697 return 0;
3698 }
Qemu copy for testing