2 * QEMU PC System Emulator
4 * Copyright (c) 2003 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
42 #include <sys/ioctl.h>
43 #include <sys/socket.h>
45 #include <linux/if_tun.h>
53 #define DEBUG_LOGFILE "/tmp/vl.log"
54 #define DEFAULT_NETWORK_SCRIPT "/etc/vl-ifup"
56 //#define DEBUG_UNUSED_IOPORT
57 //#define DEBUG_IRQ_LATENCY
59 #define PHYS_RAM_BASE 0xa8000000
60 #define KERNEL_LOAD_ADDR 0x00100000
61 #define INITRD_LOAD_ADDR 0x00400000
62 #define KERNEL_PARAMS_ADDR 0x00090000
64 /* from plex86 (BSD license) */
65 struct __attribute__ ((packed
)) linux_params
{
66 // For 0x00..0x3f, see 'struct screen_info' in linux/include/linux/tty.h.
67 // I just padded out the VESA parts, rather than define them.
69 /* 0x000 */ uint8_t orig_x
;
70 /* 0x001 */ uint8_t orig_y
;
71 /* 0x002 */ uint16_t ext_mem_k
;
72 /* 0x004 */ uint16_t orig_video_page
;
73 /* 0x006 */ uint8_t orig_video_mode
;
74 /* 0x007 */ uint8_t orig_video_cols
;
75 /* 0x008 */ uint16_t unused1
;
76 /* 0x00a */ uint16_t orig_video_ega_bx
;
77 /* 0x00c */ uint16_t unused2
;
78 /* 0x00e */ uint8_t orig_video_lines
;
79 /* 0x00f */ uint8_t orig_video_isVGA
;
80 /* 0x010 */ uint16_t orig_video_points
;
81 /* 0x012 */ uint8_t pad0
[0x20 - 0x12]; // VESA info.
82 /* 0x020 */ uint16_t cl_magic
; // Commandline magic number (0xA33F)
83 /* 0x022 */ uint16_t cl_offset
; // Commandline offset. Address of commandline
84 // is calculated as 0x90000 + cl_offset, bu
85 // only if cl_magic == 0xA33F.
86 /* 0x024 */ uint8_t pad1
[0x40 - 0x24]; // VESA info.
88 /* 0x040 */ uint8_t apm_bios_info
[20]; // struct apm_bios_info
89 /* 0x054 */ uint8_t pad2
[0x80 - 0x54];
91 // Following 2 from 'struct drive_info_struct' in drivers/block/cciss.h.
92 // Might be truncated?
93 /* 0x080 */ uint8_t hd0_info
[16]; // hd0-disk-parameter from intvector 0x41
94 /* 0x090 */ uint8_t hd1_info
[16]; // hd1-disk-parameter from intvector 0x46
96 // System description table truncated to 16 bytes
97 // From 'struct sys_desc_table_struct' in linux/arch/i386/kernel/setup.c.
98 /* 0x0a0 */ uint16_t sys_description_len
;
99 /* 0x0a2 */ uint8_t sys_description_table
[14];
101 // [1] machine submodel id
105 /* 0x0b0 */ uint8_t pad3
[0x1e0 - 0xb0];
106 /* 0x1e0 */ uint32_t alt_mem_k
;
107 /* 0x1e4 */ uint8_t pad4
[4];
108 /* 0x1e8 */ uint8_t e820map_entries
;
109 /* 0x1e9 */ uint8_t eddbuf_entries
; // EDD_NR
110 /* 0x1ea */ uint8_t pad5
[0x1f1 - 0x1ea];
111 /* 0x1f1 */ uint8_t setup_sects
; // size of setup.S, number of sectors
112 /* 0x1f2 */ uint16_t mount_root_rdonly
; // MOUNT_ROOT_RDONLY (if !=0)
113 /* 0x1f4 */ uint16_t sys_size
; // size of compressed kernel-part in the
114 // (b)zImage-file (in 16 byte units, rounded up)
115 /* 0x1f6 */ uint16_t swap_dev
; // (unused AFAIK)
116 /* 0x1f8 */ uint16_t ramdisk_flags
;
117 /* 0x1fa */ uint16_t vga_mode
; // (old one)
118 /* 0x1fc */ uint16_t orig_root_dev
; // (high=Major, low=minor)
119 /* 0x1fe */ uint8_t pad6
[1];
120 /* 0x1ff */ uint8_t aux_device_info
;
121 /* 0x200 */ uint16_t jump_setup
; // Jump to start of setup code,
122 // aka "reserved" field.
123 /* 0x202 */ uint8_t setup_signature
[4]; // Signature for SETUP-header, ="HdrS"
124 /* 0x206 */ uint16_t header_format_version
; // Version number of header format;
125 /* 0x208 */ uint8_t setup_S_temp0
[8]; // Used by setup.S for communication with
126 // boot loaders, look there.
127 /* 0x210 */ uint8_t loader_type
;
132 // T=2: bootsect-loader
136 /* 0x211 */ uint8_t loadflags
;
137 // bit0 = 1: kernel is loaded high (bzImage)
138 // bit7 = 1: Heap and pointer (see below) set by boot
140 /* 0x212 */ uint16_t setup_S_temp1
;
141 /* 0x214 */ uint32_t kernel_start
;
142 /* 0x218 */ uint32_t initrd_start
;
143 /* 0x21c */ uint32_t initrd_size
;
144 /* 0x220 */ uint8_t setup_S_temp2
[4];
145 /* 0x224 */ uint16_t setup_S_heap_end_pointer
;
146 /* 0x226 */ uint8_t pad7
[0x2d0 - 0x226];
148 /* 0x2d0 : Int 15, ax=e820 memory map. */
149 // (linux/include/asm-i386/e820.h, 'struct e820entry')
152 #define E820_RESERVED 2
153 #define E820_ACPI 3 /* usable as RAM once ACPI tables have been read */
161 /* 0x550 */ uint8_t pad8
[0x600 - 0x550];
163 // BIOS Enhanced Disk Drive Services.
164 // (From linux/include/asm-i386/edd.h, 'struct edd_info')
165 // Each 'struct edd_info is 78 bytes, times a max of 6 structs in array.
166 /* 0x600 */ uint8_t eddbuf
[0x7d4 - 0x600];
168 /* 0x7d4 */ uint8_t pad9
[0x800 - 0x7d4];
169 /* 0x800 */ uint8_t commandline
[0x800];
172 uint64_t gdt_table
[256];
173 uint64_t idt_table
[48];
176 #define KERNEL_CS 0x10
177 #define KERNEL_DS 0x18
179 typedef void (IOPortWriteFunc
)(CPUX86State
*env
, uint32_t address
, uint32_t data
);
180 typedef uint32_t (IOPortReadFunc
)(CPUX86State
*env
, uint32_t address
);
182 #define MAX_IOPORTS 4096
184 char phys_ram_file
[1024];
185 CPUX86State
*global_env
;
186 CPUX86State
*cpu_single_env
;
187 FILE *logfile
= NULL
;
189 IOPortReadFunc
*ioport_read_table
[3][MAX_IOPORTS
];
190 IOPortWriteFunc
*ioport_write_table
[3][MAX_IOPORTS
];
192 /***********************************************************/
195 uint32_t default_ioport_readb(CPUX86State
*env
, uint32_t address
)
197 #ifdef DEBUG_UNUSED_IOPORT
198 fprintf(stderr
, "inb: port=0x%04x\n", address
);
203 void default_ioport_writeb(CPUX86State
*env
, uint32_t address
, uint32_t data
)
205 #ifdef DEBUG_UNUSED_IOPORT
206 fprintf(stderr
, "outb: port=0x%04x data=0x%02x\n", address
, data
);
210 /* default is to make two byte accesses */
211 uint32_t default_ioport_readw(CPUX86State
*env
, uint32_t address
)
214 data
= ioport_read_table
[0][address
](env
, address
);
215 data
|= ioport_read_table
[0][address
+ 1](env
, address
+ 1) << 8;
219 void default_ioport_writew(CPUX86State
*env
, uint32_t address
, uint32_t data
)
221 ioport_write_table
[0][address
](env
, address
, data
& 0xff);
222 ioport_write_table
[0][address
+ 1](env
, address
+ 1, (data
>> 8) & 0xff);
225 uint32_t default_ioport_readl(CPUX86State
*env
, uint32_t address
)
227 #ifdef DEBUG_UNUSED_IOPORT
228 fprintf(stderr
, "inl: port=0x%04x\n", address
);
233 void default_ioport_writel(CPUX86State
*env
, uint32_t address
, uint32_t data
)
235 #ifdef DEBUG_UNUSED_IOPORT
236 fprintf(stderr
, "outl: port=0x%04x data=0x%02x\n", address
, data
);
240 void init_ioports(void)
244 for(i
= 0; i
< MAX_IOPORTS
; i
++) {
245 ioport_read_table
[0][i
] = default_ioport_readb
;
246 ioport_write_table
[0][i
] = default_ioport_writeb
;
247 ioport_read_table
[1][i
] = default_ioport_readw
;
248 ioport_write_table
[1][i
] = default_ioport_writew
;
249 ioport_read_table
[2][i
] = default_ioport_readl
;
250 ioport_write_table
[2][i
] = default_ioport_writel
;
254 /* size is the word size in byte */
255 int register_ioport_read(int start
, int length
, IOPortReadFunc
*func
, int size
)
267 for(i
= start
; i
< start
+ length
; i
+= size
)
268 ioport_read_table
[bsize
][i
] = func
;
272 /* size is the word size in byte */
273 int register_ioport_write(int start
, int length
, IOPortWriteFunc
*func
, int size
)
285 for(i
= start
; i
< start
+ length
; i
+= size
)
286 ioport_write_table
[bsize
][i
] = func
;
290 void pstrcpy(char *buf
, int buf_size
, const char *str
)
300 if (c
== 0 || q
>= buf
+ buf_size
- 1)
307 /* strcat and truncate. */
308 char *pstrcat(char *buf
, int buf_size
, const char *s
)
313 pstrcpy(buf
+ len
, buf_size
- len
, s
);
317 int load_kernel(const char *filename
, uint8_t *addr
)
319 int fd
, size
, setup_sects
;
320 uint8_t bootsect
[512];
322 fd
= open(filename
, O_RDONLY
);
325 if (read(fd
, bootsect
, 512) != 512)
327 setup_sects
= bootsect
[0x1F1];
330 /* skip 16 bit setup code */
331 lseek(fd
, (setup_sects
+ 1) * 512, SEEK_SET
);
332 size
= read(fd
, addr
, 16 * 1024 * 1024);
342 /* return the size or -1 if error */
343 int load_image(const char *filename
, uint8_t *addr
)
346 fd
= open(filename
, O_RDONLY
);
349 size
= lseek(fd
, 0, SEEK_END
);
350 lseek(fd
, 0, SEEK_SET
);
351 if (read(fd
, addr
, size
) != size
) {
359 void cpu_x86_outb(CPUX86State
*env
, int addr
, int val
)
361 ioport_write_table
[0][addr
& (MAX_IOPORTS
- 1)](env
, addr
, val
);
364 void cpu_x86_outw(CPUX86State
*env
, int addr
, int val
)
366 ioport_write_table
[1][addr
& (MAX_IOPORTS
- 1)](env
, addr
, val
);
369 void cpu_x86_outl(CPUX86State
*env
, int addr
, int val
)
371 ioport_write_table
[2][addr
& (MAX_IOPORTS
- 1)](env
, addr
, val
);
374 int cpu_x86_inb(CPUX86State
*env
, int addr
)
376 return ioport_read_table
[0][addr
& (MAX_IOPORTS
- 1)](env
, addr
);
379 int cpu_x86_inw(CPUX86State
*env
, int addr
)
381 return ioport_read_table
[1][addr
& (MAX_IOPORTS
- 1)](env
, addr
);
384 int cpu_x86_inl(CPUX86State
*env
, int addr
)
386 return ioport_read_table
[2][addr
& (MAX_IOPORTS
- 1)](env
, addr
);
389 /***********************************************************/
390 void ioport80_write(CPUX86State
*env
, uint32_t addr
, uint32_t data
)
394 void hw_error(const char *fmt
, ...)
399 fprintf(stderr
, "qemu: hardware error: ");
400 vfprintf(stderr
, fmt
, ap
);
401 fprintf(stderr
, "\n");
403 cpu_x86_dump_state(global_env
, stderr
, X86_DUMP_FPU
| X86_DUMP_CCOP
);
409 /***********************************************************/
411 static uint8_t vga_index
;
412 static uint8_t vga_regs
[256];
413 static int last_cursor_pos
;
415 void update_console_messages(void)
417 int c
, i
, cursor_pos
, eol
;
419 cursor_pos
= vga_regs
[0x0f] | (vga_regs
[0x0e] << 8);
421 for(i
= last_cursor_pos
; i
< cursor_pos
; i
++) {
422 c
= phys_ram_base
[0xb8000 + (i
) * 2];
433 last_cursor_pos
= cursor_pos
;
436 /* just to see first Linux console messages, we intercept cursor position */
437 void vga_ioport_write(CPUX86State
*env
, uint32_t addr
, uint32_t data
)
444 vga_regs
[vga_index
] = data
;
445 if (vga_index
== 0x0f)
446 update_console_messages();
452 /***********************************************************/
455 #define RTC_SECONDS 0
456 #define RTC_SECONDS_ALARM 1
457 #define RTC_MINUTES 2
458 #define RTC_MINUTES_ALARM 3
460 #define RTC_HOURS_ALARM 5
461 #define RTC_ALARM_DONT_CARE 0xC0
463 #define RTC_DAY_OF_WEEK 6
464 #define RTC_DAY_OF_MONTH 7
473 /* PC cmos mappings */
474 #define REG_EQUIPMENT_BYTE 0x14
476 uint8_t cmos_data
[128];
479 void cmos_ioport_write(CPUX86State
*env
, uint32_t addr
, uint32_t data
)
482 cmos_index
= data
& 0x7f;
486 uint32_t cmos_ioport_read(CPUX86State
*env
, uint32_t addr
)
493 /* toggle update-in-progress bit for Linux (same hack as
495 ret
= cmos_data
[cmos_index
];
496 if (cmos_index
== RTC_REG_A
)
497 cmos_data
[RTC_REG_A
] ^= 0x80;
498 else if (cmos_index
== RTC_REG_C
)
499 cmos_data
[RTC_REG_C
] = 0x00;
505 static inline int to_bcd(int a
)
507 return ((a
/ 10) << 4) | (a
% 10);
517 cmos_data
[RTC_SECONDS
] = to_bcd(tm
->tm_sec
);
518 cmos_data
[RTC_MINUTES
] = to_bcd(tm
->tm_min
);
519 cmos_data
[RTC_HOURS
] = to_bcd(tm
->tm_hour
);
520 cmos_data
[RTC_DAY_OF_WEEK
] = to_bcd(tm
->tm_wday
);
521 cmos_data
[RTC_DAY_OF_MONTH
] = to_bcd(tm
->tm_mday
);
522 cmos_data
[RTC_MONTH
] = to_bcd(tm
->tm_mon
);
523 cmos_data
[RTC_YEAR
] = to_bcd(tm
->tm_year
% 100);
525 cmos_data
[RTC_REG_A
] = 0x26;
526 cmos_data
[RTC_REG_B
] = 0x02;
527 cmos_data
[RTC_REG_C
] = 0x00;
528 cmos_data
[RTC_REG_D
] = 0x80;
530 cmos_data
[REG_EQUIPMENT_BYTE
] = 0x02; /* FPU is there */
532 register_ioport_write(0x70, 2, cmos_ioport_write
, 1);
533 register_ioport_read(0x70, 2, cmos_ioport_read
, 1);
536 /***********************************************************/
537 /* 8259 pic emulation */
541 typedef struct PicState
{
542 uint8_t last_irr
; /* edge detection */
543 uint8_t irr
; /* interrupt request register */
544 uint8_t imr
; /* interrupt mask register */
545 uint8_t isr
; /* interrupt service register */
546 uint8_t priority_add
; /* used to compute irq priority */
548 uint8_t read_reg_select
;
549 uint8_t special_mask
;
552 uint8_t rotate_on_autoeoi
;
553 uint8_t init4
; /* true if 4 byte init */
556 /* 0 is master pic, 1 is slave pic */
558 int pic_irq_requested
;
560 /* set irq level. If an edge is detected, then the IRR is set to 1 */
561 static inline void pic_set_irq1(PicState
*s
, int irq
, int level
)
566 if ((s
->last_irr
& mask
) == 0)
570 s
->last_irr
&= ~mask
;
574 static inline int get_priority(PicState
*s
, int mask
)
580 while ((mask
& (1 << ((priority
+ s
->priority_add
) & 7))) == 0)
585 /* return the pic wanted interrupt. return -1 if none */
586 static int pic_get_irq(PicState
*s
)
588 int mask
, cur_priority
, priority
;
590 mask
= s
->irr
& ~s
->imr
;
591 priority
= get_priority(s
, mask
);
594 /* compute current priority */
595 cur_priority
= get_priority(s
, s
->isr
);
596 if (priority
> cur_priority
) {
597 /* higher priority found: an irq should be generated */
604 /* raise irq to CPU if necessary. must be called every time the active
606 static void pic_update_irq(void)
610 /* first look at slave pic */
611 irq2
= pic_get_irq(&pics
[1]);
613 /* if irq request by slave pic, signal master PIC */
614 pic_set_irq1(&pics
[0], 2, 1);
615 pic_set_irq1(&pics
[0], 2, 0);
617 /* look at requested irq */
618 irq
= pic_get_irq(&pics
[0]);
622 pic_irq_requested
= 8 + irq2
;
624 /* from master pic */
625 pic_irq_requested
= irq
;
627 cpu_x86_interrupt(global_env
, CPU_INTERRUPT_HARD
);
631 #ifdef DEBUG_IRQ_LATENCY
632 int64_t irq_time
[16];
633 int64_t cpu_get_ticks(void);
639 void pic_set_irq(int irq
, int level
)
642 if (level
!= irq_level
[irq
]) {
643 printf("pic_set_irq: irq=%d level=%d\n", irq
, level
);
644 irq_level
[irq
] = level
;
647 #ifdef DEBUG_IRQ_LATENCY
649 irq_time
[irq
] = cpu_get_ticks();
652 pic_set_irq1(&pics
[irq
>> 3], irq
& 7, level
);
656 int cpu_x86_get_pic_interrupt(CPUX86State
*env
)
658 int irq
, irq2
, intno
;
660 /* signal the pic that the irq was acked by the CPU */
661 irq
= pic_irq_requested
;
662 #ifdef DEBUG_IRQ_LATENCY
663 printf("IRQ%d latency=%Ld\n", irq
, cpu_get_ticks() - irq_time
[irq
]);
666 printf("pic_interrupt: irq=%d\n", irq
);
671 pics
[1].isr
|= (1 << irq2
);
672 pics
[1].irr
&= ~(1 << irq2
);
674 intno
= pics
[1].irq_base
+ irq2
;
676 intno
= pics
[0].irq_base
+ irq
;
678 pics
[0].isr
|= (1 << irq
);
679 pics
[0].irr
&= ~(1 << irq
);
683 void pic_ioport_write(CPUX86State
*env
, uint32_t addr
, uint32_t val
)
689 printf("pic_write: addr=0x%02x val=0x%02x\n", addr
, val
);
691 s
= &pics
[addr
>> 7];
696 memset(s
, 0, sizeof(PicState
));
700 hw_error("single mode not supported");
702 hw_error("level sensitive irq not supported");
703 } else if (val
& 0x08) {
705 s
->read_reg_select
= val
& 1;
707 s
->special_mask
= (val
>> 5) & 1;
712 s
->rotate_on_autoeoi
= val
>> 7;
714 case 0x20: /* end of interrupt */
716 priority
= get_priority(s
, s
->isr
);
718 s
->isr
&= ~(1 << ((priority
+ s
->priority_add
) & 7));
721 s
->priority_add
= (s
->priority_add
+ 1) & 7;
725 s
->isr
&= ~(1 << priority
);
728 s
->priority_add
= (val
+ 1) & 7;
732 s
->isr
&= ~(1 << priority
);
733 s
->priority_add
= (priority
+ 1) & 7;
738 switch(s
->init_state
) {
745 s
->irq_base
= val
& 0xf8;
756 s
->auto_eoi
= (val
>> 1) & 1;
763 uint32_t pic_ioport_read(CPUX86State
*env
, uint32_t addr1
)
770 s
= &pics
[addr
>> 7];
773 if (s
->read_reg_select
)
781 printf("pic_read: addr=0x%02x val=0x%02x\n", addr1
, ret
);
788 register_ioport_write(0x20, 2, pic_ioport_write
, 1);
789 register_ioport_read(0x20, 2, pic_ioport_read
, 1);
790 register_ioport_write(0xa0, 2, pic_ioport_write
, 1);
791 register_ioport_read(0xa0, 2, pic_ioport_read
, 1);
794 /***********************************************************/
795 /* 8253 PIT emulation */
797 #define PIT_FREQ 1193182
799 #define RW_STATE_LSB 0
800 #define RW_STATE_MSB 1
801 #define RW_STATE_WORD0 2
802 #define RW_STATE_WORD1 3
803 #define RW_STATE_LATCHED_WORD0 4
804 #define RW_STATE_LATCHED_WORD1 5
806 typedef struct PITChannelState
{
807 int count
; /* can be 65536 */
808 uint16_t latched_count
;
811 uint8_t bcd
; /* not supported */
812 uint8_t gate
; /* timer start */
813 int64_t count_load_time
;
814 int64_t count_last_edge_check_time
;
817 PITChannelState pit_channels
[3];
819 int pit_min_timer_count
= 0;
821 int64_t ticks_per_sec
;
823 int64_t get_clock(void)
826 gettimeofday(&tv
, NULL
);
827 return tv
.tv_sec
* 1000000LL + tv
.tv_usec
;
830 int64_t cpu_get_ticks(void)
833 asm("rdtsc" : "=A" (val
));
837 void cpu_calibrate_ticks(void)
842 ticks
= cpu_get_ticks();
844 usec
= get_clock() - usec
;
845 ticks
= cpu_get_ticks() - ticks
;
846 ticks_per_sec
= (ticks
* 1000000LL + (usec
>> 1)) / usec
;
849 /* compute with 96 bit intermediate result: (a*b)/c */
850 static uint64_t muldiv64(uint64_t a
, uint32_t b
, uint32_t c
)
855 #ifdef WORDS_BIGENDIAN
865 rl
= (uint64_t)u
.l
.low
* (uint64_t)b
;
866 rh
= (uint64_t)u
.l
.high
* (uint64_t)b
;
869 res
.l
.low
= (((rh
% c
) << 32) + (rl
& 0xffffffff)) / c
;
873 static int pit_get_count(PITChannelState
*s
)
878 d
= muldiv64(cpu_get_ticks() - s
->count_load_time
, PIT_FREQ
, ticks_per_sec
);
884 counter
= (s
->count
- d
) & 0xffff;
887 counter
= s
->count
- (d
% s
->count
);
893 /* get pit output bit */
894 static int pit_get_out(PITChannelState
*s
)
899 d
= muldiv64(cpu_get_ticks() - s
->count_load_time
, PIT_FREQ
, ticks_per_sec
);
903 out
= (d
>= s
->count
);
906 out
= (d
< s
->count
);
909 if ((d
% s
->count
) == 0 && d
!= 0)
915 out
= (d
% s
->count
) < (s
->count
>> 1);
919 out
= (d
== s
->count
);
925 /* get the number of 0 to 1 transitions we had since we call this
927 /* XXX: maybe better to use ticks precision to avoid getting edges
928 twice if checks are done at very small intervals */
929 static int pit_get_out_edges(PITChannelState
*s
)
935 ticks
= cpu_get_ticks();
936 d1
= muldiv64(s
->count_last_edge_check_time
- s
->count_load_time
,
937 PIT_FREQ
, ticks_per_sec
);
938 d2
= muldiv64(ticks
- s
->count_load_time
,
939 PIT_FREQ
, ticks_per_sec
);
940 s
->count_last_edge_check_time
= ticks
;
944 if (d1
< s
->count
&& d2
>= s
->count
)
958 v
= s
->count
- (s
->count
>> 1);
959 d1
= (d1
+ v
) / s
->count
;
960 d2
= (d2
+ v
) / s
->count
;
965 if (d1
< s
->count
&& d2
>= s
->count
)
974 static inline void pit_load_count(PITChannelState
*s
, int val
)
978 s
->count_load_time
= cpu_get_ticks();
979 s
->count_last_edge_check_time
= s
->count_load_time
;
981 if (s
== &pit_channels
[0] && val
<= pit_min_timer_count
) {
983 "\nWARNING: vl: on your system, accurate timer emulation is impossible if its frequency is more than %d Hz. If using a 2.5.xx Linux kernel, you must patch asm/param.h to change HZ from 1000 to 100.\n\n",
984 PIT_FREQ
/ pit_min_timer_count
);
988 void pit_ioport_write(CPUX86State
*env
, uint32_t addr
, uint32_t val
)
998 s
= &pit_channels
[channel
];
999 access
= (val
>> 4) & 3;
1002 s
->latched_count
= pit_get_count(s
);
1003 s
->rw_state
= RW_STATE_LATCHED_WORD0
;
1006 s
->mode
= (val
>> 1) & 7;
1008 s
->rw_state
= access
- 1 + RW_STATE_LSB
;
1012 s
= &pit_channels
[addr
];
1013 switch(s
->rw_state
) {
1015 pit_load_count(s
, val
);
1018 pit_load_count(s
, val
<< 8);
1020 case RW_STATE_WORD0
:
1021 case RW_STATE_WORD1
:
1022 if (s
->rw_state
& 1) {
1023 pit_load_count(s
, (s
->latched_count
& 0xff) | (val
<< 8));
1025 s
->latched_count
= val
;
1033 uint32_t pit_ioport_read(CPUX86State
*env
, uint32_t addr
)
1039 s
= &pit_channels
[addr
];
1040 switch(s
->rw_state
) {
1043 case RW_STATE_WORD0
:
1044 case RW_STATE_WORD1
:
1045 count
= pit_get_count(s
);
1046 if (s
->rw_state
& 1)
1047 ret
= (count
>> 8) & 0xff;
1050 if (s
->rw_state
& 2)
1054 case RW_STATE_LATCHED_WORD0
:
1055 case RW_STATE_LATCHED_WORD1
:
1056 if (s
->rw_state
& 1)
1057 ret
= s
->latched_count
>> 8;
1059 ret
= s
->latched_count
& 0xff;
1066 void speaker_ioport_write(CPUX86State
*env
, uint32_t addr
, uint32_t val
)
1068 speaker_data_on
= (val
>> 1) & 1;
1069 pit_channels
[2].gate
= val
& 1;
1072 uint32_t speaker_ioport_read(CPUX86State
*env
, uint32_t addr
)
1075 out
= pit_get_out(&pit_channels
[2]);
1076 return (speaker_data_on
<< 1) | pit_channels
[2].gate
| (out
<< 5);
1084 cpu_calibrate_ticks();
1086 for(i
= 0;i
< 3; i
++) {
1087 s
= &pit_channels
[i
];
1090 pit_load_count(s
, 0);
1093 register_ioport_write(0x40, 4, pit_ioport_write
, 1);
1094 register_ioport_read(0x40, 3, pit_ioport_read
, 1);
1096 register_ioport_read(0x61, 1, speaker_ioport_read
, 1);
1097 register_ioport_write(0x61, 1, speaker_ioport_write
, 1);
1100 /***********************************************************/
1101 /* serial port emulation */
1105 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
1107 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
1108 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
1109 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
1110 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
1112 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
1113 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
1115 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
1116 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
1117 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
1118 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
1120 #define UART_LSR_TEMT 0x40 /* Transmitter empty */
1121 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
1122 #define UART_LSR_BI 0x10 /* Break interrupt indicator */
1123 #define UART_LSR_FE 0x08 /* Frame error indicator */
1124 #define UART_LSR_PE 0x04 /* Parity error indicator */
1125 #define UART_LSR_OE 0x02 /* Overrun error indicator */
1126 #define UART_LSR_DR 0x01 /* Receiver data ready */
1128 typedef struct SerialState
{
1130 uint8_t rbr
; /* receive register */
1132 uint8_t iir
; /* read only */
1135 uint8_t lsr
; /* read only */
1140 SerialState serial_ports
[1];
1142 void serial_update_irq(void)
1144 SerialState
*s
= &serial_ports
[0];
1146 if ((s
->lsr
& UART_LSR_DR
) && (s
->ier
& UART_IER_RDI
)) {
1147 s
->iir
= UART_IIR_RDI
;
1148 } else if ((s
->lsr
& UART_LSR_THRE
) && (s
->ier
& UART_IER_THRI
)) {
1149 s
->iir
= UART_IIR_THRI
;
1151 s
->iir
= UART_IIR_NO_INT
;
1153 if (s
->iir
!= UART_IIR_NO_INT
) {
1154 pic_set_irq(UART_IRQ
, 1);
1156 pic_set_irq(UART_IRQ
, 0);
1160 void serial_ioport_write(CPUX86State
*env
, uint32_t addr
, uint32_t val
)
1162 SerialState
*s
= &serial_ports
[0];
1170 if (s
->lcr
& UART_LCR_DLAB
) {
1171 s
->divider
= (s
->divider
& 0xff00) | val
;
1173 s
->lsr
&= ~UART_LSR_THRE
;
1174 serial_update_irq();
1178 ret
= write(1, &ch
, 1);
1180 s
->lsr
|= UART_LSR_THRE
;
1181 s
->lsr
|= UART_LSR_TEMT
;
1182 serial_update_irq();
1186 if (s
->lcr
& UART_LCR_DLAB
) {
1187 s
->divider
= (s
->divider
& 0x00ff) | (val
<< 8);
1190 serial_update_irq();
1212 uint32_t serial_ioport_read(CPUX86State
*env
, uint32_t addr
)
1214 SerialState
*s
= &serial_ports
[0];
1221 if (s
->lcr
& UART_LCR_DLAB
) {
1222 ret
= s
->divider
& 0xff;
1225 s
->lsr
&= ~(UART_LSR_DR
| UART_LSR_BI
);
1226 serial_update_irq();
1230 if (s
->lcr
& UART_LCR_DLAB
) {
1231 ret
= (s
->divider
>> 8) & 0xff;
1258 #define TERM_ESCAPE 0x01 /* ctrl-a is used for escape */
1259 static int term_got_escape
;
1261 void term_print_help(void)
1264 "C-a h print this help\n"
1265 "C-a x exit emulatior\n"
1266 "C-a b send break (magic sysrq)\n"
1267 "C-a C-a send C-a\n"
1271 /* called when a char is received */
1272 void serial_received_byte(SerialState
*s
, int ch
)
1274 if (term_got_escape
) {
1275 term_got_escape
= 0;
1286 s
->lsr
|= UART_LSR_BI
| UART_LSR_DR
;
1287 serial_update_irq();
1292 } else if (ch
== TERM_ESCAPE
) {
1293 term_got_escape
= 1;
1297 s
->lsr
|= UART_LSR_DR
;
1298 serial_update_irq();
1302 /* init terminal so that we can grab keys */
1303 static struct termios oldtty
;
1305 static void term_exit(void)
1307 tcsetattr (0, TCSANOW
, &oldtty
);
1310 static void term_init(void)
1314 tcgetattr (0, &tty
);
1317 tty
.c_iflag
&= ~(IGNBRK
|BRKINT
|PARMRK
|ISTRIP
1318 |INLCR
|IGNCR
|ICRNL
|IXON
);
1319 tty
.c_oflag
|= OPOST
;
1320 tty
.c_lflag
&= ~(ECHO
|ECHONL
|ICANON
|IEXTEN
|ISIG
);
1321 tty
.c_cflag
&= ~(CSIZE
|PARENB
);
1324 tty
.c_cc
[VTIME
] = 0;
1326 tcsetattr (0, TCSANOW
, &tty
);
1330 fcntl(0, F_SETFL
, O_NONBLOCK
);
1333 void serial_init(void)
1335 SerialState
*s
= &serial_ports
[0];
1337 s
->lsr
= UART_LSR_TEMT
| UART_LSR_THRE
;
1339 register_ioport_write(0x3f8, 8, serial_ioport_write
, 1);
1340 register_ioport_read(0x3f8, 8, serial_ioport_read
, 1);
1345 /***********************************************************/
1346 /* ne2000 emulation */
1348 //#define DEBUG_NE2000
1350 #define NE2000_IOPORT 0x300
1351 #define NE2000_IRQ 9
1353 #define MAX_ETH_FRAME_SIZE 1514
1355 #define E8390_CMD 0x00 /* The command register (for all pages) */
1356 /* Page 0 register offsets. */
1357 #define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */
1358 #define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */
1359 #define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */
1360 #define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */
1361 #define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */
1362 #define EN0_TSR 0x04 /* Transmit status reg RD */
1363 #define EN0_TPSR 0x04 /* Transmit starting page WR */
1364 #define EN0_NCR 0x05 /* Number of collision reg RD */
1365 #define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */
1366 #define EN0_FIFO 0x06 /* FIFO RD */
1367 #define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */
1368 #define EN0_ISR 0x07 /* Interrupt status reg RD WR */
1369 #define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */
1370 #define EN0_RSARLO 0x08 /* Remote start address reg 0 */
1371 #define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */
1372 #define EN0_RSARHI 0x09 /* Remote start address reg 1 */
1373 #define EN0_RCNTLO 0x0a /* Remote byte count reg WR */
1374 #define EN0_RCNTHI 0x0b /* Remote byte count reg WR */
1375 #define EN0_RSR 0x0c /* rx status reg RD */
1376 #define EN0_RXCR 0x0c /* RX configuration reg WR */
1377 #define EN0_TXCR 0x0d /* TX configuration reg WR */
1378 #define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */
1379 #define EN0_DCFG 0x0e /* Data configuration reg WR */
1380 #define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */
1381 #define EN0_IMR 0x0f /* Interrupt mask reg WR */
1382 #define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */
1384 #define EN1_PHYS 0x11
1385 #define EN1_CURPAG 0x17
1386 #define EN1_MULT 0x18
1388 /* Register accessed at EN_CMD, the 8390 base addr. */
1389 #define E8390_STOP 0x01 /* Stop and reset the chip */
1390 #define E8390_START 0x02 /* Start the chip, clear reset */
1391 #define E8390_TRANS 0x04 /* Transmit a frame */
1392 #define E8390_RREAD 0x08 /* Remote read */
1393 #define E8390_RWRITE 0x10 /* Remote write */
1394 #define E8390_NODMA 0x20 /* Remote DMA */
1395 #define E8390_PAGE0 0x00 /* Select page chip registers */
1396 #define E8390_PAGE1 0x40 /* using the two high-order bits */
1397 #define E8390_PAGE2 0x80 /* Page 3 is invalid. */
1399 /* Bits in EN0_ISR - Interrupt status register */
1400 #define ENISR_RX 0x01 /* Receiver, no error */
1401 #define ENISR_TX 0x02 /* Transmitter, no error */
1402 #define ENISR_RX_ERR 0x04 /* Receiver, with error */
1403 #define ENISR_TX_ERR 0x08 /* Transmitter, with error */
1404 #define ENISR_OVER 0x10 /* Receiver overwrote the ring */
1405 #define ENISR_COUNTERS 0x20 /* Counters need emptying */
1406 #define ENISR_RDC 0x40 /* remote dma complete */
1407 #define ENISR_RESET 0x80 /* Reset completed */
1408 #define ENISR_ALL 0x3f /* Interrupts we will enable */
1410 /* Bits in received packet status byte and EN0_RSR*/
1411 #define ENRSR_RXOK 0x01 /* Received a good packet */
1412 #define ENRSR_CRC 0x02 /* CRC error */
1413 #define ENRSR_FAE 0x04 /* frame alignment error */
1414 #define ENRSR_FO 0x08 /* FIFO overrun */
1415 #define ENRSR_MPA 0x10 /* missed pkt */
1416 #define ENRSR_PHY 0x20 /* physical/multicast address */
1417 #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
1418 #define ENRSR_DEF 0x80 /* deferring */
1420 /* Transmitted packet status, EN0_TSR. */
1421 #define ENTSR_PTX 0x01 /* Packet transmitted without error */
1422 #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
1423 #define ENTSR_COL 0x04 /* The transmit collided at least once. */
1424 #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */
1425 #define ENTSR_CRS 0x10 /* The carrier sense was lost. */
1426 #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */
1427 #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
1428 #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */
1430 #define NE2000_MEM_SIZE 32768
1432 typedef struct NE2000State
{
1445 uint8_t phys
[6]; /* mac address */
1447 uint8_t mult
[8]; /* multicast mask array */
1448 uint8_t mem
[NE2000_MEM_SIZE
];
1451 NE2000State ne2000_state
;
1453 char network_script
[1024];
1455 void ne2000_reset(void)
1457 NE2000State
*s
= &ne2000_state
;
1460 s
->isr
= ENISR_RESET
;
1470 /* duplicate prom data */
1471 for(i
= 15;i
>= 0; i
--) {
1472 s
->mem
[2 * i
] = s
->mem
[i
];
1473 s
->mem
[2 * i
+ 1] = s
->mem
[i
];
1477 void ne2000_update_irq(NE2000State
*s
)
1480 isr
= s
->isr
& s
->imr
;
1482 pic_set_irq(NE2000_IRQ
, 1);
1484 pic_set_irq(NE2000_IRQ
, 0);
1490 int fd
, ret
, pid
, status
;
1492 fd
= open("/dev/net/tun", O_RDWR
);
1494 fprintf(stderr
, "warning: could not open /dev/net/tun: no virtual network emulation\n");
1497 memset(&ifr
, 0, sizeof(ifr
));
1498 ifr
.ifr_flags
= IFF_TAP
| IFF_NO_PI
;
1499 pstrcpy(ifr
.ifr_name
, IFNAMSIZ
, "tun%d");
1500 ret
= ioctl(fd
, TUNSETIFF
, (void *) &ifr
);
1502 fprintf(stderr
, "warning: could not configure /dev/net/tun: no virtual network emulation\n");
1506 printf("Connected to host network interface: %s\n", ifr
.ifr_name
);
1507 fcntl(fd
, F_SETFL
, O_NONBLOCK
);
1510 /* try to launch network init script */
1514 execl(network_script
, network_script
, ifr
.ifr_name
, NULL
);
1517 while (waitpid(pid
, &status
, 0) != pid
);
1518 if (!WIFEXITED(status
) ||
1519 WEXITSTATUS(status
) != 0) {
1520 fprintf(stderr
, "%s: could not launch network script for '%s'\n",
1521 network_script
, ifr
.ifr_name
);
1527 void net_send_packet(NE2000State
*s
, const uint8_t *buf
, int size
)
1530 printf("NE2000: sending packet size=%d\n", size
);
1532 write(net_fd
, buf
, size
);
1535 /* return true if the NE2000 can receive more data */
1536 int ne2000_can_receive(NE2000State
*s
)
1538 int avail
, index
, boundary
;
1540 if (s
->cmd
& E8390_STOP
)
1542 index
= s
->curpag
<< 8;
1543 boundary
= s
->boundary
<< 8;
1544 if (index
< boundary
)
1545 avail
= boundary
- index
;
1547 avail
= (s
->stop
- s
->start
) - (index
- boundary
);
1548 if (avail
< (MAX_ETH_FRAME_SIZE
+ 4))
1553 void ne2000_receive(NE2000State
*s
, uint8_t *buf
, int size
)
1556 int total_len
, next
, avail
, len
, index
;
1558 #if defined(DEBUG_NE2000)
1559 printf("NE2000: received len=%d\n", size
);
1562 index
= s
->curpag
<< 8;
1563 /* 4 bytes for header */
1564 total_len
= size
+ 4;
1565 /* address for next packet (4 bytes for CRC) */
1566 next
= index
+ ((total_len
+ 4 + 255) & ~0xff);
1567 if (next
>= s
->stop
)
1568 next
-= (s
->stop
- s
->start
);
1569 /* prepare packet header */
1571 p
[0] = ENRSR_RXOK
; /* receive status */
1574 p
[3] = total_len
>> 8;
1577 /* write packet data */
1579 avail
= s
->stop
- index
;
1583 memcpy(s
->mem
+ index
, buf
, len
);
1586 if (index
== s
->stop
)
1590 s
->curpag
= next
>> 8;
1592 /* now we can signal we have receive something */
1594 ne2000_update_irq(s
);
1597 void ne2000_ioport_write(CPUX86State
*env
, uint32_t addr
, uint32_t val
)
1599 NE2000State
*s
= &ne2000_state
;
1604 printf("NE2000: write addr=0x%x val=0x%02x\n", addr
, val
);
1606 if (addr
== E8390_CMD
) {
1607 /* control register */
1609 if (val
& E8390_START
) {
1610 /* test specific case: zero length transfert */
1611 if ((val
& (E8390_RREAD
| E8390_RWRITE
)) &&
1613 s
->isr
|= ENISR_RDC
;
1614 ne2000_update_irq(s
);
1616 if (val
& E8390_TRANS
) {
1617 net_send_packet(s
, s
->mem
+ (s
->tpsr
<< 8), s
->tcnt
);
1618 /* signal end of transfert */
1621 ne2000_update_irq(s
);
1626 offset
= addr
| (page
<< 4);
1629 s
->start
= val
<< 8;
1639 ne2000_update_irq(s
);
1645 s
->tcnt
= (s
->tcnt
& 0xff00) | val
;
1648 s
->tcnt
= (s
->tcnt
& 0x00ff) | (val
<< 8);
1651 s
->rsar
= (s
->rsar
& 0xff00) | val
;
1654 s
->rsar
= (s
->rsar
& 0x00ff) | (val
<< 8);
1657 s
->rcnt
= (s
->rcnt
& 0xff00) | val
;
1660 s
->rcnt
= (s
->rcnt
& 0x00ff) | (val
<< 8);
1667 ne2000_update_irq(s
);
1669 case EN1_PHYS
... EN1_PHYS
+ 5:
1670 s
->phys
[offset
- EN1_PHYS
] = val
;
1675 case EN1_MULT
... EN1_MULT
+ 7:
1676 s
->mult
[offset
- EN1_MULT
] = val
;
1682 uint32_t ne2000_ioport_read(CPUX86State
*env
, uint32_t addr
)
1684 NE2000State
*s
= &ne2000_state
;
1685 int offset
, page
, ret
;
1688 if (addr
== E8390_CMD
) {
1692 offset
= addr
| (page
<< 4);
1703 case EN1_PHYS
... EN1_PHYS
+ 5:
1704 ret
= s
->phys
[offset
- EN1_PHYS
];
1709 case EN1_MULT
... EN1_MULT
+ 7:
1710 ret
= s
->mult
[offset
- EN1_MULT
];
1718 printf("NE2000: read addr=0x%x val=%02x\n", addr
, ret
);
1723 void ne2000_asic_ioport_write(CPUX86State
*env
, uint32_t addr
, uint32_t val
)
1725 NE2000State
*s
= &ne2000_state
;
1729 printf("NE2000: asic write val=0x%04x\n", val
);
1731 p
= s
->mem
+ s
->rsar
;
1732 if (s
->dcfg
& 0x01) {
1745 if (s
->rsar
== s
->stop
)
1748 /* signal end of transfert */
1749 s
->isr
|= ENISR_RDC
;
1750 ne2000_update_irq(s
);
1754 uint32_t ne2000_asic_ioport_read(CPUX86State
*env
, uint32_t addr
)
1756 NE2000State
*s
= &ne2000_state
;
1760 p
= s
->mem
+ s
->rsar
;
1761 if (s
->dcfg
& 0x01) {
1763 ret
= p
[0] | (p
[1] << 8);
1773 if (s
->rsar
== s
->stop
)
1776 /* signal end of transfert */
1777 s
->isr
|= ENISR_RDC
;
1778 ne2000_update_irq(s
);
1781 printf("NE2000: asic read val=0x%04x\n", ret
);
1786 void ne2000_reset_ioport_write(CPUX86State
*env
, uint32_t addr
, uint32_t val
)
1788 /* nothing to do (end of reset pulse) */
1791 uint32_t ne2000_reset_ioport_read(CPUX86State
*env
, uint32_t addr
)
1797 void ne2000_init(void)
1799 register_ioport_write(NE2000_IOPORT
, 16, ne2000_ioport_write
, 1);
1800 register_ioport_read(NE2000_IOPORT
, 16, ne2000_ioport_read
, 1);
1802 register_ioport_write(NE2000_IOPORT
+ 0x10, 1, ne2000_asic_ioport_write
, 1);
1803 register_ioport_read(NE2000_IOPORT
+ 0x10, 1, ne2000_asic_ioport_read
, 1);
1804 register_ioport_write(NE2000_IOPORT
+ 0x10, 2, ne2000_asic_ioport_write
, 2);
1805 register_ioport_read(NE2000_IOPORT
+ 0x10, 2, ne2000_asic_ioport_read
, 2);
1807 register_ioport_write(NE2000_IOPORT
+ 0x1f, 1, ne2000_reset_ioport_write
, 1);
1808 register_ioport_read(NE2000_IOPORT
+ 0x1f, 1, ne2000_reset_ioport_read
, 1);
1812 /***********************************************************/
1817 /* Bits of HD_STATUS */
1818 #define ERR_STAT 0x01
1819 #define INDEX_STAT 0x02
1820 #define ECC_STAT 0x04 /* Corrected error */
1821 #define DRQ_STAT 0x08
1822 #define SEEK_STAT 0x10
1823 #define SRV_STAT 0x10
1824 #define WRERR_STAT 0x20
1825 #define READY_STAT 0x40
1826 #define BUSY_STAT 0x80
1828 /* Bits for HD_ERROR */
1829 #define MARK_ERR 0x01 /* Bad address mark */
1830 #define TRK0_ERR 0x02 /* couldn't find track 0 */
1831 #define ABRT_ERR 0x04 /* Command aborted */
1832 #define MCR_ERR 0x08 /* media change request */
1833 #define ID_ERR 0x10 /* ID field not found */
1834 #define MC_ERR 0x20 /* media changed */
1835 #define ECC_ERR 0x40 /* Uncorrectable ECC error */
1836 #define BBD_ERR 0x80 /* pre-EIDE meaning: block marked bad */
1837 #define ICRC_ERR 0x80 /* new meaning: CRC error during transfer */
1839 /* Bits of HD_NSECTOR */
1843 #define TAG_MASK 0xf8
1845 #define IDE_CMD_RESET 0x04
1846 #define IDE_CMD_DISABLE_IRQ 0x02
1848 /* ATA/ATAPI Commands pre T13 Spec */
1849 #define WIN_NOP 0x00
1851 * 0x01->0x02 Reserved
1853 #define CFA_REQ_EXT_ERROR_CODE 0x03 /* CFA Request Extended Error Code */
1855 * 0x04->0x07 Reserved
1857 #define WIN_SRST 0x08 /* ATAPI soft reset command */
1858 #define WIN_DEVICE_RESET 0x08
1860 * 0x09->0x0F Reserved
1862 #define WIN_RECAL 0x10
1863 #define WIN_RESTORE WIN_RECAL
1865 * 0x10->0x1F Reserved
1867 #define WIN_READ 0x20 /* 28-Bit */
1868 #define WIN_READ_ONCE 0x21 /* 28-Bit without retries */
1869 #define WIN_READ_LONG 0x22 /* 28-Bit */
1870 #define WIN_READ_LONG_ONCE 0x23 /* 28-Bit without retries */
1871 #define WIN_READ_EXT 0x24 /* 48-Bit */
1872 #define WIN_READDMA_EXT 0x25 /* 48-Bit */
1873 #define WIN_READDMA_QUEUED_EXT 0x26 /* 48-Bit */
1874 #define WIN_READ_NATIVE_MAX_EXT 0x27 /* 48-Bit */
1878 #define WIN_MULTREAD_EXT 0x29 /* 48-Bit */
1880 * 0x2A->0x2F Reserved
1882 #define WIN_WRITE 0x30 /* 28-Bit */
1883 #define WIN_WRITE_ONCE 0x31 /* 28-Bit without retries */
1884 #define WIN_WRITE_LONG 0x32 /* 28-Bit */
1885 #define WIN_WRITE_LONG_ONCE 0x33 /* 28-Bit without retries */
1886 #define WIN_WRITE_EXT 0x34 /* 48-Bit */
1887 #define WIN_WRITEDMA_EXT 0x35 /* 48-Bit */
1888 #define WIN_WRITEDMA_QUEUED_EXT 0x36 /* 48-Bit */
1889 #define WIN_SET_MAX_EXT 0x37 /* 48-Bit */
1890 #define CFA_WRITE_SECT_WO_ERASE 0x38 /* CFA Write Sectors without erase */
1891 #define WIN_MULTWRITE_EXT 0x39 /* 48-Bit */
1893 * 0x3A->0x3B Reserved
1895 #define WIN_WRITE_VERIFY 0x3C /* 28-Bit */
1897 * 0x3D->0x3F Reserved
1899 #define WIN_VERIFY 0x40 /* 28-Bit - Read Verify Sectors */
1900 #define WIN_VERIFY_ONCE 0x41 /* 28-Bit - without retries */
1901 #define WIN_VERIFY_EXT 0x42 /* 48-Bit */
1903 * 0x43->0x4F Reserved
1905 #define WIN_FORMAT 0x50
1907 * 0x51->0x5F Reserved
1909 #define WIN_INIT 0x60
1911 * 0x61->0x5F Reserved
1913 #define WIN_SEEK 0x70 /* 0x70-0x7F Reserved */
1914 #define CFA_TRANSLATE_SECTOR 0x87 /* CFA Translate Sector */
1915 #define WIN_DIAGNOSE 0x90
1916 #define WIN_SPECIFY 0x91 /* set drive geometry translation */
1917 #define WIN_DOWNLOAD_MICROCODE 0x92
1918 #define WIN_STANDBYNOW2 0x94
1919 #define WIN_STANDBY2 0x96
1920 #define WIN_SETIDLE2 0x97
1921 #define WIN_CHECKPOWERMODE2 0x98
1922 #define WIN_SLEEPNOW2 0x99
1926 #define WIN_PACKETCMD 0xA0 /* Send a packet command. */
1927 #define WIN_PIDENTIFY 0xA1 /* identify ATAPI device */
1928 #define WIN_QUEUED_SERVICE 0xA2
1929 #define WIN_SMART 0xB0 /* self-monitoring and reporting */
1930 #define CFA_ERASE_SECTORS 0xC0
1931 #define WIN_MULTREAD 0xC4 /* read sectors using multiple mode*/
1932 #define WIN_MULTWRITE 0xC5 /* write sectors using multiple mode */
1933 #define WIN_SETMULT 0xC6 /* enable/disable multiple mode */
1934 #define WIN_READDMA_QUEUED 0xC7 /* read sectors using Queued DMA transfers */
1935 #define WIN_READDMA 0xC8 /* read sectors using DMA transfers */
1936 #define WIN_READDMA_ONCE 0xC9 /* 28-Bit - without retries */
1937 #define WIN_WRITEDMA 0xCA /* write sectors using DMA transfers */
1938 #define WIN_WRITEDMA_ONCE 0xCB /* 28-Bit - without retries */
1939 #define WIN_WRITEDMA_QUEUED 0xCC /* write sectors using Queued DMA transfers */
1940 #define CFA_WRITE_MULTI_WO_ERASE 0xCD /* CFA Write multiple without erase */
1941 #define WIN_GETMEDIASTATUS 0xDA
1942 #define WIN_ACKMEDIACHANGE 0xDB /* ATA-1, ATA-2 vendor */
1943 #define WIN_POSTBOOT 0xDC
1944 #define WIN_PREBOOT 0xDD
1945 #define WIN_DOORLOCK 0xDE /* lock door on removable drives */
1946 #define WIN_DOORUNLOCK 0xDF /* unlock door on removable drives */
1947 #define WIN_STANDBYNOW1 0xE0
1948 #define WIN_IDLEIMMEDIATE 0xE1 /* force drive to become "ready" */
1949 #define WIN_STANDBY 0xE2 /* Set device in Standby Mode */
1950 #define WIN_SETIDLE1 0xE3
1951 #define WIN_READ_BUFFER 0xE4 /* force read only 1 sector */
1952 #define WIN_CHECKPOWERMODE1 0xE5
1953 #define WIN_SLEEPNOW1 0xE6
1954 #define WIN_FLUSH_CACHE 0xE7
1955 #define WIN_WRITE_BUFFER 0xE8 /* force write only 1 sector */
1956 #define WIN_WRITE_SAME 0xE9 /* read ata-2 to use */
1957 /* SET_FEATURES 0x22 or 0xDD */
1958 #define WIN_FLUSH_CACHE_EXT 0xEA /* 48-Bit */
1959 #define WIN_IDENTIFY 0xEC /* ask drive to identify itself */
1960 #define WIN_MEDIAEJECT 0xED
1961 #define WIN_IDENTIFY_DMA 0xEE /* same as WIN_IDENTIFY, but DMA */
1962 #define WIN_SETFEATURES 0xEF /* set special drive features */
1963 #define EXABYTE_ENABLE_NEST 0xF0
1964 #define WIN_SECURITY_SET_PASS 0xF1
1965 #define WIN_SECURITY_UNLOCK 0xF2
1966 #define WIN_SECURITY_ERASE_PREPARE 0xF3
1967 #define WIN_SECURITY_ERASE_UNIT 0xF4
1968 #define WIN_SECURITY_FREEZE_LOCK 0xF5
1969 #define WIN_SECURITY_DISABLE 0xF6
1970 #define WIN_READ_NATIVE_MAX 0xF8 /* return the native maximum address */
1971 #define WIN_SET_MAX 0xF9
1972 #define DISABLE_SEAGATE 0xFB
1974 /* set to 1 set disable mult support */
1975 #define MAX_MULT_SECTORS 8
1981 typedef void EndTransferFunc(struct IDEState
*);
1983 typedef struct IDEState
{
1985 int cylinders
, heads
, sectors
;
1992 uint16_t nsector
; /* 0 is 256 to ease computations */
1998 /* 0x3f6 command, only meaningful for drive 0 */
2000 /* depends on bit 4 in select, only meaningful for drive 0 */
2001 struct IDEState
*cur_drive
;
2002 BlockDriverState
*bs
;
2003 int req_nb_sectors
; /* number of sectors per interrupt */
2004 EndTransferFunc
*end_transfer_func
;
2007 uint8_t io_buffer
[MAX_MULT_SECTORS
*512 + 4];
2010 BlockDriverState
*bs_table
[MAX_DISKS
];
2011 IDEState ide_state
[MAX_DISKS
];
2013 static void padstr(char *str
, const char *src
, int len
)
2016 for(i
= 0; i
< len
; i
++) {
2021 *(char *)((long)str
^ 1) = v
;
2026 static void ide_identify(IDEState
*s
)
2029 unsigned int oldsize
;
2031 memset(s
->io_buffer
, 0, 512);
2032 p
= (uint16_t *)s
->io_buffer
;
2034 stw(p
+ 1, s
->cylinders
);
2035 stw(p
+ 3, s
->heads
);
2036 stw(p
+ 4, 512 * s
->sectors
); /* sectors */
2037 stw(p
+ 5, 512); /* sector size */
2038 stw(p
+ 6, s
->sectors
);
2039 stw(p
+ 20, 3); /* buffer type */
2040 stw(p
+ 21, 512); /* cache size in sectors */
2041 stw(p
+ 22, 4); /* ecc bytes */
2042 padstr((uint8_t *)(p
+ 27), "QEMU HARDDISK", 40);
2043 #if MAX_MULT_SECTORS > 1
2044 stw(p
+ 47, MAX_MULT_SECTORS
);
2046 stw(p
+ 48, 1); /* dword I/O */
2047 stw(p
+ 49, 1 << 9); /* LBA supported, no DMA */
2048 stw(p
+ 51, 0x200); /* PIO transfer cycle */
2049 stw(p
+ 52, 0x200); /* DMA transfer cycle */
2050 stw(p
+ 54, s
->cylinders
);
2051 stw(p
+ 55, s
->heads
);
2052 stw(p
+ 56, s
->sectors
);
2053 oldsize
= s
->cylinders
* s
->heads
* s
->sectors
;
2054 stw(p
+ 57, oldsize
);
2055 stw(p
+ 58, oldsize
>> 16);
2056 if (s
->mult_sectors
)
2057 stw(p
+ 59, 0x100 | s
->mult_sectors
);
2058 stw(p
+ 60, s
->nb_sectors
);
2059 stw(p
+ 61, s
->nb_sectors
>> 16);
2060 stw(p
+ 80, (1 << 1) | (1 << 2));
2061 stw(p
+ 82, (1 << 14));
2062 stw(p
+ 83, (1 << 14));
2063 stw(p
+ 84, (1 << 14));
2064 stw(p
+ 85, (1 << 14));
2066 stw(p
+ 87, (1 << 14));
2069 static inline void ide_abort_command(IDEState
*s
)
2071 s
->status
= READY_STAT
| ERR_STAT
;
2072 s
->error
= ABRT_ERR
;
2075 static inline void ide_set_irq(IDEState
*s
)
2077 if (!(ide_state
[0].cmd
& IDE_CMD_DISABLE_IRQ
)) {
2078 pic_set_irq(s
->irq
, 1);
2082 /* prepare data transfer and tell what to do after */
2083 static void ide_transfer_start(IDEState
*s
, int size
,
2084 EndTransferFunc
*end_transfer_func
)
2086 s
->end_transfer_func
= end_transfer_func
;
2087 s
->data_ptr
= s
->io_buffer
;
2088 s
->data_end
= s
->io_buffer
+ size
;
2089 s
->status
|= DRQ_STAT
;
2092 static void ide_transfer_stop(IDEState
*s
)
2094 s
->end_transfer_func
= ide_transfer_stop
;
2095 s
->data_ptr
= s
->io_buffer
;
2096 s
->data_end
= s
->io_buffer
;
2097 s
->status
&= ~DRQ_STAT
;
2100 static int64_t ide_get_sector(IDEState
*s
)
2103 if (s
->select
& 0x40) {
2105 sector_num
= ((s
->select
& 0x0f) << 24) | (s
->hcyl
<< 16) |
2106 (s
->lcyl
<< 8) | s
->sector
;
2108 sector_num
= ((s
->hcyl
<< 8) | s
->lcyl
) * s
->heads
* s
->sectors
+
2109 (s
->select
& 0x0f) * s
->sectors
+
2115 static void ide_set_sector(IDEState
*s
, int64_t sector_num
)
2117 unsigned int cyl
, r
;
2118 if (s
->select
& 0x40) {
2119 s
->select
= (s
->select
& 0xf0) | (sector_num
>> 24);
2120 s
->hcyl
= (sector_num
>> 16);
2121 s
->lcyl
= (sector_num
>> 8);
2122 s
->sector
= (sector_num
);
2124 cyl
= sector_num
/ (s
->heads
* s
->sectors
);
2125 r
= sector_num
% (s
->heads
* s
->sectors
);
2128 s
->select
= (s
->select
& 0xf0) | (r
/ s
->sectors
);
2129 s
->sector
= (r
% s
->sectors
) + 1;
2133 static void ide_sector_read(IDEState
*s
)
2138 s
->status
= READY_STAT
| SEEK_STAT
;
2139 sector_num
= ide_get_sector(s
);
2142 /* no more sector to read from disk */
2143 ide_transfer_stop(s
);
2145 #if defined(DEBUG_IDE)
2146 printf("read sector=%Ld\n", sector_num
);
2148 if (n
> s
->req_nb_sectors
)
2149 n
= s
->req_nb_sectors
;
2150 ret
= bdrv_read(s
->bs
, sector_num
, s
->io_buffer
, n
);
2151 ide_transfer_start(s
, 512 * n
, ide_sector_read
);
2153 ide_set_sector(s
, sector_num
+ n
);
2158 static void ide_sector_write(IDEState
*s
)
2163 s
->status
= READY_STAT
| SEEK_STAT
;
2164 sector_num
= ide_get_sector(s
);
2165 #if defined(DEBUG_IDE)
2166 printf("write sector=%Ld\n", sector_num
);
2169 if (n
> s
->req_nb_sectors
)
2170 n
= s
->req_nb_sectors
;
2171 ret
= bdrv_write(s
->bs
, sector_num
, s
->io_buffer
, n
);
2173 if (s
->nsector
== 0) {
2174 /* no more sector to write */
2175 ide_transfer_stop(s
);
2178 if (n1
> s
->req_nb_sectors
)
2179 n1
= s
->req_nb_sectors
;
2180 ide_transfer_start(s
, 512 * n1
, ide_sector_write
);
2182 ide_set_sector(s
, sector_num
+ n
);
2186 void ide_ioport_write(CPUX86State
*env
, uint32_t addr
, uint32_t val
)
2188 IDEState
*s
= ide_state
[0].cur_drive
;
2193 printf("IDE: write addr=0x%x val=0x%02x\n", addr
, val
);
2217 unit
= (val
>> 4) & 1;
2218 s
= &ide_state
[unit
];
2219 ide_state
[0].cur_drive
= s
;
2225 #if defined(DEBUG_IDE)
2226 printf("ide: CMD=%02x\n", val
);
2233 s
->status
= READY_STAT
;
2234 ide_transfer_start(s
, 512, ide_transfer_stop
);
2236 ide_abort_command(s
);
2242 s
->status
= READY_STAT
;
2246 if (s
->nsector
> MAX_MULT_SECTORS
||
2248 (s
->nsector
& (s
->nsector
- 1)) != 0) {
2249 ide_abort_command(s
);
2251 s
->mult_sectors
= s
->nsector
;
2252 s
->status
= READY_STAT
;
2258 s
->req_nb_sectors
= 1;
2262 case WIN_WRITE_ONCE
:
2263 s
->status
= SEEK_STAT
;
2264 s
->req_nb_sectors
= 1;
2265 ide_transfer_start(s
, 512, ide_sector_write
);
2268 if (!s
->mult_sectors
)
2270 s
->req_nb_sectors
= s
->mult_sectors
;
2274 if (!s
->mult_sectors
)
2276 s
->status
= SEEK_STAT
;
2277 s
->req_nb_sectors
= s
->mult_sectors
;
2279 if (n
> s
->req_nb_sectors
)
2280 n
= s
->req_nb_sectors
;
2281 ide_transfer_start(s
, 512 * n
, ide_sector_write
);
2285 ide_abort_command(s
);
2292 uint32_t ide_ioport_read(CPUX86State
*env
, uint32_t addr
)
2294 IDEState
*s
= ide_state
[0].cur_drive
;
2306 ret
= s
->nsector
& 0xff;
2323 pic_set_irq(s
->irq
, 0);
2327 printf("ide: read addr=0x%x val=%02x\n", addr
, ret
);
2332 uint32_t ide_status_read(CPUX86State
*env
, uint32_t addr
)
2334 IDEState
*s
= ide_state
[0].cur_drive
;
2338 printf("ide: read addr=0x%x val=%02x\n", addr
, ret
);
2343 void ide_cmd_write(CPUX86State
*env
, uint32_t addr
, uint32_t val
)
2345 IDEState
*s
= &ide_state
[0];
2346 /* common for both drives */
2350 void ide_data_writew(CPUX86State
*env
, uint32_t addr
, uint32_t val
)
2352 IDEState
*s
= ide_state
[0].cur_drive
;
2356 *(uint16_t *)p
= tswap16(val
);
2359 if (p
>= s
->data_end
)
2360 s
->end_transfer_func(s
);
2363 uint32_t ide_data_readw(CPUX86State
*env
, uint32_t addr
)
2365 IDEState
*s
= ide_state
[0].cur_drive
;
2370 ret
= tswap16(*(uint16_t *)p
);
2373 if (p
>= s
->data_end
)
2374 s
->end_transfer_func(s
);
2378 void ide_data_writel(CPUX86State
*env
, uint32_t addr
, uint32_t val
)
2380 IDEState
*s
= ide_state
[0].cur_drive
;
2384 *(uint32_t *)p
= tswap32(val
);
2387 if (p
>= s
->data_end
)
2388 s
->end_transfer_func(s
);
2391 uint32_t ide_data_readl(CPUX86State
*env
, uint32_t addr
)
2393 IDEState
*s
= ide_state
[0].cur_drive
;
2398 ret
= tswap32(*(uint32_t *)p
);
2401 if (p
>= s
->data_end
)
2402 s
->end_transfer_func(s
);
2406 void ide_reset(IDEState
*s
)
2408 s
->mult_sectors
= MAX_MULT_SECTORS
;
2409 s
->status
= READY_STAT
;
2420 for(i
= 0; i
< MAX_DISKS
; i
++) {
2422 s
->bs
= bs_table
[i
];
2424 bdrv_get_geometry(s
->bs
, &nb_sectors
);
2425 cylinders
= nb_sectors
/ (16 * 63);
2426 if (cylinders
> 16383)
2428 else if (cylinders
< 2)
2430 s
->cylinders
= cylinders
;
2433 s
->nb_sectors
= nb_sectors
;
2438 register_ioport_write(0x1f0, 8, ide_ioport_write
, 1);
2439 register_ioport_read(0x1f0, 8, ide_ioport_read
, 1);
2440 register_ioport_read(0x3f6, 1, ide_status_read
, 1);
2441 register_ioport_write(0x3f6, 1, ide_cmd_write
, 1);
2444 register_ioport_write(0x1f0, 2, ide_data_writew
, 2);
2445 register_ioport_read(0x1f0, 2, ide_data_readw
, 2);
2446 register_ioport_write(0x1f0, 4, ide_data_writel
, 4);
2447 register_ioport_read(0x1f0, 4, ide_data_readl
, 4);
2450 /***********************************************************/
2451 /* cpu signal handler */
2452 static void host_segv_handler(int host_signum
, siginfo_t
*info
,
2455 if (cpu_signal_handler(host_signum
, info
, puc
))
2461 static int timer_irq_pending
;
2462 static int timer_irq_count
;
2464 static void host_alarm_handler(int host_signum
, siginfo_t
*info
,
2467 /* NOTE: since usually the OS asks a 100 Hz clock, there can be
2468 some drift between cpu_get_ticks() and the interrupt time. So
2469 we queue some interrupts to avoid missing some */
2470 timer_irq_count
+= pit_get_out_edges(&pit_channels
[0]);
2471 if (timer_irq_count
) {
2472 if (timer_irq_count
> 2)
2473 timer_irq_count
= 2;
2475 /* just exit from the cpu to have a chance to handle timers */
2476 cpu_x86_interrupt(global_env
, CPU_INTERRUPT_EXIT
);
2477 timer_irq_pending
= 1;
2481 /* main execution loop */
2483 CPUState
*cpu_gdbstub_get_env(void *opaque
)
2488 void main_loop(void *opaque
)
2490 struct pollfd ufds
[2], *pf
, *serial_ufd
, *net_ufd
, *gdb_ufd
;
2491 int ret
, n
, timeout
;
2493 CPUState
*env
= global_env
;
2497 ret
= cpu_x86_exec(env
);
2499 /* if hlt instruction, we wait until the next IRQ */
2500 if (ret
== EXCP_HLT
)
2504 /* poll any events */
2507 if (!(serial_ports
[0].lsr
& UART_LSR_DR
)) {
2510 pf
->events
= POLLIN
;
2514 if (net_fd
> 0 && ne2000_can_receive(&ne2000_state
)) {
2517 pf
->events
= POLLIN
;
2521 if (gdbstub_fd
> 0) {
2523 pf
->fd
= gdbstub_fd
;
2524 pf
->events
= POLLIN
;
2528 ret
= poll(ufds
, pf
- ufds
, timeout
);
2530 if (serial_ufd
&& (serial_ufd
->revents
& POLLIN
)) {
2531 n
= read(0, &ch
, 1);
2533 serial_received_byte(&serial_ports
[0], ch
);
2536 if (net_ufd
&& (net_ufd
->revents
& POLLIN
)) {
2537 uint8_t buf
[MAX_ETH_FRAME_SIZE
];
2539 n
= read(net_fd
, buf
, MAX_ETH_FRAME_SIZE
);
2542 memset(buf
+ n
, 0, 60 - n
);
2545 ne2000_receive(&ne2000_state
, buf
, n
);
2548 if (gdb_ufd
&& (gdb_ufd
->revents
& POLLIN
)) {
2550 /* stop emulation if requested by gdb */
2551 n
= read(gdbstub_fd
, buf
, 1);
2558 if (timer_irq_pending
) {
2561 timer_irq_pending
= 0;
2568 printf("Virtual Linux version " QEMU_VERSION
", Copyright (c) 2003 Fabrice Bellard\n"
2569 "usage: vl [options] bzImage [kernel parameters...]\n"
2571 "'bzImage' is a Linux kernel image (PAGE_OFFSET must be defined\n"
2572 "to 0x90000000 in asm/page.h and arch/i386/vmlinux.lds)\n"
2574 "General options:\n"
2575 "-initrd file use 'file' as initial ram disk\n"
2576 "-hda file use 'file' as hard disk 0 image\n"
2577 "-hdb file use 'file' as hard disk 1 image\n"
2578 "-m megs set virtual RAM size to megs MB\n"
2579 "-n script set network init script [default=%s]\n"
2582 "-s wait gdb connection to port %d\n"
2583 "-p port change gdb connection port\n"
2584 "-d output log in /tmp/vl.log\n"
2586 "During emulation, use C-a h to get terminal commands:\n",
2587 DEFAULT_NETWORK_SCRIPT
, DEFAULT_GDBSTUB_PORT
);
2592 struct option long_options
[] = {
2593 { "initrd", 1, NULL
, 0, },
2594 { "hda", 1, NULL
, 0, },
2595 { "hdb", 1, NULL
, 0, },
2596 { NULL
, 0, NULL
, 0 },
2599 int main(int argc
, char **argv
)
2601 int c
, ret
, initrd_size
, i
, use_gdbstub
, gdbstub_port
, long_index
;
2602 struct linux_params
*params
;
2603 struct sigaction act
;
2604 struct itimerval itv
;
2606 const char *tmpdir
, *initrd_filename
;
2607 const char *hd_filename
[MAX_DISKS
];
2609 /* we never want that malloc() uses mmap() */
2610 mallopt(M_MMAP_THRESHOLD
, 4096 * 1024);
2611 initrd_filename
= NULL
;
2612 for(i
= 0; i
< MAX_DISKS
; i
++)
2613 hd_filename
[i
] = NULL
;
2614 phys_ram_size
= 32 * 1024 * 1024;
2615 pstrcpy(network_script
, sizeof(network_script
), DEFAULT_NETWORK_SCRIPT
);
2617 gdbstub_port
= DEFAULT_GDBSTUB_PORT
;
2619 c
= getopt_long_only(argc
, argv
, "hm:dn:sp:", long_options
, &long_index
);
2624 switch(long_index
) {
2626 initrd_filename
= optarg
;
2629 hd_filename
[0] = optarg
;
2632 hd_filename
[1] = optarg
;
2640 phys_ram_size
= atoi(optarg
) * 1024 * 1024;
2641 if (phys_ram_size
<= 0)
2648 pstrcpy(network_script
, sizeof(network_script
), optarg
);
2654 gdbstub_port
= atoi(optarg
);
2662 setvbuf(stdout
, NULL
, _IOLBF
, 0);
2664 logfile
= fopen(DEBUG_LOGFILE
, "w");
2666 perror(DEBUG_LOGFILE
);
2669 setvbuf(logfile
, NULL
, _IOLBF
, 0);
2672 /* open the virtual block devices */
2673 for(i
= 0; i
< MAX_DISKS
; i
++) {
2674 if (hd_filename
[i
]) {
2675 bs_table
[i
] = bdrv_open(hd_filename
[i
]);
2677 fprintf(stderr
, "vl: could not open hard disk image '%s\n",
2684 /* init network tun interface */
2687 /* init the memory */
2688 tmpdir
= getenv("VLTMPDIR");
2691 snprintf(phys_ram_file
, sizeof(phys_ram_file
), "%s/vlXXXXXX", tmpdir
);
2692 if (mkstemp(phys_ram_file
) < 0) {
2693 fprintf(stderr
, "Could not create temporary memory file '%s'\n",
2697 phys_ram_fd
= open(phys_ram_file
, O_CREAT
| O_TRUNC
| O_RDWR
, 0600);
2698 if (phys_ram_fd
< 0) {
2699 fprintf(stderr
, "Could not open temporary memory file '%s'\n",
2703 ftruncate(phys_ram_fd
, phys_ram_size
);
2704 unlink(phys_ram_file
);
2705 phys_ram_base
= mmap((void *)PHYS_RAM_BASE
, phys_ram_size
,
2706 PROT_WRITE
| PROT_READ
, MAP_SHARED
| MAP_FIXED
,
2708 if (phys_ram_base
== MAP_FAILED
) {
2709 fprintf(stderr
, "Could not map physical memory\n");
2713 /* now we can load the kernel */
2714 ret
= load_kernel(argv
[optind
], phys_ram_base
+ KERNEL_LOAD_ADDR
);
2716 fprintf(stderr
, "vl: could not load kernel '%s'\n", argv
[optind
]);
2722 if (initrd_filename
) {
2723 initrd_size
= load_image(initrd_filename
, phys_ram_base
+ INITRD_LOAD_ADDR
);
2724 if (initrd_size
< 0) {
2725 fprintf(stderr
, "vl: could not load initial ram disk '%s'\n",
2731 /* init kernel params */
2732 params
= (void *)(phys_ram_base
+ KERNEL_PARAMS_ADDR
);
2733 memset(params
, 0, sizeof(struct linux_params
));
2734 params
->mount_root_rdonly
= 0;
2735 params
->cl_magic
= 0xA33F;
2736 params
->cl_offset
= params
->commandline
- (uint8_t *)params
;
2737 params
->ext_mem_k
= (phys_ram_size
/ 1024) - 1024;
2738 for(i
= optind
+ 1; i
< argc
; i
++) {
2739 if (i
!= optind
+ 1)
2740 pstrcat(params
->commandline
, sizeof(params
->commandline
), " ");
2741 pstrcat(params
->commandline
, sizeof(params
->commandline
), argv
[i
]);
2743 params
->loader_type
= 0x01;
2744 if (initrd_size
> 0) {
2745 params
->initrd_start
= INITRD_LOAD_ADDR
;
2746 params
->initrd_size
= initrd_size
;
2748 params
->orig_video_lines
= 25;
2749 params
->orig_video_cols
= 80;
2751 /* init basic PC hardware */
2753 register_ioport_write(0x80, 1, ioport80_write
, 1);
2755 register_ioport_write(0x3d4, 2, vga_ioport_write
, 1);
2764 /* setup cpu signal handlers for MMU / self modifying code handling */
2765 sigfillset(&act
.sa_mask
);
2766 act
.sa_flags
= SA_SIGINFO
;
2767 act
.sa_sigaction
= host_segv_handler
;
2768 sigaction(SIGSEGV
, &act
, NULL
);
2769 sigaction(SIGBUS
, &act
, NULL
);
2771 act
.sa_sigaction
= host_alarm_handler
;
2772 sigaction(SIGALRM
, &act
, NULL
);
2774 /* init CPU state */
2777 cpu_single_env
= env
;
2779 /* setup basic memory access */
2780 env
->cr
[0] = 0x00000033;
2781 cpu_x86_init_mmu(env
);
2783 memset(params
->idt_table
, 0, sizeof(params
->idt_table
));
2785 params
->gdt_table
[2] = 0x00cf9a000000ffffLL
; /* KERNEL_CS */
2786 params
->gdt_table
[3] = 0x00cf92000000ffffLL
; /* KERNEL_DS */
2788 env
->idt
.base
= (void *)params
->idt_table
;
2789 env
->idt
.limit
= sizeof(params
->idt_table
) - 1;
2790 env
->gdt
.base
= (void *)params
->gdt_table
;
2791 env
->gdt
.limit
= sizeof(params
->gdt_table
) - 1;
2793 cpu_x86_load_seg(env
, R_CS
, KERNEL_CS
);
2794 cpu_x86_load_seg(env
, R_DS
, KERNEL_DS
);
2795 cpu_x86_load_seg(env
, R_ES
, KERNEL_DS
);
2796 cpu_x86_load_seg(env
, R_SS
, KERNEL_DS
);
2797 cpu_x86_load_seg(env
, R_FS
, KERNEL_DS
);
2798 cpu_x86_load_seg(env
, R_GS
, KERNEL_DS
);
2800 env
->eip
= KERNEL_LOAD_ADDR
;
2801 env
->regs
[R_ESI
] = KERNEL_PARAMS_ADDR
;
2804 itv
.it_interval
.tv_sec
= 0;
2805 itv
.it_interval
.tv_usec
= 1000;
2806 itv
.it_value
.tv_sec
= 0;
2807 itv
.it_value
.tv_usec
= 10 * 1000;
2808 setitimer(ITIMER_REAL
, &itv
, NULL
);
2809 /* we probe the tick duration of the kernel to inform the user if
2810 the emulated kernel requested a too high timer frequency */
2811 getitimer(ITIMER_REAL
, &itv
);
2812 pit_min_timer_count
= ((uint64_t)itv
.it_interval
.tv_usec
* PIT_FREQ
) /
2816 cpu_gdbstub(NULL
, main_loop
, gdbstub_port
);