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Use qemu_irqs between dma controllers and esp, lance
[qemu.git] / vl.h
1 /*
2 * QEMU System Emulator header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #ifndef VL_H
25 #define VL_H
26
27 /* we put basic includes here to avoid repeating them in device drivers */
28 #include <stdlib.h>
29 #include <stdio.h>
30 #include <stdarg.h>
31 #include <string.h>
32 #include <inttypes.h>
33 #include <limits.h>
34 #include <time.h>
35 #include <ctype.h>
36 #include <errno.h>
37 #include <unistd.h>
38 #include <fcntl.h>
39 #include <sys/stat.h>
40
41 #ifndef O_LARGEFILE
42 #define O_LARGEFILE 0
43 #endif
44 #ifndef O_BINARY
45 #define O_BINARY 0
46 #endif
47
48 #ifndef ENOMEDIUM
49 #define ENOMEDIUM ENODEV
50 #endif
51
52 #ifdef _WIN32
53 #include <windows.h>
54 #define fsync _commit
55 #define lseek _lseeki64
56 #define ENOTSUP 4096
57 extern int qemu_ftruncate64(int, int64_t);
58 #define ftruncate qemu_ftruncate64
59
60
61 static inline char *realpath(const char *path, char *resolved_path)
62 {
63 _fullpath(resolved_path, path, _MAX_PATH);
64 return resolved_path;
65 }
66
67 #define PRId64 "I64d"
68 #define PRIx64 "I64x"
69 #define PRIu64 "I64u"
70 #define PRIo64 "I64o"
71 #endif
72
73 #ifdef QEMU_TOOL
74
75 /* we use QEMU_TOOL in the command line tools which do not depend on
76 the target CPU type */
77 #include "config-host.h"
78 #include <setjmp.h>
79 #include "osdep.h"
80 #include "bswap.h"
81
82 #else
83
84 #include "audio/audio.h"
85 #include "cpu.h"
86
87 #endif /* !defined(QEMU_TOOL) */
88
89 #ifndef glue
90 #define xglue(x, y) x ## y
91 #define glue(x, y) xglue(x, y)
92 #define stringify(s) tostring(s)
93 #define tostring(s) #s
94 #endif
95
96 #ifndef MIN
97 #define MIN(a, b) (((a) < (b)) ? (a) : (b))
98 #endif
99 #ifndef MAX
100 #define MAX(a, b) (((a) > (b)) ? (a) : (b))
101 #endif
102
103 /* cutils.c */
104 void pstrcpy(char *buf, int buf_size, const char *str);
105 char *pstrcat(char *buf, int buf_size, const char *s);
106 int strstart(const char *str, const char *val, const char **ptr);
107 int stristart(const char *str, const char *val, const char **ptr);
108
109 /* vl.c */
110 uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c);
111
112 void hw_error(const char *fmt, ...);
113
114 extern const char *bios_dir;
115
116 extern int vm_running;
117 extern const char *qemu_name;
118
119 typedef struct vm_change_state_entry VMChangeStateEntry;
120 typedef void VMChangeStateHandler(void *opaque, int running);
121 typedef void VMStopHandler(void *opaque, int reason);
122
123 VMChangeStateEntry *qemu_add_vm_change_state_handler(VMChangeStateHandler *cb,
124 void *opaque);
125 void qemu_del_vm_change_state_handler(VMChangeStateEntry *e);
126
127 int qemu_add_vm_stop_handler(VMStopHandler *cb, void *opaque);
128 void qemu_del_vm_stop_handler(VMStopHandler *cb, void *opaque);
129
130 void vm_start(void);
131 void vm_stop(int reason);
132
133 typedef void QEMUResetHandler(void *opaque);
134
135 void qemu_register_reset(QEMUResetHandler *func, void *opaque);
136 void qemu_system_reset_request(void);
137 void qemu_system_shutdown_request(void);
138 void qemu_system_powerdown_request(void);
139 #if !defined(TARGET_SPARC)
140 // Please implement a power failure function to signal the OS
141 #define qemu_system_powerdown() do{}while(0)
142 #else
143 void qemu_system_powerdown(void);
144 #endif
145
146 void main_loop_wait(int timeout);
147
148 extern int ram_size;
149 extern int bios_size;
150 extern int rtc_utc;
151 extern int cirrus_vga_enabled;
152 extern int vmsvga_enabled;
153 extern int graphic_width;
154 extern int graphic_height;
155 extern int graphic_depth;
156 extern const char *keyboard_layout;
157 extern int kqemu_allowed;
158 extern int win2k_install_hack;
159 extern int usb_enabled;
160 extern int smp_cpus;
161 extern int cursor_hide;
162 extern int graphic_rotate;
163 extern int no_quit;
164 extern int semihosting_enabled;
165 extern int autostart;
166 extern const char *bootp_filename;
167
168 #define MAX_OPTION_ROMS 16
169 extern const char *option_rom[MAX_OPTION_ROMS];
170 extern int nb_option_roms;
171
172 #ifdef TARGET_SPARC
173 #define MAX_PROM_ENVS 128
174 extern const char *prom_envs[MAX_PROM_ENVS];
175 extern unsigned int nb_prom_envs;
176 #endif
177
178 /* XXX: make it dynamic */
179 #define MAX_BIOS_SIZE (4 * 1024 * 1024)
180 #if defined (TARGET_PPC) || defined (TARGET_SPARC64)
181 #define BIOS_SIZE ((512 + 32) * 1024)
182 #elif defined(TARGET_MIPS)
183 #define BIOS_SIZE (4 * 1024 * 1024)
184 #endif
185
186 /* keyboard/mouse support */
187
188 #define MOUSE_EVENT_LBUTTON 0x01
189 #define MOUSE_EVENT_RBUTTON 0x02
190 #define MOUSE_EVENT_MBUTTON 0x04
191
192 typedef void QEMUPutKBDEvent(void *opaque, int keycode);
193 typedef void QEMUPutMouseEvent(void *opaque, int dx, int dy, int dz, int buttons_state);
194
195 typedef struct QEMUPutMouseEntry {
196 QEMUPutMouseEvent *qemu_put_mouse_event;
197 void *qemu_put_mouse_event_opaque;
198 int qemu_put_mouse_event_absolute;
199 char *qemu_put_mouse_event_name;
200
201 /* used internally by qemu for handling mice */
202 struct QEMUPutMouseEntry *next;
203 } QEMUPutMouseEntry;
204
205 void qemu_add_kbd_event_handler(QEMUPutKBDEvent *func, void *opaque);
206 QEMUPutMouseEntry *qemu_add_mouse_event_handler(QEMUPutMouseEvent *func,
207 void *opaque, int absolute,
208 const char *name);
209 void qemu_remove_mouse_event_handler(QEMUPutMouseEntry *entry);
210
211 void kbd_put_keycode(int keycode);
212 void kbd_mouse_event(int dx, int dy, int dz, int buttons_state);
213 int kbd_mouse_is_absolute(void);
214
215 void do_info_mice(void);
216 void do_mouse_set(int index);
217
218 /* keysym is a unicode code except for special keys (see QEMU_KEY_xxx
219 constants) */
220 #define QEMU_KEY_ESC1(c) ((c) | 0xe100)
221 #define QEMU_KEY_BACKSPACE 0x007f
222 #define QEMU_KEY_UP QEMU_KEY_ESC1('A')
223 #define QEMU_KEY_DOWN QEMU_KEY_ESC1('B')
224 #define QEMU_KEY_RIGHT QEMU_KEY_ESC1('C')
225 #define QEMU_KEY_LEFT QEMU_KEY_ESC1('D')
226 #define QEMU_KEY_HOME QEMU_KEY_ESC1(1)
227 #define QEMU_KEY_END QEMU_KEY_ESC1(4)
228 #define QEMU_KEY_PAGEUP QEMU_KEY_ESC1(5)
229 #define QEMU_KEY_PAGEDOWN QEMU_KEY_ESC1(6)
230 #define QEMU_KEY_DELETE QEMU_KEY_ESC1(3)
231
232 #define QEMU_KEY_CTRL_UP 0xe400
233 #define QEMU_KEY_CTRL_DOWN 0xe401
234 #define QEMU_KEY_CTRL_LEFT 0xe402
235 #define QEMU_KEY_CTRL_RIGHT 0xe403
236 #define QEMU_KEY_CTRL_HOME 0xe404
237 #define QEMU_KEY_CTRL_END 0xe405
238 #define QEMU_KEY_CTRL_PAGEUP 0xe406
239 #define QEMU_KEY_CTRL_PAGEDOWN 0xe407
240
241 void kbd_put_keysym(int keysym);
242
243 /* async I/O support */
244
245 typedef void IOReadHandler(void *opaque, const uint8_t *buf, int size);
246 typedef int IOCanRWHandler(void *opaque);
247 typedef void IOHandler(void *opaque);
248
249 int qemu_set_fd_handler2(int fd,
250 IOCanRWHandler *fd_read_poll,
251 IOHandler *fd_read,
252 IOHandler *fd_write,
253 void *opaque);
254 int qemu_set_fd_handler(int fd,
255 IOHandler *fd_read,
256 IOHandler *fd_write,
257 void *opaque);
258
259 /* Polling handling */
260
261 /* return TRUE if no sleep should be done afterwards */
262 typedef int PollingFunc(void *opaque);
263
264 int qemu_add_polling_cb(PollingFunc *func, void *opaque);
265 void qemu_del_polling_cb(PollingFunc *func, void *opaque);
266
267 #ifdef _WIN32
268 /* Wait objects handling */
269 typedef void WaitObjectFunc(void *opaque);
270
271 int qemu_add_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
272 void qemu_del_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
273 #endif
274
275 typedef struct QEMUBH QEMUBH;
276
277 /* character device */
278
279 #define CHR_EVENT_BREAK 0 /* serial break char */
280 #define CHR_EVENT_FOCUS 1 /* focus to this terminal (modal input needed) */
281 #define CHR_EVENT_RESET 2 /* new connection established */
282
283
284 #define CHR_IOCTL_SERIAL_SET_PARAMS 1
285 typedef struct {
286 int speed;
287 int parity;
288 int data_bits;
289 int stop_bits;
290 } QEMUSerialSetParams;
291
292 #define CHR_IOCTL_SERIAL_SET_BREAK 2
293
294 #define CHR_IOCTL_PP_READ_DATA 3
295 #define CHR_IOCTL_PP_WRITE_DATA 4
296 #define CHR_IOCTL_PP_READ_CONTROL 5
297 #define CHR_IOCTL_PP_WRITE_CONTROL 6
298 #define CHR_IOCTL_PP_READ_STATUS 7
299 #define CHR_IOCTL_PP_EPP_READ_ADDR 8
300 #define CHR_IOCTL_PP_EPP_READ 9
301 #define CHR_IOCTL_PP_EPP_WRITE_ADDR 10
302 #define CHR_IOCTL_PP_EPP_WRITE 11
303
304 typedef void IOEventHandler(void *opaque, int event);
305
306 typedef struct CharDriverState {
307 int (*chr_write)(struct CharDriverState *s, const uint8_t *buf, int len);
308 void (*chr_update_read_handler)(struct CharDriverState *s);
309 int (*chr_ioctl)(struct CharDriverState *s, int cmd, void *arg);
310 IOEventHandler *chr_event;
311 IOCanRWHandler *chr_can_read;
312 IOReadHandler *chr_read;
313 void *handler_opaque;
314 void (*chr_send_event)(struct CharDriverState *chr, int event);
315 void (*chr_close)(struct CharDriverState *chr);
316 void *opaque;
317 int focus;
318 QEMUBH *bh;
319 } CharDriverState;
320
321 CharDriverState *qemu_chr_open(const char *filename);
322 void qemu_chr_printf(CharDriverState *s, const char *fmt, ...);
323 int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len);
324 void qemu_chr_send_event(CharDriverState *s, int event);
325 void qemu_chr_add_handlers(CharDriverState *s,
326 IOCanRWHandler *fd_can_read,
327 IOReadHandler *fd_read,
328 IOEventHandler *fd_event,
329 void *opaque);
330 int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg);
331 void qemu_chr_reset(CharDriverState *s);
332 int qemu_chr_can_read(CharDriverState *s);
333 void qemu_chr_read(CharDriverState *s, uint8_t *buf, int len);
334
335 /* consoles */
336
337 typedef struct DisplayState DisplayState;
338 typedef struct TextConsole TextConsole;
339
340 typedef void (*vga_hw_update_ptr)(void *);
341 typedef void (*vga_hw_invalidate_ptr)(void *);
342 typedef void (*vga_hw_screen_dump_ptr)(void *, const char *);
343
344 TextConsole *graphic_console_init(DisplayState *ds, vga_hw_update_ptr update,
345 vga_hw_invalidate_ptr invalidate,
346 vga_hw_screen_dump_ptr screen_dump,
347 void *opaque);
348 void vga_hw_update(void);
349 void vga_hw_invalidate(void);
350 void vga_hw_screen_dump(const char *filename);
351
352 int is_graphic_console(void);
353 CharDriverState *text_console_init(DisplayState *ds);
354 void console_select(unsigned int index);
355
356 /* serial ports */
357
358 #define MAX_SERIAL_PORTS 4
359
360 extern CharDriverState *serial_hds[MAX_SERIAL_PORTS];
361
362 /* parallel ports */
363
364 #define MAX_PARALLEL_PORTS 3
365
366 extern CharDriverState *parallel_hds[MAX_PARALLEL_PORTS];
367
368 struct ParallelIOArg {
369 void *buffer;
370 int count;
371 };
372
373 /* VLANs support */
374
375 typedef struct VLANClientState VLANClientState;
376
377 struct VLANClientState {
378 IOReadHandler *fd_read;
379 /* Packets may still be sent if this returns zero. It's used to
380 rate-limit the slirp code. */
381 IOCanRWHandler *fd_can_read;
382 void *opaque;
383 struct VLANClientState *next;
384 struct VLANState *vlan;
385 char info_str[256];
386 };
387
388 typedef struct VLANState {
389 int id;
390 VLANClientState *first_client;
391 struct VLANState *next;
392 } VLANState;
393
394 VLANState *qemu_find_vlan(int id);
395 VLANClientState *qemu_new_vlan_client(VLANState *vlan,
396 IOReadHandler *fd_read,
397 IOCanRWHandler *fd_can_read,
398 void *opaque);
399 int qemu_can_send_packet(VLANClientState *vc);
400 void qemu_send_packet(VLANClientState *vc, const uint8_t *buf, int size);
401 void qemu_handler_true(void *opaque);
402
403 void do_info_network(void);
404
405 /* TAP win32 */
406 int tap_win32_init(VLANState *vlan, const char *ifname);
407
408 /* NIC info */
409
410 #define MAX_NICS 8
411
412 typedef struct NICInfo {
413 uint8_t macaddr[6];
414 const char *model;
415 VLANState *vlan;
416 } NICInfo;
417
418 extern int nb_nics;
419 extern NICInfo nd_table[MAX_NICS];
420
421 /* timers */
422
423 typedef struct QEMUClock QEMUClock;
424 typedef struct QEMUTimer QEMUTimer;
425 typedef void QEMUTimerCB(void *opaque);
426
427 /* The real time clock should be used only for stuff which does not
428 change the virtual machine state, as it is run even if the virtual
429 machine is stopped. The real time clock has a frequency of 1000
430 Hz. */
431 extern QEMUClock *rt_clock;
432
433 /* The virtual clock is only run during the emulation. It is stopped
434 when the virtual machine is stopped. Virtual timers use a high
435 precision clock, usually cpu cycles (use ticks_per_sec). */
436 extern QEMUClock *vm_clock;
437
438 int64_t qemu_get_clock(QEMUClock *clock);
439
440 QEMUTimer *qemu_new_timer(QEMUClock *clock, QEMUTimerCB *cb, void *opaque);
441 void qemu_free_timer(QEMUTimer *ts);
442 void qemu_del_timer(QEMUTimer *ts);
443 void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time);
444 int qemu_timer_pending(QEMUTimer *ts);
445
446 extern int64_t ticks_per_sec;
447 extern int pit_min_timer_count;
448
449 int64_t cpu_get_ticks(void);
450 void cpu_enable_ticks(void);
451 void cpu_disable_ticks(void);
452
453 /* VM Load/Save */
454
455 typedef struct QEMUFile QEMUFile;
456
457 QEMUFile *qemu_fopen(const char *filename, const char *mode);
458 void qemu_fflush(QEMUFile *f);
459 void qemu_fclose(QEMUFile *f);
460 void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size);
461 void qemu_put_byte(QEMUFile *f, int v);
462 void qemu_put_be16(QEMUFile *f, unsigned int v);
463 void qemu_put_be32(QEMUFile *f, unsigned int v);
464 void qemu_put_be64(QEMUFile *f, uint64_t v);
465 int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size);
466 int qemu_get_byte(QEMUFile *f);
467 unsigned int qemu_get_be16(QEMUFile *f);
468 unsigned int qemu_get_be32(QEMUFile *f);
469 uint64_t qemu_get_be64(QEMUFile *f);
470
471 static inline void qemu_put_be64s(QEMUFile *f, const uint64_t *pv)
472 {
473 qemu_put_be64(f, *pv);
474 }
475
476 static inline void qemu_put_be32s(QEMUFile *f, const uint32_t *pv)
477 {
478 qemu_put_be32(f, *pv);
479 }
480
481 static inline void qemu_put_be16s(QEMUFile *f, const uint16_t *pv)
482 {
483 qemu_put_be16(f, *pv);
484 }
485
486 static inline void qemu_put_8s(QEMUFile *f, const uint8_t *pv)
487 {
488 qemu_put_byte(f, *pv);
489 }
490
491 static inline void qemu_get_be64s(QEMUFile *f, uint64_t *pv)
492 {
493 *pv = qemu_get_be64(f);
494 }
495
496 static inline void qemu_get_be32s(QEMUFile *f, uint32_t *pv)
497 {
498 *pv = qemu_get_be32(f);
499 }
500
501 static inline void qemu_get_be16s(QEMUFile *f, uint16_t *pv)
502 {
503 *pv = qemu_get_be16(f);
504 }
505
506 static inline void qemu_get_8s(QEMUFile *f, uint8_t *pv)
507 {
508 *pv = qemu_get_byte(f);
509 }
510
511 #if TARGET_LONG_BITS == 64
512 #define qemu_put_betl qemu_put_be64
513 #define qemu_get_betl qemu_get_be64
514 #define qemu_put_betls qemu_put_be64s
515 #define qemu_get_betls qemu_get_be64s
516 #else
517 #define qemu_put_betl qemu_put_be32
518 #define qemu_get_betl qemu_get_be32
519 #define qemu_put_betls qemu_put_be32s
520 #define qemu_get_betls qemu_get_be32s
521 #endif
522
523 int64_t qemu_ftell(QEMUFile *f);
524 int64_t qemu_fseek(QEMUFile *f, int64_t pos, int whence);
525
526 typedef void SaveStateHandler(QEMUFile *f, void *opaque);
527 typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id);
528
529 int register_savevm(const char *idstr,
530 int instance_id,
531 int version_id,
532 SaveStateHandler *save_state,
533 LoadStateHandler *load_state,
534 void *opaque);
535 void qemu_get_timer(QEMUFile *f, QEMUTimer *ts);
536 void qemu_put_timer(QEMUFile *f, QEMUTimer *ts);
537
538 void cpu_save(QEMUFile *f, void *opaque);
539 int cpu_load(QEMUFile *f, void *opaque, int version_id);
540
541 void do_savevm(const char *name);
542 void do_loadvm(const char *name);
543 void do_delvm(const char *name);
544 void do_info_snapshots(void);
545
546 /* bottom halves */
547 typedef void QEMUBHFunc(void *opaque);
548
549 QEMUBH *qemu_bh_new(QEMUBHFunc *cb, void *opaque);
550 void qemu_bh_schedule(QEMUBH *bh);
551 void qemu_bh_cancel(QEMUBH *bh);
552 void qemu_bh_delete(QEMUBH *bh);
553 int qemu_bh_poll(void);
554
555 /* block.c */
556 typedef struct BlockDriverState BlockDriverState;
557 typedef struct BlockDriver BlockDriver;
558
559 extern BlockDriver bdrv_raw;
560 extern BlockDriver bdrv_host_device;
561 extern BlockDriver bdrv_cow;
562 extern BlockDriver bdrv_qcow;
563 extern BlockDriver bdrv_vmdk;
564 extern BlockDriver bdrv_cloop;
565 extern BlockDriver bdrv_dmg;
566 extern BlockDriver bdrv_bochs;
567 extern BlockDriver bdrv_vpc;
568 extern BlockDriver bdrv_vvfat;
569 extern BlockDriver bdrv_qcow2;
570
571 typedef struct BlockDriverInfo {
572 /* in bytes, 0 if irrelevant */
573 int cluster_size;
574 /* offset at which the VM state can be saved (0 if not possible) */
575 int64_t vm_state_offset;
576 } BlockDriverInfo;
577
578 typedef struct QEMUSnapshotInfo {
579 char id_str[128]; /* unique snapshot id */
580 /* the following fields are informative. They are not needed for
581 the consistency of the snapshot */
582 char name[256]; /* user choosen name */
583 uint32_t vm_state_size; /* VM state info size */
584 uint32_t date_sec; /* UTC date of the snapshot */
585 uint32_t date_nsec;
586 uint64_t vm_clock_nsec; /* VM clock relative to boot */
587 } QEMUSnapshotInfo;
588
589 #define BDRV_O_RDONLY 0x0000
590 #define BDRV_O_RDWR 0x0002
591 #define BDRV_O_ACCESS 0x0003
592 #define BDRV_O_CREAT 0x0004 /* create an empty file */
593 #define BDRV_O_SNAPSHOT 0x0008 /* open the file read only and save writes in a snapshot */
594 #define BDRV_O_FILE 0x0010 /* open as a raw file (do not try to
595 use a disk image format on top of
596 it (default for
597 bdrv_file_open()) */
598
599 void bdrv_init(void);
600 BlockDriver *bdrv_find_format(const char *format_name);
601 int bdrv_create(BlockDriver *drv,
602 const char *filename, int64_t size_in_sectors,
603 const char *backing_file, int flags);
604 BlockDriverState *bdrv_new(const char *device_name);
605 void bdrv_delete(BlockDriverState *bs);
606 int bdrv_file_open(BlockDriverState **pbs, const char *filename, int flags);
607 int bdrv_open(BlockDriverState *bs, const char *filename, int flags);
608 int bdrv_open2(BlockDriverState *bs, const char *filename, int flags,
609 BlockDriver *drv);
610 void bdrv_close(BlockDriverState *bs);
611 int bdrv_read(BlockDriverState *bs, int64_t sector_num,
612 uint8_t *buf, int nb_sectors);
613 int bdrv_write(BlockDriverState *bs, int64_t sector_num,
614 const uint8_t *buf, int nb_sectors);
615 int bdrv_pread(BlockDriverState *bs, int64_t offset,
616 void *buf, int count);
617 int bdrv_pwrite(BlockDriverState *bs, int64_t offset,
618 const void *buf, int count);
619 int bdrv_truncate(BlockDriverState *bs, int64_t offset);
620 int64_t bdrv_getlength(BlockDriverState *bs);
621 void bdrv_get_geometry(BlockDriverState *bs, int64_t *nb_sectors_ptr);
622 int bdrv_commit(BlockDriverState *bs);
623 void bdrv_set_boot_sector(BlockDriverState *bs, const uint8_t *data, int size);
624 /* async block I/O */
625 typedef struct BlockDriverAIOCB BlockDriverAIOCB;
626 typedef void BlockDriverCompletionFunc(void *opaque, int ret);
627
628 BlockDriverAIOCB *bdrv_aio_read(BlockDriverState *bs, int64_t sector_num,
629 uint8_t *buf, int nb_sectors,
630 BlockDriverCompletionFunc *cb, void *opaque);
631 BlockDriverAIOCB *bdrv_aio_write(BlockDriverState *bs, int64_t sector_num,
632 const uint8_t *buf, int nb_sectors,
633 BlockDriverCompletionFunc *cb, void *opaque);
634 void bdrv_aio_cancel(BlockDriverAIOCB *acb);
635
636 void qemu_aio_init(void);
637 void qemu_aio_poll(void);
638 void qemu_aio_flush(void);
639 void qemu_aio_wait_start(void);
640 void qemu_aio_wait(void);
641 void qemu_aio_wait_end(void);
642
643 int qemu_key_check(BlockDriverState *bs, const char *name);
644
645 /* Ensure contents are flushed to disk. */
646 void bdrv_flush(BlockDriverState *bs);
647
648 #define BDRV_TYPE_HD 0
649 #define BDRV_TYPE_CDROM 1
650 #define BDRV_TYPE_FLOPPY 2
651 #define BIOS_ATA_TRANSLATION_AUTO 0
652 #define BIOS_ATA_TRANSLATION_NONE 1
653 #define BIOS_ATA_TRANSLATION_LBA 2
654 #define BIOS_ATA_TRANSLATION_LARGE 3
655 #define BIOS_ATA_TRANSLATION_RECHS 4
656
657 void bdrv_set_geometry_hint(BlockDriverState *bs,
658 int cyls, int heads, int secs);
659 void bdrv_set_type_hint(BlockDriverState *bs, int type);
660 void bdrv_set_translation_hint(BlockDriverState *bs, int translation);
661 void bdrv_get_geometry_hint(BlockDriverState *bs,
662 int *pcyls, int *pheads, int *psecs);
663 int bdrv_get_type_hint(BlockDriverState *bs);
664 int bdrv_get_translation_hint(BlockDriverState *bs);
665 int bdrv_is_removable(BlockDriverState *bs);
666 int bdrv_is_read_only(BlockDriverState *bs);
667 int bdrv_is_inserted(BlockDriverState *bs);
668 int bdrv_media_changed(BlockDriverState *bs);
669 int bdrv_is_locked(BlockDriverState *bs);
670 void bdrv_set_locked(BlockDriverState *bs, int locked);
671 void bdrv_eject(BlockDriverState *bs, int eject_flag);
672 void bdrv_set_change_cb(BlockDriverState *bs,
673 void (*change_cb)(void *opaque), void *opaque);
674 void bdrv_get_format(BlockDriverState *bs, char *buf, int buf_size);
675 void bdrv_info(void);
676 BlockDriverState *bdrv_find(const char *name);
677 void bdrv_iterate(void (*it)(void *opaque, const char *name), void *opaque);
678 int bdrv_is_encrypted(BlockDriverState *bs);
679 int bdrv_set_key(BlockDriverState *bs, const char *key);
680 void bdrv_iterate_format(void (*it)(void *opaque, const char *name),
681 void *opaque);
682 const char *bdrv_get_device_name(BlockDriverState *bs);
683 int bdrv_write_compressed(BlockDriverState *bs, int64_t sector_num,
684 const uint8_t *buf, int nb_sectors);
685 int bdrv_get_info(BlockDriverState *bs, BlockDriverInfo *bdi);
686
687 void bdrv_get_backing_filename(BlockDriverState *bs,
688 char *filename, int filename_size);
689 int bdrv_snapshot_create(BlockDriverState *bs,
690 QEMUSnapshotInfo *sn_info);
691 int bdrv_snapshot_goto(BlockDriverState *bs,
692 const char *snapshot_id);
693 int bdrv_snapshot_delete(BlockDriverState *bs, const char *snapshot_id);
694 int bdrv_snapshot_list(BlockDriverState *bs,
695 QEMUSnapshotInfo **psn_info);
696 char *bdrv_snapshot_dump(char *buf, int buf_size, QEMUSnapshotInfo *sn);
697
698 char *get_human_readable_size(char *buf, int buf_size, int64_t size);
699 int path_is_absolute(const char *path);
700 void path_combine(char *dest, int dest_size,
701 const char *base_path,
702 const char *filename);
703
704 #ifndef QEMU_TOOL
705
706 typedef void QEMUMachineInitFunc(int ram_size, int vga_ram_size,
707 int boot_device,
708 DisplayState *ds, const char **fd_filename, int snapshot,
709 const char *kernel_filename, const char *kernel_cmdline,
710 const char *initrd_filename, const char *cpu_model);
711
712 typedef struct QEMUMachine {
713 const char *name;
714 const char *desc;
715 QEMUMachineInitFunc *init;
716 struct QEMUMachine *next;
717 } QEMUMachine;
718
719 int qemu_register_machine(QEMUMachine *m);
720
721 typedef void SetIRQFunc(void *opaque, int irq_num, int level);
722
723 #if defined(TARGET_PPC)
724 void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
725 #endif
726
727 #if defined(TARGET_MIPS)
728 void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
729 #endif
730
731 #include "hw/irq.h"
732
733 /* ISA bus */
734
735 extern target_phys_addr_t isa_mem_base;
736
737 typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data);
738 typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address);
739
740 int register_ioport_read(int start, int length, int size,
741 IOPortReadFunc *func, void *opaque);
742 int register_ioport_write(int start, int length, int size,
743 IOPortWriteFunc *func, void *opaque);
744 void isa_unassign_ioport(int start, int length);
745
746 void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
747
748 /* PCI bus */
749
750 extern target_phys_addr_t pci_mem_base;
751
752 typedef struct PCIBus PCIBus;
753 typedef struct PCIDevice PCIDevice;
754
755 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
756 uint32_t address, uint32_t data, int len);
757 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
758 uint32_t address, int len);
759 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
760 uint32_t addr, uint32_t size, int type);
761
762 #define PCI_ADDRESS_SPACE_MEM 0x00
763 #define PCI_ADDRESS_SPACE_IO 0x01
764 #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
765
766 typedef struct PCIIORegion {
767 uint32_t addr; /* current PCI mapping address. -1 means not mapped */
768 uint32_t size;
769 uint8_t type;
770 PCIMapIORegionFunc *map_func;
771 } PCIIORegion;
772
773 #define PCI_ROM_SLOT 6
774 #define PCI_NUM_REGIONS 7
775
776 #define PCI_DEVICES_MAX 64
777
778 #define PCI_VENDOR_ID 0x00 /* 16 bits */
779 #define PCI_DEVICE_ID 0x02 /* 16 bits */
780 #define PCI_COMMAND 0x04 /* 16 bits */
781 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
782 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
783 #define PCI_CLASS_DEVICE 0x0a /* Device class */
784 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
785 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
786 #define PCI_MIN_GNT 0x3e /* 8 bits */
787 #define PCI_MAX_LAT 0x3f /* 8 bits */
788
789 struct PCIDevice {
790 /* PCI config space */
791 uint8_t config[256];
792
793 /* the following fields are read only */
794 PCIBus *bus;
795 int devfn;
796 char name[64];
797 PCIIORegion io_regions[PCI_NUM_REGIONS];
798
799 /* do not access the following fields */
800 PCIConfigReadFunc *config_read;
801 PCIConfigWriteFunc *config_write;
802 /* ??? This is a PC-specific hack, and should be removed. */
803 int irq_index;
804
805 /* IRQ objects for the INTA-INTD pins. */
806 qemu_irq *irq;
807
808 /* Current IRQ levels. Used internally by the generic PCI code. */
809 int irq_state[4];
810 };
811
812 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
813 int instance_size, int devfn,
814 PCIConfigReadFunc *config_read,
815 PCIConfigWriteFunc *config_write);
816
817 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
818 uint32_t size, int type,
819 PCIMapIORegionFunc *map_func);
820
821 uint32_t pci_default_read_config(PCIDevice *d,
822 uint32_t address, int len);
823 void pci_default_write_config(PCIDevice *d,
824 uint32_t address, uint32_t val, int len);
825 void pci_device_save(PCIDevice *s, QEMUFile *f);
826 int pci_device_load(PCIDevice *s, QEMUFile *f);
827
828 typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
829 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
830 PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
831 qemu_irq *pic, int devfn_min, int nirq);
832
833 void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn);
834 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
835 uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
836 int pci_bus_num(PCIBus *s);
837 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
838
839 void pci_info(void);
840 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
841 pci_map_irq_fn map_irq, const char *name);
842
843 /* prep_pci.c */
844 PCIBus *pci_prep_init(qemu_irq *pic);
845
846 /* grackle_pci.c */
847 PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic);
848
849 /* unin_pci.c */
850 PCIBus *pci_pmac_init(qemu_irq *pic);
851
852 /* apb_pci.c */
853 PCIBus *pci_apb_init(target_ulong special_base, target_ulong mem_base,
854 qemu_irq *pic);
855
856 PCIBus *pci_vpb_init(qemu_irq *pic, int irq, int realview);
857
858 /* piix_pci.c */
859 PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic);
860 void i440fx_set_smm(PCIDevice *d, int val);
861 int piix3_init(PCIBus *bus, int devfn);
862 void i440fx_init_memory_mappings(PCIDevice *d);
863
864 int piix4_init(PCIBus *bus, int devfn);
865
866 /* openpic.c */
867 /* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
868 enum {
869 OPENPIC_OUTPUT_INT = 0, /* IRQ */
870 OPENPIC_OUTPUT_CINT, /* critical IRQ */
871 OPENPIC_OUTPUT_MCK, /* Machine check event */
872 OPENPIC_OUTPUT_DEBUG, /* Inconditional debug event */
873 OPENPIC_OUTPUT_RESET, /* Core reset event */
874 OPENPIC_OUTPUT_NB,
875 };
876 qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
877 qemu_irq **irqs, qemu_irq irq_out);
878
879 /* heathrow_pic.c */
880 qemu_irq *heathrow_pic_init(int *pmem_index);
881
882 /* gt64xxx.c */
883 PCIBus *pci_gt64120_init(qemu_irq *pic);
884
885 #ifdef HAS_AUDIO
886 struct soundhw {
887 const char *name;
888 const char *descr;
889 int enabled;
890 int isa;
891 union {
892 int (*init_isa) (AudioState *s, qemu_irq *pic);
893 int (*init_pci) (PCIBus *bus, AudioState *s);
894 } init;
895 };
896
897 extern struct soundhw soundhw[];
898 #endif
899
900 /* vga.c */
901
902 #ifndef TARGET_SPARC
903 #define VGA_RAM_SIZE (8192 * 1024)
904 #else
905 #define VGA_RAM_SIZE (9 * 1024 * 1024)
906 #endif
907
908 struct DisplayState {
909 uint8_t *data;
910 int linesize;
911 int depth;
912 int bgr; /* BGR color order instead of RGB. Only valid for depth == 32 */
913 int width;
914 int height;
915 void *opaque;
916
917 void (*dpy_update)(struct DisplayState *s, int x, int y, int w, int h);
918 void (*dpy_resize)(struct DisplayState *s, int w, int h);
919 void (*dpy_refresh)(struct DisplayState *s);
920 void (*dpy_copy)(struct DisplayState *s, int src_x, int src_y,
921 int dst_x, int dst_y, int w, int h);
922 void (*dpy_fill)(struct DisplayState *s, int x, int y,
923 int w, int h, uint32_t c);
924 void (*mouse_set)(int x, int y, int on);
925 void (*cursor_define)(int width, int height, int bpp, int hot_x, int hot_y,
926 uint8_t *image, uint8_t *mask);
927 };
928
929 static inline void dpy_update(DisplayState *s, int x, int y, int w, int h)
930 {
931 s->dpy_update(s, x, y, w, h);
932 }
933
934 static inline void dpy_resize(DisplayState *s, int w, int h)
935 {
936 s->dpy_resize(s, w, h);
937 }
938
939 int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
940 unsigned long vga_ram_offset, int vga_ram_size);
941 int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
942 unsigned long vga_ram_offset, int vga_ram_size,
943 unsigned long vga_bios_offset, int vga_bios_size);
944 int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
945 unsigned long vga_ram_offset, int vga_ram_size,
946 target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
947 int it_shift);
948
949 /* cirrus_vga.c */
950 void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
951 unsigned long vga_ram_offset, int vga_ram_size);
952 void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
953 unsigned long vga_ram_offset, int vga_ram_size);
954
955 /* vmware_vga.c */
956 void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
957 unsigned long vga_ram_offset, int vga_ram_size);
958
959 /* sdl.c */
960 void sdl_display_init(DisplayState *ds, int full_screen, int no_frame);
961
962 /* cocoa.m */
963 void cocoa_display_init(DisplayState *ds, int full_screen);
964
965 /* vnc.c */
966 void vnc_display_init(DisplayState *ds, const char *display);
967 void do_info_vnc(void);
968
969 /* x_keymap.c */
970 extern uint8_t _translate_keycode(const int key);
971
972 /* ide.c */
973 #define MAX_DISKS 4
974
975 extern BlockDriverState *bs_table[MAX_DISKS + 1];
976 extern BlockDriverState *sd_bdrv;
977 extern BlockDriverState *mtd_bdrv;
978
979 void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
980 BlockDriverState *hd0, BlockDriverState *hd1);
981 void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
982 int secondary_ide_enabled);
983 void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
984 qemu_irq *pic);
985 int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq);
986
987 /* cdrom.c */
988 int cdrom_read_toc(int nb_sectors, uint8_t *buf, int msf, int start_track);
989 int cdrom_read_toc_raw(int nb_sectors, uint8_t *buf, int msf, int session_num);
990
991 /* ds1225y.c */
992 typedef struct ds1225y_t ds1225y_t;
993 ds1225y_t *ds1225y_init(target_ulong mem_base, const char *filename);
994
995 /* es1370.c */
996 int es1370_init (PCIBus *bus, AudioState *s);
997
998 /* sb16.c */
999 int SB16_init (AudioState *s, qemu_irq *pic);
1000
1001 /* adlib.c */
1002 int Adlib_init (AudioState *s, qemu_irq *pic);
1003
1004 /* gus.c */
1005 int GUS_init (AudioState *s, qemu_irq *pic);
1006
1007 /* dma.c */
1008 typedef int (*DMA_transfer_handler) (void *opaque, int nchan, int pos, int size);
1009 int DMA_get_channel_mode (int nchan);
1010 int DMA_read_memory (int nchan, void *buf, int pos, int size);
1011 int DMA_write_memory (int nchan, void *buf, int pos, int size);
1012 void DMA_hold_DREQ (int nchan);
1013 void DMA_release_DREQ (int nchan);
1014 void DMA_schedule(int nchan);
1015 void DMA_run (void);
1016 void DMA_init (int high_page_enable);
1017 void DMA_register_channel (int nchan,
1018 DMA_transfer_handler transfer_handler,
1019 void *opaque);
1020 /* fdc.c */
1021 #define MAX_FD 2
1022 extern BlockDriverState *fd_table[MAX_FD];
1023
1024 typedef struct fdctrl_t fdctrl_t;
1025
1026 fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
1027 target_phys_addr_t io_base,
1028 BlockDriverState **fds);
1029 int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num);
1030
1031 /* eepro100.c */
1032
1033 void pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn);
1034 void pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn);
1035 void pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn);
1036
1037 /* ne2000.c */
1038
1039 void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd);
1040 void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);
1041
1042 /* rtl8139.c */
1043
1044 void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
1045
1046 /* pcnet.c */
1047
1048 void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
1049 void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
1050 qemu_irq irq);
1051
1052 /* vmmouse.c */
1053 void *vmmouse_init(void *m);
1054
1055 /* pckbd.c */
1056
1057 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
1058 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq, target_ulong base, int it_shift);
1059
1060 /* mc146818rtc.c */
1061
1062 typedef struct RTCState RTCState;
1063
1064 RTCState *rtc_init(int base, qemu_irq irq);
1065 RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq);
1066 void rtc_set_memory(RTCState *s, int addr, int val);
1067 void rtc_set_date(RTCState *s, const struct tm *tm);
1068
1069 /* serial.c */
1070
1071 typedef struct SerialState SerialState;
1072 SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr);
1073 SerialState *serial_mm_init (target_ulong base, int it_shift,
1074 qemu_irq irq, CharDriverState *chr,
1075 int ioregister);
1076 uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
1077 void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
1078 uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
1079 void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value);
1080 uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
1081 void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value);
1082
1083 /* parallel.c */
1084
1085 typedef struct ParallelState ParallelState;
1086 ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
1087
1088 /* i8259.c */
1089
1090 typedef struct PicState2 PicState2;
1091 extern PicState2 *isa_pic;
1092 void pic_set_irq(int irq, int level);
1093 void pic_set_irq_new(void *opaque, int irq, int level);
1094 qemu_irq *i8259_init(qemu_irq parent_irq);
1095 void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
1096 void *alt_irq_opaque);
1097 int pic_read_irq(PicState2 *s);
1098 void pic_update_irq(PicState2 *s);
1099 uint32_t pic_intack_read(PicState2 *s);
1100 void pic_info(void);
1101 void irq_info(void);
1102
1103 /* APIC */
1104 typedef struct IOAPICState IOAPICState;
1105
1106 int apic_init(CPUState *env);
1107 int apic_get_interrupt(CPUState *env);
1108 IOAPICState *ioapic_init(void);
1109 void ioapic_set_irq(void *opaque, int vector, int level);
1110
1111 /* i8254.c */
1112
1113 #define PIT_FREQ 1193182
1114
1115 typedef struct PITState PITState;
1116
1117 PITState *pit_init(int base, qemu_irq irq);
1118 void pit_set_gate(PITState *pit, int channel, int val);
1119 int pit_get_gate(PITState *pit, int channel);
1120 int pit_get_initial_count(PITState *pit, int channel);
1121 int pit_get_mode(PITState *pit, int channel);
1122 int pit_get_out(PITState *pit, int channel, int64_t current_time);
1123
1124 /* pcspk.c */
1125 void pcspk_init(PITState *);
1126 int pcspk_audio_init(AudioState *, qemu_irq *pic);
1127
1128 #include "hw/i2c.h"
1129
1130 #include "hw/smbus.h"
1131
1132 /* acpi.c */
1133 extern int acpi_enabled;
1134 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn);
1135 void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
1136 void acpi_bios_init(void);
1137
1138 /* pc.c */
1139 extern QEMUMachine pc_machine;
1140 extern QEMUMachine isapc_machine;
1141 extern int fd_bootchk;
1142
1143 void ioport_set_a20(int enable);
1144 int ioport_get_a20(void);
1145
1146 /* ppc.c */
1147 extern QEMUMachine prep_machine;
1148 extern QEMUMachine core99_machine;
1149 extern QEMUMachine heathrow_machine;
1150 extern QEMUMachine ref405ep_machine;
1151 extern QEMUMachine taihu_machine;
1152
1153 /* mips_r4k.c */
1154 extern QEMUMachine mips_machine;
1155
1156 /* mips_malta.c */
1157 extern QEMUMachine mips_malta_machine;
1158
1159 /* mips_int.c */
1160 extern void cpu_mips_irq_init_cpu(CPUState *env);
1161
1162 /* mips_pica61.c */
1163 extern QEMUMachine mips_pica61_machine;
1164
1165 /* mips_timer.c */
1166 extern void cpu_mips_clock_init(CPUState *);
1167 extern void cpu_mips_irqctrl_init (void);
1168
1169 /* shix.c */
1170 extern QEMUMachine shix_machine;
1171
1172 #ifdef TARGET_PPC
1173 /* PowerPC hardware exceptions management helpers */
1174 typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
1175 typedef struct clk_setup_t clk_setup_t;
1176 struct clk_setup_t {
1177 clk_setup_cb cb;
1178 void *opaque;
1179 };
1180 static inline void clk_setup (clk_setup_t *clk, uint32_t freq)
1181 {
1182 if (clk->cb != NULL)
1183 (*clk->cb)(clk->opaque, freq);
1184 }
1185
1186 clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq);
1187 /* Embedded PowerPC DCR management */
1188 typedef target_ulong (*dcr_read_cb)(void *opaque, int dcrn);
1189 typedef void (*dcr_write_cb)(void *opaque, int dcrn, target_ulong val);
1190 int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn),
1191 int (*dcr_write_error)(int dcrn));
1192 int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
1193 dcr_read_cb drc_read, dcr_write_cb dcr_write);
1194 clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq);
1195 /* Embedded PowerPC reset */
1196 void ppc40x_core_reset (CPUState *env);
1197 void ppc40x_chip_reset (CPUState *env);
1198 void ppc40x_system_reset (CPUState *env);
1199 #endif
1200 void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
1201
1202 extern CPUWriteMemoryFunc *PPC_io_write[];
1203 extern CPUReadMemoryFunc *PPC_io_read[];
1204 void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
1205
1206 /* sun4m.c */
1207 extern QEMUMachine ss5_machine, ss10_machine;
1208
1209 /* iommu.c */
1210 void *iommu_init(target_phys_addr_t addr);
1211 void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
1212 uint8_t *buf, int len, int is_write);
1213 static inline void sparc_iommu_memory_read(void *opaque,
1214 target_phys_addr_t addr,
1215 uint8_t *buf, int len)
1216 {
1217 sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
1218 }
1219
1220 static inline void sparc_iommu_memory_write(void *opaque,
1221 target_phys_addr_t addr,
1222 uint8_t *buf, int len)
1223 {
1224 sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
1225 }
1226
1227 /* tcx.c */
1228 void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
1229 unsigned long vram_offset, int vram_size, int width, int height,
1230 int depth);
1231
1232 /* slavio_intctl.c */
1233 void pic_set_irq_cpu(void *opaque, int irq, int level, unsigned int cpu);
1234 void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
1235 const uint32_t *intbit_to_level,
1236 qemu_irq **irq);
1237 void slavio_intctl_set_cpu(void *opaque, unsigned int cpu, CPUState *env);
1238 void slavio_pic_info(void *opaque);
1239 void slavio_irq_info(void *opaque);
1240
1241 /* loader.c */
1242 int get_image_size(const char *filename);
1243 int load_image(const char *filename, uint8_t *addr);
1244 int load_elf(const char *filename, int64_t virt_to_phys_addend,
1245 uint64_t *pentry, uint64_t *lowaddr, uint64_t *highaddr);
1246 int load_aout(const char *filename, uint8_t *addr);
1247 int load_uboot(const char *filename, target_ulong *ep, int *is_linux);
1248
1249 /* slavio_timer.c */
1250 void slavio_timer_init(target_phys_addr_t addr, int irq, int mode,
1251 unsigned int cpu, void *intctl);
1252
1253 /* slavio_serial.c */
1254 SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq,
1255 CharDriverState *chr1, CharDriverState *chr2);
1256 void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq);
1257
1258 /* slavio_misc.c */
1259 void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
1260 qemu_irq irq);
1261 void slavio_set_power_fail(void *opaque, int power_failing);
1262
1263 /* esp.c */
1264 void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1265 void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr,
1266 void *dma_opaque, qemu_irq irq);
1267
1268 /* sparc32_dma.c */
1269 void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
1270 void *iommu, qemu_irq **dev_irq);
1271 void ledma_memory_read(void *opaque, target_phys_addr_t addr,
1272 uint8_t *buf, int len, int do_bswap);
1273 void ledma_memory_write(void *opaque, target_phys_addr_t addr,
1274 uint8_t *buf, int len, int do_bswap);
1275 void espdma_memory_read(void *opaque, uint8_t *buf, int len);
1276 void espdma_memory_write(void *opaque, uint8_t *buf, int len);
1277 void sparc32_dma_set_reset_data(void *opaque, void (*dev_reset)(void *opaque),
1278 void *dev_opaque);
1279
1280 /* cs4231.c */
1281 void cs_init(target_phys_addr_t base, int irq, void *intctl);
1282
1283 /* sun4u.c */
1284 extern QEMUMachine sun4u_machine;
1285
1286 /* NVRAM helpers */
1287 #include "hw/m48t59.h"
1288
1289 void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value);
1290 uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr);
1291 void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value);
1292 uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr);
1293 void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value);
1294 uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr);
1295 void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
1296 const unsigned char *str, uint32_t max);
1297 int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max);
1298 void NVRAM_set_crc (m48t59_t *nvram, uint32_t addr,
1299 uint32_t start, uint32_t count);
1300 int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
1301 const unsigned char *arch,
1302 uint32_t RAM_size, int boot_device,
1303 uint32_t kernel_image, uint32_t kernel_size,
1304 const char *cmdline,
1305 uint32_t initrd_image, uint32_t initrd_size,
1306 uint32_t NVRAM_image,
1307 int width, int height, int depth);
1308
1309 /* adb.c */
1310
1311 #define MAX_ADB_DEVICES 16
1312
1313 #define ADB_MAX_OUT_LEN 16
1314
1315 typedef struct ADBDevice ADBDevice;
1316
1317 /* buf = NULL means polling */
1318 typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out,
1319 const uint8_t *buf, int len);
1320 typedef int ADBDeviceReset(ADBDevice *d);
1321
1322 struct ADBDevice {
1323 struct ADBBusState *bus;
1324 int devaddr;
1325 int handler;
1326 ADBDeviceRequest *devreq;
1327 ADBDeviceReset *devreset;
1328 void *opaque;
1329 };
1330
1331 typedef struct ADBBusState {
1332 ADBDevice devices[MAX_ADB_DEVICES];
1333 int nb_devices;
1334 int poll_index;
1335 } ADBBusState;
1336
1337 int adb_request(ADBBusState *s, uint8_t *buf_out,
1338 const uint8_t *buf, int len);
1339 int adb_poll(ADBBusState *s, uint8_t *buf_out);
1340
1341 ADBDevice *adb_register_device(ADBBusState *s, int devaddr,
1342 ADBDeviceRequest *devreq,
1343 ADBDeviceReset *devreset,
1344 void *opaque);
1345 void adb_kbd_init(ADBBusState *bus);
1346 void adb_mouse_init(ADBBusState *bus);
1347
1348 /* cuda.c */
1349
1350 extern ADBBusState adb_bus;
1351 int cuda_init(qemu_irq irq);
1352
1353 #include "hw/usb.h"
1354
1355 /* usb ports of the VM */
1356
1357 void qemu_register_usb_port(USBPort *port, void *opaque, int index,
1358 usb_attachfn attach);
1359
1360 #define VM_USB_HUB_SIZE 8
1361
1362 void do_usb_add(const char *devname);
1363 void do_usb_del(const char *devname);
1364 void usb_info(void);
1365
1366 /* scsi-disk.c */
1367 enum scsi_reason {
1368 SCSI_REASON_DONE, /* Command complete. */
1369 SCSI_REASON_DATA /* Transfer complete, more data required. */
1370 };
1371
1372 typedef struct SCSIDevice SCSIDevice;
1373 typedef void (*scsi_completionfn)(void *opaque, int reason, uint32_t tag,
1374 uint32_t arg);
1375
1376 SCSIDevice *scsi_disk_init(BlockDriverState *bdrv,
1377 int tcq,
1378 scsi_completionfn completion,
1379 void *opaque);
1380 void scsi_disk_destroy(SCSIDevice *s);
1381
1382 int32_t scsi_send_command(SCSIDevice *s, uint32_t tag, uint8_t *buf, int lun);
1383 /* SCSI data transfers are asynchrnonous. However, unlike the block IO
1384 layer the completion routine may be called directly by
1385 scsi_{read,write}_data. */
1386 void scsi_read_data(SCSIDevice *s, uint32_t tag);
1387 int scsi_write_data(SCSIDevice *s, uint32_t tag);
1388 void scsi_cancel_io(SCSIDevice *s, uint32_t tag);
1389 uint8_t *scsi_get_buf(SCSIDevice *s, uint32_t tag);
1390
1391 /* lsi53c895a.c */
1392 void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1393 void *lsi_scsi_init(PCIBus *bus, int devfn);
1394
1395 /* integratorcp.c */
1396 extern QEMUMachine integratorcp_machine;
1397
1398 /* versatilepb.c */
1399 extern QEMUMachine versatilepb_machine;
1400 extern QEMUMachine versatileab_machine;
1401
1402 /* realview.c */
1403 extern QEMUMachine realview_machine;
1404
1405 /* spitz.c */
1406 extern QEMUMachine akitapda_machine;
1407 extern QEMUMachine spitzpda_machine;
1408 extern QEMUMachine borzoipda_machine;
1409 extern QEMUMachine terrierpda_machine;
1410
1411 /* ps2.c */
1412 void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg);
1413 void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg);
1414 void ps2_write_mouse(void *, int val);
1415 void ps2_write_keyboard(void *, int val);
1416 uint32_t ps2_read_data(void *);
1417 void ps2_queue(void *, int b);
1418 void ps2_keyboard_set_translation(void *opaque, int mode);
1419 void ps2_mouse_fake_event(void *opaque);
1420
1421 /* smc91c111.c */
1422 void smc91c111_init(NICInfo *, uint32_t, qemu_irq);
1423
1424 /* pl110.c */
1425 void *pl110_init(DisplayState *ds, uint32_t base, qemu_irq irq, int);
1426
1427 /* pl011.c */
1428 void pl011_init(uint32_t base, qemu_irq irq, CharDriverState *chr);
1429
1430 /* pl050.c */
1431 void pl050_init(uint32_t base, qemu_irq irq, int is_mouse);
1432
1433 /* pl080.c */
1434 void *pl080_init(uint32_t base, qemu_irq irq, int nchannels);
1435
1436 /* pl181.c */
1437 void pl181_init(uint32_t base, BlockDriverState *bd,
1438 qemu_irq irq0, qemu_irq irq1);
1439
1440 /* pl190.c */
1441 qemu_irq *pl190_init(uint32_t base, qemu_irq irq, qemu_irq fiq);
1442
1443 /* arm-timer.c */
1444 void sp804_init(uint32_t base, qemu_irq irq);
1445 void icp_pit_init(uint32_t base, qemu_irq *pic, int irq);
1446
1447 /* arm_sysctl.c */
1448 void arm_sysctl_init(uint32_t base, uint32_t sys_id);
1449
1450 /* arm_gic.c */
1451 qemu_irq *arm_gic_init(uint32_t base, qemu_irq parent_irq);
1452
1453 /* arm_boot.c */
1454
1455 void arm_load_kernel(CPUState *env, int ram_size, const char *kernel_filename,
1456 const char *kernel_cmdline, const char *initrd_filename,
1457 int board_id, target_phys_addr_t loader_start);
1458
1459 /* sh7750.c */
1460 struct SH7750State;
1461
1462 struct SH7750State *sh7750_init(CPUState * cpu);
1463
1464 typedef struct {
1465 /* The callback will be triggered if any of the designated lines change */
1466 uint16_t portamask_trigger;
1467 uint16_t portbmask_trigger;
1468 /* Return 0 if no action was taken */
1469 int (*port_change_cb) (uint16_t porta, uint16_t portb,
1470 uint16_t * periph_pdtra,
1471 uint16_t * periph_portdira,
1472 uint16_t * periph_pdtrb,
1473 uint16_t * periph_portdirb);
1474 } sh7750_io_device;
1475
1476 int sh7750_register_io_device(struct SH7750State *s,
1477 sh7750_io_device * device);
1478 /* tc58128.c */
1479 int tc58128_init(struct SH7750State *s, char *zone1, char *zone2);
1480
1481 /* NOR flash devices */
1482 #define MAX_PFLASH 4
1483 extern BlockDriverState *pflash_table[MAX_PFLASH];
1484 typedef struct pflash_t pflash_t;
1485
1486 pflash_t *pflash_register (target_ulong base, ram_addr_t off,
1487 BlockDriverState *bs,
1488 target_ulong sector_len, int nb_blocs, int width,
1489 uint16_t id0, uint16_t id1,
1490 uint16_t id2, uint16_t id3);
1491
1492 /* nand.c */
1493 struct nand_flash_s;
1494 struct nand_flash_s *nand_init(int manf_id, int chip_id);
1495 void nand_done(struct nand_flash_s *s);
1496 void nand_setpins(struct nand_flash_s *s,
1497 int cle, int ale, int ce, int wp, int gnd);
1498 void nand_getpins(struct nand_flash_s *s, int *rb);
1499 void nand_setio(struct nand_flash_s *s, uint8_t value);
1500 uint8_t nand_getio(struct nand_flash_s *s);
1501
1502 #define NAND_MFR_TOSHIBA 0x98
1503 #define NAND_MFR_SAMSUNG 0xec
1504 #define NAND_MFR_FUJITSU 0x04
1505 #define NAND_MFR_NATIONAL 0x8f
1506 #define NAND_MFR_RENESAS 0x07
1507 #define NAND_MFR_STMICRO 0x20
1508 #define NAND_MFR_HYNIX 0xad
1509 #define NAND_MFR_MICRON 0x2c
1510
1511 #include "ecc.h"
1512
1513 /* GPIO */
1514 typedef void (*gpio_handler_t)(int line, int level, void *opaque);
1515
1516 /* ads7846.c */
1517 struct ads7846_state_s;
1518 uint32_t ads7846_read(void *opaque);
1519 void ads7846_write(void *opaque, uint32_t value);
1520 struct ads7846_state_s *ads7846_init(qemu_irq penirq);
1521
1522 /* max111x.c */
1523 struct max111x_s;
1524 uint32_t max111x_read(void *opaque);
1525 void max111x_write(void *opaque, uint32_t value);
1526 struct max111x_s *max1110_init(qemu_irq cb);
1527 struct max111x_s *max1111_init(qemu_irq cb);
1528 void max111x_set_input(struct max111x_s *s, int line, uint8_t value);
1529
1530 /* PCMCIA/Cardbus */
1531
1532 struct pcmcia_socket_s {
1533 qemu_irq irq;
1534 int attached;
1535 const char *slot_string;
1536 const char *card_string;
1537 };
1538
1539 void pcmcia_socket_register(struct pcmcia_socket_s *socket);
1540 void pcmcia_socket_unregister(struct pcmcia_socket_s *socket);
1541 void pcmcia_info(void);
1542
1543 struct pcmcia_card_s {
1544 void *state;
1545 struct pcmcia_socket_s *slot;
1546 int (*attach)(void *state);
1547 int (*detach)(void *state);
1548 const uint8_t *cis;
1549 int cis_len;
1550
1551 /* Only valid if attached */
1552 uint8_t (*attr_read)(void *state, uint32_t address);
1553 void (*attr_write)(void *state, uint32_t address, uint8_t value);
1554 uint16_t (*common_read)(void *state, uint32_t address);
1555 void (*common_write)(void *state, uint32_t address, uint16_t value);
1556 uint16_t (*io_read)(void *state, uint32_t address);
1557 void (*io_write)(void *state, uint32_t address, uint16_t value);
1558 };
1559
1560 #define CISTPL_DEVICE 0x01 /* 5V Device Information Tuple */
1561 #define CISTPL_NO_LINK 0x14 /* No Link Tuple */
1562 #define CISTPL_VERS_1 0x15 /* Level 1 Version Tuple */
1563 #define CISTPL_JEDEC_C 0x18 /* JEDEC ID Tuple */
1564 #define CISTPL_JEDEC_A 0x19 /* JEDEC ID Tuple */
1565 #define CISTPL_CONFIG 0x1a /* Configuration Tuple */
1566 #define CISTPL_CFTABLE_ENTRY 0x1b /* 16-bit PCCard Configuration */
1567 #define CISTPL_DEVICE_OC 0x1c /* Additional Device Information */
1568 #define CISTPL_DEVICE_OA 0x1d /* Additional Device Information */
1569 #define CISTPL_DEVICE_GEO 0x1e /* Additional Device Information */
1570 #define CISTPL_DEVICE_GEO_A 0x1f /* Additional Device Information */
1571 #define CISTPL_MANFID 0x20 /* Manufacture ID Tuple */
1572 #define CISTPL_FUNCID 0x21 /* Function ID Tuple */
1573 #define CISTPL_FUNCE 0x22 /* Function Extension Tuple */
1574 #define CISTPL_END 0xff /* Tuple End */
1575 #define CISTPL_ENDMARK 0xff
1576
1577 /* dscm1xxxx.c */
1578 struct pcmcia_card_s *dscm1xxxx_init(BlockDriverState *bdrv);
1579
1580 /* ptimer.c */
1581 typedef struct ptimer_state ptimer_state;
1582 typedef void (*ptimer_cb)(void *opaque);
1583
1584 ptimer_state *ptimer_init(QEMUBH *bh);
1585 void ptimer_set_period(ptimer_state *s, int64_t period);
1586 void ptimer_set_freq(ptimer_state *s, uint32_t freq);
1587 void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload);
1588 uint64_t ptimer_get_count(ptimer_state *s);
1589 void ptimer_set_count(ptimer_state *s, uint64_t count);
1590 void ptimer_run(ptimer_state *s, int oneshot);
1591 void ptimer_stop(ptimer_state *s);
1592 void qemu_put_ptimer(QEMUFile *f, ptimer_state *s);
1593 void qemu_get_ptimer(QEMUFile *f, ptimer_state *s);
1594
1595 #include "hw/pxa.h"
1596
1597 /* mcf5206.c */
1598 qemu_irq *mcf5206_init(uint32_t base, CPUState *env);
1599
1600 /* an5206.c */
1601 extern QEMUMachine an5206_machine;
1602
1603 #include "gdbstub.h"
1604
1605 #endif /* defined(QEMU_TOOL) */
1606
1607 /* monitor.c */
1608 void monitor_init(CharDriverState *hd, int show_banner);
1609 void term_puts(const char *str);
1610 void term_vprintf(const char *fmt, va_list ap);
1611 void term_printf(const char *fmt, ...) __attribute__ ((__format__ (__printf__, 1, 2)));
1612 void term_print_filename(const char *filename);
1613 void term_flush(void);
1614 void term_print_help(void);
1615 void monitor_readline(const char *prompt, int is_password,
1616 char *buf, int buf_size);
1617
1618 /* readline.c */
1619 typedef void ReadLineFunc(void *opaque, const char *str);
1620
1621 extern int completion_index;
1622 void add_completion(const char *str);
1623 void readline_handle_byte(int ch);
1624 void readline_find_completion(const char *cmdline);
1625 const char *readline_get_history(unsigned int index);
1626 void readline_start(const char *prompt, int is_password,
1627 ReadLineFunc *readline_func, void *opaque);
1628
1629 void kqemu_record_dump(void);
1630
1631 #endif /* VL_H */
Qemu copy for testing