]> git.proxmox.com Git - qemu.git/blob - vl.h
endianness functions for unaligned memory accesses
[qemu.git] / vl.h
1 /*
2 * QEMU System Emulator header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #ifndef VL_H
25 #define VL_H
26
27 /* we put basic includes here to avoid repeating them in device drivers */
28 #include <stdlib.h>
29 #include <stdio.h>
30 #include <stdarg.h>
31 #include <string.h>
32 #include <inttypes.h>
33 #include <time.h>
34 #include <ctype.h>
35 #include <errno.h>
36 #include <unistd.h>
37 #include <fcntl.h>
38 #include <sys/stat.h>
39
40 #ifndef O_LARGEFILE
41 #define O_LARGEFILE 0
42 #endif
43 #ifndef O_BINARY
44 #define O_BINARY 0
45 #endif
46
47 #ifdef _WIN32
48 #define lseek64 _lseeki64
49 #endif
50
51 #include "cpu.h"
52
53 #ifndef glue
54 #define xglue(x, y) x ## y
55 #define glue(x, y) xglue(x, y)
56 #define stringify(s) tostring(s)
57 #define tostring(s) #s
58 #endif
59
60 #if defined(WORDS_BIGENDIAN)
61 static inline uint32_t be32_to_cpu(uint32_t v)
62 {
63 return v;
64 }
65
66 static inline uint16_t be16_to_cpu(uint16_t v)
67 {
68 return v;
69 }
70
71 static inline uint32_t cpu_to_be32(uint32_t v)
72 {
73 return v;
74 }
75
76 static inline uint16_t cpu_to_be16(uint16_t v)
77 {
78 return v;
79 }
80
81 static inline uint32_t le32_to_cpu(uint32_t v)
82 {
83 return bswap32(v);
84 }
85
86 static inline uint16_t le16_to_cpu(uint16_t v)
87 {
88 return bswap16(v);
89 }
90
91 static inline uint32_t cpu_to_le32(uint32_t v)
92 {
93 return bswap32(v);
94 }
95
96 static inline uint16_t cpu_to_le16(uint16_t v)
97 {
98 return bswap16(v);
99 }
100
101 #else
102
103 static inline uint32_t be32_to_cpu(uint32_t v)
104 {
105 return bswap32(v);
106 }
107
108 static inline uint16_t be16_to_cpu(uint16_t v)
109 {
110 return bswap16(v);
111 }
112
113 static inline uint32_t cpu_to_be32(uint32_t v)
114 {
115 return bswap32(v);
116 }
117
118 static inline uint16_t cpu_to_be16(uint16_t v)
119 {
120 return bswap16(v);
121 }
122
123 static inline uint32_t le32_to_cpu(uint32_t v)
124 {
125 return v;
126 }
127
128 static inline uint16_t le16_to_cpu(uint16_t v)
129 {
130 return v;
131 }
132
133 static inline uint32_t cpu_to_le32(uint32_t v)
134 {
135 return v;
136 }
137
138 static inline uint16_t cpu_to_le16(uint16_t v)
139 {
140 return v;
141 }
142 #endif
143
144 static inline void cpu_to_le16w(uint16_t *p, uint16_t v)
145 {
146 *p = cpu_to_le16(v);
147 }
148
149 static inline void cpu_to_le32w(uint32_t *p, uint32_t v)
150 {
151 *p = cpu_to_le32(v);
152 }
153
154 static inline uint16_t le16_to_cpup(const uint16_t *p)
155 {
156 return le16_to_cpu(*p);
157 }
158
159 static inline uint32_t le32_to_cpup(const uint32_t *p)
160 {
161 return le32_to_cpu(*p);
162 }
163
164 /* unaligned versions (optimized for frequent unaligned accesses)*/
165
166 #if defined(__i386__) || defined(__powerpc__)
167
168 #define cpu_to_le16wu(p, v) cpu_to_le16w(p, v)
169 #define cpu_to_le32wu(p, v) cpu_to_le32w(p, v)
170 #define le16_to_cpupu(p) le16_to_cpup(p)
171 #define le32_to_cpupu(p) le32_to_cpup(p)
172
173 #else
174
175 static inline void cpu_to_le16wu(uint16_t *p, uint16_t v)
176 {
177 uint8_t *p1 = (uint8_t *)p;
178
179 p1[0] = v;
180 p1[1] = v >> 8;
181 }
182
183 static inline void cpu_to_le32wu(uint32_t *p, uint32_t v)
184 {
185 uint8_t *p1 = (uint8_t *)p;
186
187 p1[0] = v;
188 p1[1] = v >> 8;
189 p1[2] = v >> 16;
190 p1[3] = v >> 24;
191 }
192
193 static inline uint16_t le16_to_cpupu(const uint16_t *p)
194 {
195 const uint8_t *p1 = (const uint8_t *)p;
196 return p1[0] | (p1[1] << 8);
197 }
198
199 static inline uint32_t le32_to_cpupu(const uint32_t *p)
200 {
201 const uint8_t *p1 = (const uint8_t *)p;
202 return p1[0] | (p1[1] << 8) | (p1[2] << 16) | (p1[3] << 24);
203 }
204
205 #endif
206
207 /* vl.c */
208 extern int reset_requested;
209
210 uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c);
211
212 void hw_error(const char *fmt, ...);
213
214 int load_image(const char *filename, uint8_t *addr);
215 extern const char *bios_dir;
216
217 void pstrcpy(char *buf, int buf_size, const char *str);
218 char *pstrcat(char *buf, int buf_size, const char *s);
219
220 int serial_open_device(void);
221
222 extern int vm_running;
223
224 typedef void VMStopHandler(void *opaque, int reason);
225
226 int qemu_add_vm_stop_handler(VMStopHandler *cb, void *opaque);
227 void qemu_del_vm_stop_handler(VMStopHandler *cb, void *opaque);
228
229 void vm_start(void);
230 void vm_stop(int reason);
231
232 extern int audio_enabled;
233 extern int ram_size;
234 extern int bios_size;
235 extern int rtc_utc;
236 extern int cirrus_vga_enabled;
237
238 /* XXX: make it dynamic */
239 #if defined (TARGET_PPC)
240 #define BIOS_SIZE (512 * 1024)
241 #else
242 #define BIOS_SIZE 0
243 #endif
244
245 /* keyboard/mouse support */
246
247 #define MOUSE_EVENT_LBUTTON 0x01
248 #define MOUSE_EVENT_RBUTTON 0x02
249 #define MOUSE_EVENT_MBUTTON 0x04
250
251 typedef void QEMUPutKBDEvent(void *opaque, int keycode);
252 typedef void QEMUPutMouseEvent(void *opaque, int dx, int dy, int dz, int buttons_state);
253
254 void qemu_add_kbd_event_handler(QEMUPutKBDEvent *func, void *opaque);
255 void qemu_add_mouse_event_handler(QEMUPutMouseEvent *func, void *opaque);
256
257 void kbd_put_keycode(int keycode);
258 void kbd_mouse_event(int dx, int dy, int dz, int buttons_state);
259
260 /* async I/O support */
261
262 typedef void IOReadHandler(void *opaque, const uint8_t *buf, int size);
263 typedef int IOCanRWHandler(void *opaque);
264
265 int qemu_add_fd_read_handler(int fd, IOCanRWHandler *fd_can_read,
266 IOReadHandler *fd_read, void *opaque);
267 void qemu_del_fd_read_handler(int fd);
268
269 /* network redirectors support */
270
271 #define MAX_NICS 8
272
273 typedef struct NetDriverState {
274 int index; /* index number in QEMU */
275 uint8_t macaddr[6];
276 char ifname[16];
277 void (*send_packet)(struct NetDriverState *nd,
278 const uint8_t *buf, int size);
279 void (*add_read_packet)(struct NetDriverState *nd,
280 IOCanRWHandler *fd_can_read,
281 IOReadHandler *fd_read, void *opaque);
282 /* tun specific data */
283 int fd;
284 /* slirp specific data */
285 } NetDriverState;
286
287 extern int nb_nics;
288 extern NetDriverState nd_table[MAX_NICS];
289
290 void qemu_send_packet(NetDriverState *nd, const uint8_t *buf, int size);
291 void qemu_add_read_packet(NetDriverState *nd, IOCanRWHandler *fd_can_read,
292 IOReadHandler *fd_read, void *opaque);
293
294 /* timers */
295
296 typedef struct QEMUClock QEMUClock;
297 typedef struct QEMUTimer QEMUTimer;
298 typedef void QEMUTimerCB(void *opaque);
299
300 /* The real time clock should be used only for stuff which does not
301 change the virtual machine state, as it is run even if the virtual
302 machine is stopped. The real time clock has a frequency of 1000
303 Hz. */
304 extern QEMUClock *rt_clock;
305
306 /* Rge virtual clock is only run during the emulation. It is stopped
307 when the virtual machine is stopped. Virtual timers use a high
308 precision clock, usually cpu cycles (use ticks_per_sec). */
309 extern QEMUClock *vm_clock;
310
311 int64_t qemu_get_clock(QEMUClock *clock);
312
313 QEMUTimer *qemu_new_timer(QEMUClock *clock, QEMUTimerCB *cb, void *opaque);
314 void qemu_free_timer(QEMUTimer *ts);
315 void qemu_del_timer(QEMUTimer *ts);
316 void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time);
317 int qemu_timer_pending(QEMUTimer *ts);
318
319 extern int64_t ticks_per_sec;
320 extern int pit_min_timer_count;
321
322 void cpu_enable_ticks(void);
323 void cpu_disable_ticks(void);
324
325 /* VM Load/Save */
326
327 typedef FILE QEMUFile;
328
329 void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size);
330 void qemu_put_byte(QEMUFile *f, int v);
331 void qemu_put_be16(QEMUFile *f, unsigned int v);
332 void qemu_put_be32(QEMUFile *f, unsigned int v);
333 void qemu_put_be64(QEMUFile *f, uint64_t v);
334 int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size);
335 int qemu_get_byte(QEMUFile *f);
336 unsigned int qemu_get_be16(QEMUFile *f);
337 unsigned int qemu_get_be32(QEMUFile *f);
338 uint64_t qemu_get_be64(QEMUFile *f);
339
340 static inline void qemu_put_be64s(QEMUFile *f, const uint64_t *pv)
341 {
342 qemu_put_be64(f, *pv);
343 }
344
345 static inline void qemu_put_be32s(QEMUFile *f, const uint32_t *pv)
346 {
347 qemu_put_be32(f, *pv);
348 }
349
350 static inline void qemu_put_be16s(QEMUFile *f, const uint16_t *pv)
351 {
352 qemu_put_be16(f, *pv);
353 }
354
355 static inline void qemu_put_8s(QEMUFile *f, const uint8_t *pv)
356 {
357 qemu_put_byte(f, *pv);
358 }
359
360 static inline void qemu_get_be64s(QEMUFile *f, uint64_t *pv)
361 {
362 *pv = qemu_get_be64(f);
363 }
364
365 static inline void qemu_get_be32s(QEMUFile *f, uint32_t *pv)
366 {
367 *pv = qemu_get_be32(f);
368 }
369
370 static inline void qemu_get_be16s(QEMUFile *f, uint16_t *pv)
371 {
372 *pv = qemu_get_be16(f);
373 }
374
375 static inline void qemu_get_8s(QEMUFile *f, uint8_t *pv)
376 {
377 *pv = qemu_get_byte(f);
378 }
379
380 int64_t qemu_ftell(QEMUFile *f);
381 int64_t qemu_fseek(QEMUFile *f, int64_t pos, int whence);
382
383 typedef void SaveStateHandler(QEMUFile *f, void *opaque);
384 typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id);
385
386 int qemu_loadvm(const char *filename);
387 int qemu_savevm(const char *filename);
388 int register_savevm(const char *idstr,
389 int instance_id,
390 int version_id,
391 SaveStateHandler *save_state,
392 LoadStateHandler *load_state,
393 void *opaque);
394 void qemu_get_timer(QEMUFile *f, QEMUTimer *ts);
395 void qemu_put_timer(QEMUFile *f, QEMUTimer *ts);
396
397 /* block.c */
398 typedef struct BlockDriverState BlockDriverState;
399
400 BlockDriverState *bdrv_new(const char *device_name);
401 void bdrv_delete(BlockDriverState *bs);
402 int bdrv_open(BlockDriverState *bs, const char *filename, int snapshot);
403 void bdrv_close(BlockDriverState *bs);
404 int bdrv_read(BlockDriverState *bs, int64_t sector_num,
405 uint8_t *buf, int nb_sectors);
406 int bdrv_write(BlockDriverState *bs, int64_t sector_num,
407 const uint8_t *buf, int nb_sectors);
408 void bdrv_get_geometry(BlockDriverState *bs, int64_t *nb_sectors_ptr);
409 int bdrv_commit(BlockDriverState *bs);
410 void bdrv_set_boot_sector(BlockDriverState *bs, const uint8_t *data, int size);
411
412 #define BDRV_TYPE_HD 0
413 #define BDRV_TYPE_CDROM 1
414 #define BDRV_TYPE_FLOPPY 2
415
416 void bdrv_set_geometry_hint(BlockDriverState *bs,
417 int cyls, int heads, int secs);
418 void bdrv_set_type_hint(BlockDriverState *bs, int type);
419 void bdrv_get_geometry_hint(BlockDriverState *bs,
420 int *pcyls, int *pheads, int *psecs);
421 int bdrv_get_type_hint(BlockDriverState *bs);
422 int bdrv_is_removable(BlockDriverState *bs);
423 int bdrv_is_read_only(BlockDriverState *bs);
424 int bdrv_is_inserted(BlockDriverState *bs);
425 int bdrv_is_locked(BlockDriverState *bs);
426 void bdrv_set_locked(BlockDriverState *bs, int locked);
427 void bdrv_set_change_cb(BlockDriverState *bs,
428 void (*change_cb)(void *opaque), void *opaque);
429
430 void bdrv_info(void);
431 BlockDriverState *bdrv_find(const char *name);
432
433 /* ISA bus */
434
435 extern target_phys_addr_t isa_mem_base;
436
437 typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data);
438 typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address);
439
440 int register_ioport_read(int start, int length, int size,
441 IOPortReadFunc *func, void *opaque);
442 int register_ioport_write(int start, int length, int size,
443 IOPortWriteFunc *func, void *opaque);
444 void isa_unassign_ioport(int start, int length);
445
446 /* PCI bus */
447
448 extern int pci_enabled;
449
450 extern target_phys_addr_t pci_mem_base;
451
452 typedef struct PCIDevice PCIDevice;
453
454 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
455 uint32_t address, uint32_t data, int len);
456 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
457 uint32_t address, int len);
458 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
459 uint32_t addr, uint32_t size, int type);
460
461 #define PCI_ADDRESS_SPACE_MEM 0x00
462 #define PCI_ADDRESS_SPACE_IO 0x01
463 #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
464
465 typedef struct PCIIORegion {
466 uint32_t addr; /* current PCI mapping address. -1 means not mapped */
467 uint32_t size;
468 uint8_t type;
469 PCIMapIORegionFunc *map_func;
470 } PCIIORegion;
471
472 #define PCI_ROM_SLOT 6
473 #define PCI_NUM_REGIONS 7
474 struct PCIDevice {
475 /* PCI config space */
476 uint8_t config[256];
477
478 /* the following fields are read only */
479 int bus_num;
480 int devfn;
481 char name[64];
482 PCIIORegion io_regions[PCI_NUM_REGIONS];
483
484 /* do not access the following fields */
485 PCIConfigReadFunc *config_read;
486 PCIConfigWriteFunc *config_write;
487 int irq_index;
488 };
489
490 PCIDevice *pci_register_device(const char *name, int instance_size,
491 int bus_num, int devfn,
492 PCIConfigReadFunc *config_read,
493 PCIConfigWriteFunc *config_write);
494
495 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
496 uint32_t size, int type,
497 PCIMapIORegionFunc *map_func);
498
499 void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level);
500
501 uint32_t pci_default_read_config(PCIDevice *d,
502 uint32_t address, int len);
503 void pci_default_write_config(PCIDevice *d,
504 uint32_t address, uint32_t val, int len);
505
506 extern struct PIIX3State *piix3_state;
507
508 void i440fx_init(void);
509 void piix3_init(void);
510 void pci_bios_init(void);
511 void pci_info(void);
512
513 /* temporary: will be moved in platform specific file */
514 void pci_prep_init(void);
515 void pci_pmac_init(void);
516 void pci_ppc_bios_init(void);
517
518 /* vga.c */
519
520 #define VGA_RAM_SIZE (4096 * 1024)
521
522 typedef struct DisplayState {
523 uint8_t *data;
524 int linesize;
525 int depth;
526 void (*dpy_update)(struct DisplayState *s, int x, int y, int w, int h);
527 void (*dpy_resize)(struct DisplayState *s, int w, int h);
528 void (*dpy_refresh)(struct DisplayState *s);
529 } DisplayState;
530
531 static inline void dpy_update(DisplayState *s, int x, int y, int w, int h)
532 {
533 s->dpy_update(s, x, y, w, h);
534 }
535
536 static inline void dpy_resize(DisplayState *s, int w, int h)
537 {
538 s->dpy_resize(s, w, h);
539 }
540
541 int vga_initialize(DisplayState *ds, uint8_t *vga_ram_base,
542 unsigned long vga_ram_offset, int vga_ram_size,
543 int is_pci);
544 void vga_update_display(void);
545 void vga_screen_dump(const char *filename);
546
547 /* cirrus_vga.c */
548 void pci_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
549 unsigned long vga_ram_offset, int vga_ram_size);
550
551 void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
552 unsigned long vga_ram_offset, int vga_ram_size);
553
554 /* sdl.c */
555 void sdl_display_init(DisplayState *ds);
556
557 /* ide.c */
558 #define MAX_DISKS 4
559
560 extern BlockDriverState *bs_table[MAX_DISKS];
561
562 void isa_ide_init(int iobase, int iobase2, int irq,
563 BlockDriverState *hd0, BlockDriverState *hd1);
564 void pci_ide_init(BlockDriverState **hd_table);
565 void pci_piix3_ide_init(BlockDriverState **hd_table);
566
567 /* oss.c */
568 typedef enum {
569 AUD_FMT_U8,
570 AUD_FMT_S8,
571 AUD_FMT_U16,
572 AUD_FMT_S16
573 } audfmt_e;
574
575 void AUD_open (int rfreq, int rnchannels, audfmt_e rfmt);
576 void AUD_reset (int rfreq, int rnchannels, audfmt_e rfmt);
577 int AUD_write (void *in_buf, int size);
578 void AUD_run (void);
579 void AUD_adjust_estimate (int _leftover);
580 int AUD_get_free (void);
581 int AUD_get_live (void);
582 int AUD_get_buffer_size (void);
583 void AUD_init (void);
584
585 /* dma.c */
586 typedef int (*DMA_transfer_handler) (void *opaque, target_ulong addr, int size);
587 int DMA_get_channel_mode (int nchan);
588 void DMA_hold_DREQ (int nchan);
589 void DMA_release_DREQ (int nchan);
590 void DMA_schedule(int nchan);
591 void DMA_run (void);
592 void DMA_init (void);
593 void DMA_register_channel (int nchan,
594 DMA_transfer_handler transfer_handler, void *opaque);
595
596 /* sb16.c */
597 void SB16_run (void);
598 void SB16_init (void);
599
600 /* fdc.c */
601 #define MAX_FD 2
602 extern BlockDriverState *fd_table[MAX_FD];
603
604 typedef struct fdctrl_t fdctrl_t;
605
606 fdctrl_t *fdctrl_init (int irq_lvl, int dma_chann, int mem_mapped,
607 uint32_t io_base,
608 BlockDriverState **fds);
609 int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num);
610
611 /* ne2000.c */
612
613 void isa_ne2000_init(int base, int irq, NetDriverState *nd);
614 void pci_ne2000_init(NetDriverState *nd);
615
616 /* pckbd.c */
617
618 void kbd_init(void);
619
620 /* mc146818rtc.c */
621
622 typedef struct RTCState RTCState;
623
624 RTCState *rtc_init(int base, int irq);
625 void rtc_set_memory(RTCState *s, int addr, int val);
626 void rtc_set_date(RTCState *s, const struct tm *tm);
627
628 /* serial.c */
629
630 typedef struct SerialState SerialState;
631
632 extern SerialState *serial_console;
633
634 SerialState *serial_init(int base, int irq, int fd);
635 int serial_can_receive(SerialState *s);
636 void serial_receive_byte(SerialState *s, int ch);
637 void serial_receive_break(SerialState *s);
638
639 /* i8259.c */
640
641 void pic_set_irq(int irq, int level);
642 void pic_init(void);
643 uint32_t pic_intack_read(CPUState *env);
644 void pic_info(void);
645 void irq_info(void);
646
647 /* i8254.c */
648
649 #define PIT_FREQ 1193182
650
651 typedef struct PITState PITState;
652
653 PITState *pit_init(int base, int irq);
654 void pit_set_gate(PITState *pit, int channel, int val);
655 int pit_get_gate(PITState *pit, int channel);
656 int pit_get_out(PITState *pit, int channel, int64_t current_time);
657
658 /* pc.c */
659 void pc_init(int ram_size, int vga_ram_size, int boot_device,
660 DisplayState *ds, const char **fd_filename, int snapshot,
661 const char *kernel_filename, const char *kernel_cmdline,
662 const char *initrd_filename);
663
664 /* ppc.c */
665 void ppc_init (int ram_size, int vga_ram_size, int boot_device,
666 DisplayState *ds, const char **fd_filename, int snapshot,
667 const char *kernel_filename, const char *kernel_cmdline,
668 const char *initrd_filename);
669 void ppc_prep_init (int ram_size, int vga_ram_size, int boot_device,
670 DisplayState *ds, const char **fd_filename, int snapshot,
671 const char *kernel_filename, const char *kernel_cmdline,
672 const char *initrd_filename);
673 void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device,
674 DisplayState *ds, const char **fd_filename, int snapshot,
675 const char *kernel_filename, const char *kernel_cmdline,
676 const char *initrd_filename);
677 #ifdef TARGET_PPC
678 ppc_tb_t *cpu_ppc_tb_init (CPUState *env, uint32_t freq);
679 #endif
680 void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
681
682 extern CPUWriteMemoryFunc *PPC_io_write[];
683 extern CPUReadMemoryFunc *PPC_io_read[];
684 extern int prep_enabled;
685
686 /* NVRAM helpers */
687 #include "hw/m48t59.h"
688
689 void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value);
690 uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr);
691 void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value);
692 uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr);
693 void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value);
694 uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr);
695 void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
696 const unsigned char *str, uint32_t max);
697 int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max);
698 void NVRAM_set_crc (m48t59_t *nvram, uint32_t addr,
699 uint32_t start, uint32_t count);
700 int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
701 const unsigned char *arch,
702 uint32_t RAM_size, int boot_device,
703 uint32_t kernel_image, uint32_t kernel_size,
704 uint32_t cmdline, uint32_t cmdline_size,
705 uint32_t initrd_image, uint32_t initrd_size,
706 uint32_t NVRAM_image);
707
708 /* adb.c */
709
710 #define MAX_ADB_DEVICES 16
711
712 typedef struct ADBDevice ADBDevice;
713
714 typedef void ADBDeviceReceivePacket(ADBDevice *d, const uint8_t *buf, int len);
715
716 struct ADBDevice {
717 struct ADBBusState *bus;
718 int devaddr;
719 int handler;
720 ADBDeviceReceivePacket *receive_packet;
721 void *opaque;
722 };
723
724 typedef struct ADBBusState {
725 ADBDevice devices[MAX_ADB_DEVICES];
726 int nb_devices;
727 } ADBBusState;
728
729 void adb_receive_packet(ADBBusState *s, const uint8_t *buf, int len);
730 void adb_send_packet(ADBBusState *s, const uint8_t *buf, int len);
731
732 ADBDevice *adb_register_device(ADBBusState *s, int devaddr,
733 ADBDeviceReceivePacket *receive_packet,
734 void *opaque);
735 void adb_kbd_init(ADBBusState *bus);
736 void adb_mouse_init(ADBBusState *bus);
737
738 /* cuda.c */
739
740 extern ADBBusState adb_bus;
741 int cuda_init(void);
742
743 /* monitor.c */
744 void monitor_init(void);
745 void term_printf(const char *fmt, ...) __attribute__ ((__format__ (__printf__, 1, 2)));
746 void term_flush(void);
747 void term_print_help(void);
748
749 /* gdbstub.c */
750
751 #define DEFAULT_GDBSTUB_PORT 1234
752
753 int gdbserver_start(int port);
754
755 #endif /* VL_H */