+ gArmTokenSpaceGuid.PcdArmDmaDeviceOffset|0x0|UINT64|0x0000044\r
+\r
+[PcdsFixedAtBuild.common, PcdsPatchableInModule.common]\r
+ gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT64|0x0000002B\r
+ gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT64|0x0000002D\r
+\r
+[PcdsFixedAtBuild.ARM]\r
+ #\r
+ # ARM Security Extension\r
+ #\r
+\r
+ # Secure Configuration Register\r
+ # - BIT0 : NS - Non Secure bit\r
+ # - BIT1 : IRQ Handler\r
+ # - BIT2 : FIQ Handler\r
+ # - BIT3 : EA - External Abort\r
+ # - BIT4 : FW - F bit writable\r
+ # - BIT5 : AW - A bit writable\r
+ # - BIT6 : nET - Not Early Termination\r
+ # - BIT7 : SCD - Secure Monitor Call Disable\r
+ # - BIT8 : HCE - Hyp Call enable\r
+ # - BIT9 : SIF - Secure Instruction Fetch\r
+ # 0x31 = NS | EA | FW\r
+ gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038\r
+\r
+ # By default we do not do a transition to non-secure mode\r
+ gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E\r
+\r
+ # Non Secure Access Control Register\r
+ # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality\r
+ # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31\r
+ # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable\r
+ # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable\r
+ # 0xC00 = cp10 | cp11\r
+ gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039\r
+\r
+[PcdsFixedAtBuild.AARCH64]\r
+ #\r
+ # AArch64 Security Extension\r
+ #\r
+\r
+ # Secure Configuration Register\r
+ # - BIT0 : NS - Non Secure bit\r
+ # - BIT1 : IRQ Handler\r
+ # - BIT2 : FIQ Handler\r
+ # - BIT3 : EA - External Abort\r
+ # - BIT4 : FW - F bit writable\r
+ # - BIT5 : AW - A bit writable\r
+ # - BIT6 : nET - Not Early Termination\r
+ # - BIT7 : SCD - Secure Monitor Call Disable\r
+ # - BIT8 : HCE - Hyp Call enable\r
+ # - BIT9 : SIF - Secure Instruction Fetch\r
+ # - BIT10: RW - Register width control for lower exception levels\r
+ # - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer\r
+ # - BIT12: TWI - Trap WFI\r
+ # - BIT13: TWE - Trap WFE\r
+ # 0x501 = NS | HCE | RW\r
+ gArmTokenSpaceGuid.PcdArmScr|0x501|UINT32|0x00000038\r
+\r
+ # By default we do transition to EL2 non-secure mode with Stack for EL2.\r
+ # Mode Description Bits\r
+ # NS EL2 SP2 all interrupts disabled = 0x3c9\r
+ # NS EL1 SP1 all interrupts disabled = 0x3c5\r
+ # Other modes include using SP0 or switching to Aarch32, but these are\r
+ # not currently supported.\r
+ gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E\r
+\r
+\r
+#\r
+# These PCDs are also defined as 'PcdsDynamic' or 'PcdsPatchableInModule' to be\r
+# redefined when using UEFI in a context of virtual machine.\r
+#\r
+[PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common]\r
+\r
+ # System Memory (DRAM): These PCDs define the region of in-built system memory\r
+ # Some platforms can get DRAM extensions, these additional regions may be\r
+ # declared to UEFI using separate resource descriptor HOBs\r
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029\r
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A\r
+\r
+ gArmTokenSpaceGuid.PcdMmBufferBase|0|UINT64|0x00000045\r
+ gArmTokenSpaceGuid.PcdMmBufferSize|0|UINT64|0x00000046\r
+\r
+[PcdsFixedAtBuild.common, PcdsDynamic.common]\r
+ #\r
+ # ARM Architectural Timer\r
+ #\r
+ gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034\r
+\r
+ # ARM Architectural Timer Interrupt(GIC PPI) numbers\r
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035\r
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036\r
+ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26|UINT32|0x00000040\r
+ gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27|UINT32|0x00000041\r
+\r
+ #\r
+ # ARM Generic Watchdog\r
+ #\r
+\r
+ gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT64|0x00000007\r
+ gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT64|0x00000008\r
+ gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93|UINT32|0x00000009\r
+\r
+ #\r
+ # ARM Generic Interrupt Controller\r
+ #\r
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT64|0x0000000C\r
+ # Base address for the GIC Redistributor region that contains the boot CPU\r
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT64|0x0000000E\r
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT64|0x0000000D\r
+ gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025\r
+\r
+ #\r
+ # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.\r
+ # Note that "IO" is just another MMIO range that simulates IO space; there\r
+ # are no special instructions to access it.\r
+ #\r
+ # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are\r
+ # specific to their containing address spaces. In order to get the physical\r
+ # address for the CPU, for a given access, the respective translation value\r
+ # has to be added.\r
+ #\r
+ # The translations always have to be initialized like this, using UINT64:\r