+\r
+\r
+#\r
+# These PCDs are also defined as 'PcdsDynamic' or 'PcdsPatchableInModule' to be\r
+# redefined when using UEFI in a context of virtual machine.\r
+#\r
+[PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common]\r
+\r
+ # System Memory (DRAM): These PCDs define the region of in-built system memory\r
+ # Some platforms can get DRAM extensions, these additional regions will be declared\r
+ # to UEFI by ArmPlatformLib\r
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029\r
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A\r
+\r
+[PcdsFixedAtBuild.common, PcdsDynamic.common]\r
+ #\r
+ # ARM Architectural Timer\r
+ #\r
+ gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034\r
+\r
+ # ARM Architectural Timer Interrupt(GIC PPI) numbers\r
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035\r
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036\r
+ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26|UINT32|0x00000040\r
+ gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27|UINT32|0x00000041\r
+\r
+ #\r
+ # ARM Generic Watchdog\r
+ #\r
+\r
+ gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT32|0x00000007\r
+ gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT32|0x00000008\r
+ gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93|UINT32|0x00000009\r
+\r
+ #\r
+ # ARM Generic Interrupt Controller\r
+ #\r
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT32|0x0000000C\r
+ # Base address for the GIC Redistributor region that contains the boot CPU\r
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT32|0x0000000E\r
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000000D\r
+ gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025\r
+\r
+ #\r
+ # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.\r
+ # Note that "IO" is just another MMIO range that simulates IO space; there\r
+ # are no special instructions to access it.\r
+ #\r
+ # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are\r
+ # specific to their containing address spaces. In order to get the physical\r
+ # address for the CPU, for a given access, the respective translation value\r
+ # has to be added.\r
+ #\r
+ # The translations always have to be initialized like this, using UINT64:\r
+ #\r
+ # UINT64 IoCpuBase; // mapping target in 64-bit cpu-physical space\r
+ # UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space\r
+ # UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space\r
+ #\r
+ # PcdPciIoTranslation = IoCpuBase - PcdPciIoBase;\r
+ # PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;\r
+ # PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;\r
+ #\r
+ # because (a) the target address space (ie. the cpu-physical space) is\r
+ # 64-bit, and (b) the translation values are meant as offsets for *modular*\r
+ # arithmetic.\r
+ #\r
+ # Accordingly, the translation itself needs to be implemented as:\r
+ #\r
+ # UINT64 UntranslatedIoAddress; // input parameter\r
+ # UINT32 UntranslatedMmio32Address; // input parameter\r
+ # UINT64 UntranslatedMmio64Address; // input parameter\r
+ #\r
+ # UINT64 TranslatedIoAddress; // output parameter\r
+ # UINT64 TranslatedMmio32Address; // output parameter\r
+ # UINT64 TranslatedMmio64Address; // output parameter\r
+ #\r
+ # TranslatedIoAddress = UntranslatedIoAddress +\r
+ # PcdPciIoTranslation;\r
+ # TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +\r
+ # PcdPciMmio32Translation;\r
+ # TranslatedMmio64Address = UntranslatedMmio64Address +\r
+ # PcdPciMmio64Translation;\r
+ #\r
+ # The modular arithmetic performed in UINT64 ensures that the translation\r
+ # works correctly regardless of the relation between IoCpuBase and\r
+ # PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and\r
+ # PcdPciMmio64Base.\r
+ #\r
+ gArmTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000050\r
+ gArmTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000051\r
+ gArmTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000052\r
+ gArmTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000053\r
+ gArmTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000054\r
+ gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000055\r
+ gArmTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000056\r
+ gArmTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000057\r
+ gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000058\r
+\r
+ #\r
+ # Inclusive range of allowed PCI buses.\r
+ #\r
+ gArmTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x00000059\r
+ gArmTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000005A\r